Power Factor Correction Controller, Power Factor Correction Circuit and Control Method

Abstract

The present invention provides a power factor correction controller, a power factor correction circuit and a control method. An embodiment provides a power factor correction circuit, which includes an inductor, a power transistor, a current sensing resistor, a PFC controller and a signal integration circuit. The power transistor has a drain electrically coupled to the inductor, and also has a source and a gate. The current sensing resistor is connected between the source and the ground power supply line. The PFC controller provides a driving terminal and a multi-functional terminal. The driving terminal is coupled to the gate. The signal integration circuit is electrically coupled to the drain, the source and the multi-functional terminal to generate a multi-functional signal on the multi-functional terminal. When the power transistor is turned on and presents a short circuit, the PFC controller compares the multi-functional signal with a first preset reference signal. When the multi-functional signal exceeds the first preset reference signal, over-current protection is provided to fixedly turn off the power transistor. When the power transistor is turned off and presents an open circuit, the PFC controller detects the zero-current time when the inductor current of the inductor drops to 0 according to the multi-functional signal.

Description

Technical Field

[0001] The present invention generally relates to power factor correction (PFC), and more particularly to an active power factor correction circuit, a related power supply controller, and a control method. Background Art

[0002] PFC is a technology for increasing the power factor (PF) of a power supply. A power supply without PFC often draws a large amount of current from the AC mains in a very short period of time. Such short bursts of current can be smoothed out through active or passive techniques. In this way, the input root-mean-square (RMS) current can be reduced to increase the PF. PFC can change the waveform of the input current to maximize the real power from the AC mains.

[0003] Figure 1 Shown is a known active PFC circuit 100 having a booster architecture. The PFC controller 102 switches the power transistor 104 to control the inductor current I flowing through the inductor L L of the current waveform, with the goal of making the average of the inductor current I L be approximately a continuous sinusoidal input current, which is approximately in phase with the voltage waveform of the AC mains V AC-IN . The diode D1 provides a rectifying function to charge the output capacitor COUT with the inductor current I L to generate the output voltage V OUT . Summary of the Invention

[0004] An embodiment of the present invention provides a power factor correction circuit, which includes an inductor, a power transistor, a current detection resistor, a PFC controller, and a signal integration circuit. The power transistor has a drain electrically coupled to the inductor, and also has a source and a gate. The current detection resistor is connected between the source and a grounded power supply line. The PFC controller provides a driving terminal and a multi-functional terminal. The driving terminal is coupled to the gate. The signal integration circuit is electrically coupled to the drain, the source, and the multi-functional terminal, and is used to generate a multi-functional signal on the multi-functional terminal. When the power transistor is turned on and presents a short circuit, the PFC controller compares the multi-functional signal with a first preset reference signal, and when the multi-functional signal exceeds the first preset reference signal, provides overcurrent protection to fixedly turn off the power transistor. When the power transistor is turned off and presents an open circuit, the PFC controller detects a zero current time when the inductor current of the inductor drops to 0 according to the multi-functional signal.

[0005] An embodiment of the present invention provides a PFC controller. The PFC controller includes a driver, a multi-functional terminal, a zero current detector, and a protection device. The driver is used to drive a power transistor, which has a drain and a source. The multi-functional terminal is electrically coupled to the drain and the source through a signal integration circuit. There is a multi-functional signal on the multi-functional terminal. The zero current detector is electrically coupled to the multi-functional terminal, and according to the multi-functional signal, when the driver turns off the power transistor and presents an open circuit, detects a zero current time when the current of an inductor drops to 0. The protection device is electrically coupled to the multi-functional terminal, and according to the multi-functional signal, when the driver turns on the power transistor and presents a short circuit, compares the multi-functional signal with a first preset reference signal, and when the multi-functional signal exceeds the first preset reference signal, provides overcurrent protection to fixedly turn off the power transistor.

[0006] An embodiment of the present invention provides a PFC control method. The PFC control method includes: driving a power transistor, which has a drain and a source, and the drain is electrically coupled to an inductor; providing a multi-functional terminal, which is electrically coupled to the drain and the source through a signal integration circuit, wherein there is a multi-functional signal on the multi-functional terminal; according to the multi-functional signal, when the power transistor is turned off and presents an open circuit, detecting a zero current time when the current of the inductor drops to 0; and according to the multi-functional signal, when the power transistor is turned on and presents a short circuit, comparing the multi-functional signal with a first preset reference signal, and when the multi-functional signal exceeds the first preset reference signal, providing overcurrent protection to fixedly turn off the power transistor. Description of the Drawings

[0007] Figure 1 Show a known active PFC circuit 100.

[0008] Figure 2 Displays the active PFC circuit 200 implemented according to the present invention.

[0009] Figure 3 Displays Figure 2 the gate signal V G , the current detection signal V CS , the inductor current I L , the drain signal V D , and the signal waveforms of the multifunctional signal V CS / ZCD .

[0010] Figure 4 Displays Figure 2 the PFC controller 202 in

[0011]

Symbol Explanation

[0012] 100, 200 PFC circuit

[0013] 102 PFC controller

[0014] 104 Power transistor

[0015] 201 Filter capacitor

[0016] 202 PFC controller

[0017] 204 Power transistor

[0018] 206 Signal integration circuit

[0019] 210 Connection point

[0020] 302 ZCD detector

[0021] 304 Trough detector

[0022] 306 Overcurrent detector

[0023] 308 Diode short - circuit detector

[0024] 310 Overvoltage detector

[0025] 312 Pulse width modulator

[0026] 314 Driver

[0027] 316 Sampler

[0028] 318 Comparator

[0029] 320 Comparator

[0030] 322 Timer

[0031] BR Bridge Rectifier

[0032] C1 and C2 Capacitor Pair

[0033] COUT Output Capacitor

[0034] CS / ZCD Multifunctional Terminal

[0035] D Drain

[0036] D1 Diode

[0037] DRV Drive Terminal

[0038] I IN Input Current

[0039] I L Inductor Current

[0040] L Inductor

[0041] R1 and R2 Resistor Pair

[0042] RCS Current Sensing Resistor

[0043] S Source

[0044] S DSCP Protection Signal

[0045] S OCP Protection Signal

[0046] S OVP Protection Signal

[0047] S PWM PWM Signal

[0048] S V Trough Signal

[0049] S ZCD Pulse

[0050] tzcd Zero-Current Time

[0051] T CYC Switching Period

[0052] T OFF Turn-Off Time

[0053] T ON Turn-On Time

[0054] V AC-IN AC Mains

[0055] V CS Current Sensing Signal

[0056] VCS / ZCD Multifunctional signal

[0057] V D Drain signal

[0058] V DSCP Diode short - circuit protection reference signal

[0059] V G Gate signal

[0060] V IN Input voltage power supply

[0061] VL1, VL2 troughs

[0062] V OCP Over - current protection reference signal

[0063] V OVP Over - voltage reference signal

[0064] V OUT Output voltage

[0065] V SAMP Sample signal Specific implementation manners

[0066] In this specification, there are some identical symbols, which represent elements with the same or similar structures, functions, and principles, and can be inferred by those skilled in the art according to the teachings of this specification. For the sake of simplicity of the specification, the elements with the same symbols will not be restated.

[0067] In an embodiment of the present invention, a PFC controller controls a power transistor, which is connected in series with an inductor to perform PFC. The PFC controller is a packaged single - chip with a multifunctional terminal, which is electrically coupled to the drain and source of the power transistor through a signal integration circuit. According to a multifunctional signal on the multifunctional terminal, the PFC controller detects an inductor current when the power transistor is turned on, and a zero - current time when the inductor current drops to 0 when the power transistor is turned off, and provides some protection mechanisms.

[0068] Figure 2 Figure 200 shows an active PFC circuit implemented according to the present invention, which has a booster architecture. The PFC circuit 200 includes a bridge rectifier BR, a filter capacitor 201, an inductor L, a PFC controller 202, a power transistor 204, a signal integration circuit 206, a current - sensing resistor RCS, a diode D1, and an output capacitor COUT. The PFC circuit 200 may have Figure 2 other elements not shown. For the sake of simplicity in illustration,Figure 2 These components that are not shown are omitted. The drain D of the power transistor 204 is electrically connected to the inductor L and the diode D1. There is a drain signal V on the drain D D . The current sensing resistor RCS is connected between the source S of the power transistor 204 and a grounded power supply line, and there is a current sensing signal V on the terminal 208 CS . When the power transistor 204 is turned on and presents as a short circuit, the current sensing signal V CS can represent the inductor current I flowing through the inductor L L .

[0069] The bridge rectifier BR provides full-wave rectification to convert the AC mains voltage V AC-IN into a DC input voltage power supply V IN and the grounded power supply line. The inductor L is electrically connected between the input voltage power supply V IN and the drain D of the power transistor 204. The output of the bridge rectifier BR is filtered by the inductor L and the filter capacitor 201 to generate a continuous input current I IN . In some embodiments, the PFC controller 202 is a packaged single-chip integrated circuit that generates a gate signal V G using pulse width modulation or other modulation techniques, and turns on or off the power transistor 204 through the drive terminal DRV (or pin) to regulate the output voltage V OUT , and makes the waveform of the input current I IN substantially in phase with the voltage waveform of the input voltage V IN to achieve the purpose of PFC. The power transistor 204 can be a metal oxide semiconductor transistor. The PFC circuit 200 can operate in boundary mode, discontinuous conduction mode (CCM), or burst mode. The output voltage V OUT can be used to supply power to Figure 2 the load or other power converters not shown in

[0070] The signal integration circuit 206 is electrically coupled to both the source S and the drain D at the same time to integrate the current sensing signal V CS and the drain signal V D to provide a multifunctional signal V at the multifunctional terminal CS / ZCD (or pin) of the PFC controller 202 CS / ZCD。The signal integration circuit 206 has resistor pairs R1 and R2, and capacitor pairs C1 and C2, all connected in series between the source S and the drain D. The connection point 210 between the resistor pairs R1 and R2 and the capacitor pairs C1 and C2 is electrically connected to the multifunctional terminal CS / ZCD. When the power transistor 204 is turned on, the multifunctional signal V CS / ZCD can approximately represent the current detection signal V CS , based on which the PFC controller 202 can determine whether the inductor current I L is too large to perform corresponding protection. When the power transistor 204 is turned off, the multifunctional signal V CS / ZCD can approximately represent the drain signal V D , based on which the PFC controller 202 can determine a zero-current time tzcd when the inductor current I L drops to 0, and whether the output voltage V OUT is too high to perform corresponding control.

[0071] Figure 3 Show Figure 2 the gate signal V G , current detection signal V CS , inductor current I L , drain signal V D , and the signal waveforms of the multifunctional signal V CS / ZCD . Figure 4 Show Figure 2 the PFC controller 202 in

[0072] Please also refer to Figure 3 and Figure 4 . A switching period T CYC includes a turn-on time T ON and a turn-off time T OFF . The turn-on time T ON refers to the time when the gate signal V G is logically "1", and is also the time when a short circuit exists between the source S and the drain D of the power transistor 204. In contrast, the turn-off time T OFF refers to the time when the gate signal V G is logically "0", and is also the time when an open circuit exists between the source S and the drain D of the power transistor 204.

[0073] The pulse width modulator 312 generates a PWM signal S PWM , and the driver 314 generates a gate signal V PWM with appropriate voltage or current based on the PWM signal S Gto drive the power transistor 204. Logically, the PWM signal S PWM is the same as the gate signal V G . For example, the pulse width modulator 312 determines the ON time T ON in a constant ON-time mode based on a compensation signal (not shown).

[0074] During the ON time T ON , the power transistor 204 presents a short circuit, so Figure 3 in the inductor current I L and the current detection signal V CS increase linearly with time. Also, because the power transistor 204 presents a short circuit, the current detection signal V CS is approximately equal to the drain signal V D , and is also approximately equal to the multifunctional signal V CS / ZCD , as Figure 3 shown. During the ON time T ON , under normal operation, the diode D1 is reverse biased and in the off state.

[0075] The overcurrent detector 306 detects the multifunctional signal V ON during the ON time T CS / ZCD . For example, during the ON time T ON , the overcurrent detector 306 compares the multifunctional signal V CS / ZCD with the over current protection (OCP) reference signal V OCP . When the multifunctional signal V CS / ZCD exceeds the OCP reference signal V OCP , the overcurrent detector 306 provides a protection signal S OCP , which can disable the pulse width modulator 312 to quickly and fixedly turn off the power transistor 204. This can prevent excessive inductor current I OUT generated by an overloaded load powered by the output voltage V L . Similarly, the diode short circuit detector 308 compares the multifunctional signal V CS / ZCD with the diode short circuit protection (DSCP) reference signal V DSCP . When the multifunctional signal V CS / ZCD exceeds the DSCP reference signal V DSCP , the overcurrent detector 306 provides a protection signal S DSCP, its disable pulse width modulator 312 quickly and fixedly turns off the power transistor 204. This can prevent the problem of excessive inductance current I caused by the short circuit failure of the diode D1. L Excessive problem.

[0076] During the turn-off time T OFF , the current detection signal V CS is approximately 0V, so the multifunctional signal V CS / ZCD is approximately proportional to the drain signal V D . The multifunctional signal V CS / ZCD can be used to represent the drain signal V D , as shown in Figure 3 .

[0077] During the turn-off time T OFF , the ZCD detector 302 detects the zero current time tzcd when the inductance current I of the inductor L drops to 0 according to the multifunctional signal V CS / ZCD , as shown in L . In Figure 3 , soon after the turn-off time T Figure 3 starts, the sampler 316 samples the multifunctional signal V OFF to generate a sample signal V CS / ZCD . The comparator 318 compares the sample signal V SAMP and the multifunctional signal V SAMP to determine the zero current time tzcd. For example, when the multifunctional signal V CS / ZCD drops and is less than the sample signal V CS / ZCD by a fixed offset V SAMP by a fixed offset V OFFSET , it is determined as the zero current time tzcd, providing a pulse S ZCD . After the turn-off time T OFF starts and before the zero current time tzcd, the diode D1 is forward biased and in the on state.

[0078] During the turn-off time T OFF , after the zero current time tzcd, the valley detector 304 detects the time when the valley voltages VL1 and VL2 generated by the simple harmonic oscillation of the drain voltage V CS / ZCD on the drain D occur according to the multifunctional signal V D , so as to provide a valley signal S V to the pulse width modulator 312. The pulse width modulator 312 can be designed to start the turn-on time T CYC of the next switching cycle T ON approximately when a valley occurs for valley switching. Valley switching can enable the power transistor 204 to have lower switching losses and improve the conversion efficiency.

[0079] The pulse width modulator 312 can start the next switching period T ZCD based on the pulse S V and the valley signal S CYC for the turn-on time T ON of the next switching period T ON . After the zero-current time tzcd and before the next turn-on time T

[0080] , the diode D1 is reverse-biased and in the off state. OFF During the off time T CS / ZCD , the overvoltage detector 310 detects whether the multifunctional signal V CS / ZCD is too high to provide overvoltage protection (OVP). The comparator 320 compares the multifunctional signal V OVP with the overvoltage reference signal V CS / ZCD . When the multifunctional signal V OVP continues to exceed the overvoltage reference signal V OVP for a time exceeding the preset time (several switching periods) calculated by the timer 322, the timer 322 issues a protection signal S

[0081] which can disable the pulse width modulator 312 to quickly and fixedly turn off the power transistor 204.

[0082] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims

1. A power factor correction circuit, comprising: An inductor; A power transistor, having a drain electrically coupled to the inductor, a source, and a gate; A current sensing resistor is connected between the source and the grounded power supply line; A power factor correction controller provides a driving terminal and a multi-functional terminal, wherein the driving terminal is coupled to the gate; and A signal integration circuit is electrically coupled to the drain, the source, and the multi-functional terminal for generating a multi-functional signal on the multi-functional terminal; Wherein, the power factor correction controller is configured to: When the power transistor is turned on and presents a short circuit, compare the multi-functional signal with a first preset reference signal to provide over-current protection to fixedly turn off the power transistor; and When the power transistor is turned off and presents an open circuit, detect the zero current time when the inductor current drops to 0 based on the multi-functional signal.

2. The power factor correction circuit according to claim 1, wherein The power factor correction controller is configured to, when the power transistor is turned off and presents an open circuit, compare the multi-functional signal with a second preset reference signal to provide over-voltage protection to fixedly turn off the power transistor.

3. The power factor correction circuit according to claim 1, wherein The power factor correction controller is configured to, after the zero current time, detect the trough generated by the oscillation of the drain voltage on the drain based on the multi-functional signal.

4. The power factor correction circuit according to claim 1, wherein The signal integration circuit includes a pair of resistors connected in series between the current sensing resistor and the drain, and the connection point between the pair of resistors is electrically coupled to the multi-functional terminal.

5. The power factor correction circuit according to claim 1, wherein The signal integration circuit includes a pair of capacitors connected in series between the current sensing resistor and the drain, and the connection point between the pair of capacitors is electrically coupled to the multi-functional terminal.

6. A power factor correction controller, comprising: A driver for driving a power transistor, which has a drain and a source; The multi-functional terminal is used to be electrically coupled to the drain and the source through the signal integration circuit, and the multi-functional terminal has a multi-functional signal; A zero current detector is electrically coupled to the multi-functional terminal, and based on the multi-functional signal, when the driver turns off the power transistor and presents an open circuit, detects the zero current time when one of the inductor currents drops to 0; And A protection device is electrically coupled to the multi-functional terminal, and based on the multi-functional signal, when the driver turns on the power transistor and presents a short circuit, compares the multi-functional signal with a first preset reference signal to provide over-current protection to fixedly turn off the power transistor.

7. The power factor correction controller according to claim 6, wherein When the driver turns off the power transistor and presents an open circuit, the protection device compares the multi-functional signal with a second preset reference signal to provide over-voltage protection to fixedly turn off the power transistor.

8. The power factor correction controller according to claim 6, wherein When the driver turns off the power transistor, the zero current detector samples the multi-functional signal to generate a sample signal, and compares the sample signal and the multi-functional signal to determine the zero current time.

9. A power factor correction control method, comprising: Driving a power transistor, which has a drain and a source, the drain being electrically coupled to an inductor; Provide a multi-functional terminal, which is electrically coupled to the drain and the source through the signal integration circuit, wherein the multi-functional terminal has a multi-functional signal; Based on the multi-functional signal, when the power transistor is turned off and presents an open circuit, detect the zero current time when the inductor current drops to 0; and Based on the multi-functional signal, when the power transistor is turned on and presents a short circuit, compare the multi-functional signal with a first preset reference signal to provide over-current protection to fixedly turn off the power transistor.

10. The power factor correction control method according to claim 9, comprising: When the power transistor is turned off and presents an open circuit, comparing the multifunctional signal with a second preset reference signal to provide overvoltage protection to fixedly turn off the power transistor.

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