Synchronous rectification control circuit and switching power supply system

Abstract

A synchronous rectification control circuit and a switching power supply system, wherein the synchronous rectification control circuit includes: a sampling circuit, a turn-on comparison circuit, a turn-off comparison circuit, a drive control circuit, and an anti-false start-up circuit, wherein: the sampling circuit has a first terminal coupled to the first output terminal of the transformer; the anti-false start-up circuit has a first input terminal coupled to the second terminal of the sampling circuit; the turn-on comparison circuit has a first input terminal coupled to the second terminal of the sampling circuit, and a second input terminal coupled to the output terminal of the anti-false start-up circuit; the turn-off comparison circuit has an input terminal coupled to the second terminal of the sampling circuit; and the drive control circuit has a first input terminal coupled to the output terminal of the turn-on comparison circuit, and a second input terminal coupled to the output terminal of the turn-off comparison circuit. The above scheme can prevent the synchronous rectification control circuit from falsely starting.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a synchronous rectification control circuit and a switching power supply system. Background Art

[0002] The flyback switching power supply system has the advantages of simple circuit structure, input and output voltage isolation, low cost and small size, and has been widely used.

[0003] When a flyback switching power supply system is used in applications with high output current, traditional secondary rectifier diodes introduce significant conduction and reverse recovery losses, resulting in low power system efficiency. To reduce the losses caused by the rectifier diodes, existing technologies employ MOSFETs with extremely low on-resistance as rectifiers, effectively improving power system efficiency.

[0004] Reference Figure 1 , provides a schematic diagram of the structure of an existing synchronous rectification control circuit. The synchronous rectification control circuit includes a power circuit and a control circuit. The control circuit comprises a turn-on comparison circuit 101, a turn-off comparison circuit 102, and a drive control circuit 103. The control circuit also includes a sampling circuit, which typically uses a MOS transistor N2 as the sampling MOS transistor. The sampling MOS transistor N2 detects the portion of the source-drain difference of the switching MOS transistor N1 that is lower than the voltage VCC, thereby obtaining a sampled voltage VDET.

[0005] The first terminal of the sampling MOS transistor N2 is coupled to the first output terminal of the transformer, the switching MOS transistor N1 is coupled to the first output terminal of the transformer, and the gate of the switching transistor N1 is coupled to the output terminal of the driving control circuit 203. The input voltage of the transformer is Vin, and the output voltage is Vout.

[0006] The on-comparison circuit 101 generates an on-signal SR_ON based on the sampled voltage VDET and outputs it to the drive control circuit 103. The off-comparison circuit 102 generates an off-signal SR_OFF based on the sampled voltage VDET and outputs it to the drive control circuit 103. The drive control circuit 103 generates a drive signal GATE based on the on-signal SR_ON and the off-signal SR_OFF and outputs it to the gate of the switch MOS transistor N1 to control the on / off state of the switch MOS transistor N1.

[0007] However, the synchronous rectification control circuit provided in the prior art still has the problem of being turned on by mistake. Summary of the Invention

[0008] The technical problem solved by the embodiments of the present invention is that a synchronous rectification control circuit may be mistakenly turned on.

[0009] To solve the above technical problems, an embodiment of the present invention provides a synchronous rectification control circuit, comprising: a sampling circuit, a turn-on comparison circuit, a turn-off comparison circuit, a drive control circuit, and an anti-false start circuit, wherein: the sampling circuit has a first terminal coupled to the first output terminal of the transformer and is adapted to obtain a sampled voltage; the anti-false start circuit has a first input terminal coupled to the second terminal of the sampling circuit and is adapted to generate and output a turn-on enable signal based on the sampled voltage; the turn-on comparison circuit has a first input terminal coupled to the second terminal of the sampling circuit and a second input terminal coupled to the output terminal of the anti-false start circuit; and is adapted to generate and output a turn-on signal upon receiving the turn-on enable signal; the turn-off comparison circuit has an input terminal coupled to the second terminal of the sampling circuit and is adapted to generate and output a turn-off signal based on the sampled signal; the drive control circuit has a first input terminal coupled to the output terminal of the turn-on comparison circuit and a second input terminal coupled to the output terminal of the turn-off comparison circuit; and is adapted to generate a corresponding drive signal based on the turn-on signal and the turn-off signal and output the drive signal to a power switch tube coupled to the first output terminal of the transformer to control the switching state of the power switch tube.

[0010] Optionally, the anti-mistaken start-up circuit includes: a first transmission gate circuit, a second transmission gate circuit and a first-level sub-circuit, wherein: the first transmission gate circuit has an input end connected to ground, an output end coupled to the second input end of the first-level sub-circuit and the output end of the second transmission gate circuit, a first control end coupled to the second control end of the second transmission gate circuit, and a second control end coupled to the first control end of the second transmission gate circuit; the second transmission gate circuit has an input end inputting a first reference voltage, and an output end coupled to the second input end of the first-level sub-circuit; the first control signal of the first control end and the second control signal of the second control end of the first transmission gate circuit are determined by the magnitude relationship between the first reference voltage and the sampling voltage; the first-level sub-circuit has a first input end coupled to the first input end of the anti-mistaken start-up circuit, and an output end coupled to the output end of the anti-mistaken start-up circuit.

[0011] Optionally, the first-stage sub-circuit includes: a first comparator, a first inverter, a first NMOS transistor, a first current source, a first capacitor, a fourth comparator, and a first D-type flip-flop, wherein: the first comparator has a first input terminal that is the first input terminal of the first-stage sub-circuit, a second input terminal that is the second input terminal of the first-stage sub-circuit, and an output terminal that is coupled to the input terminal of the first inverter, the first control terminal of the first transmission gate circuit, and the second control terminal of the second transmission gate circuit; the first inverter has an output terminal that is coupled to the gate of the first NMOS transistor, the second control terminal of the first transmission gate circuit, and the first control terminal of the second transmission gate circuit. The first NMOS transistor has a drain coupled to the second end of the first current source, the first end of the first capacitor and the second input end of the fourth comparator; its source is grounded; the first capacitor has a second end grounded; the first current source has a first end connected to a preset power supply voltage; the fourth comparator has a first input end inputting a second reference voltage, and an output end generating a first turn-on enable sub-signal; the first D flip-flop has a clock signal input end coupled to the output end of the fourth comparator, a D end inputting a preset signal, and a Q end coupled to the output end of the first-stage sub-circuit; the first turn-on enable sub-signal is output via the Q end to obtain the turn-on enable signal.

[0012] Optionally, the anti-misstart circuit has a second input terminal coupled to the first output terminal of the transformer and a third input terminal coupled to the second output terminal of the transformer, and is suitable for determining to generate the start-up enable signal based on the output voltage of the first output terminal of the transformer and the second output terminal of the transformer.

[0013] Optionally, the anti-error start-up circuit includes: a second-level sub-circuit, a first voltage-divider resistor, a second voltage-divider resistor, a third voltage-divider resistor and a fourth voltage-divider resistor, and an OR gate circuit, wherein: the first voltage-divider resistor, its first end is coupled to the second input end of the anti-error start-up circuit, and its second end is coupled to the first input end of the second-level sub-circuit and the first end of the second voltage-divider resistor; the second end of the second voltage-divider resistor, its second end is grounded; the third voltage-divider resistor, its first end is coupled to the third input end of the anti-error start-up circuit, and its second end is coupled to the first end of the fourth voltage-divider resistor; the voltage of the second end of the third voltage-divider resistor is the first voltage divider; the fourth voltage-divider resistor, its second end is grounded; the second-level sub-circuit, its second input end inputs the first voltage divider, and its output end is coupled to the second input end of the OR gate circuit; the OR gate circuit, its first input end is coupled to the output end of the second-level sub-circuit, and its output end is coupled to the output end of the anti-error start-up circuit.

[0014] Optionally, the second-stage sub-circuit includes: a second comparator, a second inverter, a second NMOS transistor, a second current source, a second capacitor, a fifth comparator and a second D-type flip-flop, wherein: the first input terminal of the second comparator is the first input terminal of the second-stage sub-circuit, and the second input terminal is the second input terminal of the second-stage sub-circuit; the input terminal of the second inverter is coupled to the output terminal of the second comparator; the gate of the second NMOS transistor is coupled to the output terminal of the second inverter, the drain of the second NMOS transistor is coupled to the second terminal of the second current source, the second input terminal of the fifth comparator and the first terminal of the second capacitor, and the source of the second NMOS transistor is grounded; the first terminal of the second current source is connected to a preset power supply voltage; the second terminal of the second capacitor is grounded; the first input terminal of the fifth comparator inputs a third reference voltage; the clock signal input terminal of the second D-type flip-flop is coupled to the output terminal of the fifth comparator, the D terminal inputs a preset signal, and the Q terminal is coupled to the output terminal of the second-stage sub-circuit.

[0015] Optionally, the anti-misstart circuit also includes: a third-level sub-circuit, a fifth voltage-dividing resistor, and the OR gate circuit also includes a third input terminal; wherein: the fifth voltage-dividing voltage, its first end is coupled to the second end of the fourth voltage-dividing resistor, its second end is grounded, and the voltage of the first end of the fifth voltage-dividing resistor is the second voltage-dividing resistor; the third-level sub-circuit, its first input end is coupled to the second end of the first voltage-dividing resistor, its second input end inputs the second voltage-dividing resistor, and its output end is coupled to the third input terminal of the OR gate circuit.

[0016] Optionally, the third-stage sub-circuit includes: a third comparator, a third inverter, a third NMOS transistor, a third current source, a third capacitor, a sixth comparator and a third D-type flip-flop, wherein: the first input terminal of the third comparator is the first input terminal of the third-stage sub-circuit, and the second input terminal of the third-stage sub-circuit is the second input terminal of the third-stage sub-circuit; the input terminal of the third inverter is coupled to the output terminal of the third comparator; the gate of the third NMOS transistor is coupled to the output terminal of the third inverter, the drain of the third NMOS transistor is coupled to the second terminal of the third current source, the second input terminal of the sixth comparator and the first terminal of the third capacitor, and the source of the third NMOS transistor is grounded; the first terminal of the third current source is connected to a preset power supply voltage; the second terminal of the third capacitor is grounded; the first input terminal of the sixth comparator inputs a fourth reference voltage; the clock signal input terminal of the third D-type flip-flop is coupled to the output terminal of the sixth comparator, the D terminal inputs a preset signal, and the Q terminal is coupled to the output terminal of the third-stage sub-circuit.

[0017] Optionally, the synchronous rectification control circuit also includes: a light load detection circuit, whose input end is coupled to the second end of the sampling circuit, and whose first output end is coupled to the third input end of the start comparison circuit, the fourth input end of the anti-false start circuit, and the second input end of the shutdown comparison circuit; the light load detection circuit is suitable for determining whether to generate a light load signal to the start comparison circuit, the anti-false start circuit and the shutdown comparison circuit according to the switching frequency of the sampling voltage; the start comparison circuit, the anti-false start circuit and the shutdown comparison circuit enter a sleep state after receiving the light load signal.

[0018] Optionally, the light load detection circuit includes: a pre-pulse signal generating circuit, a pulse signal generating circuit and a light load signal generating circuit, wherein: the pre-pulse signal generating circuit, whose input end is coupled to the second end of the sampling circuit, is suitable for generating and outputting a pre-pulse signal when it is detected that the duration of the sampling voltage being continuously at a high level reaches a preset first time length; the pulse signal generating circuit, whose input end is coupled to the input end of the pre-pulse signal generating circuit, is suitable for converting the pre-pulse signal into a pulse signal; the light load signal generating circuit, whose input end is coupled to the output end of the pre-pulse signal generating circuit, is suitable for generating and outputting the light load signal when it is detected that the number of times the pulse signal is received reaches a second preset value.

[0019] Optionally, the pre-pulse signal generating circuit includes: a first Schmitt trigger, a fourth current source, a fourth NMOS transistor, a fifth NMOS transistor, a fourth capacitor, a seventh comparator and a first counter, wherein: the first Schmitt trigger, its input end inputs the sampling voltage, and its output end is coupled to the gate of the fourth NMOS transistor and the control end of the first counter; the fourth NMOS transistor, its drain is coupled to the second end of the fourth current source and the second input end of the seventh comparator, and its source is grounded; the fourth current source, its first end is connected to a preset power supply voltage; the fifth NMOS transistor A MOS transistor, a gate of which is coupled to the output terminal of the seventh comparator, a drain of which is coupled to the second input terminal of the seventh comparator, and a source of which is grounded; a first end of the fourth capacitor is coupled to the second input terminal of the seventh comparator, and a second end of the fourth capacitor is grounded; a first input terminal of the seventh comparator inputs a fifth reference voltage, and an output terminal of the seventh comparator is coupled to the input terminal of the first counter; an output terminal of the first counter is coupled to the output terminal of the pre-pulse signal generating circuit; the pre-pulse signal generating circuit is suitable for outputting the pre-pulse signal when the count value of the first counter reaches a first preset value.

[0020] Optionally, the pulse signal generating circuit includes: a fifth inverter, a first delay circuit and a second NAND gate circuit, wherein: the input end of the fifth inverter is coupled to the input end of the pulse signal generating circuit, and the output end is coupled to the first input end of the second NAND gate circuit and the first end of the first delay circuit; the second end of the first delay circuit is coupled to the second input end of the second NAND gate circuit; and the output end of the second NAND gate circuit is coupled to the output end of the pulse signal generating circuit.

[0021] Optionally, the output terminal of the second NAND gate circuit is coupled to the output terminal of the pulse signal generating circuit. The input terminal of the sixth inverter is the first input terminal of the light-load signal generating circuit, and the output terminal of the sixth inverter is coupled to the input terminal of the second counter. The output terminal of the second counter is coupled to the output terminal of the light-load signal generating circuit. The light-load signal generating circuit is adapted to generate and output the light-load signal when the count value of the second counter reaches a second preset value.

[0022] Optionally, the light load signal generating circuit further includes: a detection trigger sub-circuit, whose input end inputs the sampling voltage, whose control end is coupled to the output end of the pre-pulse signal generating circuit, whose first output end is coupled to the control end of the second counter, and whose second output end is coupled to the output end of the light load signal generating circuit; the detection trigger sub-circuit is suitable for outputting a first trigger signal to the control end of the second counter when it is detected that the sampling voltage is at a low level for a consecutive number of times reaching a third preset value; and is suitable for outputting a second trigger signal when the sampling voltage is at a low level for a consecutive number of times reaching a fourth preset value after detecting that the light load signal is generated, so that the light load signal generating circuit stops generating the light load signal.

[0023] Optionally, the detection trigger sub-circuit includes: a second Schmitt trigger, a seventh inverter, and a third counter; wherein: the second Schmitt trigger, whose input end inputs the sampling voltage, and whose output end is coupled to the input end of the seventh inverter; the seventh inverter, whose output end is coupled to the input end of the third counter; the third counter, whose control end is coupled to the output end of the pre-pulse signal generating circuit, whose first output end is the first output end of the detection trigger sub-circuit, and whose second output end is the second output end of the detection trigger sub-circuit.

[0024] An embodiment of the present invention further provides a switching power supply system, comprising: any one of the above-mentioned synchronous rectification control circuits.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0026] A circuit to prevent erroneous start-up is provided in the synchronous rectification control circuit. This circuit generates a start-up enable signal based on the sampled voltage and outputs it to the start-up comparison circuit. The start-up comparison circuit generates a start-up signal only after receiving the start-up enable signal, effectively preventing the synchronous rectification control circuit from erroneously starting up.

[0027] Furthermore, the synchronous rectification control circuit also includes a light-load detection circuit that determines whether a light-load signal is generated by detecting the switching frequency of the sampled voltage. If a light-load signal is generated, the generated light-load signal is output to the start-up comparison circuit, the false start prevention circuit, and the shutdown comparison circuit to control the start-up comparison circuit, the false start prevention circuit, and the shutdown comparison circuit to enter a dormant state, thereby saving power consumption of the synchronous rectification control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a structural diagram of an existing synchronous rectification control circuit;

[0029] Figure 2 1 is a schematic structural diagram of a synchronous rectification control circuit according to an embodiment of the present invention;

[0030] Figure 3 1 is a schematic structural diagram of an anti-misoperational start-up circuit according to an embodiment of the present invention;

[0031] Figure 4 2 is a schematic structural diagram of another anti-misoperation circuit in an embodiment of the present invention;

[0032] Figure 5 This is a working waveform diagram of an anti-misoperational start circuit in an embodiment of the present invention;

[0033] Figure 6 is a structural diagram of another synchronous rectification control circuit in an embodiment of the present invention;

[0034] Figure 7 is a structural diagram of a light load detection circuit in an embodiment of the present invention;

[0035] Figure 8 This is a working waveform diagram of a light load detection circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0036] Reference Figure 1 In the prior art, a turn-on comparison circuit distinguishes the high plateau waveform and the ringing waveform of the sampled voltage VDET by the difference in area between the two, and then generates a turn-on signal. However, in some special application scenarios, the difference in area between the high plateau waveform and the ringing waveform of the sampled voltage VDET is small, resulting in false turn-on errors.

[0037] In an embodiment of the present invention, a mis-startup prevention circuit is provided in the synchronous rectification control circuit. The mis-startup prevention circuit generates a start-up enable signal based on the sampled voltage and outputs it to the start-up comparison circuit. The start-up comparison circuit generates a start-up signal only after receiving the start-up enable signal, thereby effectively preventing mis-startup of the synchronous rectification control circuit.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Reference Figure 2 , an embodiment of the present invention provides a synchronous rectification control circuit 200. In the embodiment of the present invention, the synchronous rectification control circuit 200 includes: a sampling circuit, a turn-on comparison circuit 201, a turn-off comparison circuit 202, a drive control circuit 203 and an anti-mistaken turn-on circuit 204, wherein:

[0040] A sampling circuit, a first terminal of which is coupled to the first output terminal of the transformer and is adapted to obtain a sampling voltage VDET;

[0041] The anti-false start circuit 204 has a first input terminal coupled to the second terminal of the sampling circuit and is adapted to generate and output a start-up enable signal according to the sampling voltage VDET;

[0042] The start-up comparison circuit 201 has a first input terminal coupled to the second terminal of the sampling circuit, and a second input terminal coupled to the output terminal of the false start prevention circuit 204; and is adapted to generate and output a start signal upon receiving a start enable signal;

[0043] A shutdown comparison circuit 202, whose input terminal is coupled to the second terminal of the sampling circuit, is adapted to generate and output a shutdown signal according to the sampling signal;

[0044] The drive control circuit 203 has a first input terminal coupled to the output terminal of the turn-on comparison circuit 201 and a second input terminal coupled to the output terminal of the turn-off comparison circuit 202. The drive control circuit 203 is adapted to generate a corresponding drive signal according to the turn-on signal and the turn-off signal and output the drive signal to the power switch tube coupled to the first output terminal of the transformer to control the switching state of the power switch tube.

[0045] Reference Figure 3 , a schematic diagram of the structure of an anti-misoperational opening circuit in an embodiment of the present invention is given. Figure 3 Provide explanation.

[0046] In an embodiment of the present invention, the false start prevention circuit 204 may include: a first transmission gate TRAN1 circuit, a second transmission gate TRAN2 circuit, and a first-stage sub-circuit, wherein:

[0047] An input terminal of the first transmission gate TRAN1 circuit is grounded, an output terminal of the first transmission gate TRAN1 circuit is coupled to the second input terminal of the first-stage sub-circuit and the output terminal of the second transmission gate TRAN2 circuit, a first control terminal of the first transmission gate TRAN1 circuit is coupled to the second control terminal of the second transmission gate TRAN2 circuit, and the second control terminal of the first transmission gate TRAN1 circuit is coupled to the first control terminal of the second transmission gate TRAN2 circuit;

[0048] The first reference voltage Vref1 is input to an input terminal of the second transmission gate TRAN2 circuit, an output terminal of the second transmission gate TRAN2 circuit is coupled to the second input terminal of the first-stage sub-circuit and the output terminal of the first transmission gate TRAN1 circuit, a first control terminal of the second transmission gate TRAN2 circuit is coupled to the second control terminal of the first transmission gate TRAN1 circuit, and a second control terminal of the second transmission gate TRAN2 circuit is coupled to the first control terminal of the first transmission gate TRAN1 circuit; an input signal at the first control terminal of the first transmission gate TRAN1 circuit and the second control terminal of the second transmission gate TRAN2 circuit is related to the magnitude between the first reference voltage Vref1 and the sampling voltage VDET;

[0049] The first input terminal of the first-stage sub-circuit can be coupled to the output terminal of the sampling circuit and is suitable for receiving the sampling voltage VDET; the second input terminal of the first-stage sub-circuit can select the input ground potential or the first reference voltage Vref1, and the output terminal of the first-stage sub-circuit is coupled to the output terminal of the anti-false start-up circuit 204.

[0050] In the embodiment of the present invention, the first control terminal of the first transmission gate TRAN1 circuit is terminal C, and the second control terminal of the first transmission gate TRAN1 circuit is terminal C inverse. The first control terminal of the second transmission gate TRAN2 circuit is terminal C, and the second control terminal of the second transmission gate TRAN2 circuit is terminal C inverse.

[0051] In an embodiment of the present invention, the first-stage sub-circuit may include: a first comparator Comp1, a first inverter INV1, a first NMOS transistor MN1, a first current source I1, a first capacitor C1, a fourth comparator Comp4, and a first D flip-flop D1, wherein:

[0052] A first input terminal of the first comparator Comp1 is a first input terminal of the first-stage sub-circuit, a second input terminal of the first comparator Comp1 is a second input terminal of the first-stage sub-circuit, and a first output terminal of the first comparator Comp1 is coupled to an input terminal of the first inverter INV1, a first control terminal of the first transmission gate TRAN1 circuit, and a second control terminal of the second transmission gate TRAN2 circuit;

[0053] The output terminal of the first inverter INV1 is coupled to the second control terminal of the first transmission gate TRAN1 circuit, the first control terminal of the second transmission gate TRAN2 circuit, and the gate of the first NMOS transistor MN1;

[0054] The drain of the first NMOS transistor MN1 is coupled to the second end of the first current source I1, the second input end of the fourth comparator Comp4, and the first end of the first capacitor C1; the source of the first NMOS transistor MN1 is coupled to the second end of the first capacitor C1 and ground;

[0055] The first capacitor C1 is coupled between the drain and source of the first NMOS transistor MN1; a first terminal of the first current source I1 inputs a preset power supply voltage;

[0056] The first input terminal of the fourth comparator Comp4 inputs the second reference voltage Vref2, and the output terminal of the fourth comparator Comp4 generates a first start-up enable sub-signal;

[0057] The clock signal input terminal of the first D flip-flop D1 is coupled to the output terminal of the fourth comparator Comp4 , the D terminal of the first D flip-flop D1 inputs a preset signal 1 ′ b1 , and the Q terminal of the first D flip-flop D1 is coupled to the output terminal of the first stage sub-circuit.

[0058] In a specific implementation, the anti-incorrection start-up circuit 204 may also be composed of multiple sub-circuits. The anti-incorrection start-up circuit 204 may also include a second input terminal and a third input terminal. The second input terminal of the anti-incorrection start-up circuit 204 may be coupled to the first output terminal of the transformer, and the third input terminal of the anti-incorrection start-up circuit 204 may be coupled to the second output terminal of the transformer. The anti-incorrection start-up circuit 204 may also determine to generate a start-up enable signal based on the output voltages of the first output terminal of the transformer and the second output terminal of the transformer.

[0059] Reference Figure 4 , a structural schematic diagram of another anti-misoperational start-up circuit in an embodiment of the present invention is given.

[0060] In an embodiment of the present invention, the anti-incorrect start-up circuit 204 may further include a second-stage sub-circuit, a first voltage-dividing resistor R11, a second voltage-dividing resistor R12, a third voltage-dividing resistor R13, a fourth voltage-dividing resistor R14, and an OR gate circuit, wherein:

[0061] The first input terminal of the second-stage sub-circuit is coupled to the second terminal of the first voltage-dividing resistor R11, the second input terminal of the second-stage sub-circuit inputs the first divided voltage, and the output terminal of the second-stage sub-circuit is coupled to the second input terminal of the OR gate circuit;

[0062] A first voltage-dividing resistor R11 and a second voltage-dividing resistor R12 form a voltage-dividing network; a first end of the first voltage-dividing resistor R11 is coupled to a first end of the sampling circuit, and a second end of the first voltage-dividing resistor R11 is coupled to a first end of the second voltage-dividing resistor R12. A second end of the second voltage-dividing resistor R12 is grounded;

[0063] A third voltage-dividing resistor R13 and a fourth voltage-dividing resistor R14 form a voltage-dividing network; a first end of the third voltage-dividing resistor R13 is coupled to the third input end of the false start prevention circuit 204, and a second end of the third voltage-dividing resistor R13 is coupled to the first end of the fourth voltage-dividing resistor R14; a second end of the fourth voltage-dividing resistor R14 is grounded; and a voltage at a second end of the third voltage-dividing resistor R13 is the first divided voltage.

[0064] The OR gate circuit includes two input terminals. A first output terminal of the OR gate circuit is coupled to the output terminal of the second-stage sub-circuit. An output terminal of the OR gate circuit is coupled to the output terminal of the false start prevention circuit 204 .

[0065] In an embodiment of the present invention, the second-stage sub-circuit may include: a second comparator Comp2, a second inverter INV2, a second NMOS transistor MN2, a second current source I2, a second capacitor C2, a fifth comparator Comp5, and a second D flip-flop D2, wherein:

[0066] The first input terminal of the second comparator Comp2 is the first input terminal of the second-stage sub-circuit, the second input terminal of the second comparator Comp2 is the second input terminal of the second-stage sub-circuit, and the output terminal of the second comparator Comp2 is coupled to the input terminal of the second inverter INV2;

[0067] An output terminal of the second inverter INV2 is coupled to a gate of the second NMOS transistor MN2;

[0068] The drain of the second NMOS transistor MN2 is coupled to the second end of the second current source I2, the second input end of the fifth comparator Comp5, and the first end of the second capacitor C2; the source of the second NMOS transistor MN2 is coupled to the second end of the second capacitor C2 and ground;

[0069] The second capacitor C2 is coupled between the drain and source of the second NMOS transistor MN2; the first end of the second current source I2 inputs a preset power supply voltage;

[0070] The first input terminal of the fifth comparator Comp5 inputs the third reference voltage Vref3, and the output terminal of the fifth comparator Comp5 generates a second start-up enable sub-signal;

[0071] The clock signal input terminal of the second D flip-flop D2 is coupled to the output terminal of the fifth comparator Comp5, the D terminal of the second D flip-flop D2 inputs a preset signal, and the Q terminal of the second D flip-flop D2 is coupled to the output terminal of the second stage sub-circuit.

[0072] In a specific implementation, the anti-misoperational start-up circuit 204 may further include a third-stage sub-circuit, a fifth voltage-dividing resistor R15, and the OR gate circuit may further include a third input terminal, wherein:

[0073] The first input terminal of the third-stage sub-circuit is coupled to the second terminal of the first voltage-dividing resistor R11, the second input terminal of the third-stage sub-circuit inputs the second divided voltage, and the output terminal of the third-stage sub-circuit is coupled to the third input terminal of the OR gate circuit OR3;

[0074] The OR gate circuit OR1 is a three-input OR gate circuit suitable for performing an OR operation on the outputs of the first-level sub-circuit, the second-level sub-circuit and the third-level sub-circuit, and generating and outputting a start-up enable signal according to the obtained OR operation result.

[0075] The third voltage-divider resistor R13, the fourth voltage-divider resistor R14, and the fifth voltage-divider resistor R15 form a voltage-divider network. The first end of the fifth voltage-divider resistor R15 is coupled to the second end of the fourth voltage-divider resistor R14, and the second end of the fifth voltage-divider resistor R15 is grounded. The voltage at the first end of the fifth voltage-divider resistor R15 is the second divided voltage.

[0076] In an embodiment of the present invention, the first end of the third voltage-dividing resistor R13 is input with the output voltage of the transformer, the second end of the third voltage-dividing resistor R13 is coupled to the first end of the fourth voltage-dividing resistor R14; the second end of the fourth voltage-dividing resistor R14 is coupled to the first end of the fifth voltage-dividing resistor R15; and the second end of the fifth voltage-dividing resistor R15 is grounded.

[0077] In an embodiment of the present invention, the third-stage sub-circuit may include: a third comparator Comp3, a third inverter INV3, a third NMOS transistor MN3, a third current source I3, a third capacitor C3, a sixth comparator Comp6, and a third D flip-flop D3, wherein:

[0078] The first input terminal of the third comparator Comp3 is the first input terminal of the third-stage sub-circuit, the second input terminal of the third comparator Comp3 is the second input terminal of the third-stage sub-circuit, and the first output terminal of the third comparator Comp3 is coupled to the input terminal of the third inverter INV3;

[0079] An output terminal of the third inverter INV3 is coupled to a gate of the third NMOS transistor MN3;

[0080] The drain of the third NMOS transistor MN3 is coupled to the second end of the third current source I3, the second input end of the sixth comparator Comp6, and the first end of the third capacitor C3; the source of the third NMOS transistor MN3 is coupled to the second end of the third capacitor C3 and ground;

[0081] The third capacitor C3 is coupled between the drain and source of the third NMOS transistor MN3; a first terminal of the third current source I3 inputs a preset power supply voltage;

[0082] The first input terminal of the sixth comparator Comp6 inputs the fourth reference voltage Vref4, and the output terminal of the sixth comparator Comp6 generates a second start-up enable sub-signal;

[0083] The clock signal input terminal of the third D flip-flop D3 is coupled to the output terminal of the sixth comparator Comp6 , the D terminal of the third D flip-flop D3 inputs a preset signal, and the Q terminal of the third D flip-flop D3 is coupled to the output terminal of the third stage sub-circuit.

[0084] In a specific implementation, the anti-incorrect-start circuit 204 may include only the first-level subcircuit, or only the first-level and second-level subcircuits, or simultaneously include the first-level, second-level, and third-level subcircuits. The anti-incorrect-start circuit 204 may also include a fourth-level subcircuit or more subcircuits. The circuit structures of the fourth-level subcircuit or more subcircuits may refer to the second-level subcircuit or third-level subcircuit described above.

[0085] In the embodiments of the present invention, unless otherwise specified, the first input terminal of a comparator is the positive input terminal of the comparator, and the second input terminal of a comparator is the negative input terminal of the comparator. For example, the first input terminal of the first comparator Comp1 is the "+" terminal of the first comparator Comp1, and the second input terminal of the first comparator Comp1 is the "-" terminal of the first comparator Comp1.

[0086] The following combination Figure 4 , the working principle of the anti-misoperational start circuit 204 provided in the above embodiment of the present invention is described.

[0087] The first input of the first comparator Comp1 receives the sampling voltage VDET, and the second input of the first comparator Comp1 is gated to ground or the first reference voltage Vref1. When the sampling voltage VDET is greater than the first reference voltage Vref1, the gate of the first NMOS transistor MN1 is at a low level. At this point, the second input of the first comparator Comp1 is gated to ground, and the first current source I1 charges the first capacitor C1. When the voltage at the first terminal of the first capacitor C1 reaches the second reference voltage Vref2, the output of the fourth comparator Comp4 outputs a low level, and the first D-type flip-flop D1 outputs a high level. At this point, the enable signal is at a high level.

[0088] During the charging process of the first capacitor C1, if the sampling voltage VDET is less than 0, the gate of the first NMOS transistor MN1 is at a high potential, and the charge accumulated on the first capacitor C1 is cleared. The charge needs to be accumulated again, that is, the first current source I1 is used to charge the first capacitor C1 again.

[0089] The first input terminal of the second comparator Comp2 receives a resistor-divided voltage n3*SW, where SW is the output voltage of the first output terminal of the transformer. The second input terminal of the second comparator Comp2 receives a resistor-divided voltage n1*Vout, where Vout is the output voltage of the second output terminal of the transformer. When n3*SW>n1*Vout, the gate of the second NMOS transistor MN2 is at a low potential, and the second current source I2 charges the second capacitor C2. When the voltage at the first terminal of the second capacitor C2 reaches the third reference voltage Vref3, the third D-type flip-flop D3 outputs a high level, and the enable signal is now at a high level.

[0090] During the charging process of the second capacitor C2, if n3*SW<n1*Vout, the gate of the second NMOS transistor MN2 is at a high potential, the charge accumulated on the second capacitor C2 is cleared, and charge accumulation needs to be performed again, that is, the second current source I2 is used to charge the second capacitor C2 again.

[0091] The first input terminal of the third comparator Comp3 receives the resistor-divided voltage n3*SW, and the second input terminal of the third comparator Comp3 receives the resistor-divided voltage n2*Vout. When n3*SW>n2*Vout, the gate of the third NMOS transistor MN3 is at a low potential, and the third current source I3 charges the third capacitor C3. When the voltage at the first terminal of the third capacitor C3 reaches the fourth reference voltage Vref4, the fourth D-type flip-flop D4 outputs a high level, and the enable signal is now at a high level.

[0092] During the charging process of the third capacitor C3, if n3*SW<n2*Vout, the gate of the third NMOS transistor MN3 is at a high potential, and the charge accumulated on the third capacitor C3 is cleared. Charge accumulation needs to be performed again, that is, the third current source I3 is used to charge the third capacitor C3 again.

[0093] Depend on Figure 4 It can be seen that when any one of the first D flip-flop D1 , the second D flip-flop D2 and the third D flip-flop D3 is at a high level, the OR gate circuit outputs a high level, thereby generating a turn-on enable signal.

[0094] Reference Figure 5 , a working waveform diagram of an anti-misoperational start-up circuit in an embodiment of the present invention is given.

[0095] Figure 5At time t0, SW> the first reference voltage Vref1, and the minimum off-time toffmin1 begins to be measured. At time t1, the sampled voltage VDET> the first reference voltage Vref1 for a certain period of time, and the output terminal of the fourth comparator Comp4 outputs a high level MOS_EN_ON1. At time t2, SW> (n1 / n3)*Vout, and the minimum off-time toffmin2 begins to be measured. At time t3, SW> (n2 / n3)*Vout, and the minimum off-time toffmin3 begins to be measured. At time t4, SW> (n2 / n3)*Vout for a certain period of time, and the output terminal of the sixth comparator Comp6 outputs a high level MOS_EN_ON3. At time t5, SW> (n1 / n3)*Vout for a certain period of time, and the output terminal of the fifth comparator Comp5 outputs a high level MOS_EN_ON2. At time t6, since any of MOS_EN_ON1, MOS_EN_ON2, and MOS_EN_ON3 are high, the anti-false start circuit 204 generates a start enable signal.

[0096] In a specific implementation, the synchronous rectification control circuit 200 may further include a light-load detection circuit.

[0097] In an embodiment of the present invention, the input terminal of the light load detection circuit can be coupled to the second terminal of the sampling circuit, and the first output terminal of the light load detection circuit can be coupled to the third input terminal of the start-up comparison circuit 201, the fourth input terminal of the anti-false start-up circuit 204, and the second input terminal of the shutdown comparison circuit 202. The light load detection circuit can obtain the switching frequency of the sampled voltage VDET and determine whether to generate a light load signal based on the switching frequency of the sampled voltage VDET. When the light load detection circuit outputs a light load signal, the start-up comparison circuit 201, the anti-false start-up circuit 204, and the shutdown comparison circuit 202 enter a dormant state after receiving the light load signal, thereby reducing the power consumption of the synchronous rectification control circuit 200.

[0098] Reference Figure 6 , a structural diagram of another synchronous rectification control circuit 200 in an embodiment of the present invention is given. Figure 2 compared to, Figure 6 The synchronous rectification control circuit 200 further includes a light load detection circuit 205. Figure 6 Provide explanation.

[0099] In a specific implementation, the light load detection circuit 205 may include a pre-pulse signal generating circuit, a pulse signal generating circuit, and a light load signal generating circuit, wherein:

[0100] The pre-pulse signal generating circuit inputs a sampling voltage VDET at its input terminal, and its output terminal is coupled to the control terminal of the pulse signal generating circuit. The pre-pulse signal generating circuit is adapted to generate and output a pre-pulse signal when it is detected that the sampling voltage VDET remains at a high level for a first predetermined time period.

[0101] The input terminal of the pulse signal generating circuit inputs the pre-pulse signal, and the output terminal is coupled to the first input terminal of the light-load signal generating circuit, and is suitable for generating a pulse signal according to the pre-pulse signal and outputting the pulse signal to the first input terminal of the light-load signal generating circuit;

[0102] The output end of the light-load signal generating circuit is coupled to the output end of the light-load detecting circuit, and is adapted to generate and output a light-load signal when it is detected that the number of continuously received pulse signals reaches a second preset value.

[0103] Reference Figure 7 , a structural schematic diagram of a light load detection circuit in an embodiment of the present invention is given.

[0104] In an embodiment of the present invention, the pre-pulse signal generating circuit may include a first Schmitt trigger, a fourth current source I4, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a fourth capacitor C4, a seventh comparator Comp7, and a first counter, wherein:

[0105] The input terminal of the first Schmitt trigger is input with the sampling voltage VDET, and the output terminal of the first Schmitt trigger is coupled with the gate of the fourth NMOS transistor MN4 and the control terminal of the first counter;

[0106] The drain of the fourth NMOS transistor MN4 is coupled to the second terminal of the fourth current source I4 and the second input terminal of the seventh comparator Comp7. The source of the fourth NMOS transistor MN4 is grounded. The second terminal of the fourth current source I4 is connected to a preset power supply voltage.

[0107] A drain of the fifth NMOS transistor MN5 is coupled to the second input terminal of the seventh comparator Comp7, a gate of the fifth NMOS transistor MN5 is coupled to the output terminal of the seventh comparator Comp7, and a source of the fifth NMOS transistor MN5 is grounded;

[0108] A first terminal of the fourth capacitor C4 is coupled to the second input terminal of the seventh comparator Comp7, and a second terminal of the fourth capacitor C4 is grounded;

[0109] A first input terminal of the seventh comparator Comp7 is input with the fifth reference voltage Vref5, and an output terminal of the seventh comparator Comp7 is coupled to the gate of the fifth NMOS transistor MN5 and the input terminal of the first counter;

[0110] The control end of the first counter is coupled to the output end of the first Schmitt trigger, and the output end of the first counter is coupled to the control end of the pulse signal generating circuit.

[0111] In an embodiment of the present invention, the count value of the first counter is used to represent the duration that the sampling voltage VDET remains at a high level. When the count value of the first counter reaches a first preset value, the duration corresponding to the first preset value is the first duration, at which time the pre-pulse signal generating circuit generates a pre-pulse signal.

[0112] like Figure 4 As shown, when the sampling voltage VDET remains at a high level, the sampling voltage VDET is inverted by the first Schmitt trigger, and the gate of the fourth NMOS transistor MN4 is at a low level, so the fourth NMOS transistor MN4 is disconnected. The fourth current source I4 charges the fourth capacitor C4. When the voltage at the first terminal of the fourth capacitor C4 reaches the fifth reference voltage Vref5, the seventh comparator Comp7 outputs a high level. At this time, the fifth NMOS transistor MN5 turns on, the charge accumulated on the fourth capacitor C4 is released, and the output of the seventh comparator Comp7 switches from a high level to a low level. The first counter can record the number of flips of the seventh comparator Comp7. Each time the seventh comparator Comp7 flips, the count value of the first counter increases by 1. When the count value of the first counter reaches a first preset value, the pre-pulse signal generating circuit generates a pre-pulse signal.

[0113] In an embodiment of the present invention, the first counter may include a fourth inverter INV4, a fourth D flip-flop D4, a fifth D flip-flop D5, a sixth D flip-flop D6, and a first NAND gate circuit NAND1, wherein:

[0114] An input terminal of the fourth inverter INV4 is a control terminal of the first counter, and an output terminal of the fourth inverter INV4 is coupled to reset terminals of the fourth D flip-flop D4, the fifth D flip-flop D5, and the sixth D flip-flop D6 respectively;

[0115] A clock signal input terminal of the fourth D flip-flop D4 is an input terminal of the first counter and is coupled to the output terminal of the seventh comparator Comp7; a D terminal of the fourth D flip-flop D4 is coupled to a Q NOT terminal of the fourth D flip-flop D4; and a Q terminal of the fourth D flip-flop D4 is coupled to a clock signal input terminal of the fifth D flip-flop D5 and a first input terminal of the first NAND gate circuit NAND1;

[0116] The D terminal of the fifth D flip-flop D5 is coupled to the Q NOT terminal of the fifth D flip-flop D5 , and the Q terminal of the fifth D flip-flop D5 is coupled to the clock signal input terminal of the sixth D flip-flop D6 and the second input terminal of the first NAND gate circuit NAND1 ;

[0117] The D terminal of the sixth D flip-flop D6 is coupled to the Q NOT terminal of the sixth D flip-flop D6 , and the Q terminal of the sixth D flip-flop D6 is coupled to the third input terminal of the first NAND gate circuit NAND1 ;

[0118] An output terminal of the third NAND gate circuit NAND3 is coupled to an output terminal of the first counter. The third NAND gate circuit NAND3 performs a NAND operation on the Q-terminal output of the fourth D flip-flop D4, the Q-terminal output of the fifth D flip-flop D5, and the Q-terminal output of the sixth D flip-flop D6. When the Q-terminal output of the fourth D flip-flop D4, the Q-terminal output of the fifth D flip-flop D5, and the Q-terminal output of the sixth D flip-flop D6 are all 1, the pre-pulse signal generating circuit generates a pre-pulse signal Pre_pulse.

[0119] It should be noted that the structure of the first counter described above corresponds to an application scenario in which the first preset value of the first counter is 7. When the Q-end output of the fourth D flip-flop D4, the Q-end output of the fifth D flip-flop D5, and the Q-end output of the sixth D flip-flop D6 of the first counter are all 1, it means that the count value of the first counter reaches 7. At this time, the pre-pulse signal generating circuit generates the pre-pulse signal Pre_pulse.

[0120] In the embodiment of the present invention, the active state of the pre-pulse signal Pre_pulse is a low level.

[0121] In practical applications, the first counter may also have other structures. For example, when the count value of the first counter is 3, it is determined that the count value of the first counter reaches the first preset value. At this time, the first counter may only include the fourth D flip-flop D4 and the fifth D flip-flop D5.

[0122] The first preset value corresponding to the first counter may also be other values, such as 3 or 15, or other values.

[0123] In an embodiment of the present invention, the pulse signal generating circuit may include: a fifth inverter INV5, a first delay circuit, and a second NAND gate circuit NAND2, wherein:

[0124] The input end of the fifth inverter INV5 is the input end of the pulse signal generating circuit, and the output end of the fifth inverter INV5 is coupled to the first input end of the second NAND gate circuit NAND2 and the first end of the first delay circuit;

[0125] The second terminal of the first delay circuit is coupled to the second input terminal of the second NAND gate circuit NAND2;

[0126] The output end of the second NAND gate circuit NAND2 is the output end of the pulse signal generating circuit.

[0127] In an embodiment of the present invention, the light-load signal generating circuit may include a sixth inverter INV6 and a second counter, wherein:

[0128] An input terminal of the sixth inverter INV6 is a first input terminal of the light-load signal generating circuit, and an output terminal of the sixth inverter INV6 is coupled to an input terminal of the second counter;

[0129] When the second counter detects that the pulse signal of the second preset value is continuously received, the second counter generates a light load signal and outputs it through the output terminal.

[0130] The second counter may include a seventh D flip-flop D7, an eighth D flip-flop D8, and a third NAND gate circuit NAND3, wherein:

[0131] A clock signal input terminal of the seventh D flip-flop D7 is coupled to the input terminal of the second counter, a D terminal of the seventh D flip-flop D7 is coupled to a Q NOT terminal of the seventh D flip-flop D7, and a Q terminal of the seventh D flip-flop D7 is coupled to the clock signal input terminal of the eighth D flip-flop D8 and the first input terminal of the third NAND gate circuit NAND3;

[0132] The D terminal of the eighth D flip-flop D8 is coupled to the Q NOT terminal of the eighth D flip-flop D8 , and the Q terminal of the eighth D flip-flop D8 is coupled to the second input terminal of the third NAND gate circuit NAND3 ;

[0133] An output terminal of the third NAND gate circuit NAND3 is coupled to an output terminal of the second counter.

[0134] It should be noted that the aforementioned structure of the second counter corresponds to an application scenario in which the second preset value of the second counter is 3. When the Q-terminal output of the seventh D flip-flop D7 and the Q-terminal output of the eighth D flip-flop D8 are both 1, it means that the count value of the second counter reaches 3. At this time, the light-load signal generating circuit generates and outputs a light-load signal.

[0135] It is understandable that if the second preset value is other values, the structure of the corresponding second counter can be determined according to the second preset value, and is not limited to the structure of the second counter provided in the above embodiment of the present invention.

[0136] In a specific implementation, the light-load signal generating circuit may further include a detection trigger sub-circuit, wherein the input end of the detection trigger sub-circuit inputs the sampling voltage VDET, the control end is coupled to the output end of the pre-pulse signal generating circuit, and the first output end of the detection trigger sub-circuit is coupled to the control end of the second counter, and is suitable for outputting a first trigger signal to the control end of the second counter when the number of consecutive times that the sampling voltage VDET is detected to be low reaches a third preset value.

[0137] In an embodiment of the present invention, the detection trigger sub-circuit can also output a second trigger signal after detecting the generation of a light load signal, if the sampling voltage VDET is at a low level for a consecutive number of times reaching a fourth preset value, so that the light load signal generating circuit stops generating the light load signal, that is, controls the synchronous rectification circuit to exit the light load mode.

[0138] In an embodiment of the present invention, the detection trigger sub-circuit may include: a second Schmitt trigger, a seventh inverter INV7, and a third counter, wherein:

[0139] The sampling voltage VDET is input to the input terminal of the second Schmitt trigger, and the output terminal of the second Schmitt trigger is coupled to the input terminal of the seventh inverter INV7;

[0140] An output terminal of the seventh inverter INV7 is coupled to an input terminal of the third counter;

[0141] The control end of the third counter is coupled to the output end of the pre-pulse signal generating circuit, the first output end of the third counter is coupled to the control end of the second counter, and the second output end of the third counter is coupled to the output end of the light-load signal generating circuit.

[0142] In an embodiment of the present invention, when the count value of the third counter reaches a third preset value, a first trigger signal is output to the control end of the second counter; when the generation of a light load signal is detected, if the count value of the third counter reaches a fourth preset value, a second trigger signal is output to the output end of the light load signal generating circuit.

[0143] In an embodiment of the present invention, the third counter may include: a ninth D flip-flop D9, a tenth D flip-flop D10, an eleventh D flip-flop D11, a twelfth D flip-flop D12, a thirteenth D flip-flop D13, a fourteenth D flip-flop D14, a fourth NAND gate circuit NAND4, a fifth NAND gate circuit NAND5, and an eighth inverter INV8, wherein:

[0144] A clock signal input terminal of the ninth D flip-flop D9 is coupled to the input terminal of the third counter, a D terminal of the ninth D flip-flop D9 is coupled to the Q NOT terminal of the ninth D flip-flop D9, and a Q terminal of the ninth D flip-flop D9 is coupled to the clock signal input terminal of the tenth D flip-flop D10 and the first input terminal of the fourth NAND gate circuit NAND4;

[0145] The D terminal of the tenth D flip-flop D10 is coupled to the Q non-terminal of the tenth D flip-flop D10 , and the Q terminal of the tenth D flip-flop D10 is coupled to the clock signal input terminal of the eleventh D flip-flop D11 ;

[0146] A D terminal of the eleventh D flip-flop D11 is coupled to a Q NOT terminal of the eleventh D flip-flop D11, a second input terminal of the fourth NAND gate circuit NAND4, and a first input terminal of the fifth NAND gate circuit NAND5, and a Q terminal of the eleventh D flip-flop D11 is coupled to a clock signal input terminal of the twelfth D flip-flop D12;

[0147] The D terminal of the twelfth D flip-flop D12 is coupled to the Q non-terminal of the twelfth D flip-flop D12 , and the Q terminal of the twelfth D flip-flop D12 is coupled to the second input terminal of the fifth NAND gate circuit NAND5 ;

[0148] A clock signal input terminal of the thirteenth D flip-flop D13 is coupled to the output terminal of the fourth NAND gate circuit NAND4, a D terminal of the thirteenth D flip-flop D13 inputs a preset signal, a Q terminal of the thirteenth D flip-flop D13 is coupled to the input terminal of the eighth inverter INV8, and an output terminal of the eighth inverter INV8 is coupled to the first output terminal of the third counter;

[0149] A clock signal input terminal of the fourteenth D flip-flop D14 is coupled to the output terminal of the third NAND gate circuit NAND3, a preset signal is input to the D terminal of the fourteenth D flip-flop D14, a reset terminal of the fourteenth D flip-flop D14 is coupled to the output terminal of the fifth NAND gate circuit NAND5, and a Q terminal of the fourteenth D flip-flop D14 is coupled to the output terminal of the light-load detection circuit.

[0150] In a specific implementation, the detection trigger sub-circuit may further include a NOR gate circuit NOR1. A first input terminal of the NOR gate circuit NOR1 is coupled to an output terminal of the second NAND gate circuit NAND2, a second input terminal of the NOR gate circuit NOR2 is coupled to an output terminal of the eighth inverter, and an output terminal of the NOR gate circuit NOR2 is coupled to an input terminal of the sixth inverter INV6.

[0151] It should be noted that the structure of the third counter described above corresponds to an application scenario where the third preset value is 5 and the fourth preset value is 12. If the third preset value and / or the fourth preset value is other values, the structure of the third counter can be adjusted accordingly.

[0152] Reference Figure 8 , gives a working waveform diagram of a light load detection circuit in an embodiment of the present invention.

[0153] Figure 8In the embodiment, at time t0~t1, the time tdelay when the sampling voltage VDET is high exceeds the first preset time pre_time, and a valid pre-pulse signal Pre_pulse is generated; at time t1~t2, three pre-pulse signals Pre_pulse are accumulated continuously, and the number of times T when the sampling voltage VDET is detected to be low at time t1~t2 is less than 5 times, and the light load detection circuit generates a high-level light load signal LL_MODE.

[0154] At time t2 to t3, if the sampling voltage VDET is detected to be low for a continuous cumulative number of times T>12 times, the light load mode is exited and the light load detection circuit stops generating the light load signal.

[0155] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium, which may include: ROM, RAM, disk or CD, etc.

[0156] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A synchronous rectification control circuit, characterized in that: include: Sampling circuit, turn-on comparison circuit, turn-off comparison circuit, drive control circuit and anti-misoperational start circuit, wherein: The sampling circuit has a first terminal coupled to the first output terminal of the transformer and is adapted to obtain a sampled voltage; The anti-mistaken start circuit has a first input terminal coupled to the second terminal of the sampling circuit, and is adapted to generate and output a start enable signal according to the sampling voltage; The anti-false start-up circuit includes: a first transmission gate circuit, a second transmission gate circuit, and a first-stage sub-circuit, wherein: the first transmission gate circuit has an input terminal connected to ground, an output terminal coupled to the second input terminal of the first-stage sub-circuit and the output terminal of the second transmission gate circuit, a first control terminal coupled to the second control terminal of the second transmission gate circuit, and a second control terminal coupled to the first control terminal of the second transmission gate circuit; the second transmission gate circuit has an input terminal inputted with a first reference voltage, and an output terminal coupled to the second input terminal of the first-stage sub-circuit; a first control signal at the first control terminal of the first transmission gate circuit and a second control signal at the second control terminal of the first transmission gate circuit are determined by the magnitude relationship between the first reference voltage and the sampling voltage; the first input terminal of the first-stage sub-circuit is coupled to the first input terminal of the anti-false start-up circuit, and the output terminal of the first-stage sub-circuit is coupled to the output terminal of the anti-false start-up circuit; The start-up comparison circuit has a first input terminal coupled to the second terminal of the sampling circuit, and a second input terminal coupled to the output terminal of the false start prevention circuit; and is adapted to generate and output a start signal upon receiving the start-up enable signal; The shutdown comparison circuit has an input terminal coupled to the second terminal of the sampling circuit and is adapted to generate and output a shutdown signal according to the sampled voltage; The drive control circuit has a first input terminal coupled to the output terminal of the turn-on comparison circuit and a second input terminal coupled to the output terminal of the turn-off comparison circuit; and is adapted to generate a corresponding drive signal according to the turn-on signal and the turn-off signal and output the drive signal to the power switch tube coupled to the first output terminal of the transformer to control the switching state of the power switch tube.

2. The synchronous rectification control circuit according to claim 1, wherein: The first-stage sub-circuit includes: a first comparator, a first inverter, a first NMOS transistor, a first current source, a first capacitor, a fourth comparator, and a first D-flip-flop, wherein: The first comparator has a first input terminal that is the first input terminal of the first-stage sub-circuit, a second input terminal that is the second input terminal of the first-stage sub-circuit, and an output terminal that is coupled to the input terminal of the first inverter, the first control terminal of the first transmission gate circuit, and the second control terminal of the second transmission gate circuit; The first inverter has an output terminal coupled to the gate of the first NMOS transistor, the second control terminal of the first transmission gate circuit, and the first control terminal of the second transmission gate circuit; The first NMOS transistor has a drain coupled to the second end of the first current source, the first end of the first capacitor, and the second input end of the fourth comparator; and a source grounded; The first capacitor has a second end grounded; The first current source has a first terminal connected to a preset power supply voltage; The fourth comparator has a first input terminal inputting a second reference voltage and an output terminal generating a first start-up enable sub-signal; The clock signal input terminal of the first D flip-flop is coupled to the output terminal of the fourth comparator, the D terminal inputs a preset signal, and the Q terminal is coupled to the output terminal of the first-stage sub-circuit; the first turn-on enable sub-signal is output via the Q terminal to obtain the turn-on enable signal.

3. The synchronous rectification control circuit according to claim 1, wherein: The anti-misoperational start-up circuit has a second input terminal coupled to the first output terminal of the transformer, and a third input terminal coupled to the second output terminal of the transformer, and is suitable for determining and generating the start-up enable signal based on the output voltage of the first output terminal of the transformer and the output voltage of the second output terminal of the transformer.

4. The synchronous rectification control circuit according to claim 3, wherein: The anti-misoperational start-up circuit includes: a second-stage sub-circuit, a first voltage-dividing resistor, a second voltage-dividing resistor, a third voltage-dividing resistor, a fourth voltage-dividing resistor, and an OR gate circuit, wherein: The first voltage-dividing resistor has a first end coupled to the second input end of the anti-false start circuit, and a second end coupled to the first input end of the second-stage sub-circuit and the first end of the second voltage-dividing resistor; The second voltage-dividing resistor has a second end grounded; The third voltage-dividing resistor has a first end coupled to the third input end of the anti-false start circuit, and a second end coupled to the first end of the fourth voltage-dividing resistor; the voltage at the second end of the third voltage-dividing resistor is the first divided voltage; The fourth voltage-dividing resistor has a second end grounded; The second-stage sub-circuit has a second input terminal inputting the first divided voltage, and an output terminal coupled to the second input terminal of the OR gate circuit; The OR gate circuit has a first input terminal coupled to the output terminal of the second-stage sub-circuit, and an output terminal coupled to the output terminal of the anti-misoperational start-up circuit.

5. The synchronous rectification control circuit according to claim 4, wherein: The second-stage sub-circuit includes: a second comparator, a second inverter, a second NMOS transistor, a second current source, a second capacitor, a fifth comparator, and a second D flip-flop, wherein: The second comparator has a first input terminal that is the first input terminal of the second-stage sub-circuit and a second input terminal that is the second input terminal of the second-stage sub-circuit; the second inverter, an input terminal of which is coupled to the output terminal of the second comparator; The second NMOS transistor has a gate coupled to the output terminal of the second inverter, a drain coupled to the second terminal of the second current source, the second input terminal of the fifth comparator, and the first terminal of the second capacitor, and a source grounded; The second current source has a first terminal connected to a preset power supply voltage; The second capacitor has a second end grounded; The fifth comparator has a first input terminal inputting a third reference voltage; The second D flip-flop has a clock signal input terminal coupled to the output terminal of the fifth comparator, a D terminal inputting a preset signal, and a Q terminal coupled to the output terminal of the second-stage sub-circuit.

6. The synchronous rectification control circuit according to claim 4, wherein: The anti-misoperational start-up circuit further includes: a third-level subcircuit, a fifth voltage-dividing resistor, and the OR gate circuit further includes a third input terminal; wherein: The fifth voltage-dividing resistor has a first end coupled to the second end of the fourth voltage-dividing resistor, a second end grounded, and a voltage at the first end of the fifth voltage-dividing resistor is the second divided voltage; The third-stage sub-circuit has a first input terminal coupled to the second terminal of the first voltage-dividing resistor, a second input terminal inputting the second divided voltage, and an output terminal coupled to the third input terminal of the OR gate circuit.

7. The synchronous rectification control circuit according to claim 6, wherein: The third-stage sub-circuit includes: a third comparator, a third inverter, a third NMOS transistor, a third current source, a third capacitor, a sixth comparator, and a third D flip-flop, wherein: The third comparator has a first input terminal that is the first input terminal of the third-stage sub-circuit and a second input terminal that is the second input terminal of the third-stage sub-circuit; the third inverter, an input terminal of which is coupled to the output terminal of the third comparator; The third NMOS transistor has a gate coupled to the output terminal of the third inverter, a drain coupled to the second terminal of the third current source, the second input terminal of the sixth comparator, and the first terminal of the third capacitor, and a source grounded; The third current source has a first terminal connected to a preset power supply voltage; The second end of the third capacitor is grounded; The sixth comparator has a first input terminal inputting a fourth reference voltage; The clock signal input terminal of the third D flip-flop is coupled to the output terminal of the sixth comparator, the D terminal thereof inputs a preset signal, and the Q terminal thereof is coupled to the output terminal of the third-stage sub-circuit.

8. The synchronous rectification control circuit according to claim 1, wherein: Also includes: a light-load detection circuit, having an input terminal coupled to the second terminal of the sampling circuit and a first output terminal coupled to the third input terminal of the turn-on comparison circuit, the fourth input terminal of the false-start prevention circuit, and the second input terminal of the turn-off comparison circuit; the light-load detection circuit being adapted to determine whether to generate a light-load signal to the turn-on comparison circuit, the false-start prevention circuit, and the turn-off comparison circuit based on a switching frequency of the sampled voltage; The start-up comparison circuit, the anti-mistaken start-up circuit, and the shutdown comparison circuit enter a dormant state after receiving the light-load signal.

9. The synchronous rectification control circuit according to claim 8, wherein: The light load detection circuit includes: a pre-pulse signal generating circuit, a pulse signal generating circuit and a light load signal generating circuit, wherein: The pre-pulse signal generating circuit has an input terminal coupled to the second terminal of the sampling circuit and is adapted to generate and output a pre-pulse signal when detecting that the duration of the sampling voltage being continuously at a high level reaches a preset first duration; The pulse signal generating circuit has an input terminal coupled to the input terminal of the pre-pulse signal generating circuit and is adapted to convert the pre-pulse signal into a pulse signal; The light-load signal generating circuit has an input end coupled to the output end of the pre-pulse signal generating circuit and is adapted to generate and output the light-load signal when it is detected that the number of times the pulse signal is received reaches a second preset value.

10. The synchronous rectification control circuit according to claim 9, wherein: The pre-pulse signal generating circuit includes: a first Schmitt trigger, a fourth current source, a fourth NMOS transistor, a fifth NMOS transistor, a fourth capacitor, a seventh comparator and a first counter, wherein: The first Schmitt trigger has an input terminal inputting the sampling voltage and an output terminal coupled to the gate of the fourth NMOS transistor and the control terminal of the first counter; The fourth NMOS transistor has a drain coupled to the second end of the fourth current source and the second input end of the seventh comparator, and a source grounded; The fourth current source has a first terminal connected to a preset power supply voltage; The fifth NMOS transistor has a gate coupled to the output terminal of the seventh comparator, a drain coupled to the second input terminal of the seventh comparator, and a source grounded; the fourth capacitor, a first terminal of which is coupled to the second input terminal of the seventh comparator, and a second terminal of which is grounded; The seventh comparator has a first input terminal inputting a fifth reference voltage and an output terminal coupled to the input terminal of the first counter; The first counter has an output terminal coupled to an output terminal of the pre-pulse signal generating circuit; The pre-pulse signal generating circuit is adapted to output the pre-pulse signal when the count value of the first counter reaches a first preset value.

11. The synchronous rectification control circuit according to claim 9, wherein: The pulse signal generating circuit includes: a fifth inverter, a first delay circuit and a second NAND gate circuit, wherein: the fifth inverter, an input end of which is coupled to the input end of the pulse signal generating circuit, and an output end of which is coupled to the first input end of the second NAND gate circuit and the first end of the first delay circuit; The first delay circuit has a second terminal coupled to the second input terminal of the second NAND gate circuit; An output terminal of the second NAND gate circuit is coupled to an output terminal of the pulse signal generating circuit.

12. The synchronous rectification control circuit according to claim 9, wherein: The light-load signal generating circuit includes: a sixth inverter and a second counter, wherein: the sixth inverter, whose input terminal is the first input terminal of the light-load signal generating circuit, and whose output terminal is coupled to the input terminal of the second counter; the second counter, an output terminal of which is coupled to an output terminal of the light-load signal generating circuit; The light-load signal generating circuit is adapted to generate and output the light-load signal when the count value of the second counter reaches a second preset value.

13. The synchronous rectification control circuit according to claim 12, wherein: The light-load signal generating circuit further includes: a detection trigger sub-circuit, having an input terminal inputting the sampling voltage, a control terminal coupled to the output terminal of the pre-pulse signal generating circuit, a first output terminal coupled to the control terminal of the second counter, and a second output terminal coupled to the output terminal of the light-load signal generating circuit; The detection trigger sub-circuit is suitable for outputting a first trigger signal to the control end of the second counter when it is detected that the number of consecutive times that the sampling voltage is at a low level reaches a third preset value; and is suitable for outputting a second trigger signal when the number of consecutive times that the sampling voltage is at a low level reaches a fourth preset value after detecting that the light load signal is generated, so that the light load signal generating circuit stops generating the light load signal.

14. The synchronous rectification control circuit according to claim 13, wherein: The detection trigger sub-circuit includes: a second Schmitt trigger, a seventh inverter, and a third counter; wherein: The second Schmitt trigger has an input terminal inputting the sampling voltage and an output terminal coupled to the input terminal of the seventh inverter; the seventh inverter, an output terminal of which is coupled to the input terminal of the third counter; The third counter has a control end coupled to the output end of the pre-pulse signal generating circuit, a first output end being the first output end of the detection trigger sub-circuit, and a second output end being the second output end of the detection trigger sub-circuit.

15. A switching power supply system, characterized in that: include: The synchronous rectification control circuit according to any one of claims 1 to 14.

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