Device, Method and Electronic System for Controlling an Internal Reset Signal

Abstract

The present invention provides a device, a method and an electronic system for controlling an internal reset signal. The internal reset signal is synchronized with a clock signal. The device includes a clock switching circuit and a plurality of DFFs serially coupled. The clock switching circuit receives the clock signal and is configured to output the clock signal in an on state and block the clock signal in an off state. The plurality of DFFs are coupled to the clock switching circuit and driven by the clock signal. The plurality of DFFs are configured to enable the internal reset signal in response to the external reset signal being enabled, and disable the internal reset signal after a predetermined number of clock signal cycles after the external reset signal is disabled. The present invention can synchronize the internal reset signal with the clock signal and avoid the metastability problem between different transmitter paths.

Description

Technical Field

[0001] The present invention relates to an electronic system, and more particularly, to the field of frequency dividers for generating local oscillator signals. Background Art

[0002] The background art description provided herein is for the purpose of generally presenting the content of the present invention. The content described in this background art section and other descriptions that do not qualify as prior art at the time of application should not be considered as prior art to the present invention, either explicitly or implicitly.

[0003] A transceiver may have multiple transmitter (TX) paths. Each path may have its own local oscillator (LO) signal, and the local oscillator signal may be generated by a divide-by-2 (Div2) frequency divider associated with the path. Although these frequency dividers may output LOs of the same frequency, the phases of these LOs may be different and may change, which may cause a problem of meta-stability. To avoid the meta-stability problem, it is necessary to synchronize different frequency dividers so that their phase differences can be kept constant. Summary of the Invention

[0004] In view of the above problems, the present invention provides an apparatus, a method, and an electronic system for controlling an internal reset signal.

[0005] Aspects of the present invention provide an apparatus for controlling an internal reset signal that is synchronized with a clock signal. The apparatus includes a clock switching circuit and a plurality of DFFs serially coupled. The clock switching circuit receives the clock signal and is configured to output the clock signal in an on state and block the clock signal in an off state. The plurality of DFFs serially coupled are coupled to the clock switching circuit and are driven by the clock signal. The plurality of DFFs serially coupled are configured to enable the internal reset signal in response to an external reset signal being enabled, and to disable the internal reset signal after a predetermined number of clock signal cycles after the external reset signal is disabled.

[0006] Aspects of the present invention provide a method for controlling an internal reset signal that is synchronized with a clock signal. The method includes: receiving the clock signal through a clock switching circuit; enabling the internal reset signal through a plurality of serially-coupled D flip-flops (DFFs) in response to an external reset signal being enabled; and disabling the internal reset signal through the plurality of serially-coupled DFFs after a predetermined number of clock signal cycles after the external reset signal is disabled. The clock switching circuit outputs the clock signal in an on state and blocks the clock signal in an off state; the plurality of serially-coupled DFFs are coupled to the clock switching circuit and are driven by the clock signal.

[0007] Aspects of the present invention provide an electronic system that includes a local divider reset circuit. The local divider reset circuit includes a clock switching circuit and a plurality of serially-coupled DFFs. The clock switching circuit receives the clock signal and is configured to output the clock signal in an on state and block the clock signal in an off state. The plurality of serially-coupled DFFs are coupled to the clock switching circuit and are driven by the clock signal. The plurality of serially-coupled DFFs are configured to enable an internal reset signal in response to an external reset signal being enabled and to disable the internal reset signal after a predetermined number of clock signal cycles after the external reset signal is disabled.

[0008] By using the apparatus, method, and electronic system for controlling an internal reset signal provided by the present invention, the internal reset signal can be synchronized with the clock signal, and metastability problems between different transmitter paths can be avoided.

[0009] Many objects, features, and advantages of the present invention will be apparent when the following detailed description of the embodiments of the present invention is read in conjunction with the accompanying drawings. However, the drawings used herein are for the purpose of description and should not be considered limiting. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various embodiments of the present invention, presented as examples, will be described in detail with reference to the following drawings, in which like reference numerals represent like elements, and:

[0011] Figure 1 An exemplary local divider reset (LORST) circuit according to an embodiment of the present invention is shown.

[0012] Figures 2A to 2D The detailed operation of the LORST circuit according to an embodiment of the present invention is shown.

[0013] Figure 3 An exemplary timing diagram for controlling an internal reset signal RST_INT according to an embodiment of the present invention is shown.

[0014] Figure 4 Shows an exemplary timing diagram according to an embodiment of the present invention.

[0015] Figure 5 Shows an exemplary frequency divider circuit block and corresponding detailed circuit according to an embodiment of the present invention.

[0016] Figure 6 Shows an example of controlling two frequency divider circuit blocks according to an embodiment of the present invention.

[0017] Figure 7A Shows an exemplary local LORST configuration according to an embodiment of the present invention.

[0018] Figure 7B Shows an exemplary cascade LORST configuration according to an embodiment of the present invention.

[0019] Figures 8A to 8D Shows the detailed operation of the cascade LORST configuration according to an embodiment of the present invention.

[0020] Figure 8E Shows an alternative option of the cascade LORST configuration according to an embodiment of the present invention.

[0021] Figure 9 Shows a flowchart of an exemplary process according to an embodiment of the present invention.

[0022] Figures 10A to 10C Shows some exemplary transceivers according to an embodiment of the present invention. Detailed Description

[0023] Figure 1 Shows an exemplary local divider reset (LORST) circuit 100 according to an embodiment of the present invention. The LORST circuit 100 includes a clock switch circuit 101 and a plurality (e.g., M) of serially-coupled D flip-flops (DFFs).

[0024] The clock switch circuit 101 receives a clock signal CLK and is controlled by a reset signal RST. The clock signal CLK can be a global clock signal or a local clock signal. The reset signal RST can be a global reset signal or a local reset signal. In the present invention, the clock signal CLK and the reset signal RST can also be referred to as an external clock signal and an external reset signal, respectively. Note that the external reset signal RST does not have the timing information of the external clock signal CLK. That is, the external reset signal RST may not be synchronized with the external clock signal CLK.

[0025] The clock switching circuit 101 includes a switch 102 and an inverter 103. The input terminal of the switch 102 is coupled to an external clock signal CLK, and the output terminal of the switch 102 is coupled to the clock terminal of each DFF among a plurality of DFFs of the LORST circuit 100. Additionally, the control terminal of the switch 102 is coupled to the output terminal of the inverter 103. The input terminal of the inverter 103 is coupled to an external reset signal RST.

[0026] The operation of the clock switching circuit 101 is controlled by an external reset signal RST. When the external reset signal RST is enabled, the clock switching circuit 101 can block the external clock signal CLK, such that no clock signal triggers the plurality of DFFs. When the external reset signal RST is disabled, the clock switching circuit 101 can allow the external clock signal CLK to pass through and become an internal clock signal CLK_INT that triggers the plurality of DFFs.

[0027] In Figure 1 it is assumed that the external reset signal RST is enabled when at logic 1 (e.g., power supply voltage VCC) and disabled when at logic 0 (e.g., ground voltage GND), and the switch 102 is turned on and off when the control terminal of the switch 102 is set to logic 1 and logic 0, respectively. Thus, when the external reset signal RST is enabled, the inverter 103 receives logic 1 and outputs logic 0, setting the control terminal of the switch 102 to logic 0. Consequently, the switch 102 is turned off, and then the external clock signal CLK is blocked by the switch 102. When the external reset signal RST is disabled, the inverter 103 receives logic 0 and outputs logic 1, setting the control terminal of the switch 102 to logic 1. Therefore, the switch 102 is turned on, and then the external clock signal CLK can pass through the switch 102 and become the internal clock signal CLK_INT coupled to the clock terminal of each DFF.

[0028] Note that in other embodiments, the external reset signal RST can be enabled when at logic 0 and disabled when at logic 1. Thus, the switch 102 is turned on and off when the control terminal of the switch 102 is set to logic 0 and logic 1, respectively.

[0029] Refer again to Figure 1, each DFF in the LORST circuit 100 includes a data terminal D, an output terminal Q (and / or an inverted output terminal QB), a reset terminal R, and a clock terminal. A plurality of DFFs are serially coupled from the first DFF 104 to the last DFF 107. That is, the data terminal D of the current DFF (e.g., DFF 105) is coupled to the output terminal Q of the previous DFF (e.g., DFF 104), and the output terminal Q of the current DFF is coupled to the data terminal D of the next DFF (e.g., DFF 106).

[0030] According to aspects of the present invention, the LORST circuit 100 may output an internal reset signal RST_INT through the inverted output terminal QB of the last DFF 107.

[0031] In Figure 1 the example, it is assumed that the internal reset signal RST_INT is enabled when at logic 1 and disabled when at logic 0, so the data terminal D of the first DFF 104 is coupled to logic 1. However, it should be noted that if the internal reset signal RST_INT is enabled when at logic 0 and disabled when at logic 1, in another example, the data terminal D of the first DFF 104 may be coupled to logic 0 (e.g., GND). In such an example, when the external reset signal RST is enabled, each DFF outputs logic 1, such that through the inverted output terminal QB of the last DFF 107, the internal reset signal RST_INT is set to logic 0. When the external reset signal RST is disabled, after M clock signal cycles, since the data terminal D of the first DFF 104 is coupled to logic 0, the internal reset signal RST_INT is disabled when at logic 1. Therefore, the data terminal D of the first DFF is coupled to the logic voltage at which the internal reset signal RST_INT can be enabled.

[0032] In addition, in the LORST circuit 100, the clock terminal and the reset terminal of each DFF are respectively coupled to the output terminal of the switch 102 and the external reset signal RST. The inverted output terminal QB of the last DFF 107 is coupled to Figure 1 a plurality of (e.g., N) frequency divider blocks DIV-1 to DIV-N in the example. However, in another example, the inverted output terminal QB of the last DFF 107 may be coupled to various circuit blocks through a reset function.

[0033] According to aspects of the present invention, the internal reset signal RST_INT may be synchronized with an external clock signal CLK to reset Figure 1The frequency divider blocks DIV-1 to DIV-N in the example or various circuit blocks in other examples. The operations for resetting the frequency divider blocks DIV-1 to DIV-N (or various circuit blocks in other examples) include: (1) resetting all internal nodes of the frequency divider block with a predetermined voltage; (2) using the LORST circuit to generate an internal reset signal RST_INT synchronized with the external clock signal CLK; (3) unlocking the frequency divider so that the frequency divider can run freely.

[0034] Specifically, when the external reset signal RST is enabled, the external clock signal CLK is blocked, and each DFF is set to the reset mode, and thus outputs logic 0. As a result, the internal reset signal RST_INT is set to logic 1 through the inverted output terminal QB of the last DFF 107. When the external reset signal RST is disabled, each DFF is set to the standby mode, and the external clock signal CLK is transmitted to each DFF through the switch 102. After a plurality of clock signal cycles, the internal reset signal RST_INT flips from logic 1 to logic 0. Therefore, the internal reset signal RST_INT can be synchronized with the external clock signal CLK. The number of clock signal cycles depends on the total number of DFFs. In Figure 1 it, the total number of DFFs is M.

[0035] Figures 2A to 2D shows the detailed operation of the LORST circuit 100 according to an embodiment of the present invention. Assume that when the internal reset signal is enabled at logic 1 and disabled at logic 0, all the DIV-1 to DIV-N blocks are set to the reset mode and the standby mode, respectively.

[0036] In the first step, as Figure 2A shown, when the external reset signal RST is enabled at logic 1 and the inverter 103 outputs logic 0, the switch 102 is turned off and the external clock signal CLK is blocked by the switch 102. The internal clock signal CLK_INT is set to logic 0, and each DFF is set to the reset mode and outputs logic 0. As a result, the internal reset signal RST_INT is enabled and set to logic 1 through the inverted output terminal QB of the last DFF 107.

[0037] In the second step, as Figure 2BAs shown, after a certain number of clock signal cycles after the first step, the external reset signal RST changes from logic 1 to logic 0. That is, the external reset signal RST changes from the enabled state to the disabled state, so each DFF changes from the reset mode to the standby mode. However, due to the propagation delay, the inverter 103 still outputs logic 0, so the external clock signal CLK is still blocked by the switch 102, making the internal clock signal CLK_INT still set to logic 0.

[0038] In the third step, as Figure 2C shown, the LORST circuit 100 has completed the conversion from the reset mode to the standby mode. Therefore, the external reset signal RST is disabled when it is at logic 0, and the inverter 103 outputs logic 1, making the switch 102 turn on and the clock signal CLK pass through the switch 102 to start the internal clock signal CLK_INT. After the first clock signal cycle of the internal clock signal CLK_INT, since the data terminal D of the first DFF 104 is coupled to logic 1 (e.g., VCC), the first DFF 104 flips from logic 0 to logic 1. However, the outputs of other DFFs including the last DFF 107 are not flipped and are still set to logic 0. Therefore, the internal reset signal RST_INT is still enabled and set to logic 1 through the inverted output terminal QB of the last DFF 107.

[0039] In the fourth step, as Figure 2D shown, after the conversion from the reset mode to the standby mode, the LORST circuit 100 has completed M clock signal cycles. That is, the LORST circuit has completed the first M clock signal cycles of the internal clock signal CLK_INT. Therefore, all the outputs of multiple DFFs including the last DFF 107 are flipped and set to logic 1, and the internal reset signal RST_INT is disabled through the inverted output terminal QB of the last DFF 107 and flips from logic 1 to logic 0.

[0040] Through this operation, the internal reset signal RST_INT can be synchronized with the external clock signal CLK to reset the frequency divider block (or various circuit modules in other examples) coupled to the internal reset signal RST_INT.

[0041] Figure 3 FIG. 300 shows an exemplary timing diagram for controlling the internal reset signal RST_INT according to an embodiment of the present invention. For simplicity, the external reset signal RST is set to be synchronized with the clock signal CLK. However, it should be noted that the external reset signal RST may not be synchronized with the clock signal CLK and may be enabled and disabled randomly.

[0042] In timing diagram 300, waveform 301 depicts the external reset signal RST, waveform 302 depicts the external clock signal CLK, and waveform 303 depicts the internal reset signal RST_INT. At T1, the external reset signal RST is enabled when it is at logic 1, so the LORST circuit 100 is set to the reset mode, enabling the internal reset signal RST_INT. At T2, the external reset signal RST is disabled when it is at logic 0, so the LORST circuit 100 is set to the standby mode. However, since the inverted output terminal QB of the last DFF 107 has not been flipped, the internal reset signal RST_INT remains enabled when it is at logic 1. At T3, since the inverted output terminal QB of the last DFF 107 is flipped after multiple clock signal cycles, the internal reset signal RST_INT is disabled when it is at logic 0. The number of clock signal cycles between T2 and T3 depends on the total number of DFFs.

[0043] Figure 4 An exemplary timing diagram 400 according to an embodiment of the present invention is shown. In timing diagram 400, waveform 410 depicts a clock signal CLK_IN with a frequency of freq, which is input to a frequency divider circuit of 2-divider (DIV2). The DIV2 frequency divider circuit can output a divided clock signal with a frequency of freq / 2. The DIV2 frequency divider is a rising-edge triggered circuit.

[0044] Note that, for simplicity, a DIV2 frequency divider is used in the Figure 4 example. In another example, other types of frequency dividers, such as a 3-divider (DIV3) or a 4-divider (DIV4) frequency divider, can be used.

[0045] In timing diagram 400, waveform 420 depicts the reset signal RST1 for resetting the DIV2 circuit block. When the reset signal RST1 is enabled at logic 1, the DIV2 circuit block is set to the reset mode and suspends the output of the divided clock signal. When the reset signal RST1 is disabled at logic 0, the DIV2 circuit block is set to the standby mode and resumes the output of the divided clock signal. The divided clock signal is referred to as CLK_OUT1 and is represented by waveform 430. Note that the reset signal RST1 is synchronized with the input clock signal CLK_IN, so the falling edge 421 of the disabled reset signal RST1 is synchronized with the falling edge 411 of the input clock signal CLK_IN. After the reset signal RST1 is disabled at the falling edge 421, the divided clock signal CLK_OUT1 starts free running at the next rising edge of the input clock signal CLK_IN (i.e., rising edge 412). Therefore, the rising edge 431 of the first clock of the divided clock signal CLK_OUT1 is synchronized with the rising edge 412 of the input clock signal CLK_IN.

[0046] Still referring to timing diagram 400, waveform 440 depicts the reset signal RST2 for resetting the same DIV2 circuit block. When the reset signal RST2 is enabled at logic 1, the DIV2 circuit block is set to the reset mode and suspends the output of the divided clock signal; when the reset signal RST2 is disabled at logic 0, the DIV2 circuit block is set to the standby mode and resumes the output of the divided clock signal. The divided clock signal is referred to as CLK_OUT2 and is represented by waveform 450. It should be noted that the reset signal RST2 is not synchronized with the input clock signal CLK_IN, so the falling edge 441 of the disabled reset signal RST2 is not synchronized with any rising or falling edge of the input clock signal CLK_IN. After the reset signal RST2 is disabled at the falling edge 441, the divided clock signal CLK_OUT2 starts free running at the next rising edge of the input clock signal CLK_IN (i.e., rising edge 413). Therefore, the rising edge 451 of the first clock of the divided clock signal CLK_OUT2 is synchronized with the rising edge 413 of the clock signal CLK_IN.

[0047] Note that in timing diagram 400, the divided clock signals CLK_OUT1 and CLK_OUT2 have complementary phases. This indicates that the phase of the divided clock signal (e.g., CLK_OUT2) controlled by the random reset signal (e.g., RST2) can be different or even complementary to the phase of the divided clock signal (e.g., CLK_OUT1) controlled by the synchronously reset signal (e.g., RST1). Therefore, for multiple divided clock signals, it is desirable to use a synchronous reset signal so that each divided clock signal can have a predetermined phase.

[0048] Figure 5 An exemplary divider circuit block 500 and corresponding detailed circuitry according to an embodiment of the present invention are shown. The divider circuit block 500 is a DIV2 block that receives an input clock signal (e.g., Figure 4 input clock signal CLK_IN 410 in the example) having a frequency of freq at an input terminal CLK_IN and outputs a divided clock signal (e.g., Figure 4 divided clock signal CLK_OUT1 430 or CLK_OUT2 450 in the example) having a frequency of freq / 2 at an output terminal CLK_OUT. A reset terminal RST is used to receive a reset signal (e.g., Figure 4 reset signal RST1 420 or RST2 440 in the example), and the reset signal is enabled and disabled to set the divider circuit block 500 to a reset mode and a standby mode, respectively. That is, when the reset signal (e.g., RST1420) is enabled (e.g., at logic 1), the divided clock signal (e.g., CLK_OUT1 430) is turned off, and each internal node of the divider circuit block 500 is set to have a respective predefined charge. When the reset signal (e.g., RST1 420) is disabled (e.g., at logic 0), the divided clock signal (e.g., CLK_OUT1 430) is turned on, and the initial phase of the divided clock signal is defined by the preset voltage of the internal nodes of the divider circuit block 500.

[0049] Specifically, when the reset signal is enabled at logic 1 (i.e., the inverse reset signal is disabled at logic 0), transistors M1 - M4 conduct. As a result, the logic voltages at nodes 501 and 505 are logic 0, and the logic voltages at nodes 502 and 506 are logic 1. The internal terminals CLK and CLKB are logic 0 and logic 1 respectively. Since the logic voltages of nodes 505 and 506 are logic 0 and logic 1, due to inverters 560 and 561, the logic voltages of nodes 507 and 508 are logic 1 and logic 0 respectively. Since the logic voltages of nodes 501 and 502 are logic 0 and logic 1 respectively, transmission gates 540 and 541 are turned off, and transmission gates 570 and 571 are turned on, resulting in the logic voltages at nodes 509 and 510 being logic 1 and logic 0 respectively. Therefore, the logic voltages on the output terminal CLK_OUT and the inverted output terminal CLKB_OUT of the frequency divider circuit block 500 are logic 0 and logic 1 respectively. Due to inverters 530 and 531, the logic voltages at nodes 503 and 504 are logic 1 and logic 0 respectively. Modules 550 and 580 are equivalent to the latch modules in the frequency divider circuit block 500.

[0050] When the reset signal of the frequency divider circuit block 500 is enabled, the output terminal CLK_OUT becomes logic 0. When the reset signal is disabled, the divided - frequency clock signal can be output from the output terminal CLK_OUT. Therefore, the first clock signal period of the divided - frequency clock signal always goes from logic 0 to logic 1, indicating the predetermined phase of the divided - frequency clock signal.

[0051] Figure 5 The detailed circuit of the frequency divider circuit block shown is merely exemplary and not a limitation of the present invention. Those skilled in the art can adopt any other structural form of the frequency divider circuit.

[0052] Figure 6 An example of controlling two frequency divider circuit blocks according to an embodiment of the present invention is shown. In Figure 6 There are two divide - by - two (DIV2) circuit blocks. That is, the first DIV2 block 610 receives the first input clock signal CLK 601 and outputs the first divided - frequency clock signal 604, and the second DIV2 block 620 receives the second input clock signal CLK_60 602 and outputs the second divided - frequency clock signal 605. Note that the first input clock signal CLK 601 and the second input clock signal CLK_60 602 have the same frequency. However, in some embodiments, the phases of these two input clock signals can be different. For example, the phase difference between the first input clock signal CLK601 and the second input clock signal CLK_60602 can be 60°.

[0053] In Figure 6In it, the reset terminals of the first DIV2 block 610 and the second DIV2 block 620 are coupled to an internal reset signal RST_INT 603 that is synchronized with the first clock signal CLK601. When the internal reset signal RST_INT 603 is enabled at logic 1, both the first DIV2 block 610 and the second DIV2 block 620 are set to the reset mode, and all internal nodes of the first DIV2 block 610 and the second DIV2 block 620 are set to have predefined voltages. When the internal reset signal RST_INT603 is disabled at logic 0, both the first DIV2 block 610 and the second DIV2 block 620 are set to the standby mode, and the first clock period of both the first divided clock signal 604 and the second divided clock signal 605 is from logic 0 to logic 1. In addition, the phase difference between the first divided clock signal 604 and the second divided clock signal 605 is the same as the phase difference between the first input clock signal CLK 601 and the second input clock signal CLK_60 602.

[0054] Figure 7A Shows an exemplary local LORST configuration according to an embodiment of the present invention. In Figure 7A it, two DIV2 blocks 701 and 702 are placed close to each other, so a single LORST block 703 is used to control the two DIV2 blocks 701 and 702 by generating an internal reset signal RST_INT. However, if the two DIV2 blocks 701 and 702 are placed far from each other, using a single LORST to control the DIV2 blocks 701 and 702 may cause a metastability problem.

[0055] Figure 7B Shows an exemplary cascade LORST configuration according to an embodiment of the present invention. In Figure 7B it, two DIV2 blocks 711 and 712 are separated far from each other such that each block is associated with its respective local LORST block. For example, the DIV2 block 711 is associated with the local LORST block 713, and the DIV2 block 712 is associated with the local LORST block 714. Each DIV2 block receives an internal clock signal and outputs a divided clock signal. For example, the DIV2 block 711 receives the internal clock signal CLK_IN1 and outputs the divided clock signal CLK_D1, while the DIV2 block 712 receives the internal clock signal CLK_IN2 and outputs the divided clock signal CLK_D2. The internal clock signals CLK_IN1 and CLK_IN2 both come from an external clock signal CLK. However, in some related cases, at least one of the internal clock signals may not be synchronized with the external clock CLK, resulting in a meta-stability problem.

[0056] To avoid metastability issues, a buffer circuit block 718 is inserted between the external clock signal CLK and the DIV2 blocks 711 and 712. The buffer circuit block 718 includes a buffer 716, a switch 717, and a local LORST block 715. The LORST block 715 can output a switch control signal CLK_SW for controlling the switch 717. In one embodiment, when the switch control signal CLK_SW is set to logic 1, the switch 717 is turned off, and when the switch control signal CLK_SW is set to logic 0, the switch 717 is turned on. Thus, the switch control signal CLK_SW is synchronized with the external clock signal CLK through LORST 715.

[0057] When the switch 717 is turned on, the internal clock signals CLK_IN1 and CLK_IN2 can be synchronized with the external clock signal CLK. Thus, the initial waveforms (or phases) of the two internal clock signals are the same. For example, the first clock cycle of the two internal clock signals always goes from logic 0 to logic 1. Additionally, each internal clock signal is input to the corresponding DIV2 block and the local LORST associated with the DIV2 block. For example, the internal clock signal CLK_IN1 is input to the DIV2 block 711 and the LORST block 713, while the internal clock signal CLK_IN2 is input to the DIV2 block 712 and the LORST block 714. Thus, for different LORST blocks, the internal clock signals have the same predefined initial waveform (or phase). Metastability issues between different transmitter paths can be avoided.

[0058] Note that the reset terminals of all the local LORST blocks 713 - 715 are coupled to the same external reset signal RST.

[0059] Figures 8A to 8D The detailed operation of a cascaded LORST configuration according to an embodiment of the present invention is shown. Note that each LORST block in the cascaded LORST configuration includes M DFFs.

[0060] In the first step, as Figure 8A shown, the external reset signal RST is enabled at logic 1, so that all the local LORST blocks are set to the reset mode and output logic 1. That is, the internal reset signal RST_INT1 output from the LORST block 713 is set to logic 1, the internal reset signal RST_INT2 output from the LORST block 714 is set to logic 1, and the switch control signal CLK_SW output from the LORST block 715 is set to logic 1. Thus, both the DIV2 blocks 711 and 712 are set to the reset mode; the switch 717 is turned off; the internal clock signals CLK_IN1 and CLK_IN2 are both set to logic 0; and the divided clock signals CLK_D1 and CLK_D2 are both set to logic 0.

[0061] In the second step, as Figure 8B shown, after a certain number of clock cycles after the first step, the external reset signal RST changes from logic 1 to logic 0. That is, the external reset signal RST changes from the enabled state to the disabled state. Then, all LORST blocks 713 - 715 are set to the standby mode, and the LORST block 715 starts to run freely, but the LORST blocks 713 and 714 do not start to run freely because the internal clock signals CLK_IN1 and CLK_IN2 are still set to logic 0. Due to the propagation delay, the outputs of the local LORST blocks are still set to logic 1. Therefore, the internal reset signals RST_INT1 and RST_INT2 and the switch control signal CLK_SW are still set to logic 1; both DIV2 blocks 711 and 712 are set to the reset mode; the switch 717 remains open; the internal clock signals CLK_IN1 and CLK_IN2 and the divided clock signals CLK_D1 and CLK_D2 are still set to logic 0.

[0062] In the third step, as Figure 8C shown, after M clock cycles after the second step (i.e., the transition of the external reset signal RST from the enabled state to the disabled state), the external reset signal RST is still disabled and set to logic 0. Since the LORST block 715 includes M DFFs, the switch control signal CLK_SW output from the LORST block 715 changes from logic 1 to logic 0. Then, the switch 717 turns off, and the external clock signal CLK can pass through the switch 717 to start the internal clock signals CLK_IN1 and CLK_IN2. Therefore, both internal clock signals CLK_IN1 and CLK_IN2 start to rise from logic 0 to logic 1. However, the internal reset signals RST_INT1 and RST_INT2 are both still set to logic 1. Therefore, both DIV2 blocks 711 and 712 are set to the reset mode; the divided clock signals CLK_D1 and CLK_D2 are still set to logic 0.

[0063] In the fourth step, as Figure 8D shown, after M clock cycles after the third step (i.e., 2M clock signal cycles after the transition from the enabled state to the disabled state), the external reset signal RST is still disabled and set to logic 0. That is, both internal clock signals CLK_IN1 and CLK_IN2 have operated for M clock cycles. Since both LORST blocks 713 and 714 contain M DFFs, the corresponding internal reset signals RST_INT1 / RST_INT2 are disabled and change from logic 1 to logic 0, and then the divided clock signals CLK_D1 / CLK_D2 start to rise from logic 0 to logic 1.

[0064] Through this operation, the initial waveforms (or phases) of different LORST blocks can be the same, even if these LORST blocks are separated from each other by a large distance.

[0065] Figure 8E An alternative option of the cascaded LORST configuration according to an embodiment of the present invention is shown. In Figure 8E , the LORST 715 in the buffer circuit block 718 and the local LORST blocks (e.g., LORST blocks 713 and 714) are controlled by different external reset signals. For example, RST1 controls the LORST block 715, and RST2 controls the LORST blocks 713 and 714. The control timings of RST1 and RST2 can be different. That is, RST1 can be later or earlier than RST2. RST1 can be a delayed version of RST2, or RST2 can be a delayed version of RST1. It should be noted that the present invention does not limit the timing relationship between RST1 and RST2.

[0066] Figure 9 A flowchart of an exemplary process 900 according to an embodiment of the present invention is shown. The process 900 is used to control an internal reset signal synchronized with a clock signal. The process 900 may start from step S910, where the process 900 receives a clock signal through a clock switching circuit. The clock switching circuit outputs the clock signal in the on state and blocks the clock signal in the off state. Then, the process 900 proceeds to step S920.

[0067] In step S920, in response to the external reset signal being enabled, the process 900 enables the internal reset signal through a plurality of serially coupled D flip - flops (DFFs). Then, the process 900 proceeds to step S930.

[0068] In step S930, after a predetermined number of clock signal cycles after the external reset signal is disabled, the process 900 disables the internal reset signal through a plurality of serially coupled DFFs. The plurality of serially coupled DFFs are coupled to the clock switching circuit and are driven by the clock signal. Then, the process 900 terminates.

[0069] In one embodiment, the data terminal of the first DFF among the plurality of DFFs is coupled to a logic voltage enabling the internal reset signal, and the inverted output terminal of the last DFF among the plurality of DFFs is coupled to the internal reset signal.

[0070] In one embodiment, the input terminal of the clock switching circuit is coupled to the clock signal, the output terminal of the clock switching circuit is coupled to the clock terminal of each of the plurality of DFFs, and the control terminal of the clock switching circuit is coupled to the external reset signal.

[0071] In one embodiment, in response to an external reset signal being enabled, the clock switching circuit is in an off state, such that a clock signal is not output to a plurality of DFFs, and in response to the external reset signal being disabled, the clock switching circuit is in an on state, whereby the clock signal is output to the plurality of DFFs.

[0072] In one embodiment, the external reset signal is coupled to the reset terminal of each DFF among the plurality of DFFs.

[0073] In one embodiment, in response to the external reset signal being enabled and disabled respectively, each DFF is set to a reset mode and a standby mode.

[0074] In one embodiment, a predetermined number of clock signal periods depends on the total number of DFFs.

[0075] Generally, process 900 can be appropriately modified by modifying one or more operations in the corresponding process, adding one or more operations, omitting one or more operations, etc. For example, additional operations can be added, where one or more specific processes can be selected from a process set including process 900.

[0076] Figures 10A to 10C Some exemplary transceivers according to embodiments of the present invention are shown. As Figure 10A shown, a first transceiver 1010 configured with a phase rotation (PR) architecture employs a LORST block 1011 to synchronize the phases of two path dividers 1012 and 1013. Referring to Figure 10B , a second transceiver 1020 configured with a low power mode (LPM) architecture for gain slicing employs a LORST block 1021 to synchronize the phases of different divider slices (e.g., divider slice 1022 and divider slice 1023). Referring to Figure 10C , a third transceiver 1030 configured with a plurality of transmitters (TXs) for multiple input multiple output (MIMO) employs a plurality of LORST blocks (e.g., LORST blocks 1031 and 1032) to synchronize the phases of different TXs (e.g., TXA 1033 and TXB 1034).

[0077] It should be noted that both LORST blocks 1011 and 1021 can have a local LORST configuration, while LORST blocks 1031 and 1032 can have a cascaded LORST configuration.

[0078] In accordance with aspects of the present invention, at least some of the various processes, operations, and techniques described above can be implemented using hardware, a processor executing firmware instructions, a processor executing software instructions, or any combination thereof. Moreover, at least some of the various processes, operations, and techniques described above can be performed in a different order (and / or simultaneously) and still achieve the desired results. When implemented using a processor executing software or firmware instructions, the software or firmware instructions can be stored in any computer-readable memory, such as a magnetic disk, an optical disk, or other storage media, or in random access memory (RAM), read-only memory (ROM), flash memory, a processor, a hard disk drive, an optical disk drive, a tape drive, etc. Similarly, the software or firmware instructions can be transmitted to a user or system by any known or desired transfer method, for example, on a computer-readable magnetic disk or other removable computer storage mechanism, or via a communication medium. A communication medium typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transmission mechanism. The term "modulated data signal" refers to a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, communication media include wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, radio frequency, infrared, and other wireless media. Thus, the software or firmware instructions can be transmitted to a user or system via a communication channel such as a telephone line, DSL line, cable television line, fiber optic line, wireless communication channel, the Internet, etc. (equivalent to providing such software via a removable storage medium). The software or firmware instructions can include machine-readable instructions that, when executed by a processor, cause the processor to perform various actions.

[0079] When implemented in hardware, the hardware can include one or more of discrete components, integrated circuits, application-specific integrated circuits (ASICs), etc.

[0080] Although aspects of the present invention have been described in connection with specific embodiments of the invention presented as examples, alternatives, modifications, and variations to the examples can be made. Accordingly, the embodiments set forth herein are intended to be illustrative and not limiting. Changes can be made without departing from the scope of the claims set forth below.

Claims

1. A device for controlling an internal reset signal, the internal reset signal being synchronized with a clock signal, the device comprising: A clock switching circuit that receives the clock signal and is configured to output the clock signal in an on state and block the clock signal in an off state; And A plurality of serially-coupled D flip-flops DFF coupled to the clock switching circuit and driven by the clock signal, the plurality of serially-coupled DFFs being configured to enable the internal reset signal in response to an external reset signal being enabled and, after a predetermined number of clock signal cycles after the external reset signal is disabled, disable the internal reset signal; Wherein each of the plurality of serially-coupled DFFs includes a data terminal, an output terminal and / or an inverted output terminal, a reset terminal, and a clock terminal, and the output terminal of the previous DFF in two adjacent DFFs is coupled to the data terminal of the subsequent DFF in the two adjacent DFFs.

2. The device according to claim 1, wherein: The data terminal of the first DFF among the plurality of DFFs is coupled to a logic voltage that enables the internal reset signal; and The inverted output terminal of the last DFF among the plurality of DFFs outputs the internal reset signal.

3. The device according to claim 1, wherein: The input terminal of the clock switching circuit is coupled to the clock signal; The output terminal of the clock switching circuit is coupled to the clock terminal of each of the plurality of DFFs; And The control terminal of the clock switching circuit is coupled to the external reset signal.

4. The apparatus according to claim 3, wherein, In response to the external reset signal being enabled, the clock switching circuit is in an off state such that the clock signal is not output to the plurality of DFFs, and in response to the external reset signal being disabled, the clock switching circuit is in an on state such that the clock signal is output to the plurality of DFFs.

5. The device according to claim 1, wherein the external reset signal is coupled to the reset terminal of each of the plurality of DFFs.

6. The device according to claim 5, wherein, In response to the external reset signal being enabled and disabled respectively, each DFF is set to a reset mode and a standby mode respectively.

7. The device according to claim 1, wherein the predetermined number of the clock signal cycles depends on the total number of the plurality of DFFs.

8. A method for controlling an internal reset signal, the internal reset signal being synchronized with a clock signal, the method comprising: Receiving the clock signal through a clock switching circuit; Enabling the internal reset signal through a plurality of serially-coupled D flip-flops DFF in response to an external reset signal being enabled; And Disabling the internal reset signal through the plurality of serially-coupled DFFs after a predetermined number of clock signal cycles after the external reset signal is disabled, wherein The clock switching circuit outputs the clock signal in an on state and blocks the clock signal in an off state; The plurality of serially-coupled DFFs are coupled to the clock switching circuit and driven by the clock signal; Each of the plurality of serially-coupled DFFs includes a data terminal, an output terminal and / or an inverted output terminal, a reset terminal, and a clock terminal, and the output terminal of the previous DFF of two adjacent DFFs is coupled to the data terminal of the subsequent DFF of the two adjacent DFFs.

9. The method according to claim 8, wherein: the data terminal of the first DFF of the plurality of DFFs is coupled to a logic voltage enabling the internal reset signal; and the inverted output terminal of the last DFF of the plurality of DFFs outputs the internal reset signal.

10. The method according to claim 8, wherein: the input terminal of the clock switching circuit is coupled to the clock signal; the output terminal of the clock switching circuit is coupled to the clock terminal of each of the plurality of DFFs; and the control terminal of the clock switching circuit is coupled to the external reset signal.

11. The method according to claim 8, wherein, In response to the external reset signal being enabled, the clock switching circuit is in an off state such that the clock signal is not output to the plurality of DFFs, and in response to the external reset signal being disabled, the clock switching circuit is in an on state such that the clock signal is output to the plurality of DFFs.

12. The method according to claim 8, wherein, The external reset signal is coupled to the reset terminal of each of the plurality of DFFs.

13. The method according to claim 12, wherein, In response to the external reset signal being enabled and disabled respectively, each DFF is set to a reset mode and a standby mode respectively.

14. The method according to claim 8, wherein, The predetermined number of the clock signal periods depends on the total number of the plurality of DFFs.

15. An electronic system, comprising a local frequency divider reset circuit, the local frequency divider reset circuit comprising: a clock switching circuit that receives a clock signal and is configured to output the clock signal in an on state and block the clock signal in an off state; and a plurality of serially-coupled D flip-flops DFFs that are coupled to the clock switching circuit and driven by the clock signal, and the plurality of serially-coupled DFFs are configured to enable an internal reset signal in response to an external reset signal being enabled, and disable the internal reset signal after a predetermined number of clock signal periods after the external reset signal is disabled; wherein each of the plurality of serially-coupled DFFs includes a data terminal, an output terminal and / or an inverted output terminal, a reset terminal, and a clock terminal, and the output terminal of the previous DFF of two adjacent DFFs is coupled to the data terminal of the subsequent DFF of the two adjacent DFFs.

16. The electronic system according to claim 15, wherein: the data terminal of the first DFF of the plurality of DFFs is coupled to a logic voltage enabling the internal reset signal; and the inverted output terminal of the last DFF of the plurality of DFFs outputs the internal reset signal.

17. The electronic system according to claim 15, wherein: the input terminal of the clock switching circuit is coupled to the clock signal; the output terminal of the clock switching circuit is coupled to the clock terminal of each of the plurality of DFFs; and The control terminal of the clock switching circuit is coupled to the external reset signal.

18. The electronic system according to claim 15, wherein, In response to the external reset signal being enabled, the clock switching circuit is in an off state such that the clock signal is not output to the plurality of DFFs, and in response to the external reset signal being disabled, the clock switching circuit is in an on state such that the clock signal is output to the plurality of DFFs.

19. The electronic system according to claim 15, wherein, The external reset signal is coupled to the reset terminal of each of the plurality of DFFs such that in response to the external reset signal being enabled and disabled respectively, each DFF is set to a reset mode and a standby mode respectively.

20. The electronic system according to claim 15, wherein, The predetermined number of the clock signal periods depends on the total number of the plurality of DFFs.

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