Semiconductor device and method for manufacturing the same, three-dimensional memory device, and memory system

Abstract

The present application provides a kind of semiconductor device and its manufacturing method, three-dimensional storage device and storage system, semiconductor device includes: substrate, substrate includes first area and second area, first area is formed with recess; first shallow trench isolation structure and second shallow trench isolation structure in first area and second area respectively;First gate oxide layer on recess and second gate oxide layer on second area and second shallow trench isolation structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method, a three-dimensional storage device, and a storage system. Background Technology

[0002] As the storage density requirements of 3D-NAND flash memory increase, the feature size of existing devices is also shrinking. On the control chip of 3D-NAND flash memory, high-voltage device area and low-voltage device area are generally formed simultaneously. As the feature size of the device shrinks to a certain node, the field-effect transistors in the existing high-voltage device area and low-voltage device area will exhibit severe short-channel effect.

[0003] In addition, since the breakdown voltage requirements of the high-voltage device region and the low-voltage device region are different, it is difficult to manufacture semiconductor devices that can both avoid severe short-channel effects and meet the breakdown voltage requirements of different device regions based on existing processes.

[0004] Therefore, existing technologies have shortcomings and need to be improved and developed.

[0005] Technical issues

[0006] This invention provides a semiconductor device and its manufacturing method, which effectively avoids severe short-channel effects in semiconductor devices while simultaneously meeting the breakdown voltage requirements of different device regions in the semiconductor device.

[0007] Technical solutions

[0008] In a first aspect, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate, the substrate including a first region and a second region; forming a trench in the first region; forming a first oxide layer located in the first region and a second oxide layer located in the second region to form a first gate oxide layer in the trench; forming a first mask layer on the first oxide layer and the second oxide layer; forming a first shallow trench isolation structure and a second shallow trench isolation structure in the first region and the second region respectively, the height of the first shallow trench isolation structure in a first direction being greater than the height of the second shallow trench isolation structure in the first direction; removing the first mask layer; and forming a second gate oxide layer on the second region and the second shallow trench isolation structure.

[0009] More preferably, the substrate further includes a third region; forming a groove in the first region includes forming the groove and the scribe line in the first region and the third region, respectively.

[0010] Further preferably, forming a first shallow trench isolation structure and a second shallow trench isolation structure on the first region and the second region respectively includes: etching the first mask layer and the substrate to form an isolation trench in the substrate; filling the isolation trench with an isolation material to form a first shallow trench isolation structure in the first region; and etching the isolation material distributed in the second region to form a second shallow trench isolation structure.

[0011] More preferably, forming the second gate oxide layer located on the second region and the second shallow trench isolation structure includes: etching the second oxide layer; and forming the second gate oxide layer on the surface of the substrate in the second region and on the sidewall of the isolation trench.

[0012] More preferably, the thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

[0013] More preferably, after forming the second gate oxide layer located in the second region, the method further includes: forming a first gate layer on the surface of the first gate oxide layer; and forming a second gate layer on the surface of the second gate oxide layer.

[0014] More preferably, the second gate oxide layer is formed using a thermal oxidation process.

[0015] More preferably, the material of the first mask layer is silicon nitride.

[0016] More preferably, the first region is used to form a concave-gate field-effect transistor, and the second region is used to form a fin-like field-effect transistor.

[0017] In a second aspect, the present invention also provides a semiconductor device, comprising: a substrate including a first region and a second region, the first region having a groove formed thereon; a first shallow trench isolation structure and a second shallow trench isolation structure respectively located in the first region and the second region, the height of the first shallow trench isolation structure in a first direction being greater than the height of the second shallow trench isolation structure in the first direction; a first gate oxide layer located on the groove and a second gate oxide layer located on the second region and the second shallow trench isolation structure.

[0018] More preferably, the substrate further includes a third region, wherein a dicing groove is formed in the third region.

[0019] More preferably, the semiconductor device further includes:

[0020] A first gate layer located on the surface of the first gate oxide layer; a second gate layer located on the surface of the second gate oxide layer.

[0021] More preferably, the first region is used to form a concave-gate field-effect transistor, and the second region is used to form a fin-like field-effect transistor.

[0022] Thirdly, the present invention also provides a three-dimensional storage device, the three-dimensional storage device comprising a storage cell array and peripheral circuitry, wherein the peripheral circuitry comprises semiconductor devices as described in any of the preceding claims.

[0023] Fourthly, the present invention also provides a storage system including a controller and a three-dimensional storage device, the controller being coupled to the three-dimensional storage device and used to control the three-dimensional storage device to store data, the three-dimensional storage device including a semiconductor device as described in any of the preceding claims.

[0024] Beneficial effects

[0025] The semiconductor device and its manufacturing method provided by the present invention, on the one hand, by forming a groove on the first region and forming a first gate oxide layer on the groove, it is beneficial to form a gate with a larger channel length in the first region, thereby mitigating the short-channel effect in the first region; on the other hand, by forming a second shallow trench isolation structure in the second region, making the height of the first shallow trench isolation structure greater than the height of the second shallow trench isolation structure, and forming a second gate oxide layer on the second shallow trench isolation structure, it is beneficial to form a fin-like field-effect transistor in the second region, thereby also mitigating the short-channel effect in the second region. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the present invention, the drawings used in the description of the various embodiments made according to the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 This is a schematic flowchart of a semiconductor device manufacturing method provided in an embodiment of the present invention;

[0028] Figure 2 This is a schematic flowchart of another semiconductor device manufacturing method provided in an embodiment of the present invention;

[0029] Figure 3 This is a schematic flowchart of another semiconductor device manufacturing method provided in an embodiment of the present invention;

[0030] Figures 4A-4M These are schematic cross-sectional views of the semiconductor device provided in the embodiments of the present invention at various stages.

[0031] Figure 5This is a schematic diagram of the structure of a three-dimensional storage device provided in an embodiment of the present invention;

[0032] Figure 6 This is a schematic diagram of the structure of a storage system provided in an embodiment of the present invention.

[0033] Embodiments of the present invention

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0035] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0036] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0037] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0038] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0039] Please see Figure 1 , Figure 1 This is a schematic flowchart of a semiconductor device manufacturing method provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the specific process of this manufacturing method can be as follows:

[0040] Step S101: Provide a substrate, the substrate including a first region and a second region.

[0041] The cross-sectional structure diagram after step S101 is shown below. Figure 4A As shown.

[0042] Specifically, the substrate 10 can be made of semiconductor materials such as silicon, germanium, or silicon-on-insulator (SOI). In this embodiment, the substrate 10 may include a first region (region A) and a second region (region B). Region A is a high-voltage device region used to form the concave-gate transistor in this embodiment of the invention. Region B is a low-voltage device region. Further, the low-voltage device region may also include a low-low voltage device region, whose breakdown voltage is lower than that of the low-voltage device region. Region B is used to form a fin-like transistor similar to a FinFET in this embodiment of the invention. In a fin-like transistor, the gate can surround the channel from three sides, increasing the gate's control area over the channel and greatly enhancing the gate control capability. This effectively suppresses the short-channel effect and reduces the subthreshold leakage current. Since the high-voltage device region requires a higher breakdown voltage, the source-drain junction depth of the device is required to be deeper, and the height of the "Fin" (fin structure) of the corresponding fin-type transistor is also higher. However, it is difficult to form a three-sided gate structure on the higher Fin in the current process, so fin-type transistors are not used in region A.

[0043] Step S102: Form a groove in the first region.

[0044] The cross-sectional structure diagram of the semiconductor device after step S102 is shown below. Figure 4B As shown.

[0045] Specifically, the groove 101 facilitates the subsequent formation of a gate with a larger channel length in the first region, thereby mitigating the short-channel effect in the first region. The groove 101 can be formed by etching the substrate 10 using plasma etching, reactive ion etching, and / or wet etching processes. In this embodiment of the invention, the groove 101 can be formed in region A using plasma etching, specifically by mixing gases of Cl2, BCl3, He, and CF4 in a certain proportion for etching.

[0046] The substrate 10 also includes a third region (region C), which serves as an isolation layer when separating semiconductor devices from the wafer and also functions as a process monitoring layer. For example, test patterns can be formed in the third region to monitor process fluctuations (such as photolithography) in real time. Specifically, step S102 may involve forming the groove and dicing groove in the first region and the third region, respectively. A schematic diagram of the structure after this step is shown below. Figure 4C As shown.

[0047] Specifically, in existing processes, dicing grooves are generally formed by laser etching, so the formation of groove 101 is completed in steps. However, in this embodiment of the invention, by designing a mask with the pattern of groove 101 and dicing groove 103, the groove 101 and dicing groove 103 are formed simultaneously on the substrate 10 through photolithography and etching processes. Therefore, process steps are saved, which is beneficial to saving process costs.

[0048] Step S103: Form a first oxide layer located in the first region and a second oxide layer located in the second region to form a first gate oxide layer on the groove.

[0049] The cross-sectional structure diagram of the semiconductor device after step S103 is shown below. Figure 4D As shown.

[0050] Specifically, in this embodiment, the formation process of the first oxide layer 11A and the second oxide layer 11B includes thermal oxidation, soft plasma oxidation, or UV photo-assisted oxidation. In this example, when the substrate 10 is selected as a silicon substrate, both the first oxide layer 11A and the second oxide layer 11B are silicon oxide. The first oxide layer 11A serves as the first gate oxide layer in region A.

[0051] Step S104: Form a first mask layer located on the first oxide layer and the second oxide layer.

[0052] The structural diagram after step S104 is as follows: Figure 4E As shown.

[0053] Specifically, the first mask layer 12 is a hard mask layer, and the specific material can be silicon nitride. The first oxide layer 11A and the second oxide layer 11B help to reduce the stress on the substrate 10 caused by the formation of the silicon nitride layer. In this example, the silicon nitride layer can be formed by LPCVD process.

[0054] Step S105: A first shallow trench isolation structure and a second shallow trench isolation structure are formed on the first region and the second region respectively. The height of the first shallow trench isolation structure in the first direction is greater than the height of the second shallow trench isolation structure in the first direction.

[0055] Please see Figure 2 , Figure 2 This is a flowchart of another semiconductor device manufacturing method provided in an embodiment of the present invention, such as... Figure 2 As shown, step S105 may include:

[0056] Step S1051: The substrate is etched to form isolation trenches. A cross-sectional view of the semiconductor device after step S1051 is shown below. Figure 4F As shown.

[0057] Step S1052: Fill the isolation trench with an insulating material to form a first shallow trench isolation structure in the first region. A cross-sectional view of the semiconductor device after step S1052 is shown below. Figure 4G As shown.

[0058] Step S1053: The isolator distributed in the second region is etched to form a second shallow trench isolation structure. A cross-sectional view of the semiconductor device after step S1053 is shown below. Figure 4H As shown.

[0059] Specifically, a photoresist pattern defining the location of the isolation trench 102 and having an opening can be formed by coating a photoresist (not shown in the figure) on the surface of the first mask layer 12 and performing photolithography processes such as exposure and development. Then, reactive ion etching (RIE) or plasma etching processes are used to etch the first mask layer 12, the first oxide layer 11A, and the second oxide layer 11B through the opening to expose the surface of the substrate 10. Then, using a fluorine-containing etching gas, the substrate 10 is etched again with the first mask layer 12 as a mask, thereby forming the isolation trench 102 in the substrate 10. The isolation trench 102 includes a first sub-isolation trench 102A and a second sub-isolation trench 102B. The first sub-isolation trench 102A and the second sub-isolation trench 102B can be formed in one step, that is, they have the same height. Subsequently, the spacer 13 can be deposited in the isolation trench 102 and on the first mask layer 12 using a high-density plasma chemical vapor deposition process. Then, a planarization process, such as chemical mechanical polishing, is used to planarize the spacer 13 so that it is flush with the first mask layer 12. Finally, the spacer 13 located in the second sub-isolation trench 102B is selectively etched to form a second shallow trench isolation structure 13B. The height H1 of the first shallow trench isolation structure 13A in a first direction is greater than the height H2 of the second shallow trench isolation structure in the same first direction, where the first direction refers to the thickness direction of the substrate 10. It should be noted that, in this embodiment, the second shallow trench isolation structure 13B is etched to be lower than the substrate 10. Therefore, the first shallow trench isolation structure 13A is higher than the substrate 10, and the substrate 10 is higher than the second shallow trench isolation structure 13B, so that the portion of the substrate 10 protruding from the second shallow trench isolation structure 13B serves as the fin structure in the fin-like field-effect transistor in region B.

[0060] Step S106: Remove the first mask layer.

[0061] The cross-sectional structure diagram of the semiconductor device after step S106 is shown below. Figure 4I As shown.

[0062] Specifically, in this example, when the first mask layer 12 is made of silicon nitride, it can be removed using hot phosphoric acid.

[0063] Step S107: Form a second gate oxide layer on the second region and the second shallow trench isolation structure.

[0064] Please refer to Figure 2 Specifically, step S107 may include:

[0065] Step S1071: Etch the second oxide layer.

[0066] The cross-sectional structure diagram of the semiconductor device after step S1071 is shown below. Figure 4J As shown.

[0067] Step S1072: A second gate oxide layer is formed on the surface of the substrate in the second region and on the sidewall of the isolation trench.

[0068] The cross-sectional structure diagram of the semiconductor device after step S107 is shown below. Figure 4K As shown.

[0069] Specifically, since region B is used to form a fin-type field-effect transistor, a gate oxide layer surrounding the sidewalls and top surface of the fin-type structure needs to be formed on the corresponding fin-type structure. Due to the aforementioned steps, a second oxide layer 11B is formed on the top surface of the corresponding fin-type structure. In order to form a gate oxide layer of uniform thickness on the corresponding fin-type structure, the second oxide layer 11B is first selectively etched away. Then, a second gate oxide layer 11B' is formed on the surface of the substrate 10 in the second region and on the sidewalls 1021 of the isolation trench 102 through a thermal oxidation process. Since the second gate oxide layer 11B' is formed by an oxidation process rather than an atomic deposition process, the second gate oxide layer 11B' can completely cover the sidewalls 1021 of the isolation trench 102, while only partially covering the second shallow trench isolation structure 13B.

[0070] Please see Figure 3 , Figure 3 This is a flowchart of another semiconductor device manufacturing method provided in an embodiment of the present invention, such as... Figure 3 As shown, the procedure following step S107 further includes:

[0071] Step S108: Form a first gate layer on the surface of the first gate oxide layer.

[0072] Step S109: Form a second gate layer on the surface of the second gate oxide layer.

[0073] The cross-sectional structure diagram of the semiconductor device after step S109 is shown below. Figure 4L And as shown in 4M.

[0074] Specifically, in Figure 4L as well as Figure 4M In order to better illustrate the structure of the second gate layer 14B, at least two adjacent trench isolation structures 13B are shown. Additionally, as... Figure 4M As shown, to better illustrate the isolation effect of the shallow trench isolation structure 13A on adjacent gate structures, two adjacent shallow trench isolation structures 13A are shown, and it can be seen that multiple shallow trench isolation structures are formed in region A. The first gate layer 14A, after patterning etching, is used as the gate of a concave-gate transistor, and the second gate layer 14B, after patterning etching, is used as the gate of a fin-like field-effect transistor. The second gate layer 14B can surround the channel (i.e., the fin-like structure 10B in the figure) from three sides, increasing the control area of ​​the gate on the channel, thus greatly enhancing the gate control capability, thereby effectively suppressing the short-channel effect and reducing the subthreshold leakage current.

[0075] Please see Figures 4A-4M The present invention also provides a semiconductor device 100, which can be formed by the above-described manufacturing method. The semiconductor device 100 includes: a substrate 10, which includes a first region (region A) and a second region (region B). A groove 101 is formed in the first region A; a first shallow trench isolation structure 13A and a second shallow trench isolation structure 13B located in the first region and the second region, respectively. The height H1 of the first shallow trench isolation structure 13A is greater than the height H2 of the second shallow trench isolation structure 13B; a first gate oxide layer 11A located on the groove 101 and a second gate oxide layer 11B' located on the second region and the second shallow trench isolation structure 13B.

[0076] Specifically, the substrate 10 can be made of semiconductor materials such as silicon, germanium, or silicon-on-insulator (SOI). In this embodiment, the substrate 10 may include a first region (region A) and a second region (region B). Region A is a high-voltage device region, used to form the concave-gate transistor in this embodiment of the invention. Region B is a low-voltage device region, which may further include a low-low voltage device region with a lower breakdown voltage than the low-voltage device region. Region B is used to form a fin-type field-effect transistor in this embodiment of the invention, where the gate surrounds the channel from three sides, increasing the gate's control area over the channel and greatly enhancing the gate control capability. This effectively suppresses the short-channel effect and reduces the subthreshold leakage current. Since the high-voltage device region requires a high breakdown voltage, the source-drain junction depth of the device is required to be deep, and the corresponding fin-type structure height is also high. However, existing processes make it difficult to form a three-sided gate structure on a high fin-type structure, so FinFET is not used in region A. The groove 101 facilitates the subsequent formation of a gate with a larger channel length in the first region, thereby mitigating the short-channel effect in the first region.

[0077] The substrate 10 also includes a third region (C region), which has a dicing groove 103 formed thereon.

[0078] The substrate 10 also includes a third region (region C), which serves to isolate the semiconductor device during separation from the wafer and also monitors the process. For example, test patterns can be formed in the third region to monitor process fluctuations (such as photolithography). Specifically, in existing processes, dicing grooves are generally formed by laser etching, thus the formation of the groove 101 is done in steps. However, in this embodiment of the invention, by designing a mask with the patterns of the groove 101 and the dicing groove 103, the groove 101 and the dicing groove 103 are simultaneously formed on the substrate 10 through photolithography and etching processes. Therefore, process steps are saved, which helps to reduce process costs.

[0079] The semiconductor device 100 further includes: a first gate layer 14A located on the surface of the first gate oxide layer 11A; and a second gate layer 14B located on the surface of the second gate oxide layer 11B'.

[0080] Specifically, in Figure 4L as well as Figure 4M In order to better illustrate the structure of the second gate layer 14B, at least two adjacent trench isolation structures 13B are shown. Additionally, as... Figure 4MAs shown, to better illustrate the isolation effect of the shallow trench isolation structure 13A on adjacent gate structures, two adjacent shallow trench isolation structures 13A are shown, and it can be seen that multiple shallow trench isolation structures are formed in region A. The first gate layer 14A, after patterning etching, is used as the gate of a concave-gate transistor, and the second gate layer 14B, after patterning etching, is used as the gate of a fin-like field-effect transistor. The second gate layer 14B can surround the channel (i.e., the fin-like structure 10B in the figure) from three sides, increasing the control area of ​​the gate on the channel, thus greatly enhancing the gate control capability, thereby effectively suppressing the short-channel effect and reducing the subthreshold leakage current.

[0081] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of a three-dimensional storage device provided in an embodiment of the present invention. The three-dimensional storage device 500 includes a storage cell array 502 and peripheral circuitry 501, wherein the peripheral circuitry 501 includes the aforementioned semiconductor device 100. Specifically, the three-dimensional storage device 500 may be a NAND chip.

[0082] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a storage system provided in an embodiment of the present invention. The storage system 600 includes a controller 602 and a three-dimensional storage device 601. The controller 602 is coupled to the three-dimensional storage device 601 and is used to control the three-dimensional storage device 601 to store data. The three-dimensional storage device 601 includes the aforementioned semiconductor device 100. Specifically, the storage system 600 may be a solid-state drive (SSD).

[0083] The semiconductor device and its manufacturing method provided by the present invention, on the one hand, by forming a groove on the first region and forming a first gate oxide layer on the groove, it is beneficial to form a gate with a larger channel length in the first region, thereby mitigating the short-channel effect in the first region; on the other hand, by forming a second shallow trench isolation structure in the second region, making the height of the first shallow trench isolation structure greater than the height of the second shallow trench isolation structure, and forming a second gate oxide layer on the second shallow trench isolation structure, it is beneficial to form a fin-like field-effect transistor in the second region, thereby also mitigating the short-channel effect in the second region.

[0084] In addition to the embodiments described above, the present invention may have other implementations. All technical solutions formed by equivalent substitutions or equivalent replacements fall within the protection scope claimed by the present invention.

[0085] In summary, although the preferred embodiments of the present invention have been disclosed above, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor device, wherein, include: A substrate is provided, the substrate comprising a first region and a second region; A groove is formed in the first region; A first oxide layer located in the first region and a second oxide layer located in the second region are formed to form a first gate oxide layer on the groove; A first mask layer is formed on the first oxide layer and the second oxide layer; A first shallow trench isolation structure and a second shallow trench isolation structure are formed on the first region and the second region, respectively. The height of the first shallow trench isolation structure in the first direction is greater than the height of the second shallow trench isolation structure in the first direction. The first shallow trench isolation structure penetrates the first mask layer and the first gate oxide layer. Remove the first mask layer; A second gate oxide layer is formed on the second region and the second shallow trench isolation structure; After the second gate oxide layer is formed, a first gate layer is formed on the surface of the first gate oxide layer, and the first shallow trench isolation structure extends through the first gate layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein, The substrate further includes a third region; forming a groove in the first region includes: The groove and the scribing groove are formed in the first region and the third region, respectively.

3. The method for manufacturing a semiconductor device according to claim 1, wherein, The step of forming a first shallow trench isolation structure and a second shallow trench isolation structure on the first region and the second region respectively includes: An isolation trench is formed in the substrate; The isolation groove is filled with an isolation material to form a first shallow trench isolation structure in the first region; The separators distributed in the second region are etched to form a second shallow trench isolation structure.

4. The method for manufacturing a semiconductor device according to claim 3, wherein, The formation of the second gate oxide layer located in the second region and the second shallow trench isolation structure includes: The second oxide layer is etched; A second gate oxide layer is formed on the surface of the substrate in the second region and on the sidewalls of the isolation trench.

5. The method for manufacturing a semiconductor device according to claim 1, wherein, The thickness of the first gate oxide layer is greater than the thickness of the second gate oxide layer.

6. The method for manufacturing a semiconductor device according to claim 1, wherein, After forming the second gate oxide layer located in the second region, the method further includes: A second gate layer is formed on the surface of the second gate oxide layer.

7. The method for manufacturing a semiconductor device according to claim 1, wherein, The second gate oxide layer is formed using a thermal oxidation process.

8. The method for manufacturing a semiconductor device according to claim 1, wherein, The material of the first mask layer is silicon nitride.

9. The method for manufacturing a semiconductor device according to claim 1, wherein, The first region is used to form a concave-gate field-effect transistor, and the second region is used to form a fin field-effect transistor.

10. A semiconductor device, wherein, include: A substrate, the substrate comprising a first region and a second region, the first region having a groove formed thereon; A first shallow trench isolation structure and a second shallow trench isolation structure are respectively located in the first region and the second region, wherein the height of the first shallow trench isolation structure in the first direction is greater than the height of the second shallow trench isolation structure in the first direction; A first gate oxide layer located on the groove and a second gate oxide layer located on the second region and the second shallow trench isolation structure, wherein the first shallow trench isolation structure penetrates the first gate oxide layer; The first gate layer is located on the surface of the first gate oxide layer, and the shallow trench isolation structure extends through the first gate layer.

11. The semiconductor device according to claim 10, wherein, The substrate further includes a third region, which has scribe grooves formed thereon.

12. The semiconductor device according to claim 10, wherein, Also includes: The second gate layer is located on the surface of the second gate oxide layer.

13. The semiconductor device according to claim 10, wherein, The first region is used to form a concave-gate field-effect transistor, and the second region is used to form a fin-like field-effect transistor.

14. A three-dimensional storage device, wherein, The three-dimensional storage device includes a storage cell array and peripheral circuitry, wherein the peripheral circuitry includes the semiconductor device as described in claim 10.

15. A storage system, wherein, The device includes a controller and a three-dimensional storage device, the controller being coupled to the three-dimensional storage device and used to control the three-dimensional storage device to store data, the three-dimensional storage device including the semiconductor device as described in claim 10.

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