Dynamic power consumption test device and method for programmable logic device

Abstract

The present invention discloses a method and device for testing dynamic power consumption of a programmable logic device, which comprises: a clock generation unit, a winding resource excitation unit, a winding resource test unit and a current sampling unit connected in sequence, wherein the clock generation unit is used to generate a clock signal with a period flip and transmit it to the winding resource excitation unit, and the winding resource test unit is used to generate different dynamic power consumptions, and the dynamic power consumption value is calculated by sampling the output drive current and the preset voltage of the power supply of the programmable logic device. By testing different winding resource interconnection modes to measure the dynamic power consumption values ​​in each mode, the dynamic power consumption of the interconnection line resources in the programmable logic device FPGA is measured by the interconnection test method, and the dynamic power consumption of the interconnection line in the winding resource FPGA of the programmable logic device can be accurately measured, thereby improving the accuracy of the power consumption analysis and evaluation EDA tool software model of the programmable logic device.

Description

Technical Field

[0001] The present application relates to the field of programmable logic device testing, and in particular to a dynamic power consumption testing device and method for programmable logic devices. Background Art

[0002] Programmable logic devices, or FPGAs, are a type of semi-customized circuit in the field of application-specific integrated circuits and have developed rapidly in recent years. As the scale of FPGAs continues to increase, the reliability issues caused by chip power consumption and heat generation are receiving more and more attention. The power consumption of FPGAs will affect the power supply design and heat dissipation solution of their working systems, and power consumption analysis and testing are required during the project design process.

[0003] In the existing FPGA power consumption modeling methods, theoretical models are established based on the equivalent load of the interconnection line and the number of driving loads, or the power consumption of the interconnection line is included in the logic resources of other unit modules, without modeling and measuring it separately. When constructing the FPGA routing resource vector for power consumption test, the resources of the interconnection line cannot be separated in the test vector. There must be input and output units, logic resources, clocks, etc., so it is difficult to accurately measure the dynamic power consumption of the interconnection line. Summary of the invention

[0004] The present application provides a dynamic power consumption test device and method for a programmable logic device, so as to solve the problem that it is difficult to accurately measure the dynamic power consumption of interconnection lines when constructing a power consumption test programmable logic device wiring resource vector.

[0005] To solve the above technical problems, a technical solution adopted in the present application is: to provide a dynamic power consumption test device for a programmable logic device, which includes: a clock generation unit, a winding resource excitation unit, a winding resource test unit and a current sampling unit connected in sequence.

[0006] The clock generation unit is used to generate a periodically flipped clock signal and transmit it to the winding resource excitation unit. The winding resource excitation unit is used to convert the received clock signal into a flip signal and transmit it to the winding resource testing unit. The winding resource testing unit is used to receive the flip signal and generate different dynamic power consumption according to different preset winding resource interconnection modes. The winding resource interconnection mode refers to the use of different interconnection line connection methods between internal resources of the winding resource to achieve signal transmission between internal resources. The current sampling unit obtains the output drive current of the power supply of the programmable logic device in the current winding resource interconnection mode by sampling, and calculates the dynamic power consumption value based on the drive current and the preset voltage.

[0007] Furthermore, the winding resource test unit also includes an interconnection signal line, and the interconnection signal line connects the winding resource excitation unit and a mux configuration point of the winding resource test unit.

[0008] More specifically, the winding resource test unit also includes an SRB signal alternating connection module and a CLB configurable logic module; the SRB signal alternating connection module is signal-connected to the CLB configurable logic module to achieve signal transmission between internal resources.

[0009] In a specific implementation, the mux configuration points of the winding resource test unit are connected through the interconnected signal lines based on the MUX selection structure relationship.

[0010] In order to solve the above technical problems, a dynamic power consumption test method for a programmable logic device is provided, comprising:

[0011] Corresponding to the Double line, Single line, and Quad line connection modes inside the winding resource test unit, each SRB signal alternately connects the module mux configuration point;

[0012] After configuring each SRB signal alternate connection module mux configuration point in a preset different interconnection signal line connection mode, performing test vector configuration on each SRB signal alternate connection module mux configuration point;

[0013] The clock generation unit and the winding resource excitation unit are used to perform flip excitation within the clock cycle, so that the winding resource test unit after the SRB signal is alternately connected to the module mux configuration point in different interconnection signal line connection modes receives the flip excitation to generate dynamic power consumption;

[0014] The output drive current bit stream file of the programmable logic device power supply of the winding resource test unit is sampled, and the dynamic power consumption value of the winding resource is calculated based on the drive current and the preset voltage.

[0015] The beneficial effect of the present application is: a dynamic power consumption test device for a programmable logic device of the present application comprises: a clock generation unit, a winding resource excitation unit, a winding resource test unit and a current sampling unit connected in sequence, the clock generation unit is used to generate a periodically flipped clock signal and transmit it to the winding resource excitation unit, the winding resource excitation unit is used to convert the received clock signal into a flip signal and transmit it to the winding resource test unit, the winding resource test unit is used to receive the flip signal and generate different dynamic power consumption according to different preset winding resource interconnection modes, the winding resource interconnection mode refers to the use of different interconnection line connection methods between internal resources of the winding resource to realize signal transmission between internal resources, the current sampling unit obtains the output drive current of the power supply of the programmable logic device by sampling and calculates the dynamic power consumption value according to the drive current and the preset voltage. The dynamic power consumption of interconnecting wires in programmable logic devices, i.e., winding resource FPGAs, is measured by testing different interconnection modes of programmable logic devices using a dynamic power consumption test method to obtain dynamic power consumption values ​​in respective modes. The dynamic power consumption of interconnecting wires in programmable logic devices, i.e., winding resource FPGAs, is measured using a winding resource interconnection test method. This method can accurately measure the dynamic power consumption of interconnecting wires in programmable logic devices, i.e., winding resource FPGAs, and improve the accuracy of EDA tool software models for power consumption analysis and evaluation of FPGAs. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of a dynamic power consumption test device for a programmable logic device according to an embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of the wiring resources of a programmable logic device FPGA according to an embodiment of the present invention;

[0018] Figure 3 It is a schematic diagram of the internal connection lines of the programmable logic device FPGA winding resources according to an embodiment of the present invention;

[0019] Figure 4 is a schematic diagram of a ring oscillation generated by a trigger and an inverter according to an embodiment of the present invention;

[0020] Figure 5a -b is a schematic diagram of a single winding circuit to be tested a and an extended test vector b of the circuit to be tested according to an embodiment of the present invention;

[0021] Figure 5c -f is a schematic diagram of power consumption and multiple loads of a common configuration point for winding gating according to an embodiment of the present invention;

[0022] Figure 6 It is a schematic diagram of a dynamic power consumption test method for a programmable logic device according to an embodiment of the present invention;

[0023] Figure 7a-c is a schematic diagram of a MUX gating architecture according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0025] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0026] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0027] Figure 1 The present application provides a dynamic power consumption test device for a programmable logic device, which comprises: a clock generation unit 1, a winding resource excitation unit 2, a winding resource test unit 3 and a current sampling unit 4 which are connected in sequence.

[0028] The clock generation unit 1 is used to generate a periodic flip clock signal and transmit it to the winding resource excitation unit 2. The clock generation unit 1 can be an external clock chip or a crystal oscillator, and the periodic clock signal is input into the FPGA chip through the dedicated clock pin of the programmable logic device, i.e., the FPGA chip. The periodic clock signal can also be generated by the OSC (oscillation circuit) inside the FPGA chip. The signal can be sent to all clock ports inside the FPGA chip through the global clock tree.

[0029] The winding resource excitation unit 2 is used to convert the received clock signal into a flip signal and transmit it to the winding resource test unit 3. Figure 2 The link relationship of the winding resource in the circuit needs to transmit the clock cycle signal to the winding resource test unit 3, referring to Figure 4 , using the ring oscillation generated by the trigger and the inverter, the periodic signal from the clock is divided and then output to the winding resource test unit 3. In this way, the flip signal of the winding resource test unit 3 is obtained.

[0030] Among them, the winding resource testing unit 3 is used to receive the flip signal and generate different dynamic power consumption according to different preset winding resource interconnection modes. The winding resource interconnection mode refers to the use of different interconnection line connection methods between internal resources of the winding resource to realize signal transmission between internal resources.

[0031] In the winding resource test unit 3 inside the FPGA, the winding resource test unit to be tested is composed of a single line across adjacent Block modules, a double line across two Block modules, a Quae line across four Block modules, and other link structures, and there are line types in different directions, as follows Figure 3 Take a single line as an example, select multiple adjacent winding resources, such as Figure 5a As shown, the single lines are linked to form the circuit a to be tested, and the winding resources of different line types, such as single lines across adjacent Block modules, double lines across two Block modules, and Quae lines across four Block modules, are tested. That is, different dynamic power consumption tests are generated for the winding resource test unit according to different winding resource interconnection modes.

[0032] Among them, the current sampling unit obtains the output drive current of the power supply of the programmable logic device in the current winding resource interconnection mode by sampling, and calculates the dynamic power consumption value according to the drive current and the preset voltage. In the winding resources inside the FPGA, the FPGA power consumption is divided into static power consumption and dynamic power consumption. The static power consumption is the power consumption generated by various leakages (leakage) of all circuits of the FPGA chip. The dynamic power consumption is the transient power consumption of the capacitor charging and discharging generated by the signal flipping under normal operation of the chip and the power consumption generated on the equivalent resistance. The current sampling unit samples the external analog signal, that is, samples the output drive current of the dynamic working current of the power supply of the programmable logic device and the known preset voltage and calculates the dynamic power consumption of the winding resource through a simple formula P=UI. The known preset voltage is a conventional parameter of the programmable logic device.

[0033] Specifically, the winding resource test unit that generates dynamic power consumption also includes an SRB signal alternating connection module and a CLB configurable logic module; the SRB signal alternating connection module is signal-connected to the CLB configurable logic module, wherein SRB (Switch Routing Block) is a signal alternating connection module, which is used to realize the function of signal transmission between resources inside the FPGA, and the specific implementation method is to use MUX matrices of various sizes to plan the type, size, and direction of the signal. CLB (Configurable Logic Block) is a CLB configurable logic module.

[0034] Furthermore, the winding resource test unit 3 also includes an interconnection signal line, which connects the logic resources, clock resources, and input and output IO of the winding resource test unit 3 inside the FPGA into a whole to achieve the function of signal transmission, and is a vital part of the resources in the FPGA. For the dynamic power consumption of the FPGA, the power consumption of the interconnection line is an important component. Accurately and effectively testing and analyzing the dynamic power consumption of the interconnection lines in the FPGA is a key link in the dynamic power consumption analysis of the FPGA. The interconnection signal line connects the mux configuration point of the winding resource excitation unit 2 and the winding resource test unit 3, and through the connection of the interconnection signal line, different mux configuration point configurations are tested separately.

[0035] In a specific implementation, the mux configuration points of the winding resource test unit 3 are turned on through the interconnected signal lines based on the MUX selection structure relationship. The mux configuration point winding selection relationship has multiple on-off modes, and the on-off modes of the mux configuration points of the winding resource test unit 3 are converted respectively to meet the test requirements.

[0036] Schematic diagram of a flow chart of a method for testing dynamic power consumption of a programmable logic device according to an embodiment of the present invention. It should be noted that if there are substantially the same results, the method of the present application is not limited to Figure 6 The process sequence shown is limited. Figure 6 As shown, the method comprises the steps of:

[0037] A dynamic power consumption test method for a programmable logic device, comprising:

[0038] Step S1, respectively configure each SRB signal alternate connection module mux configuration point according to the Double line, Single line, and Quad line connection mode inside the winding resource test unit;

[0039] Specifically, in the routing resources inside the FPGA, there are different line types according to the architecture, for example, a single line across adjacent blocks, a double line across two blocks, a Quae line across four blocks, etc. In addition, there are line types according to the selection relationship in different directions; the mux configuration point inside the routing resource test unit can be configured to select the on-off mode inside the resource, and perform dynamic power consumption testing based on the structure of the routing resource.

[0040] Specifically, the configuration points of the SRB signal alternate connection modules mux respectively correspond to the Double line, Single line, and Quad line connection modes inside the winding resource test unit, including:

[0041] S11, switching on and off the SRB signal alternate connection module mux configuration points corresponding to different gating relationships;

[0042] Specifically, Figure 7a -c shows the routing resources based on the MUX gating architecture. The signal passes through the input port, and there can be multiple output ports to output the signal according to the mux configuration point. Usually, a gating path will have two levels of mux configuration points (S_MUX and Z_MUX) to control whether the path is gating. Then, the two levels of mux configuration points can be turned on and off corresponding to different gating relationships.

[0043] S12, performing traversal tests on the connection modes of Double line, Single line and Quad line corresponding to all the SRB signal alternate connection modules.

[0044] Specifically, we can take a single line as an example and select multiple adjacent winding resources. Figure 5a As shown, the single lines are linked together to form the circuit under test a for testing, and the traversal test corresponding to the Double line, Single line, and Quad line connection methods refers to obtaining different dynamic power consumption under different interconnection modes.

[0045] Step S2, after configuring each SRB signal alternate connection module mux configuration point in a preset different interconnection signal line connection mode, test vector configuration is performed on each SRB signal alternate connection module mux configuration point;

[0046] Extending the test vector according to the type of the winding resource and the test purpose, configuring the test vector for each SRB signal alternate connection module mux configuration point includes:

[0047] Step S21, by modifying the SRB signal alternate connection module to disconnect the mux configuration point at the first-level SRB signal alternate connection module connected to the excitation output, the signal is disconnected inside the first-level SRB signal alternate connection module;

[0048] According to the structure of the winding gating resource, taking the winding resource test unit of a single line as an example, in order to measure the dynamic power consumption of the winding resource, it is necessary to design an incremental extended test vector b. By modifying the configuration point of the SRB at the first level SRB connected to the stimulus output, the signal is disconnected inside the SRB, such as Figure 5b shown.

[0049] Step S22: Modify the SRB signal to alternately connect the module mux configuration points to a load number of 3, and output the driving load power consumption.

[0050] In order to test the fan out of the driving load power consumption of the winding resource, the configuration point expansion vector c is modified, refer to Figure 5f As shown, by modifying the configuration point of each SRB signal alternately connected module on the test circuit, the load number of each SRB signal alternately connected module is set to 3 for testing.

[0051] Because the dynamic current generated by a single test circuit is very small, it is difficult to collect current signals using analog sampling circuits. Therefore, it is necessary to use software means to use the different interconnection modes of the winding resource test units connected to the above test configuration as a template, and expand and cover the entire FPGA chip according to the structure and scale of the winding resource test units of the programmable logic device FPGA chip. Then use the software to layout the winding and generate a programmable downloadable bitstream file.

[0052] Step S3, using the clock generation unit and the winding resource excitation unit to perform flip excitation within the clock cycle, so that the winding resource test unit after the SRB signal alternately connected to the module mux configuration point in different interconnection signal line connection modes receives the flip excitation to generate dynamic power consumption;

[0053] The clock generation unit generates a clock cycle signal, and operates in different SRB signal alternating connection mode connection configuration modes to generate dynamic power consumption.

[0054] Step S4, sampling the output drive current bit stream file of the programmable logic device FPGA chip power supply of the winding resource test unit, and calculating the dynamic power consumption value of the winding resource according to the drive current and the preset voltage.

[0055] The multiple test circuit bitstream files generated in step S3 are downloaded to the FPGA chip through the programming download tool, the FPGA chip is powered on, and the clock output is turned on. The FPGA chip test circuit works with the excitation corresponding to the reference clock frequency. At this time, the total current P (total) of the current working is collected through the analog sampling circuit. This current includes a static current component P (static) and a dynamic current component P (dynamic). The dynamic current component includes the power consumption P (io) of the basic input and output unit IO, the clock tree power consumption P (clk), the logic resource power consumption P (logic) and the winding resource power consumption P (routing).

[0056] (1)P(total)=P(static)+P(dynamic);

[0057] (2)P(dynamic)=P(io)+P(clk)+P(logic)+P(routing).

[0058] Furthermore, by sampling the output drive current bit stream file of the programmable logic device FPGA power supply, the dynamic power consumption of the winding resources is calculated, and the dynamic power consumption of the winding resources under different voltage conditions and frequencies is measured by changing the power supply voltage or clock frequency, and the dynamic power consumption data of the winding resources is calculated and extracted:

[0059] The winding resource test unit has a different winding connection structure when configured, but the other parts are exactly the same. Figure 5a As shown in Figure 2 and Figure 2, compared with circuit b, circuit a has more winding resources than circuit b, but the number of other resources is the same and the structure and signal flipping during operation are the same, so:

[0060] (3)δP(ab)=P(a)–P(b)=n*P(routing);

[0061] Where: n represents the number of routing resources between test circuits a and b, and P (routing) is the power consumption of a single routing resource.

[0062] Figure 5a As shown in Figure 2 and Figure 3, for test vectors a and c, the number of fan-outs of the driving load of the winding resources is different, but the other circuit structures, resources, and signal flips during operation are consistent, so:

[0063] (4) δP(ca)=P(c)–P(a)=n*P(fan out=2);

[0064] Wherein: n represents the number of single winding resources in the test circuits a and c, and P (fan out = 2) represents the dynamic power consumption when the number of load fan outs driven by the winding resources is equal to 2.

[0065] By dividing the power consumption difference δP of the incremental test circuit by the number of corresponding types of winding resources in the test circuit, the dynamic power consumption of a single winding resource in the FPGA chip can be obtained.

[0066] By changing the power supply voltage or clock frequency, the dynamic power consumption of the routing resources under different voltage conditions and frequencies can be measured. By changing the connection mode of different interconnect signal lines, the dynamic power consumption of different types of routing resources can be measured.

[0067] Furthermore, by sampling the output drive current bit stream file of the programmable logic device FPGA power supply and calculating the dynamic power consumption of the winding resources based on the drive current and the preset voltage, it also includes extending the internal enable and disable of the winding enable MUX resources to test the power consumption of the shared configuration points of the winding resources and the fan-out power consumption of multiple loads. Figure 5c -e, according to the internal winding resource architecture of FPGA, find the corresponding winding resource type starting from the input port, then find the corresponding configuration point according to the relationship between the internal path and configuration point of the winding MUX resource and set the corresponding configuration point according to the winding type to be tested, and test the power consumption of the shared configuration point of the winding resource and the fan-out power consumption of multiple loads.

[0068] Finally, according to the number of resources inside the programmable logic device FPGA, the full chip test is completed by changing the different interconnection routing mode planning. After the full chip test is completed, the internal gating and cutoff of the extended routing gating MUX resources are used to test the power consumption of the shared configuration points of the routing resources and the fan-out power consumption of multiple loads, such as Figure 5c -e as shown, the different bitstream files generated by the above configuration test are obtained for subsequent analysis.

[0069] The present application discloses a dynamic power consumption test device for a programmable logic device, comprising: a clock generation unit, a winding resource excitation unit, a winding resource test unit and a current sampling unit connected in a corresponding manner, wherein the clock generation unit is used to generate a periodically flipped clock signal and transmit it to the winding resource excitation unit, the winding resource excitation unit is used to convert the received clock signal into a flip signal and transmit it to the winding resource test unit, the winding resource test unit is used to receive the flip signal and generate different dynamic power consumption according to different preset winding resource interconnection modes, the winding resource interconnection mode refers to the use of different interconnection line connection methods between internal resources of the winding resource to realize signal transmission between internal resources, and the current sampling unit samples and obtains the output drive current of the power supply of the programmable logic device, and calculates the dynamic power consumption value according to the drive current. Different winding resource interconnection modes are tested by the dynamic power consumption test method for programmable logic devices to measure the dynamic power consumption values ​​in each mode. The dynamic power consumption of the interconnection line resources in the winding resource FPGA of the programmable logic device is measured by the winding resource interconnection test method. The dynamic power consumption of the interconnection lines in the winding resource FPGA of the programmable logic device can be measured accurately, thereby improving the accuracy of the power consumption analysis and evaluation EDA tool software model of the programmable logic device FPGA.

[0070] In the several embodiments provided in the present application, it should be understood that the disclosed terminals, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0071] In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of software functional units. The above is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the description and drawings of this application, or directly or indirectly used in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A dynamic power consumption test device for a programmable logic device, characterized in that: It includes: A clock generation unit, a winding resource excitation unit, a winding resource testing unit and a current sampling unit connected in sequence; The clock generation unit is used to generate a periodically flipped clock signal and transmit it to the winding resource excitation unit, the winding resource excitation unit is used to convert the received clock signal into a flip signal and transmit it to the winding resource testing unit, the winding resource testing unit is used to receive the flip signal and generate different dynamic power consumption according to different preset winding resource interconnection modes, the current sampling unit samples and obtains the output drive current of the power supply of the programmable logic device in the current winding resource interconnection mode, and calculates the dynamic power consumption value according to the drive current and the preset voltage; The different winding resource interconnection modes are that different interconnection line connection modes are used between internal resources of the winding resources to realize signal transmission between internal resources.

2. The dynamic power consumption test device according to claim 1, characterized in that: The winding resource testing unit further comprises an interconnection signal line, wherein the interconnection signal line connects the winding resource excitation unit and a mux configuration point of the winding resource testing unit.

3. The dynamic power consumption test device according to claim 2, characterized in that: The mux configuration points of the winding resource test unit are turned on through the interconnected signal lines based on the MUX gating structure relationship.

4. The dynamic power consumption test device according to claim 1, characterized in that: The winding resource test unit also includes an SRB signal alternating connection module and a CLB configurable logic module; the SRB signal alternating connection module is signal-connected to the CLB configurable logic module to achieve signal transmission between internal resources.

5. A dynamic power consumption test method for a programmable logic device, characterized in that: include: Corresponding to the Double line, Single line, and Quad line connection modes inside the winding resource test unit, each SRB signal alternately connects the module mux configuration point; After configuring each SRB signal alternate connection module mux configuration point in a preset different interconnection signal line connection mode, performing test vector configuration on each SRB signal alternate connection module mux configuration point; The clock generation unit and the winding resource excitation unit are used to perform flip excitation within the clock cycle, so that the winding resource test unit after the module mux configuration point is configured with each SRB signal alternately connected in different interconnection signal line connection modes receives the flip excitation to generate dynamic power consumption; The output drive current bit stream file of the programmable logic device power supply of the winding resource test unit is sampled, and the dynamic power consumption value of the winding resource is calculated based on the drive current and the preset voltage.

6. The method according to claim 5, characterized in that Corresponding to the Double line, Single line, and Quad line connection modes inside the winding resource test unit, the SRB signal alternate connection module mux configuration points are configured separately, including: The SRB signal alternate connection module mux configuration points are switched on and off corresponding to different MUX gating structure relationships; A traversal test is performed on all the SRB signal alternate connection modules corresponding to the Double line, Single line, and Quad line connection modes.

7. The method according to claim 5, characterized in that Performing test vector configuration on each SRB signal alternate connection module mux configuration point includes: By modifying the SRB signal alternate connection module, the mux configuration point at the first-level SRB signal alternate connection module connected to the excitation output is in a disconnected state, and the signal is disconnected inside the first-level SRB signal alternate connection module; By modifying the SRB signal, the module mux configuration point is alternately connected to be in a load number 3 state, and the output drives the load power consumption.

8. The method according to claim 5, characterized in that The step of calculating the dynamic power consumption of the winding resources by sampling the output drive current bit stream file of the programmable logic device power supply also includes: extending the internal enable and disable of the winding enable MUX resources to test the power consumption of the shared configuration points of the winding resources and the fan-out power consumption of multiple loads.

9. The method according to claim 5, characterized in that The dynamic power consumption of the winding resources is obtained by sampling the output drive current bit stream file of the programmable logic device power supply and calculating the dynamic power consumption of the winding resources based on the drive current and the preset voltage. The dynamic power consumption of the winding resources under different voltage conditions and frequencies is measured by changing the power supply voltage or clock frequency, and the dynamic power consumption data of the winding resources is calculated and extracted.

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