Data processing method, device and computer-readable storage medium based on SCM

Abstract

The present invention provides a data processing method, device and computer-readable storage medium based on SCM, the method comprising: a main processor unit executes a first instruction obtained from a random access memory unit, the first instruction is used to make the main processor unit write preset data to the second storage area of ​​a flash memory unit through a memory control unit, and the first instruction is mapped from the first storage area of ​​the flash memory unit to the random access memory unit by the memory control unit; a coprocessor unit executes a second instruction obtained from the random access memory unit, the second instruction is used to make the coprocessor unit perform a logical operation on the preset data obtained from the second storage area, and write the logical operation result to the third storage area of ​​the flash memory unit through the memory control unit, and the second instruction is mapped from the fourth storage area of ​​the flash memory unit to the random access memory unit by the memory control unit. The present invention can maximize the performance of the main processor unit and the coprocessor unit.

Description

Technical Field

[0001] The present invention relates to the field of computer data processing, and more specifically, to a data processing method and device based on SCM and a computer-readable storage medium. Background Art

[0002] At present, DRAM (Dynamic Random Access Memory) includes synchronous dynamic random access memory (SDRAM), double data rate (DDR) SDRAM, second generation double data rate (DDR2) SDRAM, third generation double data rate (DDR3) SDRAM and fourth generation double data rate (DDR4) SDRAM and other types, which are widely used in various computer systems. When these computer systems execute programs, the relevant programs and data executed by the CPU (central processing unit) must be placed in DRAM first. When executing the program, the CPU fetches instructions from DRAM and executes them according to the contents of the current program pointer register, and then fetches the next instruction and executes it, and so on until the program ends. The execution stops. Its working process is the process of continuously fetching and executing instructions, and finally putting the calculated results into the memory address specified by the instruction.

[0003] However, due to the high cost of DRAM, its storage capacity is usually limited, so most programs are stored in relatively low-cost large-capacity storage devices, such as hard disks, solid-state drives, etc. When the computer is running, the CPU needs to move the data in the large-capacity storage device to DRAM, and write the data in DRAM to the large-capacity storage device. In addition, because the interaction speed between the large-capacity storage device and the central processing unit is much lower than the interaction speed between the central processing unit and DRAM, the overall operating efficiency of the computer system is greatly affected.

[0004] In addition, in some computer systems, in order to improve the efficiency of program execution, a coprocessor is usually used to assist the main processor to process parts of the program that the main processor cannot execute or executes inefficiently. However, in such computer systems, the output processing of the coprocessor is controlled and executed by the main processor, resulting in the inability to maximize the performance of the main processor and the coprocessor. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a data processing method, device and computer-readable storage medium based on SCM in view of the problem that the performance of the main processor and the coprocessor cannot be fully utilized in the above-mentioned computer system in which the main processor and the coprocessor cooperate.

[0006] The technical solution of the present invention to solve the above technical problem is to provide a data processing method based on SCM, wherein the SCM includes a random access memory unit, a memory control unit and a flash memory unit, and the method includes:

[0007] The main processor unit executes a first instruction obtained from the random access memory unit, wherein the first instruction is used to enable the main processor unit to write preset data into the second storage area of ​​the flash memory unit through the memory control unit, and the first instruction is mapped from the first storage area of ​​the flash memory unit to the random access memory unit by the memory control unit;

[0008] The coprocessor unit executes a second instruction obtained from the random access memory unit, wherein the second instruction is used to enable the coprocessor unit to perform a logical operation on the preset data obtained from the second storage area, and write the logical operation result to the third storage area of ​​the flash memory unit through the memory control unit, and the second instruction is mapped from the fourth storage area of ​​the flash memory unit to the random access memory unit by the memory control unit.

[0009] As a further optimization of the present invention, the method further comprises:

[0010] The main processor unit executes a third instruction obtained from the random access memory unit, and the third instruction is used to enable the main processor unit to read the logical operation result of the third storage area of ​​the flash memory unit through the memory control unit, and the third instruction is mapped from the first storage area of ​​the flash memory unit to the random access memory unit by the memory control unit.

[0011] As a further optimization of the present invention, the preset data is external input data obtained by the main processor unit from an input device or a network device;

[0012] The method also includes: the main processor unit executes a fourth instruction obtained from the random access memory unit, the fourth instruction is used to enable the main processor unit to output the logic operation result, and the fourth instruction is mapped by the memory control unit from the first storage area of ​​the flash memory unit to the random access memory unit.

[0013] As a further optimization of the present invention, the method further comprises:

[0014] The main processor unit executes a fifth instruction input by an input device or a network device, and the fifth instruction is used to enable the main processor unit to generate a new second instruction and write the new second instruction into the fourth storage area of ​​the flash memory unit through the memory control unit and replace the original second instruction in the fourth storage area.

[0015] As a further optimization of the present invention, the method further comprises:

[0016] The main processor unit executes a fifth instruction obtained from the random access memory unit, the fifth instruction is used to enable the main processor unit to generate a new second instruction and write the new second instruction to the fourth storage area of ​​the flash memory unit through the memory control unit and replace the original second instruction in the fourth storage area, and the fifth instruction is mapped from the first storage area of ​​the flash memory unit to the random access memory unit by the memory control unit.

[0017] As a further optimization of the present invention, the coprocessor unit is a graphics processor or an embedded neural network processor, and the second instructions include operating system instructions of the coprocessor unit and artificial intelligence algorithm instructions for execution by the coprocessor unit.

[0018] As a further optimization of the present invention, the random access memory unit includes a first random access memory and a second random access memory;

[0019] The method further comprises:

[0020] The memory control unit reads and feeds back a corresponding first instruction from the first random access memory according to a request of the main processor unit, and when the first instruction in the first random access memory meets a first preset condition, obtains a subsequent instruction set of the first instruction from the first storage area of ​​the flash memory unit and writes the subsequent instruction set into the first random access memory;

[0021] The memory control unit reads and feeds back the corresponding second instruction from the second random access memory according to the request of the coprocessor unit, and when the second instruction in the second random access memory meets the second preset condition, obtains the subsequent instruction of the second instruction from the fourth storage area of ​​the flash memory unit and writes it into the second random access memory.

[0022] As a further optimization of the present invention, the random access memory unit includes a first random access memory and a second random access memory, and the memory control unit includes a first memory controller and a second memory controller;

[0023] The method further comprises:

[0024] The first memory control unit reads and feeds back a corresponding first instruction from the first random access memory according to a request of the main processor unit, and when the first instruction in the first random access memory meets a first preset condition, obtains a subsequent instruction set of the first instruction from the first storage area of ​​the flash memory unit and writes it into the first random access memory;

[0025] The second memory control unit reads and feeds back the corresponding second instruction from the second random access memory according to the request of the coprocessor unit, and when the second instruction in the second random access memory meets the second preset condition, obtains the subsequent instruction of the second instruction from the fourth storage area of ​​the flash memory unit and writes it into the second random access memory.

[0026] As a further optimization of the present invention, the random access memory unit includes a first mapping area and a second mapping area;

[0027] The method further comprises:

[0028] The memory control unit reads and feeds back the corresponding first instruction from the first mapping area according to the request of the main processor unit, and when the first instruction in the first mapping area meets the first preset condition, obtains a subsequent instruction set of the first instruction from the first storage area of ​​the flash memory unit and writes it into the first mapping area;

[0029] The memory control unit reads and feeds back the corresponding second instruction from the second mapping area according to the request of the coprocessor unit, and when the second instruction in the second mapping area meets the second preset condition, obtains the subsequent instruction of the second instruction from the fourth storage area of ​​the flash memory unit and writes it into the second mapping area.

[0030] As a further optimization of the present invention, the random access memory unit, the memory control unit and the flash memory unit are packaged together to form an SCM chip.

[0031] The present invention also provides a data processing device based on SCM, including a main processor, a coprocessor and an SCM, and the SCM includes a random access memory unit, a memory control unit and a flash memory unit, the flash memory unit stores a computer program that can be executed in the main processor and the coprocessor, and when the main processor and the coprocessor execute the computer program, the steps of the data processing method based on SCM as described above are implemented.

[0032] The present invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the steps of the SCM-based data processing method as described above.

[0033] The present invention has the following beneficial effects: the main processor unit writes preset data into the flash memory unit of the SCM, the coprocessor unit directly obtains instructions and data from the flash memory unit, and writes the processing results back to the flash memory unit for further processing by the main processor unit, so that the data processing process of the coprocessor unit is independent of the main processor unit, thereby maximizing the performance of the main processor unit and the coprocessor unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a flow chart of a data processing method based on SCM provided by an embodiment of the present invention;

[0035] Figure 2 is a structural schematic diagram of a device for executing the SCM-based data processing method provided in an embodiment of the present invention;

[0036] Figure 3 is a schematic diagram of data flow in a data processing method based on SCM provided by an embodiment of the present invention;

[0037] Figure 4 is a flow chart of a data processing method based on SCM provided by another embodiment of the present invention;

[0038] Figure 5 It is a schematic diagram of a data processing device based on SCM provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0040] The SCM-based data processing method of the present invention can be applied to electronic devices having SCM (Storage Class Memory), a main processor unit and a coprocessor unit, such as a personal computer, a server, a mobile phone, a tablet, etc. Figure 2As shown, the SCM 23 includes a random access memory unit 231, a memory control unit 232, and a flash memory unit 233. In the SCM 23, the random access memory unit 231 is electrically connected (for example, through an internal bus) to the memory control unit 232, and the memory control unit 232 is also electrically connected to the flash memory unit 233 (for example, through an internal bus). The random access memory unit 15 maps part of the storage space in the flash memory unit 233 through the memory control unit 13. During the operation of the SCM 23, the random access memory unit 231 stores the data and instructions that the processor is currently executing or about to execute, while the flash memory unit 233 is used to store data and instructions that need to be stored for a long time.

[0041] In one embodiment of the present invention, the random access memory unit 231, the memory control unit 232, and the flash memory unit 233 can be integrated into the same SCM chip, which includes a unified external interface and is installed on a circuit board (such as a motherboard of a computer system) through the external interface, thereby exchanging data with the main processor unit 21 and the coprocessor unit 22 through the computer's memory bus.

[0042] In practical applications, the random access memory unit 231, the memory control unit 232, the flash memory unit 233, the main processor unit 21, and the coprocessor unit 22 can be integrated into the same processor chip, which includes a unified external interface and is installed on a circuit board (such as a motherboard of a computer system) through the external interface, so that it can communicate with external devices (such as a network adapter, input and output devices, etc.) through the circuit board to achieve signal input and output operations. Alternatively, the random access memory unit 231, the memory control unit 232, and the flash memory unit 233 can also be integrated into multiple chips respectively, and these chips are assembled / welded to the same circuit board, and are electrically connected through the circuit board and provide a unified external interface, and then plugged into the motherboard of the computer through the external interface, so as to exchange data with the main processor unit 21 and the coprocessor unit 22 on the motherboard of the computer.

[0043] In one embodiment of the present invention, the flash memory unit 233 may specifically use a NAND memory chip with a relatively large storage capacity, relatively low cost, and relatively slow data access speed, which can save data in a power-off state; the random access memory unit 231 may specifically use a DDR, DDR2, DDR3, DDR4, DDR5 or phase change memory memory chip with a relatively small storage capacity, relatively high cost, and relatively fast data access speed, that is, the data storage capacity of the random access memory unit 231 is smaller than the data storage capacity of the flash memory unit 16. Considering the cost factor, the random access memory unit 231 preferably uses a memory chip that cannot retain the stored data when the power is off.

[0044] The storage data of the flash memory unit 233 with larger storage capacity and lower cost is mapped to the random access memory unit 231 with smaller storage capacity and higher cost through the memory control unit 232, and the above-mentioned mapping operation does not occupy the clock cycle of the main processor unit 21, and the memory bus between the main processor unit 21 and the random access memory unit 231. High-speed data processing can be achieved when the storage capacity of the random access memory unit 231 is small, so that the main processor unit 21 can always be in an efficient operating state, greatly improving the operating efficiency of electronic devices such as computer systems.

[0045] like Figure 1 FIG. 1 is a flow chart of a data processing method based on SCM provided by an embodiment of the present invention, the method comprising:

[0046] Step S11: The main processor unit 21 executes the first instruction obtained from the random access memory unit 231, and the first instruction is mapped from the first storage area of ​​the flash memory unit 233 to the random access memory unit 231 by the memory control unit 232. The first storage area is dedicated to storing instructions and data for execution by the main processor unit 21, such as the operating system and algorithm of the main processor unit 21.

[0047] The first instruction is used to make the main processor unit 21 write the preset data to the second storage area of ​​the flash memory unit 233 through the memory control unit 232, that is, when the main processor unit 21 executes the first instruction, the preset data is written to the second storage area of ​​the flash memory unit 233 through the memory control unit 232. The second storage area is used to store data for execution by the main processor unit 21 and the coprocessor unit 22 at the same time, that is, the second storage area is a shared storage area of ​​the main processor unit 21 and the coprocessor unit 22. The data in the second storage area can be mapped to the random access memory unit 231 through the memory control unit 232 so that the coprocessor unit 22 can read it. In actual applications, the preset data can be data received through a network device, data input through an input device, or data stored in the flash memory unit 233, etc.

[0048] In one embodiment of the present invention, the memory control unit 232 can read and feedback corresponding data and instructions from the random access memory unit 231 according to the request of the main processor unit 21, that is, when the memory control unit 232 receives the read / write request of the main processor unit 21, it obtains the data or instructions corresponding to the read / write request from the random access memory unit 231 and sends the data or instructions corresponding to the read / write request to the main processor unit 21 through the memory bus, and writes the execution result of the main processor unit 21 to the random access memory unit 231. The above operation process is the same as the data interaction process between the existing processor and the internal memory (such as DRAM), which will not be repeated here.

[0049] Step S12: The coprocessor unit 22 executes the second instruction obtained from the random access memory unit 231, and the second instruction is mapped from the fourth storage area of ​​the flash memory unit 233 to the random access memory unit 231 by the memory control unit 232. The fourth storage area is dedicated to storing instructions and data for execution by the coprocessor unit 22, such as the operating system or algorithm of the coprocessor unit 22.

[0050] The second instruction is used to make the coprocessor unit 22 perform a logic operation on the preset data obtained from the second storage area, and write the logic operation result to the third storage area of ​​the flash memory unit 233 through the memory control unit 232. The third storage area is used to store data for execution by the main processor unit 21 and the coprocessor unit 22 at the same time, that is, the third storage area is a shared storage area of ​​the main processor unit 21 and the coprocessor unit 22. The data in the third storage area can be mapped to the random access memory unit 231 through the memory control unit 232 so that the main processor unit 21 can read it.

[0051] In one embodiment of the present invention, the memory control unit 232 can read and feed back corresponding data and instructions from the random access memory unit 231 according to the request of the coprocessor unit 22, that is, when the memory control unit 232 receives the read / write request of the coprocessor unit 22, it obtains the data or instructions corresponding to the read / write request from the random access memory unit 231 and sends the data or instructions corresponding to the read / write request to the coprocessor unit 22 through the memory bus, and writes the execution result of the coprocessor unit 22 to the random access memory unit 231. The above operation process is the same as the data interaction process between the existing processor and the internal memory (such as DRAM), which will not be repeated here.

[0052] In the above-mentioned SCM-based data processing method, the main processor unit 21 writes preset data into the flash memory unit 233 of the SCM, and the coprocessor unit 22 directly obtains instructions and data from the flash memory unit 233, and writes the processing results back to the flash memory unit 233 for further processing by the main processor unit 21, so that the data processing of the coprocessor unit 22 and the execution process of the main processor unit are independent of each other, thereby maximizing the performance of the main processor unit 21 and the coprocessor unit 22.

[0053] In one embodiment of the present invention, the coprocessor unit 22 is a graphics processor, an embedded neural network processor or other similar processors, and the second instruction includes an operating system instruction of the coprocessor unit 22 and an artificial intelligence algorithm instruction for execution by the coprocessor unit 22. In this embodiment, the main processor unit 21 can write the original data that needs to execute the artificial intelligence algorithm into the shared storage area of ​​the flash memory unit 233 of the SCM 23, and the coprocessor unit 22 directly obtains the original data from the above-mentioned shared storage area and executes the artificial intelligence algorithm, and then writes the label data obtained by executing the artificial intelligence algorithm back to the shared storage area of ​​the flash memory unit 233 for further processing by the main processor unit 21.

[0054] In one embodiment of the present invention, the random access memory unit 231 may include a first random access memory and a second random access memory that are independent of each other, wherein the first random access memory is used for access by the main processor unit 21, and the second random access memory is used for access by the coprocessor unit 22. The memory control unit 232 reads and feeds back the corresponding first instruction from the first random access memory according to the request of the main processor unit 21, and when the first instruction in the first random access memory meets the first preset condition, obtains the subsequent instruction set of the above-mentioned first instruction from the first storage area of ​​the flash memory unit 233 and writes it to the first random access memory; the memory control unit 232 reads and feeds back the corresponding second instruction from the second random access memory according to the request of the coprocessor unit 22, and when the second instruction in the second random access memory meets the second preset condition, obtains the subsequent instruction of the second instruction from the fourth storage area of ​​the flash memory unit 233 and writes it to the second random access memory.

[0055] Specifically, the first preset condition may be (i.e., the memory control unit 232 may map the first instruction in the flash memory unit 233 to the first random memory in the following manner): when the number of first instructions in the first random memory waiting to be read by the main processor unit 21 is less than a preset value, or when the time for executing the first instruction in the first random memory waiting to be read in the main processor unit 21 is expected to be less than a preset time, the memory control unit 232 obtains the subsequent instruction set of the first instruction from the first storage area in the flash memory unit 233, and updates and stores the subsequent instruction set of the first instruction in the first random memory. Thus, the data instructions in the first random memory can be updated in time without affecting the operation of the main processor unit 21.

[0056] Similarly, the second preset condition may be (i.e., the memory control unit 232 may map the second instruction in the flash memory unit 233 to the second random memory in the following manner): when the number of second instructions in the second random memory waiting to be read by the coprocessor unit 22 is less than a preset value, or when the estimated execution time of the second instruction in the second random memory waiting to be read in the coprocessor unit 22 is less than a preset time, the memory control unit 232 obtains the subsequent instruction set of the second instruction from the fourth storage area of ​​the flash memory unit 233, and updates and stores the subsequent instruction set of the second instruction in the second random memory. Thus, the instructions in the second random memory can be updated in time without affecting the operation of the coprocessor unit 22.

[0057] Since the memory control unit 232 can directly predict the subsequent instruction set that needs to be executed according to the instruction set being executed by the main processor unit 21 and the coprocessor unit 22, and update the content in the random access memory unit 231 according to the prediction result, the main processor unit 21 and the coprocessor unit 22 do not need to interact with the flash memory unit 233, and the memory bus will not be occupied. That is, for the main processor unit 21 and the coprocessor unit 22, the operation of the above-mentioned memory control unit 232 is transparent, and the data movement operation of the random access memory unit 231 does not require the participation of the main processor unit 21 and the coprocessor unit 22, and does not need to allocate time management. The main processor unit 21 and the coprocessor unit 22 only use the random access memory unit 231 and the flash memory unit 233 as an extra-large DRAM, and the data is permanently and automatically solidified. As a result, the main processor unit 21 and the coprocessor unit 22 can always be in an efficient operating state, which is suitable for fields with high requirements for computing resources such as cloud computing, and can greatly improve the operating efficiency of the system.

[0058] In practical applications, the random access memory unit 231 may include a first random access memory and a second random access memory that are independent of each other, and accordingly, the memory control unit 232 may also include a first memory controller and a second memory controller that are independent of each other. At this time, the first memory control unit reads and feeds back the corresponding first instruction from the first random access memory according to the request of the main processor unit 21, and when the first instruction in the first random access memory meets the first preset condition, obtains the subsequent instruction set of the first instruction from the first storage area of ​​the flash memory unit 233 and writes it to the first random access memory; the second memory control unit reads and feeds back the corresponding second instruction from the second random access memory according to the request of the coprocessor unit 22, and when the second instruction in the second random access memory meets the second preset condition, obtains the subsequent instruction of the second instruction from the fourth storage area of ​​the flash memory unit 233 and writes it to the second random access memory.

[0059] In addition, the random access memory unit 231 may also be composed of a single physical memory, which includes a first mapping area and a second mapping area, wherein the first mapping area is used to cache instructions and data for execution by the main processor unit 21, and the second mapping area is used to cache instructions and data for execution by the coprocessor unit 22. That is, the memory control unit 232 reads and feeds back the corresponding instruction (e.g., the first instruction) from the first mapping area of ​​the random access memory unit 231 according to the request of the main processor unit 21, and when the first instruction in the first mapping area meets the first preset condition, obtains the subsequent instruction set of the above-mentioned first instruction from the first storage area of ​​the flash memory unit 233 and writes it to the first mapping area; the memory control unit 232 reads and feeds back the corresponding second instruction from the second mapping area of ​​the random access memory unit 231 according to the request of the coprocessor unit 22, and when the second instruction in the second mapping area meets the second preset condition, obtains the subsequent instruction of the second instruction from the fourth storage area of ​​the flash memory unit 233 and writes it to the second mapping area.

[0060] In another embodiment of the present invention, the data processing method based on SCM can perform logical operations (such as AI operations, etc.) on external input data (such as data from a network or input device). Figure 3-4 As shown, the method includes:

[0061] Step S41: The main processor unit 21 executes the first instruction obtained from the random access memory unit 231, and the first instruction is mapped from the first storage area of ​​the flash memory unit 233 to the random access memory unit 231 by the memory control unit 232. The above-mentioned first instruction is used to enable the main processor unit 21 to write the preset data to the second storage area of ​​the flash memory unit 233 through the memory control unit 232, that is, when the main processor unit 21 executes the first instruction, the preset data is written to the second storage area of ​​the flash memory unit 233 through the memory control unit 232.

[0062] Step S42: The coprocessor unit 22 executes the second instruction obtained from the random access memory unit 231, and the second instruction is mapped from the fourth storage area of ​​the flash memory unit 233 to the random access memory unit 231 by the memory control unit 232. The second instruction is used to enable the coprocessor unit 22 to perform a logic operation on the preset data obtained from the second storage area, and write the logic operation result to the third storage area of ​​the flash memory unit 233 through the memory control unit 232.

[0063] Step S43: The main processor unit 21 executes the third instruction obtained from the random access memory unit 231, and the third instruction is mapped from the first storage area of ​​the flash memory unit 233 to the random access memory unit 231 by the memory control unit 232. The third instruction is used to enable the main processor unit 21 to read the logic operation result of the third storage area of ​​the flash memory unit 233 through the memory control unit, that is, when the main processor unit 21 executes the third instruction, it obtains the logic operation result written by the coprocessor unit 22 from the third storage area of ​​the flash memory unit 233 through the memory control unit 232.

[0064] Step S44: the main processor unit 21 executes the fourth instruction obtained from the random access memory unit 231, and the fourth instruction is mapped from the first storage area of ​​the flash memory unit 233 to the random access memory unit 231 by the memory control unit 232. The fourth instruction is used to make the main processor unit 21 output the logic operation result, that is, when the main processor unit 21 executes the fourth instruction, it outputs the logic operation result obtained in step S43.

[0065] The above-mentioned SCM-based data processing method can be applied to network data processing, such as cloud computing, etc. Through the cooperation of the main processor unit 21 and the coprocessor unit 22, the main processor unit 21 and the coprocessor unit 22 each exert their maximum performance to achieve efficient network data processing.

[0066] In one embodiment of the present invention, when the logic operation method of the coprocessor unit 22 needs to be updated (for example, a better logic operation method appears), the logic operation method of the coprocessor 22 can be updated in the following manner:

[0067] The main processor unit 21 executes the fifth instruction input by the input device or network equipment, and the fifth instruction is used to enable the main processor unit 21 to generate a new second instruction and write the new second instruction into the fourth storage area of ​​the flash memory unit 233 through the memory control unit to replace the original second instruction in the fourth storage area.

[0068] In addition, when the logic operation method of the coprocessor unit 22 needs to be switched (for example, in the main program of the main processor unit 21, it is necessary to switch from the accelerated operation of the image segmentation algorithm to the accelerated operation of the image recognition algorithm), the logic operation method of the coprocessor 22 can be updated in the following manner:

[0069] The main processor unit 21 executes the fifth instruction obtained from the random access memory unit 231, and the fifth instruction is mapped from the first storage area of ​​the flash memory unit 233 to the random access memory unit 231 by the memory control unit 232. The fifth instruction is used to enable the main processor unit 21 to generate a new second instruction and write the new second instruction to the fourth storage area of ​​the flash memory unit 233 through the memory control unit 232 to replace the original second instruction in the fourth storage area.

[0070] Before the main processor unit 21 executes the fifth instruction, that is, before executing the second instruction replacement operation, the main processor unit 21 can generate instructions to stop the coprocessor unit 22 from running; after the second instruction replacement operation is completed, the main processor unit 21 can generate instructions to restart the coprocessor unit 22, and then use a new logical operation method to process the data stored by the main processor unit 21 in the second storage area of ​​the flash memory unit 233.

[0071] Combination Figure 5 As shown, the present invention also provides a data processing device, which includes a main processor 51, a coprocessor 52 and an SCM 53, and the SCM 53 includes a random access memory unit, a memory control unit and a flash memory unit, the flash memory unit stores a computer program that can be executed in the main processor 51 and the coprocessor 52, and when the main processor 51 and the coprocessor 52 execute the computer program, the steps of the data processing method based on the SCM as described above are implemented.

[0072] The data processing device in this embodiment is the same as the above Figure 1-4 The SCM-based data processing method in the corresponding embodiment belongs to the same concept, and its specific implementation process is detailed in the corresponding method embodiment, and the technical features in the method embodiment are applicable in the device embodiment, which will not be repeated here.

[0073] An embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the data processing method based on SCM as described above.

[0074] The computer-readable storage medium in this embodiment is the same as the above Figure 1-4 The SCM-based data processing method in the corresponding embodiment belongs to the same concept, and its specific implementation process is detailed in the corresponding method embodiment, and the technical features in the method embodiment are applicable to the device embodiment, which will not be repeated here.

[0075] It should be understood that the order of execution of the steps in the above embodiments does not imply a sequence of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0076] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0077] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0078] In the embodiments provided in the present application, it should be understood that the disclosed SCM-based data processing method and device may be implemented in other ways.

[0079] The present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of each of the above-mentioned method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or interface switching device that can carry the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0080] The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in the relevant technical field without departing from the purpose of the present invention. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

Claims

1. A data processing method based on SCM, characterized in that: The SCM includes a random access memory unit, a memory control unit and a flash memory unit, and the method includes: The main processor unit executes a first instruction obtained from the random access memory unit, the first instruction is used to enable the main processor unit to write preset data into the second storage area of ​​the flash memory unit through the memory control unit, and the first instruction is mapped from the first storage area of ​​the flash memory unit to the random access memory unit by the memory control unit, and the main processor unit executes a third instruction obtained from the random access memory unit, the third instruction is used to enable the main processor unit to read a logic operation result of the third storage area of ​​the flash memory unit through the memory control unit, and the third instruction is mapped from the first storage area of ​​the flash memory unit to the random access memory unit by the memory control unit; The coprocessor unit executes a second instruction obtained from the random access memory unit, wherein the second instruction is used to enable the coprocessor unit to perform a logical operation on the preset data obtained from the second storage area, and write the logical operation result to the third storage area of ​​the flash memory unit through the memory control unit, and the second instruction is mapped from the fourth storage area of ​​the flash memory unit to the random access memory unit by the memory control unit.

2. The data processing method based on SCM according to claim 1, characterized in that: The preset data is external input data obtained by the main processor unit from an input device or a network device; The method also includes: the main processor unit executes a fourth instruction obtained from the random access memory unit, the fourth instruction is used to enable the main processor unit to output the logic operation result, and the fourth instruction is mapped by the memory control unit from the first storage area of ​​the flash memory unit to the random access memory unit.

3. The data processing method based on SCM according to claim 1, characterized in that: The method further comprises: The main processor unit executes a fifth instruction input by an input device or a network device, and the fifth instruction is used to enable the main processor unit to generate a new second instruction and write the new second instruction into the fourth storage area of ​​the flash memory unit through the memory control unit and replace the original second instruction in the fourth storage area.

4. The data processing method based on SCM according to claim 1, characterized in that: The method further comprises: The main processor unit executes a fifth instruction obtained from the random access memory unit, the fifth instruction is used to enable the main processor unit to generate a new second instruction and write the new second instruction to the fourth storage area of ​​the flash memory unit through the memory control unit and replace the original second instruction in the fourth storage area, and the fifth instruction is mapped from the first storage area of ​​the flash memory unit to the random access memory unit by the memory control unit.

5. The SCM-based data processing method according to any one of claims 1 to 4, characterized in that: The coprocessor unit is a graphics processor or an embedded neural network processor, and the second instructions include operating system instructions of the coprocessor unit and artificial intelligence algorithm instructions for execution by the coprocessor unit.

6. The data processing method based on SCM according to claim 1, characterized in that: The random access memory unit includes a first random access memory and a second random access memory; The method further comprises: The memory control unit reads and feeds back a corresponding first instruction from the first random access memory according to a request of the main processor unit, and when the first instruction in the first random access memory meets a first preset condition, obtains a subsequent instruction set of the first instruction from the first storage area of ​​the flash memory unit and writes the subsequent instruction set into the first random access memory; The memory control unit reads and feeds back the corresponding second instruction from the second random access memory according to the request of the coprocessor unit, and when the second instruction in the second random access memory meets the second preset condition, obtains the subsequent instruction of the second instruction from the fourth storage area of ​​the flash memory unit and writes it into the second random access memory.

7. The data processing method based on SCM according to claim 1, characterized in that: The random access memory unit includes a first random access memory and a second random access memory, and the memory control unit includes a first memory controller and a second memory controller; The method further comprises: The first memory controller reads and feeds back a corresponding first instruction from the first random access memory according to a request of the main processor unit, and when the first instruction in the first random access memory meets a first preset condition, obtains a subsequent instruction set of the first instruction from the first storage area of ​​the flash memory unit and writes it into the first random access memory; The second memory controller reads and feeds back the corresponding second instruction from the second random access memory according to the request of the coprocessor unit, and when the second instruction in the second random access memory meets the second preset condition, obtains the subsequent instruction of the second instruction from the fourth storage area of ​​the flash memory unit and writes it into the second random access memory.

8. The data processing method based on SCM according to claim 1, characterized in that: The random access memory unit includes a first mapping area and a second mapping area; The method further comprises: The memory control unit reads and feeds back the corresponding first instruction from the first mapping area according to the request of the main processor unit, and when the first instruction in the first mapping area meets the first preset condition, obtains a subsequent instruction set of the first instruction from the first storage area of ​​the flash memory unit and writes it into the first mapping area; The memory control unit reads and feeds back the corresponding second instruction from the second mapping area according to the request of the coprocessor unit, and when the second instruction in the second mapping area meets the second preset condition, obtains the subsequent instruction of the second instruction from the fourth storage area of ​​the flash memory unit and writes it into the second mapping area.

9. The data processing method based on SCM according to claim 1, characterized in that: The random access memory unit, the memory control unit and the flash memory unit are packaged together to form an SCM chip.

10. A data processing device, characterized in that: The invention comprises a main processor, a coprocessor and an SCM, wherein the SCM comprises a random access memory unit, a memory control unit and a flash memory unit, wherein the flash memory unit stores a computer program executable in the main processor and the coprocessor, and when the main processor and the coprocessor execute the computer program, the steps of the SCM-based data processing method as described in any one of claims 1 to 9 are implemented.

11. A computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to enable a computer to execute the steps of the SCM-based data processing method according to any one of claims 1 to 9.

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