Memory device and method of operating the same

Abstract

The present technology relates to a memory device and an operation method thereof. The memory device includes: a memory cell array including a plurality of memory cells; a data register connected to the memory cell array via bit lines and configured to store data sensed via the bit lines; a cache register configured to cache the data stored in the data register; and control logic configured to control a cache operation that receives a cache read command from a memory controller and stores the data stored in the data register in the cache register during a cache read period in response to the cache read command, wherein the control logic controls the cache operation based on whether the cache read command is the first command received after a normal read command is received from the memory controller.

Description

Technical Field

[0001] The present disclosure relates to a memory device, and more particularly, to a memory device and an operation method thereof. Background Art

[0002] A storage device is a device that stores data under the control of a host device such as a computer or a smart phone. The storage device may include a memory device in which data is stored and a memory controller that controls the memory device. The memory device is divided into a volatile memory device and a non-volatile memory device.

[0003] A volatile memory device is a device that stores data only while power is supplied and loses the stored data when the power is turned off. Examples of the volatile memory device include a static random access memory (SRAM), a dynamic random access memory (DRAM), and the like.

[0004] A non-volatile memory device is a device that does not lose data even when power is turned off. Examples of the non-volatile memory device include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, and the like. Summary of the Invention

[0005] One embodiment of the present disclosure provides a memory device and an operation method thereof that can improve the speed of a cache read operation.

[0006] A memory device according to an embodiment may include: a memory cell array including a plurality of memory cells; a data register connected to the memory cell array via bit lines and configured to store data sensed via the bit lines; a cache register configured to cache the data stored in the data register; and control logic configured to control a cache operation that receives a cache read command from a memory controller and stores the data stored in the data register in the cache register during a cache read period in response to the cache read command.

[0007] The control logic may control the cache operation based on whether the cache read command is the first command received after a normal read command is received from the memory controller.

[0008] A method of operating a memory device according to one embodiment may include: receiving a cache read command from a memory controller; determining whether the cache read command is the first command received after a normal read command is received from the memory controller; and performing a cache operation of storing data stored in a data register in a cache register according to the determination.

[0009] A method of operating a memory device according to one embodiment may include: when first data and second data are stored in respective data registers and cache registers, caching the first data from the data register to the cache register, providing the first data from the cache register in response to a cache read command, and when the first data is stored in both the data register and the cache register, providing the first data from the cache register in response to the cache read command without caching.

[0010] The present technology may provide a memory device and a method of operating the memory device that can improve the speed of a cache read operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagram for illustrating a memory system according to an embodiment of the present disclosure.

[0012] Figure 2 is for illustrating Figure 1 the signals exchanged between a memory controller and a memory device according to

[0013] Figure 3 is for illustrating Figure 1 a memory device according to

[0014] Figure 4 is for illustrating Figure 3 an embodiment of a memory cell array according to

[0015] Figure 5 is for illustrating Figure 4 a memory block according to

[0016] Figure 6 is for illustrating Figure 4 an embodiment in which a memory block according to

[0017] Figure 7 is for illustrating Figure 4 another embodiment in which a memory block according to

[0018] Figure 8 is for implementing Figure 3 some page buffers according to

[0019] Figure 9 is a waveform diagram for showing a cache read operation according to an embodiment of the present disclosure.

[0020] Figure 10 is a diagram for showing a data register and a cache register corresponding to the waveform diagram according to Figure 9 thereof.

[0021] Figure 11 is a waveform diagram for showing a method of partially skipping a cache operation included in the cache read operation according to Figure 9 and Figure 10 thereof.

[0022] Figure 12 is a diagram showing a skip signal generator for generating a skip signal according to Figure 11 thereof.

[0023] Figure 13 is a flowchart showing a method of operating a memory device according to an embodiment of the present disclosure.

[0024] Figure 14 is for showing Figure 1 a memory controller thereof.

[0025] Figure 15 is a diagram for showing another embodiment of a memory system according to Figure 1 thereof. DETAILED DESCRIPTION

[0026] The specific structural or functional descriptions showing the embodiments disclosed in the present disclosure or this application are only for describing the embodiments of the present disclosure. The embodiments of the present disclosure can be implemented in various forms, and the description is not limited to the embodiments described in the present disclosure or this application.

[0027] Figure 1 is a diagram for showing a memory system according to an embodiment of the present disclosure.

[0028] Referring to Figure 1 , the memory system 1000 may include: a memory device 1100 in which data is stored; and / or a memory controller 1200 that controls the memory device 1100 according to a request of a host 2000.

[0029] The host 2000 may communicate with the memory system 1000 using at least one of various communication methods such as Universal Serial Bus (USB), Serial ATA Interface (SATA), Serial Attached SCSI (SAS), High-Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low-Rank DIMM (LRDIMM).

[0030] The memory device 1100 may be implemented as a volatile memory device in which data is lost when power is cut off or a non-volatile memory device in which data is retained even when power is cut off. The memory device 1100 may perform a programming operation, a read operation, or an erase operation under the control of the memory controller 1200. For example, during a programming operation, the memory device 1100 may receive a command, an address, and data from the memory controller 1200 and perform a programming operation. During a read operation, the memory device 1100 may receive a command and an address from the memory controller 1200 and output the read data to the memory controller 1200. The memory device 1100 may be referred to as a chip, a wafer, or a single integrated circuit (IC).

[0031] The memory system 1000 may include a memory device group 1300 in which a plurality of memory devices 1100 are grouped, and the memory devices 1100 belonging to each memory device group 1300 may communicate with the memory controller 1200 via corresponding channels CH1 to CHk. Hereinafter, for ease of description, four memory devices are included in one memory device group connected to one channel, but the present disclosure is not limited thereto.

[0032] The memory controller 1200 may control the overall operation of the memory system 1000 and control the data exchange between the host 2000 and the memory device 1100. For example, when receiving a command from the host 2000, the memory controller 1200 may control the corresponding memory device groups 1300 connected to the respective channels CH1 to CHk according to the received command. The memory controller 1200 may control the memory devices 1100 included in the memory device groups 1300 connected to the respective channels according to the requests of the host 2000 to program, read, or erase data. In addition, the memory controller 1200 may receive data and logical addresses from the host 2000 and convert the logical addresses into physical addresses indicating the areas where the data is actually stored in the memory device 1100. In addition, the memory controller 1200 may store a logical-physical address mapping table in a buffer memory (not shown), and the logical-physical address mapping table configures the mapping relationship between the logical addresses and the physical addresses.

[0033] The memory controller 1200 may perform a status read operation before or during controlling a specific operation of the memory device 1100 to determine the status of at least one of the memory devices 1100. For example, the memory controller 1200 may transmit a status read command to the memory device 1100, and at least one of the memory devices 1100 may output status information to the memory controller 1200 in response to the status read command. In addition, the memory controller 1200 may transmit a status read command to the memory device 1100 to monitor whether a previously issued command is completed.

[0034] Figure 2 is a diagram for showing signals exchanged between a memory controller and a memory device according to Figure 1 the memory controller and the memory device.

[0035] Referring to Figure 2 , the memory controller 1200 and the memory device 1100 may exchange commands, data, and / or addresses with each other via the input / output pads DQ. For example, the input / output pads DQ may be configured with eight lines to transmit and receive 8-bit data, and each line may transmit and receive 1-bit data.

[0036] The memory device 1100 may receive a chip enable signal via the CE# pad, a write enable signal via the WE# pad, a read enable signal via the RE# pad, an address latch enable signal via the ALE pad, a command latch enable signal via the CLE pad, and a write protection signal via the WP# pad.

[0037] The address latch enable signal can be a signal sent by the memory controller 1200 to the memory device 1100 such that the memory device 1100 loads the address provided to the memory device 1100 via the input / output pad DQ into the address register. The chip enable signal can be a signal sent by the memory controller 1200 to the memory device 1100 to enable or disable one or more memory devices. The command latch enable signal can be a signal sent by the memory controller 1200 to the memory device 1100 such that the memory device 1100 loads the command provided to the memory device 1100 via the input / output pad DQ into the command register. The read enable signal can be a signal sent by the memory controller 1200 to the memory device 1100 such that the memory device 1100 transfers data to the memory controller 1200. The write enable signal can be a signal that notifies that a command, an address, and data are being transferred.

[0038] The memory device 1100 can output the ready-busy signal to the memory controller 1200 via the RB pad. The ready-busy signal can indicate whether the memory array of the memory device 1100 is in a busy state or an idle state.

[0039] Figure 2 The connection relationship between a memory device 1100 and the memory controller 1200 is shown. However, the input / output pad DQ, CE# pad, WE# pad, RE# pad, ALE pad, CLE pad, WP# pad can form a channel, and the memory controller 1200 and one of the memory device groups 1300 can be connected via the formed channel. For example, one of the memory device groups 1300 can be connected to the CE# pad.

[0040] Therefore, when the memory controller 1200 transmits a command, data, and / or an address via the input / output pad DQ included in a channel, all the memory devices 1100 connected to the corresponding channel or the memory devices 1100 selected among the memory devices 1100 connected to the corresponding channel can receive the command, data, and / or the address. For example, the memory controller 1200 can transmit a status read command via the input / output pad DQ to the memory device 1100 connected to the corresponding input / output pad DQ, and at least one of the memory devices 1100 that receives the status read command can transmit status information to the input / output pad DQ in response to the status read command.

[0041] Figure 3 is for showing Figure 1 the memory device of

[0042] Referring to Figure 3, the memory device 1100 can be implemented as a volatile memory device or a non-volatile memory device. In Figure 3 , a non-volatile memory device is shown as an example, but the present embodiment is not limited to non-volatile memory devices.

[0043] The memory device 1100 may include a memory cell array 100 in which data is stored. The memory device 1100 may include a peripheral circuit 200 configured to perform a programming operation for storing data in the memory cell array 100, a read operation for outputting the stored data, and an erase operation for erasing the stored data. The memory device 1100 may include a control logic 300 that controls the peripheral circuit 200 under the control of a memory controller 1200.

[0044] The memory cell array 100 includes a plurality of memory cells in which data is stored. For example, the memory cell array 100 may include at least one plane, which may include one or more memory blocks. In one embodiment, the plane may be a unit of a storage area accessed during a programming, reading, or erasing operation. Each memory block may include a plurality of memory cells. A structure including a plurality of planes may be referred to as a multi-plane structure. User data and information required for the operation of the memory device 1100 may be stored in the memory blocks. The memory blocks may be implemented in a two-dimensional or three-dimensional structure. A memory block having a two-dimensional structure may include memory cells arranged parallel to a substrate, and a memory block having a three-dimensional structure may include memory cells vertically stacked on the substrate.

[0045] The peripheral circuit 200 may be configured to perform programming, reading, and erase operations under the control of the control logic 300. For example, the peripheral circuit 200 may include a voltage generation circuit 210, a row decoder 220, a page buffer bank 230, a column decoder 240, an input / output circuit 250, a current sensing circuit 260, and a skip signal generator 400.

[0046] The voltage generation circuit 210 may generate various operation voltages Vop for programming, reading, and erase operations in response to an operation signal OP_CMD output from the control logic 300. For example, the voltage generation circuit 210 may generate various voltages such as a programming voltage, a verification voltage, a pass voltage, a read voltage, and an erase voltage under the control of the control logic 300.

[0047] The row decoder 220 may supply an operation voltage Vop to a local line LL connected to a selected memory block in a memory block of the memory cell array 100 in response to a row address RADD output from the control logic 300. The local line LL may include a local word line, a local drain select line, and / or a local source select line. In addition, the local line LL may include various lines such as a source line connected to the memory block.

[0048] The page buffer group 230 may be connected to bit lines BL1 to BLI connected to a memory block of the memory cell array 100. The page buffer group 230 may include a plurality of page buffers PB1 to PBI connected to the bit line BL1. The page buffers PB1 to PBI may operate in response to a page buffer control signal PBSIGNALS output from the control logic 300. For example, the page buffers PB1 to PBI may temporarily store data received via the bit lines BL1 to BLI, or may sense a voltage or current of the bit lines BL1 to BLI during a read operation or a verify operation.

[0049] The column decoder 240 may transfer data between the input / output circuit 250 and the page buffer group 230 in response to a column address CADD output from the control logic 300. For example, the column decoder 240 may exchange data with the page buffers PB1 to PB1 via a data line DL, or may exchange data with the input / output circuit 250 via a column line CL.

[0050] The input / output circuit 250 may receive a command CMD, an address ADD, and data from the memory controller 1200 via an input / output pad DQ, and output data read from the memory cell array 100 to the memory controller 1200 via the input / output pad DQ. For example, the input / output circuit 250 may transfer the command CMD and the address ADD received from the memory controller 1200 to the control logic 300, or may exchange data DATA with the column decoder 240.

[0051] During a read operation or a verify operation, the current sensing circuit 260 may generate a reference current in response to an enable bit VRY_BIT<#>, compare a sensed voltage VPB received from the page buffer group 230 with a reference voltage generated by the reference current, and output a pass signal PASS or a fail signal FAIL.

[0052] The control logic 300 may receive a command CMD and an address ADD in response to signals received via the CE#, WE#, RE#, ALE, CLE, and WP# pads. The control logic 300 may generate control signals for controlling the peripheral circuit 200 in response to the received command CMD and address ADD, and output the generated control signals to the peripheral circuit 200. For example, the control signals may include at least one of the following: an operation signal OP_CMD; a row address RADD; page buffer control signals PBSIGNALS; and an enable bit VRY_BIT<#>. The control logic 300 may output the operation signal OP_CMD to the voltage generation circuit 210, the row address RADD to the row decoder 220, the page buffer control signals PBSIGNALS to the page buffer bank 230, and the enable bit VRY_BIT<#> to the current sensing circuit 260. Additionally, the control logic 300 may determine whether a verification operation passes or fails in response to a PASS signal or a FAIL signal. Here, the command CMD may include a cache read command for performing a read operation at high speed using the cache register of the memory device 1100.

[0053] The control logic 300 may receive a cache read command from the memory controller 1200, and based on whether the received cache read command is the first command received after receiving a normal read command from the memory controller 1200, may perform a cache operation of storing data stored in a data register in the cache register during a cache read period.

[0054] For example, when the cache read command is not the first command received after receiving a normal read command from the memory controller 1200, the control logic 300 may perform a cache operation.

[0055] The skip signal generator 400 may determine whether the cache read command is the first command received after receiving a normal read command from the memory controller 1200, and based on the determination, provide a skip signal SkipSGN indicating to the control logic 300 to skip the cache operation.

[0056] The control logic 300 may skip the cache operation during the cache read period based on the skip signal SkipSGN. At this time, the control logic 300 may provide at least one signal required to generate the skip signal SkipSGN (see Figures 11 to 12 described later) to the skip signal generator 400.

[0057] The control logic 300 may output a ready-busy signal indicating the busy state of the memory device 1100 during a second period shorter than the cache read period in response to a skip signal SkipSGN to the memory controller 1200. For example, the second period may be the first cache read period tDCBSYR1 described later with reference to Figure 11 ， .

[0058] The control logic 300 may receive a normal read command from the memory controller 1200 and provide a normal read signal to the skip signal generator 400 during a third period longer than the cache read period in response to the normal read command. For example, the third period may be the normal read period tR described later with reference to Figure 9 or Figure 11 .

[0059] Figure 4 is a diagram showing Figure 3 an embodiment of the memory cell array of

[0060] Referring to Figure 4 , the memory cell array 100 includes a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate. The plurality of memory cells may be arranged along the +X direction, +Y direction, and +Z direction.

[0061] Figure 5 is a diagram for showing Figure 4 a memory block of

[0062] Referring to Figure 5 , the first memory block BLK1 among the plurality of memory blocks BLK1 to BLKz shown in Figure 4 is shown. The remaining memory blocks BLK2 to BLKz may have the same shape as the first memory block BLK1.

[0063] The first memory block BLK1 may include a plurality of cell strings ST connected between bit lines BL1 to BLI and a source line SL. For example, the cell strings ST may be respectively connected to the bit lines BL1 to BLI and may be commonly connected to the source line SL. Since the cell strings ST are configured similarly to each other, the following embodiments describe the cell string ST connected to the first bit line BL1.

[0064] The cell string ST may include a source selection transistor SST, first to nth memory cells F1 to Fn (n is a positive integer), and a drain selection transistor DST connected in series between the source line SL and the first bit line BL1. The number of source selection transistors SST and drain selection transistors DST is not limited to Figure 5 ​The quantity shown in []. The source selection transistor SST can be connected between the source line SL and the first memory cell F1. The first memory cell F1 to the nth memory cell Fn can be connected in series between the source selection transistor SST and the drain selection transistor DST. The drain selection transistor DST can be connected between the nth memory cell Fn and the first bit line BL1. Although not shown in the figure, dummy cells can be further connected between the memory cells F1 to Fn or between the source selection transistor SST and the drain selection transistor DST.

[0065] The gates of the source selection transistors SST included in different cell strings ST can be connected to the source selection line SSL, the gates of the first memory cell F1 to the nth memory cell Fn can be connected to the first word line WL1 to the nth word line WLn, and the gate of the drain selection transistor DST can be connected to the drain selection line DSL. Here, a group of memory cells connected to the word lines WL1 to WLn are called a page PG. For example, a group of first memory cells F1 connected to the first word line WL1 among the memory cells F1 to Fn included in different cell strings ST can be a physical page PPG. Programming and reading operations can be performed in units of the physical page PPG.

[0066] Figure 6 is a diagram for showing Figure 4 an embodiment in which the memory block is configured in three dimensions.

[0067] Referring to Figure 6 , shows the first memory block BLK1 among the multiple memory blocks BLK1 to BLKz shown in Figure 4 . The remaining memory blocks BLK2 to BLKz can have the same shape as the first memory block BLK1.

[0068] The memory block BLK1 implemented in a three-dimensional structure can be formed on the substrate in the vertical direction (Z direction), and can have an I shape, and can include multiple cell strings ST arranged between the bit line BL and the source line SL. Alternatively, a well can be formed instead of the source line SL. This structure is also called bit cost scalable (BiCS). For example, when the source line SL is formed horizontally on the substrate, the cell string ST having a BiCS structure can be formed on the source line SL in the vertical direction (Z direction).

[0069] More specifically, the cell strings ST may be arranged in each of a first direction (X direction) and a second direction (Y direction). The cell strings ST may include source selection lines SSL, word lines WL, and drain selection lines DSL that are stacked and spaced apart from each other. The number of the source selection lines SSL, the word lines WL, and the drain selection lines DSL is not limited to the number shown in the figure and may vary according to the memory device 1100. The cell strings ST may include a vertical channel film CH that vertically passes through the source selection lines SSL, the word lines WL, and the drain selection lines DSL and include bit lines BL that contact an upper portion of the vertical channel film CH protruding above the drain selection line DSL and extend in the second direction (Y direction). Memory cells may be formed between the word lines WL and the vertical channel film CH. A contact plug CT may be further formed between the bit line BL and the vertical channel film CH.

[0070] Figure 7 is a diagram for showing Figure 4 another embodiment in which the memory blocks are configured in three dimensions.

[0071] Referring to Figure 7 , a first memory block BLK1 among a plurality of memory blocks BLK1 to BLKz shown in Figure 4 is shown. The remaining memory blocks BLK2 to BLKz may have the same shape as the first memory block BLK1.

[0072] The first memory block BLK1 implemented in a three-dimensional structure may be formed on a substrate in a vertical direction (Z direction) and may have a U shape, and may include a source string ST_S and a drain string ST_D that are connected between a bit line BL and a source line SL. The source string ST_S and the drain string ST_D may be connected to each other via a pipe gate PG to form a U-shaped structure. The pipe gate PG may be formed in a pipeline PL. More specifically, the source string ST_S may be vertically formed between the source line SL and the pipeline PL, and the drain string ST_D may be vertically formed between the bit line BL and the pipeline PL. This structure is also referred to as pipe-shaped bit cost scalable (P-BiCS).

[0073] More specifically, the drain string ST_D and the source string ST_S may be arranged along a first direction (X direction) and a second direction (Y direction), respectively, and the drain string ST_D and the source string ST_S may be alternately arranged along the second direction Y. The drain string ST_D may include word lines WL and drain selection lines DSL that are stacked and spaced apart from each other, and include a drain vertical channel film D_CH that vertically penetrates the word lines WL and the drain selection lines DSL. The source string ST_S may include word lines WL and source selection lines SSL that are stacked and spaced apart from each other, and include a source vertical channel film S_CH that vertically penetrates the word lines WL and the source selection lines SSL. The drain vertical channel film D_CH and the source vertical channel film S_CH may be connected to each other by a gate electrode PG in a pipeline PL. The bit line BL may be in contact with an upper portion of the drain vertical channel film D_CH that protrudes above the drain selection line DSL, and may extend in the second direction (Y direction).

[0074] Figure 8 is a diagram showing some of the multiple page buffers (e.g., Figure 3 the page buffer shown in).

[0075] Referring to Figure 8 , each of the page buffers PB1, PB2, …, and PBI may include a sense latch SLATCH and a cache latch CLATCH.

[0076] During a read operation, the page buffers PB1, PB2, …, and PBI may operate in response to a control signal PBSIGNALS of the control logic 300. Specifically, the control logic 300 may receive a cache read command from the memory controller 1200, the control logic 300 may generate a control signal PBSIGNALS for controlling the cache read operation of the page buffers PB1, PB2, …, and PBI, and transmit the control signal PBSIGNALS to the page buffers PB1, PB2, …, and PBI in response to the cache read command, and the page buffers PB1, PB2, …, and PBI may perform a cache read operation in response to the page buffer control signal PBSIGNALS.

[0077] The sense latch SLATCH may store data sensed from the bit line. The data sensed from the bit line may be data determined according to the threshold voltage characteristics of the memory cells connected to the word lines selected from the local word lines. For example, the sense latch SLATCH of the first page buffer PB1 may be connected to the first bit line BL1, and may store the data sensed from the first bit line BL1.

[0078] The cache latch CLATCH can be electrically connected to the sense latch SLATCH and can cache (or store) the data stored in the sense latch SLATCH in response to the page buffer control signals PBSIGNALS. Additionally, the cache latch CLATCH can be connected to the data line DL and output the cached data to the column decoder 240 via the data line DL.

[0079] The sense latches SLATCH included in the page buffers PB1, PB2, …, and PBI can be referred to as one data register DRT, and the cache latches CLATCH included in the page buffers can be referred to as one cache register CRT. At this time, since the data register DRT and the cache register CRT store or cache the data sensed from the memory cells connected to one word line, the data register DRT and the cache register CRT can store the data corresponding to one page.

[0080] The data cached in the cache register CRT can be output to the input / output pad DQ via the column decoder 240 and the input / output circuit 250, and the memory controller 1200 can receive the data cached in the cache register CRT via the input / output pad DQ in response to the cache read command transmitted to the control logic 300.

[0081] Figure 9 is a waveform diagram for illustrating a cache read operation according to an embodiment of the present invention. Figure 10 is for illustrating the Figure 9 corresponding data register and cache register of the waveform diagram.

[0082] Referring to Figure 9 , for the cache read operation, the memory controller 1200 can first transmit the normal read commands 00h - 30h and the address addr to the memory device 1100 via the input / output pad DQ. In response to the normal read commands 00h - 30h, the control logic 300 can transmit a ready - busy signal (e.g., Figure 9 the low - level signal in Figure 10, during a normal read period tR, the control logic 300 can sense (or read) the Nth page Page N (where N is a natural number equal to or greater than 1) corresponding to the address addr in the memory cell array 100 by controlling the peripheral circuit 200, store the Nth page Page N in the data register DRT, and can cache the Nth page Page N stored in the data register DRT in the cache register CRT.

[0083] When the normal read period tR elapses, the control logic 300 can transmit a ready-busy signal indicating an idle state (e.g., Figure 9 the high-level signal in) to the memory controller 1200 via the RB pad. The memory controller 1200 can check the idle state by means of the ready-busy signal and transmit a cache read command 31h to the memory device 1100.

[0084] In response to the cache read command 31h, the control logic 300 can transmit a ready-busy signal indicating the busy state of the memory device 1100 during the first cache read period tDCBSYR1 (e.g., Figure 9 the low-level signal in) to the memory controller 1200 via the RB pad. Referring to Figure 10 , during the first cache read period tDCBSYR1, the control logic 300 can cache the Nth page Page N stored in the data register DRT in the cache register CRT again by controlling the peripheral circuit 200.

[0085] When the first cache read period tDCBSYR1 elapses, the control logic 300 can transmit a ready-busy signal indicating an idle state to the memory controller 1200 via the RB pad. Referring to Figure 9 and Figure 10 , during the first output period tOUT1 after the first cache read period tDCBSYR1, the control logic 300 can output the Nth page Page N cached in the cache register CRT to the input / output pad DQ by means of the column decoder 240 and the input / output circuit 250, and can simultaneously store the (N + 1)th page Page N+1 of the memory cell array 100 in the data register DRT. At this time, the Nth page Page N can be output to the input / output pad DQ according to the clock of the read enable signal received via the RE# pad.

[0086] After transmitting the Nth page Page N to the memory controller 1200 via the input / output pad DQ, the memory controller 1200 can transmit the cache read command 31h to the memory device 1100 again.

[0087] In response to the cache read command 31h, the control logic 300 may transmit a ready-busy signal (e.g., a low-level signal in Figure 9 ) indicating the busy state of the memory device 1100 during the second cache read period tDCBSYR2 to the memory controller 1200 via the RB pad. Referring to Figure 10 , during the second cache read period tDCBSYR2, the control logic 300 may cache the (N + 1)-th page Page N+1 stored in the data register DRT in the cache register CRT by controlling the peripheral circuit 200.

[0088] When the second cache read period tDCBSYR2 elapses, the control logic 300 may transmit a ready-busy signal indicating the idle state to the memory controller 1200 via the RB pad. Referring to Figure 9 and Figure 10 , during the second output period tOUT2 after the second cache read period tDCBSYR2, the control logic 300 may output the (N + 1)-th page Page N+1 cached in the cache register CRT to the input / output pad DQ by means of the column decoder 240 and the input / output circuit 250, and may simultaneously store the (N + 2)-th page Page N+2 of the memory cell array 100 in the data register DRT. At this time, the (N + 1)-th page Page N+1 may be output to the input / output pad DQ according to the clock of the read enable signal received via the RE# pad.

[0089] Thereafter, the memory controller 1200 may repeatedly transmit the cache read command 31h to the memory device 1100, and the memory device 1100 may perform the same operations as the above method on other pages in response to each cache read command 31h. Specifically, the above cache read operation may be repeated until the memory device 1100 receives the last cache read command 3Fh from the memory controller 1200. When the last cache read command 3Fh is received, the control logic 300 may cache the data stored in the data register DRT in the cache register CRT, and output the data cached in the cache register CRT via the input / output pad DQ, rather than storing the data in the data register DRT by sensing a new page from the memory cell array 100.

[0090] As described above, since the cache read operation outputs the page cached in the cache register CRT, and simultaneously reads a new page from the memory cell array 100 and stores the new page in the data register DRT, the page of the memory cell array 100 can be read very quickly.

[0091] The cache read period including the first cache read period tDCBSYR1 and the second cache read period tDCBSYR2 can be shorter than the normal read period tR.

[0092] Both the first cache read period tDCBSYR1 and the second cache read period tDCBSYR2 can be periods of an operation of caching data stored in the data register DRT in the cache register CRT in response to the same cache read command 31h, and can be set to have the same time interval from each other. Additionally, in the cache read period including the first cache read period tDCBSYR1 and the second cache read period tDCBSYR2, an operation of determining one of a random cache read and a sequential cache read by the control logic 300, an operation of changing a column address, etc. can be further performed.

[0093] Meanwhile, referring to Figure 10 , regarding the operation performed in the second cache read period tDCBSYR2 in response to the second cache read command, an operation of re-caching the operation of the (N + 1)-th page Page N+1 stored in the data register DRT in the cache register CRT can be performed.

[0094] However, different from the second cache read period tDCBSYR2, the operation of caching the N-th page Page N in the cache register CRT during the first cache read period tDCBSYR1 may be redundant because the N-th page Page N has been cached in the cache register CRT during the previous normal read period tR.

[0095] That is, when all of the first cache read period tDCBSYR1 and the second cache read period tDCBSYR2 and the corresponding operations are set identically, the same operation is always performed for the same cache read command. Therefore, implementation can be easy, but may include unnecessary cache operations. In the first cache read period tDCBSYR1 corresponding to the first cache read command after the normal read command, the cache operation of storing the data stored in the data register DRT in the cache register CRT can be skipped, and the first cache read period tDCBSYR1 can be set to be shorter than other cache read periods including the second cache read period tDCBSYR2 to increase the cache read operation speed.

[0096] In one embodiment, a cache operation of storing data stored in a data register DRT in a cache register CRT may be performed based on whether a cache read command is the first command received after a normal read command is received from a memory controller.

[0097] For example, when a cache read command received from the memory controller 1200 is the first command received after a normal read command is received from the memory controller 1200, the control logic 300 may skip the cache operation. Additionally, since the cache operation is skipped, a first cache read period tDCBSYR1 corresponding to the cache read command that is the first command may be set to be shorter than other cache read periods, and the control logic 300 may output a ready-busy signal indicating the busy state of the memory device 1100 during the first cache read period tDCBSYR1 that is set to be shorter than other cache read periods (e.g., a second cache read period tDBSYR2).

[0098] Figure 11 is for describing a method of partially skipping a cache operation included in a cache read operation according to Figure 9 and Figure 10 of a waveform diagram. Figure 12 is a diagram showing a skip signal generator for generating a skip signal according to Figure 11 of.

[0099] Referring to Figure 11 , the control logic 300 may receive a normal read command from the memory controller 1200 and, in response to the normal read command, generate a normal read signal CI_read_all that is activated (or has a high level) during a period corresponding to a normal read period tR.

[0100] Additionally, the control logic 300 may determine whether to store data stored in the data register DRT in the cache register CRT in each cache read period including a first cache read period tDCBSYR1' and a second cache read period tDCBSYR2, and may generate a cache completion signal DtoC_Done that is activated (or has a high level) when the data stored in the data register DRT is stored in the cache register CRT.

[0101] In one embodiment, the skip signal generator 400 may receive a normal read signal CI_read_all and a cache completion signal DtoC_Done from the control logic 300, and may use the normal read signal CI_read_all and the cache completion signal DtoC_Done to generate a skip signal SkipSGN indicating a cache operation to skip storing data to be stored in the data register DRT in the cache register CRT.

[0102] The control logic 300 may check the skip signal SkipSGN in each cache read period including a first cache read period tDCBSYR1' and a second cache read period tDCBSYR2, and may skip the cache operation based on the skip signal SkipSGN.

[0103] For example, referring to Figure 11 , the skip signal SkipSGN may be activated to a high level in response to the normal read signal CI_read_all, and may be deactivated to a low level in response to the cache completion signal DtoC_Done.

[0104] Therefore, the control logic 300 may skip the cache operation of storing the data to be stored in the data register DRT in the cache register CRT based on the skip signal SkipSGN having a high level in the first cache read period tDCBSYR1', and set the first cache read period tDCBSYR1' to be shorter than the second cache read period tDCBSYR2.

[0105] In addition, the control logic 300 may perform the cache operation of storing the data to be stored in the data register DRT in the cache register CRT based on the skip signal SkipSGN having a low level in other cache read periods including the second cache read period tDCBSYR2.

[0106] As described above, since the skip signal SkipSGN is deactivated to a low level in the first cache read period tDCBSYR1' and remains deactivated to a low level until the cache read operation ends, the control logic 300 may skip the cache operation of storing the data to be stored in the data register DRT in the cache register CRT in response to the cache read command as the first command.

[0107] To generate the above skip signal SkipSGN, the skip signal generator 400 may be implemented as Figure 12 the configuration shown.

[0108] Referring to Figure 12, the skip signal generator 400 may include a flip-flop 420 configured to receive one of a high-level signal 1 and a low-level signal 0 via an input terminal D, receive a normal read signal CI_read_all via a clock terminal clk, output the signal received via the input terminal D via an output terminal Q according to the normal read signal CI_read_all, receive a cache completion signal DtoC_Done via a reset terminal rst, and reset the output of the output terminal Q according to the cache completion signal DtoC_Done. For example, the flip-flop 420 may be a D flip-flop.

[0109] One of the high-level signal 1 and the low-level signal 0 may be applied to the input terminal D. For example, the high-level signal 1 may be a signal with a high level, and the skip signal SkipSGN may be activated to a high level, while the low-level signal 0 may be a signal with a low level, and the skip signal SkipSGN may be deactivated to a low level.

[0110] When the normal read signal CI_read_all is applied to the clock terminal clk, the signal applied to the input terminal D may be output via the output terminal Q. For example, when the high-level signal 1 is applied to the input terminal D, when the normal read signal CI_read_all is applied to the clock terminal clk, the high-level signal 1 may be output as the skip signal SkipSGN activated to a high level.

[0111] At this time, when the cache completion signal DtoC_Done is received via the reset terminal rst, the skip signal SkipSGN output via the output terminal Q is reset to be deactivated to a low level, so that the deactivated skip signal SkipSGN can be output. Since the high-level signal 1 applied to the input terminal D will not be transmitted to the output terminal Q unless the normal read signal CI_read_all is provided again via the clock terminal clk, the skip signal SkipSGN can remain deactivated.

[0112] Meanwhile, the skip signal generator 400 may further include a multiplexer 410 that selects one of a high-level signal 1 and a low-level signal 0 and outputs the selected signal to the input terminal D of the flip-flop 420. The multiplexer 410 may receive a signal opt from the control logic 300 indicating enabling or disabling the skip function for cache operations, and may select one of the high-level signal 1 and the low-level signal 0 according to the received signal opt. For example, when receiving a signal opt enabling the skip function for cache operations from the control logic 300, the multiplexer 410 may output the high-level signal 1 to the input terminal D. When receiving a signal opt disabling the skip function for cache operations from the control logic 300, the multiplexer 410 may output the low-level signal 0 to the input terminal D.

[0113] Meanwhile, in Figures 11 to 12 , the control logic 300 receives a skip signal SkipSGN from the skip signal generator 400, but is not limited thereto. For example, the control logic 300 may include the skip signal generator 400 and may skip cache operations without generating a separate skip signal SkipSGN.

[0114] Specifically, the control logic 300 may determine whether to store the data stored in the data register DRT in the cache register CRT during each cache read period in response to a cache read command, and may skip cache operations when the data stored in the data register DRT is stored in the cache register CRT. At this time, the control logic 300 may set the cache read period to be shorter than other cache read periods, and output a ready-busy signal indicating a busy state corresponding to the set short cache read period via the RB pad.

[0115] Figure 13 is a flowchart showing a method of operating a memory device according to an embodiment of the present disclosure.

[0116] Referring to Figure 13 , a method of operating a memory device according to an embodiment may include: receiving a cache read command from a memory controller (S100); determining whether the received cache read command is the first command received after receiving a normal read command from the memory controller (S110); and performing a cache operation of storing the data stored in the data register in the cache register according to the determination (S120).

[0117] When the cache read command is not the first command, a cache operation (S120) may be performed.

[0118] The determination (S110) may include determining whether to skip the execution of a cache operation based on whether data stored in a data register is stored in a cache register during a cache read period.

[0119] The execution of the cache operation (S120) may include outputting a ready-busy signal indicating the busy state of the memory device 1100 to a memory controller during a cache read period.

[0120] The output may include outputting a ready-busy signal indicating the busy state of the memory device 1100 to a memory controller during a period shorter than the cache read period when the cache read command is the first command.

[0121] A method of operating a memory device according to an embodiment may further include activating a skip signal indicating to skip a cache operation based on the determination.

[0122] The skip signal may be activated in response to a normal read command based on a normal read signal corresponding to a normal read period longer than the cache read period.

[0123] A method of operating a memory device according to an embodiment may further include deactivating the skip signal during a cache read period based on a cache completion signal indicating whether data stored in a data register is stored in a cache register.

[0124] A method of operating a memory device according to an embodiment should be construed to include the configuration or operation described with reference to Figures 1 to 12 the description.

[0125] Figure 14 is a diagram of a memory controller for specifically describing Figure 1 the description.

[0126] With reference to Figure 14 the description, the memory controller 1200 may include an internal memory 1210, a central processing unit (CPU) 1220, an error correction block 1230, a host interface 1240, a buffer memory interface 1250, and a memory interface 1260.

[0127] The internal memory 1210 may store various information required for the operation of the memory controller 1200. For example, the internal memory 1210 may include a logical and physical address mapping table. The internal memory 1210 may be configured by at least one of a random access memory (RAM), a dynamic RAM (DRAM), a static RAM (SRAM), a cache, and a tightly coupled memory (TCM), but is not limited thereto.

[0128] The CPU 1220 may perform various operations for controlling the memory device 1100 or generate various commands. When the CPU 1220 receives a request from the host 2000, the CPU 1220 may generate a command according to the received request and transmit the generated command to the error correction block 1230.

[0129] The error correction block 1230 is configured to detect and correct errors in the data received from the memory device 1100 using an error correction code (ECC). The CPU 1220 may control the memory device 1100 to adjust a read voltage and perform a reread according to the error detection result of the error correction block 1230. As an implementation, the error correction block may be provided as a component of the memory controller 1200.

[0130] The host interface 1240 may exchange commands, addresses, and data between the memory controller 1200 and the host 2000. For example, the host interface 1240 may receive a request, an address, and data from the host 2000 and output the data read from the memory device 1100 to the host 2000. The host interface 1240 may communicate with the host 2000 using protocols such as Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), or Non-Volatile Memory Express (NVMe). The host interface 1240 is not limited to the above embodiments and may include various interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0131] The buffer memory interface 1250 may transfer data between the CPU 1220 and a buffer memory (not shown) of the memory system 1000. The buffer memory (not shown) may be used as an operating memory or a cache memory of the memory controller 1200 and may store system data used in the memory system 1000 in addition to the above information. According to one embodiment, the buffer memory (not shown) may include Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), DDR4 SDRAM, Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), or Rambus Dynamic Random Access Memory (RDRAM). When the buffer memory is included in the memory controller 1200, the buffer memory interface 1250 may be omitted.

[0132] The memory interface 1260 may exchange commands, addresses, and data between the memory controller 1200 and the memory device 1100. For example, the memory interface 1260 may transmit commands, addresses, and data to the memory device 1100 via a channel and may receive data, etc., from the memory device 1100.

[0133] Figure 15 is a diagram for describing another embodiment of a memory system according to Figure 1 the present disclosure.

[0134] Referring to Figure 15 , the memory system may include a host 2000 and a memory card 70000.

[0135] The memory card 70000 may be implemented as a smart card. The memory card 70000 may include a memory device 1100, a memory controller 1200, and a card interface 7100.

[0136] The memory controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. According to one embodiment, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but is not limited thereto. Additionally, the card interface 7100 may couple data exchange between the host 2000 and the memory controller 1200 according to the protocol of the host 2000. According to one embodiment, the card interface 7100 may support a Universal Serial Bus (USB) protocol as well as an Inter-Chip (IC)-USB protocol. Here, the card interface 7100 may refer to hardware capable of supporting the protocol used by the host 2000, software installed in the hardware, or a signal transmission method.

[0137] Cross-reference to Related Applications

[0138] This application claims the priority of Korean Patent Application No. 10-2020-0076054, filed on Jun. 22, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: A memory cell array including a plurality of memory cells; A data register connected to the memory cell array via bit lines and configured to store data sensed via the bit lines; A cache register configured to cache the data stored in the data register; Control logic configured to control a cache operation, the cache operation receiving a cache read command from a memory controller and storing, in response to the cache read command, the data stored in the data register in the cache register during a cache read period, wherein the control logic controls the cache operation based on whether the cache read command is the first command received after a normal read command is received from the memory controller; And A skip signal generator configured to determine whether the cache read command is the first command and provide a skip signal indicating to the control logic to skip the cache operation based on the determination.

2. The memory device according to claim 1, wherein, When the cache read command is not the first command, the control logic controls the cache operation to perform the cache operation during the cache read period.

3. The memory device according to claim 1, wherein, The control logic is further configured to determine whether to store the data stored in the data register in the cache register during the cache read period and determine whether to skip the cache operation based on the determination.

4. The memory device according to claim 2, wherein, The control logic is further configured to output a ready-busy signal indicating a busy state of the memory device to the memory controller during the cache read period.

5. The memory device according to claim 4, wherein, When the cache read command is the first command, during a period shorter than the cache read period, the control logic outputs the ready-busy signal indicating the busy state to the memory controller.

6. The memory device according to claim 1, wherein, The control logic is further configured to provide a normal read signal corresponding to a normal read period longer than the cache read period to the skip signal generator in response to the normal read command.

7. The memory device according to claim 6, wherein, The skip signal generator is further configured to activate the skip signal based on the normal read signal.

8. The memory device according to claim 6, wherein, The control logic is further configured to generate a cache completion signal indicating whether the data stored in the data register is stored in the cache register during the cache read period.

9. The memory device according to claim 8, wherein, The skip signal generator is further configured to deactivate the skip signal based on the cache completion signal.

10. The memory device according to claim 8, wherein, The skip signal generator includes a flip-flop configured to: Receive one of a high-level signal and a low-level signal, the normal read signal, and the cache completion signal; Output the received one of the high-level signal and the low-level signal according to the normal read signal; and Reset the output in response to the cache completion signal.

11. The memory device according to claim 10, wherein, The skip signal generator further includes a multiplexer configured to select one of the high-level signal and the low-level signal and output the selected one to the flip-flop.

12. A method of operating a memory device, the method comprising: Receiving a cache read command from a memory controller; Determining whether the cache read command is the first command received after a normal read command is received from the memory controller; Performing a cache operation of storing data stored in a data register in a cache register according to the determination; And Activating a skip signal indicating to skip the cache operation according to the determination.

13. The method according to claim 12, wherein, When the cache read command is not the first command, performing the cache operation.

14. The method according to claim 12, wherein, The determination includes: determining whether to skip the execution of the cache operation according to whether data stored in the data register is stored in the cache register during a cache read period.

15. The method according to claim 12, wherein, The execution of the cache operation includes: outputting a ready-busy signal indicating a busy state of the memory device to the memory controller during a cache read period.

16. The method according to claim 15, wherein, The output includes: when the cache read command is the first command, outputting the ready-busy signal indicating the busy state to the memory controller during a period shorter than the cache read period.

17. The method according to claim 12, wherein, In response to the normal read command, activating the skip signal based on a normal read signal corresponding to a normal read period longer than the cache read period.

18. The method according to claim 12, wherein the method further comprises: During a cache read period, deactivating the skip signal based on a cache completion signal indicating whether data stored in the data register is stored in the cache register.

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