Signal processing method, device, electronic device and readable storage medium

Abstract

The embodiments of the present invention disclose a signal processing method, device, electronic device and readable storage medium. The method comprises: obtaining an input signal sequence, and processing the input signal sequence through the butterfly operation structure according to the frequency domain extraction fast Fourier transform FFT algorithm to obtain an intermediate result signal sequence; reordering the elements of the intermediate result signal sequence according to the discrete Fourier transform type; making numerical corrections to the reordered intermediate result signal sequence according to the discrete Fourier transform type to obtain the final output signal. Through the technical solution of the embodiment of the present invention, it is possible to simultaneously obtain the results of different discrete Fourier transform types of the input signal without changing the input signal and the FFT calculation process, thereby improving the calculation rate and reducing additional calculation overhead.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of signal processing technology, and in particular, to a signal processing method, device, electronic device and readable storage medium. Background Art

[0002] At present, Fast Fourier Transform (FFT) is often used when calculating Discrete Fourier Transform (DFT) to improve the calculation speed and reduce the consumption of hardware (memory) resources. When calculating the inverse Discrete Fourier Transform (IDFT), two fast calculation methods that reuse the FFT calculation structure are often used. One is to change the multiplicative coefficient of the butterfly operation, specifically: the input signal of the IDFT to be calculated is calculated according to the FFT calculation structure, and the FFT calculation structure is changed. Replace with Finally, the result output by the FFT calculation structure is divided by N. Another method is to conjugate the input signal, calculate the FFT, and finally deconjugate the FFT result.

[0003] However, if the IDFT is calculated by changing the multiplicative coefficients of the butterfly operation, the FFT calculation process will be changed; if the IDFT is calculated by taking the conjugate of the input signal, calculating the FFT, and then taking the anti-conjugate of the FFT result, the input signal needs to be numerically changed, and both of the above methods will bring additional storage or calculation overhead. Therefore, how to obtain the DFT and IDFT results of the input signal at the same time without changing the input signal and the FFT calculation process has always been a research difficulty. Summary of the invention

[0004] The embodiments of the present invention provide a signal processing method, device, electronic device and readable storage medium, which can simultaneously obtain different discrete Fourier transform types of input signal results without changing the input signal and the FFT calculation process.

[0005] In a first aspect, an embodiment of the present invention provides a signal processing method, including:

[0006] Acquire an input signal sequence, and process the input signal sequence according to a butterfly operation structure of a frequency domain extraction fast Fourier transform (FFT) algorithm through the butterfly operation structure to obtain an intermediate result signal sequence;

[0007] Reorder the elements of the intermediate result signal sequence according to the discrete Fourier transform type;

[0008] According to the discrete Fourier transform type, numerical correction is performed on the reordered intermediate result signal sequence to obtain the final output signal.

[0009] In a second aspect, an embodiment of the present invention further provides a signal processing device, the device comprising:

[0010] A frequency domain extraction butterfly operation module is used to obtain an input signal sequence, and process the input signal sequence according to the butterfly operation structure of the frequency domain extraction fast Fourier transform FFT algorithm through the butterfly operation structure to obtain an intermediate result signal sequence;

[0011] An element reordering module, used for reordering elements of the intermediate result signal sequence according to the discrete Fourier transform type;

[0012] The numerical correction module is used to perform numerical correction on the reordered intermediate result signal sequence according to the discrete Fourier transform type to obtain the final output signal.

[0013] In a third aspect, an embodiment of the present invention further provides an electronic device, including:

[0014] one or more processors;

[0015] a storage device for storing one or more programs,

[0016] When the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any embodiment of the present invention.

[0017] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in any embodiment of the present invention.

[0018] The technical solution of the embodiment of the present invention utilizes the butterfly operation structure of the fast Fourier transform FFT algorithm extracted in the frequency domain to process the input signal to obtain an intermediate result signal sequence, and then reorders the elements of the intermediate result signal sequence and performs numerical corrections according to the discrete Fourier transform type to obtain the final output signal. It can achieve the result of different discrete Fourier transform types of the input signal without changing the input signal and the FFT calculation process, thereby improving the calculation rate and reducing additional calculation overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1a is a flow chart of a signal processing method provided by an embodiment of the present invention;

[0020] Figure 1b is a schematic diagram of a DFT butterfly operation structure provided by an embodiment of the present invention;

[0021] Figure 1c It is a schematic diagram of a butterfly operation structure of a radix-2 FFT algorithm according to frequency domain extraction provided by an embodiment of the present invention;

[0022] Figure 2a is a flowchart of a preferred signal processing method provided by an embodiment of the present invention;

[0023] Figure 2b is a schematic diagram of a signal processing flow provided by an embodiment of the present invention;

[0024] Figure 3 is a structural schematic diagram of a signal processing device provided by an embodiment of the present invention;

[0025] Figure 4 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0027] Figure 1a A flowchart of a signal processing method provided by an embodiment of the present invention, Figure 1b is a schematic diagram of a DFT butterfly operation structure provided by an embodiment of the present invention, Figure 1c This is a schematic diagram of a butterfly operation structure of a radix-2 FFT algorithm according to frequency domain extraction provided by an embodiment of the present invention. This embodiment is applicable to the case where different discrete Fourier transform types of input signal results are obtained simultaneously without changing the input signal and the FFT calculation process. The method can be executed by a signal processing device, which can be implemented in hardware and / or software and can generally be integrated in an electronic device.

[0028] like Figure 1a As shown, a signal processing method provided by an embodiment of the present invention includes the following specific steps:

[0029] S110: Acquire an input signal sequence, and process the input signal sequence according to a butterfly operation structure of a frequency domain decimation fast Fourier transform (FFT) algorithm by using the butterfly operation structure to obtain an intermediate result signal sequence.

[0030] Among them, the input signal can refer to a discrete signal obtained by sampling an analog signal at a certain sampling rate; the input signal sequence can refer to a sequence obtained by arranging the input signals according to the sequence numbers of the input signals; the frequency domain fast Fourier transform FFT algorithm can be a frequency domain extraction radix-2FFT algorithm, or a frequency domain extraction radix-4FFT algorithm or other conventional algorithms; the intermediate result signal sequence can refer to a signal sequence obtained after processing by a butterfly operation structure.

[0031] It can be understood that in the embodiment of the present invention, the butterfly operation structure of the fast Fourier transform FFT algorithm according to the frequency domain extraction is determined by the type of transformation of the input signal. Exemplarily, in the embodiment of the present invention, taking the need to perform DFT on the input signal as an example, the basic principle of DFT can be as follows:

[0032]

[0033] Among them, X(k) is the DFT transform result of the input signal, N is the number of sampling points of the input signal, n is the sequence number of the input signal, k is the frequency order, that is, the kth frequency, and W is the rotation factor. and, It has the following properties:

[0034] 1) Conjugate symmetry:

[0035] 2) Periodicity:

[0036] 3) Reducibility:

[0037] The above properties can be used to change the basic principle of DFT as follows:

[0038]

[0039] Furthermore, X(k) can be divided into two parts according to the parity of k. For example, k=2r and k=2r+1 are taken as examples, where r=0, 1, ..., N / 2-1, then:

[0040]

[0041]

[0042] In summary, the calculation of N-point X(k) can be converted into the calculation of N / 2-point DFT of x1(n) and x2(n). The butterfly operation structure composed of x1(n) and x2(n) itself is as follows: Figure 1b As shown, where a=x(n), b=x(n+N / 2), A=x1(n), B=x2(n), and Figure 1cThe butterfly operation structure of the radix-2 FFT algorithm according to frequency domain extraction is the same as shown, where Figure 1c 8-point FFT calculation is used as an example. Therefore, the input signal sequence can be processed according to the butterfly operation structure of the frequency domain extraction fast Fourier transform FFT algorithm to obtain the DFT result.

[0043] Therefore, by processing the input signal sequence according to the butterfly operation structure of the frequency domain decimation fast Fourier transform FFT algorithm, the characteristics of the FFT algorithm can be used to improve the calculation speed and reduce the consumption of hardware memory resources.

[0044] Specifically, taking the input signal sequence {x(n), n=0, 1, ..., N-1} as an example, according to the butterfly operation structure of the FFT algorithm of frequency domain extraction, the calculated intermediate result signal sequence can be {X(i), i=0, 1, ..., N-1}, where N is the number of sampling points of the input signal.

[0045] S120: reordering elements of the intermediate result signal sequence according to the discrete Fourier transform type.

[0046] Optionally, the discrete Fourier transform types include: discrete Fourier transform DFT and inverse discrete Fourier transform IDFT.

[0047] The element reordering may refer to reordering the elements in the intermediate result signal sequence according to the sequence number arrangement order required by the discrete Fourier transform type. For example, taking the number of sampling points of the input signal as 8 points, Figure 1c From the schematic diagram of the butterfly operation structure of the radix-2 FFT algorithm according to frequency domain extraction, it can be seen that the arrangement order of the elements in the intermediate result signal sequence obtained after processing by the butterfly operation structure of the above FFT algorithm is 0, 4, 2, 6, 1, 5, 3, 7, which does not conform to the element arrangement order of the DFT type or IDFT type. Therefore, the elements of the intermediate result signal sequence need to be reordered to meet the requirements of the discrete Fourier transform type.

[0048] Optionally, reordering the elements of the intermediate result signal sequence according to the discrete Fourier transform type includes: determining a numerical bit flip sequence according to the sequence of the elements in the intermediate result signal sequence; determining a reordered sequence according to the numerical bit flip sequence and the discrete Fourier transform type; and reordering the elements of the intermediate result signal sequence according to the reordered sequence. The numerical bit flip sequence may refer to a sequence obtained by bit flipping the sequence numbers of the elements in the intermediate result signal sequence according to the sequence sequence.

[0049] In an optional implementation of an embodiment of the present invention, determining a numerical bit flip sequence according to a sequence of serial numbers of elements in an intermediate result signal sequence includes: converting the serial number of each element in the intermediate result signal sequence into binary to obtain a binary value; flipping the bit of the binary value between high and low bits to obtain a flipped binary value; and converting the flipped binary value into the same base as the sequence number of the element in the intermediate result signal sequence to obtain a numerical bit flip sequence.

[0050] Specifically, the sequence number required for the output result is {Idx(i), i=0, 1, ..., N-1}, where N is the number of sampling points of the input signal, the intermediate result signal sequence is {X(i), i=0, 1, ..., N-1}, the element sequence number sequence of the intermediate result signal sequence is a decimal sequence L={l, l=0, 1, ..., N-1}, and the numerical bit flip sequence number sequence is {L cvt (l), l = 0, 1, ..., N-1} as an example, the calculation process can be as follows: first, convert each element l of L into a log2 N-bit binary number l', then flip the bits of l' to get l", and finally, convert the binary number l" back to decimal to get the serial number L cvt (l). For example, when l=10, N=512, the calculation process is l′=000001010, l″=010100000, L cvt (10)=160, that is, when N=512, if the sequence number of an element in the intermediate result signal sequence is 10, the sequence number corresponding to the sequence number after the numerical bit is flipped is 160.

[0051] Therefore, by performing numerical bit flipping on the sequence numbers of each element in the intermediate result signal sequence, the conversion from the natural sequence to the reverse sequence can be achieved to determine the numerical bit flipped sequence number sequence.

[0052] In another optional implementation of the embodiment of the present invention, the reordered sequence is determined according to the numerical bit flip sequence and the discrete Fourier transform type, including: when the discrete Fourier transform type is DFT, the numerical bit flip sequence is used as the reordered sequence; when the discrete Fourier transform type is IDFT, the reordered sequence is determined based on the numerical bit flip sequence and the conversion relationship between DFT and IDFT. The conversion relationship between DFT and IDFT can be used to obtain the reordered sequence. Analyze the DFT result Y of the same sequence y(n) DFT (k) and IDFT result Y IDFT (l) is obtained, where k is the frequency order and l is the sequence number of the input signal. The specific process is as follows:

[0053]

[0054]

[0055] Substituting the variable mod(Nl, N) with l′ yields:

[0056]

[0057] Finally, we can conclude that the DFT result Y of the same sequence y(n) is DFT (k) and IDFT result Y IDFT (l) Having important relationship.

[0058] Optionally, determining the reordered sequence number based on the numerical bit flip sequence number and the conversion relationship between the DFT and the IDFT includes: determining the reordered sequence number based on the following formula: Idx(i)=mod(NL cvt (i), N), i = 0, 1, ..., N-1, where Idx(i) is the reordered sequence number sequence corresponding to IDFT, L cvt (i) is the numerical bit flip sequence corresponding to DFT, N is the number of sampling points of the input signal, and i is the sequence number of the input signal sequence.

[0059] Specifically, the numerical bit flip sequence is {L cv t(l), l=0,1,...,N-1}, the reordered sequence number is {Idx(i), i=0,1,...,N-1} as an example, when the discrete Fourier transform type is DFT, Idx(i)=L cvt (i), i = 0, 1, ..., N-1; when the discrete Fourier transform type is IDFT, Idx(i) = mod(NL cvt (i), N), i=0, 1, ..., N-1, where N is the number of sampling points of the input signal.

[0060] S130: performing numerical correction on the reordered intermediate result signal sequence according to the discrete Fourier transform type to obtain a final output signal.

[0061] The numerical correction may refer to correcting the reordered intermediate result signal sequence according to the discrete Fourier transform type so that the output signal satisfies the corresponding discrete Fourier transform type.

[0062] As mentioned before, the formulas for DFT and IDFT can be shown as follows:

[0063]

[0064]

[0065] Among them, X(k) is the DFT transform result of the input signal, x(n) is the IDFT transform result of the input signal, N is the number of sampling points of the input signal, n is the sequence number of the input signal, k is the number of frequencies, i.e., the kth frequency, and W is the rotation factor.

[0066] As can be seen from the above, DFT and IDFT have different requirements for coefficients. Therefore, the reordered intermediate result signal sequence needs to be further processed according to the discrete Fourier transform type to obtain an output signal that conforms to the discrete Fourier transform type.

[0067] In an optional implementation of an embodiment of the present invention, numerical correction is made to the reordered intermediate result signal sequence according to the discrete Fourier transform type to obtain the final output signal, including: when the discrete Fourier transform type is DFT, the reordered intermediate result signal sequence is transparently transmitted and the DFT result is output; when the discrete Fourier transform type is IDFT, the reordered intermediate result signal sequence is divided by N and the IDFT result is output, where N is the number of sampling points of the input signal sequence. Among them, transparent transmission can refer to directly outputting the reordered intermediate result signal sequence without making any changes to the reordered intermediate result signal sequence.

[0068] The technical solution of the embodiment of the present invention utilizes the butterfly operation structure of the fast Fourier transform FFT algorithm extracted in the frequency domain to process the input signal to obtain an intermediate result signal sequence, and then reorders the elements of the intermediate result signal sequence and performs numerical corrections according to the discrete Fourier transform type to obtain the final output signal. It can achieve the result of different discrete Fourier transform types of the input signal without changing the input signal and the FFT calculation process, thereby improving the calculation rate and reducing additional calculation overhead.

[0069] Figure 2a A flowchart of a preferred signal processing method provided by an embodiment of the present invention, Figure 2b It is a schematic diagram of a signal processing flow provided by an embodiment of the present invention.

[0070] like Figure 2a As shown, a preferred signal processing method provided by an embodiment of the present invention includes the following specific steps:

[0071] S210: Acquire an input signal sequence, and process the input signal sequence according to a butterfly operation structure of a frequency domain decimation fast Fourier transform (FFT) algorithm through the butterfly operation structure to obtain an intermediate result signal sequence.

[0072] The input signal sequence is {x(n), n=0, 1, ..., N-1}, and the intermediate result signal sequence is {X(i), i=0, 1, ..., N-1}.

[0073] S220: Obtain a log2 N-bit binary number l′ by performing binary conversion on each element l of the decimal sequence L={l, l=0, 1, . . . , N-1} of the elements in the intermediate result signal sequence.

[0074] S230: l″ is obtained by flipping the high and low bits of l′.

[0075] S240: Convert the binary number l″ back to decimal to obtain the numerical bit flip sequence L cvt (l).

[0076] S250: When the discrete Fourier transform type is DFT, the reordered sequence number sequence is determined as Idx(i)=L cvt (i), i = 0, 1, ..., N-1; when the discrete Fourier transform type is IDFT, the reordered sequence number sequence is determined as Idx(i) = mod(NL cvt (i), N), i=0, 1,..., N-1.

[0077] S260: According to the reordered sequence of serial numbers, the value of each element X(i) with serial numbers i=0, 1, ..., N-1 is sequentially covered to X(Idx(i)).

[0078] S270: Make numerical correction to the reordered intermediate result signal sequence according to the discrete Fourier transform type. When the discrete Fourier transform type is DFT, transparently transmit the reordered intermediate result signal sequence and output the DFT result. When the discrete Fourier transform type is IDFT, divide the reordered intermediate result signal sequence by N and output the IDFT result, where N is the number of sampling points of the input signal sequence.

[0079] The technical solution of the embodiment of the present invention utilizes the butterfly operation structure of the fast Fourier transform FFT algorithm extracted in the frequency domain, determines the reordered sequence number according to the calculated numerical bit flip sequence number and the discrete Fourier transform type, reorders the elements of the intermediate result signal sequence according to the reordered sequence number sequence, and finally performs numerical correction on the obtained signal sequence according to different discrete Fourier transform types to obtain the final output signal. It can reuse the same set of frequency domain extraction FFT calculation structure without changing the input signal and the FFT calculation process, and only reorders and divides the FFT output results to complete the calculation of DFT and IDFT at the same time, thereby improving the calculation rate and reducing additional calculation overhead.

[0080] Figure 3 The structure diagram of a signal processing device provided in an embodiment of the present invention is a schematic diagram of a signal processing device, which can execute the signal processing methods involved in the above embodiments. The device can be implemented in software and / or hardware, such as Figure 3 As shown, the signal processing device specifically includes: a frequency domain extraction butterfly operation module 310, an element reordering module 320, and a value correction module 330.

[0081] The frequency domain extraction butterfly operation module 310 is used to obtain an input signal sequence, and process the input signal sequence according to the butterfly operation structure of the frequency domain extraction fast Fourier transform FFT algorithm through the butterfly operation structure to obtain an intermediate result signal sequence;

[0082] An element reordering module 320, used to reorder the elements of the intermediate result signal sequence according to the discrete Fourier transform type;

[0083] The numerical correction module 330 is used to perform numerical correction on the reordered intermediate result signal sequence according to the discrete Fourier transform type to obtain the final output signal.

[0084] The technical solution of the embodiment of the present invention utilizes the butterfly operation structure of the fast Fourier transform FFT algorithm extracted in the frequency domain to process the input signal to obtain an intermediate result signal sequence, and then reorders the elements of the intermediate result signal sequence and performs numerical corrections according to the discrete Fourier transform type to obtain the final output signal. It can achieve the result of different discrete Fourier transform types of the input signal without changing the input signal and the FFT calculation process, thereby improving the calculation rate and reducing additional calculation overhead.

[0085] Optionally, the element reordering module 320 may include an element reordering submodule, which is used to determine a numerical bit flip sequence number sequence based on the sequence number sequence of elements in the intermediate result signal sequence; determine a reordered sequence number sequence based on the numerical bit flip sequence number sequence and a discrete Fourier transform type; and reorder elements of the intermediate result signal sequence based on the reordered sequence number sequence.

[0086] Optionally, the element reordering submodule may include a numerical bit flipping unit, which is used to obtain a binary value by converting the serial number of each element in the intermediate result signal sequence into binary; obtain a flipped binary value by flipping the bit of the binary value between high and low bits; and convert the flipped binary value into the same base as the element serial number in the intermediate result signal sequence to obtain a numerical bit flipped serial number sequence.

[0087] Optionally, the discrete Fourier transform types include: discrete Fourier transform DFT and inverse discrete Fourier transform IDFT.

[0088] Optionally, the element reordering submodule may further include a serial number sequence determination unit, which is used to use the numerical bit flipped serial number sequence as the reordered serial number sequence when the discrete Fourier transform type is DFT; when the discrete Fourier transform type is IDFT, determine the reordered serial number sequence based on the numerical bit flipped serial number sequence and the conversion relationship between DFT and IDFT.

[0089] Optionally, the sequence number determination unit may be specifically configured to determine the reordered sequence number based on the following formula: Idx(i)=mod(NL cvt (i), N), i = 0, 1, ..., N-1, where Idx(i) is the reordered sequence number sequence corresponding to IDFT, L cvt (i) is the numerical bit flip number sequence corresponding to DFT, N is the number of sampling points of the input signal, and i is the sequence number of the input signal sequence.

[0090] Optionally, the numerical correction module 330 may include a DFT numerical correction unit and an IDFT numerical correction unit;

[0091] The DFT value correction unit is used to transparently transmit the reordered intermediate result signal sequence and output the DFT result when the discrete Fourier transform type is DFT;

[0092] The IDFT value correction unit is used to divide the reordered intermediate result signal sequence by N when the discrete Fourier transform type is IDFT, and output the IDFT result, wherein N is the number of sampling points of the input signal sequence.

[0093] The signal processing device provided in the embodiment of the present invention can execute the signal processing method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0094] Figure 4 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown, the electronic device includes a processor 410, a memory 420, an input device 430, and an output device 440; the number of the processor 410 in the electronic device can be one or more. Figure 4 A processor 410 is taken as an example; the processor 410, the memory 420, the input device 430 and the output device 440 in the electronic device can be connected via a bus or other means. Figure 4 The example of connecting through bus is taken in the following.

[0095] The memory 420, as a computer-readable storage medium, can be used to store software programs, computer executable programs and modules, such as program instructions / modules corresponding to the signal processing method in the embodiment of the present invention (for example, the frequency domain extraction butterfly operation module 310, the element reordering module 320 and the numerical correction module 330 in the signal processing device). The processor 410 executes various functional applications and data processing of the electronic device by running the software programs, instructions and modules stored in the memory 420, that is, realizes the above-mentioned signal processing method.

[0096] The signal processing method comprises:

[0097] Acquire an input signal sequence, and process the input signal sequence according to a butterfly operation structure of a frequency domain extraction fast Fourier transform (FFT) algorithm through the butterfly operation structure to obtain an intermediate result signal sequence;

[0098] Reorder the elements of the intermediate result signal sequence according to the discrete Fourier transform type;

[0099] According to the discrete Fourier transform type, numerical correction is performed on the reordered intermediate result signal sequence to obtain the final output signal.

[0100] The memory 420 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system and at least one application required for a function; the data storage area may store data created according to the use of the terminal, etc. In addition, the memory 420 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 420 may further include a memory remotely arranged relative to the processor 410, and these remote memories may be connected to the electronic device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0101] The input device 430 may be used to receive input digital or character information and generate key signal input related to user settings and function control of the electronic device. The output device 440 may include a display device such as a display screen.

[0102] An embodiment of the present invention further provides a storage medium containing computer executable instructions, wherein the computer executable instructions are used to perform a signal processing method when executed by a computer processor, the method comprising:

[0103] Acquire an input signal sequence, and process the input signal sequence according to a butterfly operation structure of a frequency domain extraction fast Fourier transform (FFT) algorithm through the butterfly operation structure to obtain an intermediate result signal sequence;

[0104] Reorder the elements of the intermediate result signal sequence according to the discrete Fourier transform type;

[0105] According to the discrete Fourier transform type, numerical correction is performed on the reordered intermediate result signal sequence to obtain the final output signal.

[0106] Of course, the computer executable instructions of a storage medium including computer executable instructions provided by an embodiment of the present invention are not limited to the operations of the method described above, but can also execute related operations in the signal processing method provided by any embodiment of the present invention.

[0107] Through the above description of the implementation methods, the technicians in the relevant field can clearly understand that the present invention can be implemented by means of software and necessary general hardware, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (FLASH), a hard disk or an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0108] It is worth noting that in the embodiment of the above-mentioned signal processing device, the various units and modules included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention.

[0109] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A signal processing method, characterized in that: include: Acquire an input signal sequence, and process the input signal sequence according to a butterfly operation structure of a frequency domain extraction fast Fourier transform (FFT) algorithm through the butterfly operation structure to obtain an intermediate result signal sequence; Reorder the elements of the intermediate result signal sequence according to the discrete Fourier transform type; According to the discrete Fourier transform type, numerical correction is performed on the reordered intermediate result signal sequence to obtain the final output signal; Among them, the reordered intermediate result signal sequence is numerically corrected according to the discrete Fourier transform type, and the final output signal includes: When the discrete Fourier transform type is DFT, the reordered intermediate result signal sequence is transparently transmitted and the DFT result is output; When the discrete Fourier transform type is IDFT, the reordered intermediate result signal sequence is divided by N, and the IDFT result is output, where N is the number of sampling points of the input signal sequence.

2. The method according to claim 1, characterized in that Reordering the elements of the intermediate result signal sequence according to the discrete Fourier transform type includes: Determine a numerical bit flip sequence number sequence according to the sequence number sequence of elements in the intermediate result signal sequence; Determine a reordered sequence number sequence according to the numerical bit flip sequence number sequence and the discrete Fourier transform type; The elements of the intermediate result signal sequence are reordered according to the reordered sequence number sequence.

3. The method according to claim 2, characterized in that Determining the numerical bit flip sequence according to the sequence of the elements in the intermediate result signal sequence includes: By converting the sequence number of each element in the intermediate result signal sequence into a binary value, a binary value is obtained; Obtain a flipped binary value by flipping the bits of the binary value between high and low bits; The flipped binary value is converted into the same base as the element number in the intermediate result signal sequence to obtain a numerical bit flip number sequence.

4. The method according to claim 2, characterized in that: The discrete Fourier transform types include: discrete Fourier transform DFT and inverse discrete Fourier transform IDFT.

5. The method according to claim 4, characterized in that The reordered sequence is determined according to the numerical bit flip sequence and the discrete Fourier transform type, including: When the discrete Fourier transform type is DFT, the numerical bit flip sequence is used as the reordered sequence; When the discrete Fourier transform type is IDFT, the reordered sequence number sequence is determined based on the numerical bit flip sequence number sequence and the conversion relationship between DFT and IDFT.

6. The method according to claim 5, characterized in that The reordered sequence number sequence is determined based on the numerical bit flip sequence number and the conversion relationship between the DFT and the IDFT, including: The reordered sequence number is determined based on the following formula: Idx(i)=mod(N-L cvt (i),N),i=0,1,…,N-1; Among them, Idx(i) is the reordered sequence number sequence corresponding to IDFT, L cvt (i) is the numerical bit flip sequence corresponding to DFT, N is the number of sampling points of the input signal sequence, and i is the sequence number of the input signal sequence.

7. A signal processing device, characterized in that: include: A frequency domain extraction butterfly operation module is used to obtain an input signal sequence, and process the input signal sequence according to the butterfly operation structure of the frequency domain extraction fast Fourier transform FFT algorithm through the butterfly operation structure to obtain an intermediate result signal sequence; An element reordering module, used for reordering elements of the intermediate result signal sequence according to the discrete Fourier transform type; A numerical correction module is used to perform numerical correction on the reordered intermediate result signal sequence according to the discrete Fourier transform type to obtain the final output signal; Wherein, the numerical correction module includes a DFT numerical correction unit and an IDFT numerical correction unit; A DFT value correction unit is used to transparently transmit the reordered intermediate result signal sequence and output the DFT result when the discrete Fourier transform type is DFT; The IDFT value correction unit is used to divide the reordered intermediate result signal sequence by N when the discrete Fourier transform type is IDFT, and output the IDFT result, wherein N is the number of sampling points of the input signal sequence.

8. An electronic device, characterized in that: include: one or more processors; a storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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