Display device

Abstract

The present application relates to a display device. The display device comprises a substrate, a first circuit portion and a second circuit portion on the substrate and spaced apart from each other in a first direction, and an emission portion between the first circuit portion and the second circuit portion, the emission portion being located between the first circuit portion and the second circuit portion in a direction parallel to the substrate, wherein the first circuit portion comprises a first electrode extending to the emission portion, wherein the second circuit portion comprises a second electrode extending to the emission portion, and wherein the emission portion comprises a light emitting element located between the first electrode and the second electrode.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0075997, filed on June 22, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of this disclosure relate to display devices. Background Technology

[0004] With increasing interest in information display and growing demand for portable information media, the need for display devices has increased significantly, and their commercialization is already underway. Summary of the Invention

[0005] Various embodiments of this disclosure relate to display devices that can simplify the manufacturing process of display devices and reduce their manufacturing costs.

[0006] The aspects of this disclosure are not limited to the features described above, and those skilled in the art will clearly understand from the appended claims other aspects not mentioned.

[0007] One or more exemplary embodiments of this disclosure may include a display device comprising: a substrate; a first circuit portion and a second circuit portion, disposed on the substrate and spaced apart from each other in a first direction; and an emitting portion, located between the first circuit portion and the second circuit portion in a direction parallel to the substrate. The first circuit portion may include a first electrode extending to the emitting portion. The second circuit portion may include a second electrode extending to the emitting portion. The emitting portion may include a light-emitting element located between the first electrode and the second electrode.

[0008] In some embodiments, the display device may further include a first insulating layer, wherein at least a portion of the first insulating layer is on a first electrode, and at least another portion of the first insulating layer is on a second electrode. The first insulating layer may be located between the substrate and the light-emitting element.

[0009] In some embodiments, the first circuit portion may include a third electrode, which is located on and in contact with the first end of the first electrode and the first end of the light-emitting element. The second circuit portion may include a fourth electrode, which is located on and in contact with the second end of the second electrode and the second end of the light-emitting element.

[0010] In some embodiments, the first insulating layer may include a first opening and a second opening, wherein a portion of the first electrode is exposed through the first opening and a portion of the second electrode is exposed through the second opening. A third electrode may contact the first electrode through the first opening. A fourth electrode may contact the second electrode through the second opening.

[0011] In some embodiments, the display device may include a second insulating layer, wherein at least a portion of the second insulating layer is on the third electrode, and at least another portion of the second insulating layer is on the light-emitting element. A fourth electrode may be on the second insulating layer.

[0012] In some implementations, the third and fourth electrodes may be formed in parallel on the same layer.

[0013] In some embodiments, each of the third and fourth electrodes may include a transparent conductive oxide.

[0014] In some embodiments, the display device may further include a fixing layer that surrounds at least a portion of the outer peripheral surface of the light-emitting element and exposes a first end and a second end of the light-emitting element. The fixing layer may be located between the light-emitting element and a third electrode.

[0015] In some embodiments, the first circuit portion may include a driving transistor located between the substrate and the first electrode and electrically connected to the light-emitting element. The driving transistor may include: an active layer on the substrate; a gate electrode on the active layer; and a first transistor electrode and a second transistor electrode located above the gate electrode and in contact with the active layer.

[0016] In some embodiments, the driving transistor may further include a third transistor electrode, which is on the first transistor electrode and electrically connected to the first transistor electrode through a contact hole. The first electrode may be integrally formed with the third transistor electrode.

[0017] In some embodiments, the driving transistor may further include a third transistor electrode, which is on the first transistor electrode and electrically connected to the first transistor electrode through a contact hole. The first electrode may be integrally formed with the first transistor electrode.

[0018] In some implementations, the driving transistor may also include a bottom electrode layer between the substrate and the active layer.

[0019] In some implementations, the first insulating layer may be in contact with the substrate and the light-emitting element.

[0020] In some embodiments, each of the first electrode and the second electrode may include a metal with appropriate reflectivity.

[0021] In some embodiments, the display device may further include a wavelength conversion layer on the light-emitting element. The wavelength conversion layer may include wavelength conversion particles and scattering particles. The wavelength conversion particles may include quantum dots.

[0022] One or more exemplary embodiments of this disclosure may include a display device comprising: a substrate; a first electrode and a second electrode on the substrate, the first electrode and the second electrode being on the same layer and spaced apart from each other; a first insulating layer on the first electrode and the second electrode; a light-emitting element on the first insulating layer and located between the first electrode and the second electrode; and a driving transistor located between the substrate and the first electrode and electrically connected to the light-emitting element. The first insulating layer may be located between the substrate and the light-emitting element and may contact the substrate exposed between the first electrode and the second electrode.

[0023] In some embodiments, the display device may further include: a third electrode electrically connecting the first electrode and a first end of the light-emitting element; and a fourth electrode electrically connecting the second electrode to a second end of the light-emitting element.

[0024] In some embodiments, the first insulating layer may include a first opening and a second opening, wherein a portion of the first electrode is exposed through the first opening and a portion of the second electrode is exposed through the second opening. A third electrode may contact the first electrode through the first opening. A fourth electrode may contact the second electrode through the second opening.

[0025] In some implementations, the third and fourth electrodes may be formed in parallel on the same layer.

[0026] In some embodiments, the display device may further include a second insulating layer on the third electrode. A fourth electrode may be on the second insulating layer.

[0027] Details of the various implementation methods are included in the detailed description and accompanying drawings. Attached Figure Description

[0028] Figure 1 and Figure 2 These are perspective and cross-sectional views illustrating a light-emitting element according to one or more exemplary embodiments of the present disclosure.

[0029] Figure 3 This is a perspective cross-sectional view showing a light-emitting element according to one or more exemplary embodiments of the present disclosure.

[0030] Figure 4 This is a cross-sectional view showing a light-emitting element according to one or more exemplary embodiments of the present disclosure.

[0031] Figure 5 This is a perspective cross-sectional view showing a light-emitting element according to one or more exemplary embodiments of the present disclosure.

[0032] Figure 6 and Figure 7 These are perspective and cross-sectional views illustrating a light-emitting element according to one or more exemplary embodiments of the present disclosure.

[0033] Figure 8 This is a schematic plan view of a display device according to one or more exemplary embodiments of the present disclosure.

[0034] Figures 9A to 9C Each is a circuit diagram illustrating a pixel according to one or more exemplary embodiments of the present disclosure.

[0035] Figure 10 This is a circuit diagram illustrating a pixel according to one or more exemplary embodiments of the present disclosure.

[0036] Figure 11 It is shown that it includes Figure 8 A plan view of an example of pixels in a display device.

[0037] Figure 12 It shows along Figure 11 A cross-sectional view of pixels intercepted by line A-A'.

[0038] Figures 13 to 15 It is a cross-sectional view of the corresponding pixels included in the display device according to various embodiments, and is corresponding to Figure 11 A sectional view of line A-A'.

[0039] Figure 16 It is a cross-sectional view of pixels included in a display device according to some embodiments, and is corresponding to Figure 11 A sectional view of line A-A'. Detailed Implementation

[0040] Aspects and features of this disclosure, as well as methods for implementing this disclosure, will become apparent to those skilled in the art upon taking into account the accompanying drawings and the embodiments described in detail below. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of this disclosure to those skilled in the art, and this disclosure will be defined solely by the appended claims and their equivalents.

[0041] It should be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on, directly connected to, or directly coupled to another element or layer, or one or more intervening elements or layers may exist. The shapes, dimensions, scales, angles, quantities, etc., of the components shown in the accompanying drawings for describing embodiments are for illustrative purposes only, and this disclosure is not limited to the shapes, dimensions, scales, angles, quantities, etc., of the components shown in the drawings. The same reference numerals always denote the same elements. Furthermore, in the drawings, the expressions of components unrelated to this disclosure may be omitted or simplified to make the description of this disclosure clear.

[0042] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure. In this disclosure, the singular form is also intended to include the plural form, unless the context clearly indicates otherwise.

[0043] The features of the various embodiments of this disclosure can be paired or combined with each other, either partially or completely, and can be technically interlocked and operated in various ways. These embodiments can be performed independently or in combination.

[0044] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0045] Figure 1 and Figure 2 These are perspective and cross-sectional views illustrating a light-emitting element according to one or more exemplary embodiments of the present disclosure. Although in Figure 1 and Figure 2 The diagram shows a cylindrical rod-shaped light-emitting element (LD), but the types and / or shapes of light-emitting elements (LDs) according to this disclosure are not limited thereto.

[0046] Reference Figure 1 and Figure 2 The light-emitting element (LD) may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element (LD) may be configured as a stack formed by continuously stacking the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 in one direction.

[0047] In some embodiments, the light-emitting element (LD) can be a rod-shaped light-emitting diode manufactured in the form of a rod. Here, the term "rod-shaped" includes rod-shaped and bar-shaped forms, such as cylindrical and prismatic shapes that are longer in the longitudinal direction than in the width direction, and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light-emitting element LD can be greater than the diameter D of the light-emitting element LD (or the width of its cross-section). In other words, the aspect ratio of the light-emitting element LD can be greater than 1.

[0048] The light-emitting element (LD) may include a first end and a second end opposite to each other in one direction. The first end and the second end of the light-emitting element (LD) may be surfaces exposed to the outside. For example, a second semiconductor layer 13 may be disposed on the first end of the light-emitting element (LD) and a first semiconductor layer 11 may be disposed on the second end of the light-emitting element (LD), or the second semiconductor layer 13 may be disposed on the second end of the light-emitting element (LD) and the first semiconductor layer 11 may be disposed on the first end of the light-emitting element (LD).

[0049] In some embodiments, the light-emitting element (LD) may have small dimensions corresponding to the nanometer or micrometer scale, such as a diameter D and / or length L in the range of 100 nm to 10 μm. However, the size of the light-emitting element (LD) is not limited to this. For example, the size of the light-emitting element (LD) can be varied in various ways depending on the design conditions of various devices (e.g., display devices) that employ light-emitting devices using the light-emitting element (LD) as a light source.

[0050] The first semiconductor layer 11 may include at least one n-type semiconductor material. For example, the first semiconductor layer 11 may include an n-type semiconductor material, which includes any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and is doped with a first conductive dopant such as Si, Ge, or Sn. However, the materials used to form the first semiconductor layer 11 are not limited to these, and the first semiconductor layer 11 may be formed from various other materials.

[0051] The active layer 12 can be formed on the first semiconductor layer 11 and has a single quantum well structure or a multiple quantum well structure. When the active layer 12 includes a material with a multiple quantum well structure, the active layer 12 can have a structure formed by alternately stacking multiple quantum layers and multiple well layers.

[0052] If an electric field with a certain voltage (e.g., a predetermined voltage) or greater is applied between the opposite ends of the light-emitting element (LD), the LD emits light through the recombination of electron-hole pairs in the active layer 12. Because the light emission of the LD can be controlled based on the aforementioned principle, the LD can be used as a light source for pixels in various light-emitting devices and display devices.

[0053] The active layer 12 can emit light in the wavelength range of 400 nm to 900 nm. For example, if the active layer 12 emits light in the blue or green wavelength range, the active layer 12 may include a nitrogen-containing inorganic material, such as AlGaN or AlGaInN. If the active layer 12 has a structure formed by alternately stacking quantum layers and well layers to form a multi-quantum-well structure, the quantum layers may include inorganic materials such as AlGaN or AlGaInN, and the well layers may include inorganic materials such as GaN or AlInN. In some embodiments, the active layer 12 may include AlGaInN as the quantum layer and AlInN as the well layer.

[0054] However, the materials and structures of the light-emitting element (LD) are not limited to this. The active layer 12 may have a structure formed by alternately stacking semiconductor materials with high bandgap energy and semiconductor materials with low bandgap energy. Furthermore, depending on the wavelength range of the emitted light, the active layer 12 may include group III to group V semiconductor materials. The light emitted from the active layer 12 is not limited to light with a blue or green wavelength range, and depending on the materials included in the active layer 12, the light emitted from the active layer 12 may be light with a red wavelength range.

[0055] Light emitted from the active layer 12 can be emitted in the longitudinal direction of the light-emitting element LD to the first and second ends of the light-emitting element LD. In addition, some light emitted from the active layer 12 can be emitted to the side surface (or outer circumferential surface) of the active layer 12. In other words, the directionality of the light emitted from the active layer 12 is not limited to any one direction.

[0056] The second semiconductor layer 13 may be disposed on the active layer 12 and may comprise a semiconductor material of a different type than that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may comprise at least one p-type semiconductor material. For instance, the second semiconductor layer 13 may comprise a p-type semiconductor material comprising any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second conductive dopant such as Mg, Zn, Ca, Se, or Ba. However, the materials used to form the second semiconductor layer 13 are not limited to these, and the second semiconductor layer 13 may be formed from various other materials.

[0057] Although the first semiconductor layer 11 and the second semiconductor layer 13 are each formed as a single layer in the accompanying drawings, this disclosure is not limited thereto. For example, the number of layers included in each of the first semiconductor layer 11 and the second semiconductor layer 13 may be increased depending on the material of the active layer 12. For example, the first semiconductor layer 11 and the second semiconductor layer 13 may also include a cladding layer or a tensile strain barrier reduction (TSBR) layer.

[0058] In some embodiments, the first length L1 of the first semiconductor layer 11 may be greater than the second length L2 of the second semiconductor layer 13.

[0059] In some embodiments, the light-emitting element LD may further include an insulating film INF disposed on the surface of the light-emitting element LD. The insulating film INF may be formed on the surface of the light-emitting element LD to surround the outer peripheral surface (e.g., the outer circumferential surface) of the active layer 12, and also surround the first semiconductor layer 11 and the second semiconductor layer 13.

[0060] In some implementations, the insulating film INF may allow the first and second ends of the light-emitting element LD to be exposed. For example, the insulating film INF may expose one end of each of the first semiconductor layer 11 and the second semiconductor layer 13 disposed opposite ends of the light-emitting element LD in the longitudinal direction. In other words, the insulating film INF may expose both surfaces of the cylinder (i.e., the top surface and the bottom surface) instead of covering them.

[0061] In some embodiments, the insulating film INF may comprise a transparent insulating material. For example, the insulating film INF may comprise one or more inorganic insulating materials selected from SiO2, Si3N4, Al2O3, and TiO2, but the materials used to form the insulating film INF are not particularly limited thereto. The insulating film INF can be formed from a variety of known insulating materials.

[0062] The insulating film INF prevents the active layer 12 from short-circuiting due to contact with conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. Furthermore, the insulating film INF reduces or minimizes defects on the surface of the light-emitting element LD, thereby improving the lifetime and efficiency of the LD. When multiple light-emitting elements LD are arranged in close contact with each other, the insulating film INF prevents unwanted short circuits between the light-emitting elements LD.

[0063] In some embodiments, the light-emitting element (LD) may include not only a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, and / or an insulating film INF, but also other additional components disposed above and / or below each layer. For example, the light-emitting element (LD) may also include at least one phosphor layer, at least one active layer, at least one semiconductor material layer, and / or at least one electrode layer disposed at at least one end of the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13.

[0064] Figure 3 This is a perspective cross-sectional view illustrating a light-emitting element according to one or more exemplary embodiments of the present disclosure. For the purpose of explanation, Figure 3 The image shows a portion of the insulating film INF that has been removed.

[0065] Together Figure 1 and Figure 2 refer to Figure 3 The light-emitting element LD may also include an electrode layer 14 disposed on the second semiconductor layer 13.

[0066] Electrode layer 14 may be an ohmic contact electrode electrically connected to the second semiconductor layer 13, but this disclosure is not limited thereto. In some embodiments, electrode layer 14 may be a Schottky contact electrode. Electrode layer 14 may include a metal or a metal oxide. For example, electrode layer 14 may include Cr, Ti, Al, Au, Ni, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc.

[0067] In some embodiments, the electrode layer 14 may be substantially transparent or semi-transparent. Thus, light generated from the active layer 12 of the light-emitting element LD can be emitted to the outside after passing through the electrode layer 14.

[0068] Figure 4 This is a cross-sectional view showing a light-emitting element according to one or more exemplary embodiments of the present disclosure.

[0069] Together Figure 3 Reference Figure 4 The insulating film INF' may have at least a partially curved shape in the corner region adjacent to the electrode layer 14. In some embodiments, the curved shape may be formed by an etching process when manufacturing the light-emitting element LD.

[0070] The electrode layer 14 is not included in Figure 1 and Figure 2 In the case of the light-emitting element LD shown, the insulating film INF' may also have a shape that is at least partially curved in its corner region.

[0071] Figure 5 This is a perspective cross-sectional view illustrating a light-emitting element according to one or more exemplary embodiments of the present disclosure. For example, Figure 5 The image shows a portion of the insulating film INF that has been removed.

[0072] Together Figure 1 and Figure 2 refer to Figure 5 The light-emitting element LD may further include a third semiconductor layer 15 disposed between the first semiconductor layer 11 and the active layer 12, and a fourth semiconductor layer 16 and a fifth semiconductor layer 17 disposed between the active layer 12 and the second semiconductor layer 13. In addition, the light-emitting element LD may further include a first electrode layer 14a formed on the upper surface of the second semiconductor layer 13 and a second electrode layer 14b formed on the lower surface of the first semiconductor layer 11.

[0073] Figure 5 LEDs and Figure 1 The implementation differs in that it also includes multiple semiconductor layers 15, 16, and 17, as well as electrode layers 14a and 14b, and the active layer 12 contains other elements. Aside from these differences, the arrangement and structure of the insulating film INF are similar to... Figure 1 The setup and structure of the insulating film INF are basically the same.

[0074] As mentioned above, in Figure 1 In the light-emitting element (LD), the active layer 12 may include nitrogen (N) and emit blue or green light. Figure 5 In the light-emitting element (LD), the active layer 12 and other semiconductor layers 11, 13, 15, 16, and 17 each include a phosphorus (P) semiconductor. In other words, according to... Figure 5 The light-emitting element (LD) of the embodiment can emit red light having a center wavelength band ranging from 620 nm to 750 nm. However, the center wavelength band of red light is not limited to the above range, and it should be understood that the center wavelength band includes all wavelengths that can be considered red in the technical field of this disclosure.

[0075] Specifically, according to Figure 5 In the light-emitting element (LD) of the embodiment described above, the first semiconductor layer 11 may include an n-type semiconductor material. For example, the first semiconductor layer 11 may include an n-type semiconductor material, which includes any one of InAlGaP, GaP, AlGaP, InGaP, AlP, and InP, and is doped with a first conductive dopant such as Si, Ge, or Sn. In some embodiments, the first semiconductor layer 11 may be n-AlGaInP doped with n-type Si.

[0076] The second semiconductor layer 13 may include a p-type semiconductor material. For example, the second semiconductor layer 13 may include a p-type semiconductor material, which includes any one of InAlGaP, GaP, AlGaNP, InGaP, AlP, and InP, and is doped with a second conductive dopant such as Mg, Zn, Ca, Se, or Ba. In some embodiments, the second semiconductor layer 13 may be p-GaP doped with p-type Mg.

[0077] The active layer 12 can be disposed between the first semiconductor layer 11 and the second semiconductor layer 13. Figure 5 The active layer 12 may include a material having a single quantum well structure or a multiple quantum well structure, and in accordance with... Figure 1The active layer 12 emits light within a specific wavelength range in the same manner as the active layer 12. For example, the active layer 12 may comprise materials such as AlGaP and AlInGaP. For example, in the case where the active layer 12 has a structure formed by alternately stacking quantum layers and well layers into a multi-quantum-well structure, the quantum layers may comprise inorganic materials such as AlGaP or AlInGaP, and the well layers may comprise materials such as GaP or AlInP. In some embodiments, the active layer 12 may comprise AlGaInP as the quantum layer and AlInP as the well layer, and emit red light having a center wavelength band ranging from 620 nm to 750 nm.

[0078] Figure 5 The light-emitting element (LD) may include a cladding layer disposed adjacent to the active layer 12. For example, the third semiconductor layer 15 and the fourth semiconductor layer 16 disposed below and above the active layer 12 between the first semiconductor layer 11 and the second semiconductor layer 13, respectively, may be cladding layers.

[0079] The third semiconductor layer 15 may be disposed between the first semiconductor layer 11 and the active layer 12. The third semiconductor layer 15 may comprise an n-type semiconductor material in the same manner as the first semiconductor layer 11. In some embodiments, the third semiconductor layer 15 may be n-AlInP, but this disclosure is not limited thereto.

[0080] A fourth semiconductor layer 16 may be disposed between the active layer 12 and the second semiconductor layer 13. The fourth semiconductor layer 16 may comprise a p-type semiconductor material in the same manner as the second semiconductor layer 13. In some embodiments, the fourth semiconductor layer 16 may be p-AlInP.

[0081] A fifth semiconductor layer 17 may be disposed between the fourth semiconductor layer 16 and the second semiconductor layer 13. The fifth semiconductor layer 17 may comprise a p-type semiconductor material in the same manner as the second semiconductor layer 13 and the fourth semiconductor layer 16. In some embodiments, the fifth semiconductor layer 17 may be used to reduce the lattice constant difference between the fourth semiconductor layer 16 and the second semiconductor layer 13. For example, the fifth semiconductor layer 17 may be a tensile strain barrier reduction (TSBR) layer. In some embodiments, the fifth semiconductor layer 17 may include p-GaInP, p-AlInP, p-AlGaInP, etc., but this disclosure is not limited thereto.

[0082] The first electrode layer 14a and the second electrode layer 14b can be disposed on the second semiconductor layer 13 and the first semiconductor layer 11, respectively. The first electrode layer 14a can be disposed on the upper surface of the second semiconductor layer 13, and the second electrode layer 14b can be disposed below the lower surface of the first semiconductor layer 11. In some embodiments, at least one of the first electrode layer 14a and the second electrode layer 14b can be omitted. The first electrode layer 14a and the second electrode layer 14b each may include as... Figure 3 Examples of electrode layer 14 include at least one of the listed materials.

[0083] Figure 6 and Figure 7 These are perspective and cross-sectional views illustrating a light-emitting element according to one or more exemplary embodiments of the present disclosure.

[0084] Reference Figure 6 and Figure 7 According to some embodiments, a light-emitting element LD' includes a first semiconductor layer 11', a second semiconductor layer 13', and an active layer 12' interposed between the first semiconductor layer 11' and the second semiconductor layer 13'. In some embodiments, the first semiconductor layer 11' may be disposed in the central region of the light-emitting element LD', and the active layer 12' may be disposed on the surface of the first semiconductor layer 11' to surround at least one region of the first semiconductor layer 11' along its edge or periphery. The second semiconductor layer 13' may be disposed on the surface of the active layer 12' to surround at least one region of the active layer 12' along its edge or periphery.

[0085] The light-emitting element LD' may further include an electrode layer 14' and / or an insulating film INF', the electrode layer 14' and / or the insulating film INF' being configured to surround at least one region of the second semiconductor layer 13' along its edge or periphery. For example, the light-emitting element LD' may also include an electrode layer 14' disposed on the surface of the second semiconductor layer 13' to surround a region of the second semiconductor layer 13' and an insulating film INF' disposed on the surface of the electrode layer 14' to surround at least one region of the electrode layer 14' along its edge or periphery. In other words, the light-emitting element LD' according to the above embodiments can be implemented as a core-shell structure comprising a first semiconductor layer 11', an active layer 12', a second semiconductor layer 13', an electrode layer 14', and an insulating film INF' continuously disposed in an outward direction from the center to the periphery of the light-emitting element LD'. In some embodiments, the electrode layer 14' and / or the insulating film INF' may be omitted.

[0086] In some embodiments, the light-emitting element LD' can be configured as a multifaceted pyramid extending in one direction (e.g., the length L' direction). For example, the light-emitting element LD' can have a hexagonal pyramid shape. However, the shape of the light-emitting element LD' is not limited to the above-described shape and can be changed in various ways.

[0087] In some embodiments, the opposite ends of the first semiconductor layer 11' may have a shape that protrudes along the length L' direction of the light-emitting element LD'. The shapes of the opposite ends of the first semiconductor layer 11' may differ from each other. For example, one end of the opposite ends of the first semiconductor layer 11' located at the upper position may have a horn shape, with the width of the horn shape decreasing upward to form a apex. Furthermore, the other end of the opposite ends of the first semiconductor layer 11' located at the lower position may have a prism shape with a certain width (e.g., a predetermined width).

[0088] In some embodiments, the first semiconductor layer 11' may be disposed in the core of the light-emitting element LD', that is, disposed in the center (or middle) portion of the light-emitting element LD'. Furthermore, the light-emitting element LD' may have a shape corresponding to the shape of the first semiconductor layer 11'. For example, if the first semiconductor layer 11' has a hexagonal pyramid shape, then the light-emitting element LD' may have a hexagonal pyramid shape.

[0089] In the following exemplary implementation, the use of Figure 1 and Figure 2 An example of a light-emitting element (LD) is shown. Those skilled in the art will understand that, including... Figures 3 to 7 Various types of light-emitting elements LD / LD' shown can be applied to exemplary embodiments.

[0090] Figure 8 This is a schematic plan view of a display device according to some embodiments of the present disclosure.

[0091] Reference Figure 1 , Figure 2 and Figure 8 The display device 1000 may include a substrate SUB and a plurality of pixels PXL disposed on the substrate SUB. The substrate SUB may include a display area DA and a non-display area NDA. The plurality of pixels PXL are formed in the display area DA to display an image. The non-display area NDA is the other area of ​​the substrate SUB besides the display area DA. The non-display area NDA may surround the display area DA along its edge or periphery.

[0092] The substrate SUB can be formed from glass, quartz, ceramic, plastic, etc. When the substrate SUB includes plastic, it can be formed from a flexible substrate, but this disclosure is not limited thereto. For example, the substrate SUB can include organic materials such as polyimide (PI).

[0093] The display area DA can be the area where the pixel PXL is set. The non-display area NDA can be the area where the drivers SDV (e.g., scan driver), DDV (e.g., data driver), and EDV (e.g., transmit control driver) are set, as well as various lines used to connect the pixel PXL to the drivers SDV, DDV, and EDV.

[0094] The display area DA can have various shapes. For example, the display area DA can be set in various forms, such as a closed polygon with sides formed by linear lines, a circle or ellipse with sides formed by curves, and a semicircle or semi-ellipse with sides formed by both linear lines and curves.

[0095] In cases where the display area DA comprises multiple regions, each region may also have various shapes as described above. The surface areas of the multiple regions may be the same or different from each other. In some embodiments of this disclosure, examples will be described in which the display area DA is provided with a single region having a rectangular shape (or a generally rectangular shape) including linear sides.

[0096] The non-display area NDA can be located on at least one side of the display area DA. In some embodiments, the non-display area NDA can surround the display area DA.

[0097] Pixels PXL can be disposed in the display area DA on the substrate SUB. Each of the pixels PXL may include at least one light-emitting element LD, which is connected to scan lines and data lines and configured to be driven in response to corresponding scan signals and corresponding data signals.

[0098] Each of the pixels PXL can emit light of any color, including red, green, and blue, and is not limited to these. For example, each of the pixels PXL can emit light of any color, including cyan, magenta, yellow, and white.

[0099] In some implementations, a pixel PXL may include a first pixel PXL1 (or a first sub-pixel) configured to emit light of a first color, a second pixel PXL2 (or a second sub-pixel) configured to emit light of a second color different from the first color, and a third pixel PXL3 (or a third sub-pixel) configured to emit light of a third color different from the first or second color. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3, arranged adjacent to each other, may form a pixel unit PXU, which may emit light of various colors.

[0100] In some implementations, the first pixel PXL1 may be a red pixel that emits red light, the second pixel PXL2 may be a green pixel that emits green light, and the third pixel PXL3 may be a blue pixel that emits blue light.

[0101] In some embodiments, each pixel PXL may be provided with a light-emitting element LD configured to emit light of the same color, and may include different color conversion layers disposed on each light-emitting element LD, thereby enabling the emission of light of different colors. In some embodiments, each pixel PXL may include a light-emitting element LD configured to emit light of different colors.

[0102] Pixel PXL can be arranged on the first direction DR1 and the second direction DR2 intersecting the first direction DR1. However, the arrangement of pixel PXL is not particularly restricted and can be arranged in various forms.

[0103] The drivers SDV, DDV, and EDV can provide signals to pixel PXL via corresponding lines (not shown), and thus control the operation of pixel PXL. Figure 8 For ease of explanation, lines have been omitted.

[0104] The drivers SDV, DDV, and EDV may include a scan driver SDV, a data driver DDV, a transmit control driver EDV, and a timing controller (not shown). The scan driver SDV is configured to provide scan signals to the pixel PXL via scan lines, the data driver DDV is configured to provide data signals to the pixel PXL via data lines, and the transmit control driver EDV is configured to provide transmit control signals to the pixel PXL via transmit control lines. The timing controller can control the scan driver SDV, the data driver DDV, and the transmit control driver EDV.

[0105] In some implementations, the transmit control driver (EDV) can be omitted. Furthermore, in some implementations, the timing controller can be integrated with the data driver (DDV) and configured as a single unit.

[0106] The scan driver SDV can be disposed on one side of the substrate SUB and arranged along one direction (e.g., a second direction DR2). The scan driver SDV can be mounted on the substrate SUB as a separate component, but this disclosure is not limited thereto. For example, the scan driver SDV can be formed directly on the substrate SUB. Furthermore, the scan driver SDV can be located outside the substrate SUB and connected to the pixel PXL via a connector.

[0107] The data driver DDV can be disposed on one side of the substrate SUB and can extend in a direction (e.g., a first direction DR1) that intersects the direction of the scan driver SDV (e.g., a second direction DR2). Furthermore, the data driver DDV can be disposed as a separate component on the substrate SUB, or it can be located outside the substrate SUB and connected to the pixel PXL via a connector.

[0108] The emitter control driver (EDV) can be disposed on one side of the substrate (SUB) and can extend in the same direction (e.g., second direction DR2) as the scan driver (SDV) extends. Figure 8 As shown, the transmit control driver EDV can be located on the same side as the scan driver SDV, but this disclosure is not limited thereto. For example, the transmit control driver EDV can be located on a different side from the scan driver SDV. The transmit control driver EDV can be mounted on the substrate SUB as a separate component, but this disclosure is not limited thereto. For example, the transmit control driver EDV can be formed directly on the substrate SUB, or it can be located outside the substrate SUB and connected to the pixel PXL via a connector.

[0109] In some implementations, each of the pixels PXL may be formed by an active pixel. However, the type, structure, and / or driving scheme of the pixels PXL applicable to this disclosure are not particularly limited.

[0110] Figures 9A to 9C This is a circuit diagram illustrating pixels according to various embodiments. In some embodiments, Figures 9A to 9C An example of pixels forming an active emission display panel is shown.

[0111] Reference Figure 1 , Figure 2 and Figure 9A Each of the pixels PXL may include at least one light-emitting element LD and a driving circuit DC connected to the light-emitting element LD and configured to drive the light-emitting element LD.

[0112] The first electrode (e.g., the anode electrode) of the light-emitting element (LD) can be connected to a first driving power supply VDD via a driving circuit DC. The second electrode (e.g., the cathode electrode) of the light-emitting element (LD) can be connected to a second driving power supply VSS. The light-emitting element (LD) can emit light with a brightness corresponding to the amount of driving current controlled by the driving circuit DC.

[0113] Although only one light-emitting element (LD) is shown in 9A, this disclosure is not limited thereto. In some embodiments, a pixel PXL may include multiple light-emitting elements (LDs). The multiple light-emitting elements (LDs) included in the pixel PXL may be connected in parallel and / or in series with each other. In some embodiments, instead of one or more light-emitting elements (LDs) connected in the forward direction, or in addition to one or more light-emitting elements (LDs) connected in the forward direction, the pixel PXL may include one or more light-emitting elements (LDs) connected in the reverse direction.

[0114] The first driving power supply VDD and the second driving power supply VSS can have different potentials. For example, the first driving power supply VDD can have a potential that is equal to or greater than the threshold voltage of the light-emitting element LD. In other words, the voltage applied through the first driving power supply VDD can be greater than the voltage applied through the second driving power supply VSS.

[0115] In some embodiments of this disclosure, the driving circuit DC may include a first transistor M1, a second transistor M2, and a storage capacitor Cst.

[0116] The first electrode of the first transistor (e.g., a driver transistor) M1 may be connected to a first driving power supply VDD, and its second electrode may be electrically connected to the first electrode (e.g., the anode electrode) of the light-emitting element LD. The gate electrode of the first transistor M1 may be connected to a first node N1. The first transistor M1 may control the amount of driving current to be supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0117] The first electrode of the second transistor (e.g., a switching transistor) M2 can be connected to the data line DL, and its second electrode can be connected to the first node N1. Here, the first and second electrodes of the second transistor M2 can be different electrodes. For example, if the first electrode is the source electrode, then the second electrode is the drain electrode. The gate electrode of the second transistor M2 can be connected to the scan line SL.

[0118] When a scan signal with a voltage capable of turning on the second transistor M2 (e.g., a gate on-voltage, or a low-level voltage) is provided from the scan line SL, the second transistor M2 is turned on to electrically connect the data line DL to the first node N1. Here, the data signal of the corresponding frame is provided to the data line DL, thereby allowing the data signal to be transmitted to the first node N1. The data signal transmitted to the first node N1 can be stored in a storage capacitor Cst. For example, the storage capacitor Cst can store the charge corresponding to the data signal transmitted to the first node N1 from the data line DL.

[0119] One electrode of the storage capacitor Cst can be connected to the first drive power supply VDD, and the other electrode can be connected to the first node N1. The storage capacitor Cst can be charged with a voltage corresponding to the data signal provided to the first node N1 (or store the corresponding charge), and maintain the charging voltage until the data signal of the subsequent frame is provided.

[0120] For ease of explanation, Figure 9A A driving circuit DC with a relatively simple structure is shown. The driving circuit DC includes a second transistor M2 configured to transmit data signals to the internals of each of the pixels PXL, a storage capacitor Cst configured to store the data signals, and a first transistor M1 configured to provide a driving current corresponding to the data signals to the light-emitting element LD.

[0121] However, this disclosure is not limited thereto, and the structure of the driving circuit DC can be changed in various ways. For example, the driving circuit DC may also include other circuit elements, such as a compensation transistor configured to compensate the threshold voltage of the first transistor M1, an initialization transistor configured to initialize the first node N1, and / or an emission control transistor configured to control the emission time of the light-emitting element LD.

[0122] Furthermore, despite Figure 9A The first transistor M1 and the second transistor M2 included in the drive circuit DC are shown to be formed of P-type transistors, but this disclosure is not limited thereto. In other words, at least one of the first transistor M1 and the second transistor M2 included in the drive circuit DC can be changed to an N-type transistor.

[0123] For example, such as Figure 9B As shown, each of the first transistor M1 and the second transistor M2 in the drive circuit DC can be implemented as an N-type transistor. Aside from the change in the connection positions of some components (e.g., the storage capacitor Cst) due to the change in transistor type, Figure 9B The configuration and operation of the DC drive circuit shown can be similar to Figure 9A Configuration and operation of the DC drive circuit.

[0124] In some implementations, reference Figure 9C The pixel PXL may also include a third transistor (e.g., a sensing transistor) M3.

[0125] The gate electrode of the third transistor M3 can be connected to the sensing signal line SSL. One electrode of the third transistor M3 can be connected to the sensing line SENL, and the other electrode of the third transistor M3 can be connected to the first electrode (e.g., the anode electrode) of the light-emitting element LD. In response to a sensing signal provided to the sensing signal line SSL during a sensing cycle, the third transistor M3 can transmit the voltage value of the first electrode of the light-emitting element LD to the sensing line SENL. The voltage value transmitted through the sensing line SENL can be provided to external circuitry (e.g., a timing controller). The external circuitry can extract information about the characteristics of pixel PXL (e.g., the threshold voltage of the first transistor M1, etc.) based on the provided voltage value. The extracted characteristic information can be used to transform image data to compensate for deviations in the characteristics of pixel PXL.

[0126] Figure 10 This is a circuit diagram illustrating a pixel according to one or more exemplary embodiments of the present disclosure.

[0127] Reference Figure 10 A pixel PXL according to one or more exemplary embodiments of the present disclosure may include a light-emitting element LD, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7, and a storage capacitor Cst.

[0128] The first electrode (e.g., the anode electrode) of the light-emitting element LD can be connected to the first transistor T1 via a sixth transistor T6. The second electrode (e.g., the cathode electrode) of the light-emitting element LD can be connected to a second driving power supply VSS. The light-emitting element LD can emit light with a brightness (e.g., a predetermined brightness) corresponding to the amount of driving current supplied from the first transistor T1.

[0129] The first electrode of the first transistor (e.g., a driving transistor) T1 can be connected to the first driving power supply VDD via the fifth transistor T5, and the second electrode of the first transistor T1 can be connected to the first electrode of the light-emitting element LD via the sixth transistor T6. The first transistor T1 can control the amount of current flowing from the first driving power supply VDD to the second driving power supply VSS via the light-emitting element LD in response to the voltage of the first node N1, which is its gate electrode.

[0130] A second transistor (e.g., a switching transistor) T2 may be connected between the data line DL and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the scan line SL. When a scan signal with a gate on-state voltage (e.g., a low-level voltage) is provided to the scan line SL, the second transistor T2 may be turned on, allowing the data line DL to be electrically connected to the first electrode of the first transistor T1.

[0131] A third transistor T3 can be connected between the second electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 can be connected to the scan line SL. When a scan signal with a gate on-state voltage (e.g., a low-level voltage) is provided from the scan line SL, the third transistor T3 can be turned on, so that the second electrode of the first transistor T1 can be electrically connected to the first node N1.

[0132] A fourth transistor T4 can be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 can be connected to scan line SL-1 (e.g., the previous scan line). When a scan signal with a gate on-state voltage is provided to scan line SL-1, the fourth transistor T4 turns on, allowing the voltage of the initialization power supply Vint to be provided to the first node N1. The initialization power supply Vint can be set to a voltage lower than the voltage of the data signal.

[0133] The fifth transistor T5 can be connected between the first drive power supply VDD and the first electrode of the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to the emitter control line EL. The fifth transistor T5 can be turned on when an emitter control signal with a gate on-state voltage (e.g., a low-level voltage) is provided to the emitter control line EL, and the fifth transistor T5 can be turned off under other conditions.

[0134] The sixth transistor T6 is connected between the second electrode of the first transistor T1 and the first electrode (e.g., the anode electrode) of the light-emitting element LD. The gate electrode of the sixth transistor T6 can be connected to the emitter control line EL. The sixth transistor T6 can be turned on when an emitter control signal with a gate turn-on voltage (e.g., a low-level voltage) is provided to the emitter control line EL, and the sixth transistor T6 can be turned off under other conditions.

[0135] A seventh transistor T7 can be connected between the initialization power supply Vint and the first electrode (e.g., the anode electrode) of the light-emitting element LD. The gate electrode of the seventh transistor T7 can be connected to scan line SL+1 (e.g., the next scan line). When a scan signal with a gate on-state voltage (e.g., a low-level voltage) is provided to scan line SL+1, the seventh transistor T7 can be turned on, so that the voltage of the initialization power supply Vint can be provided to the first electrode (e.g., the anode electrode) of the light-emitting element LD.

[0136] Figure 10 The illustration shows the seventh transistor T7 with its gate electrode connected to scan line SL+1. However, the spirit of this disclosure is not limited thereto. For example, in some embodiments of this disclosure, the gate electrode of the seventh transistor T7 may be connected to scan line SL or scan line SL-1. In this case, when a scan signal with a gate on voltage is provided to scan line SL or scan line SL-1, the voltage of the initialization power supply Vint may be provided to the first electrode (e.g., the anode electrode) of the light-emitting element LD via the seventh transistor T7.

[0137] The storage capacitor Cst can be connected between the first drive power supply VDD and the first node N1. The storage capacitor Cst can store the voltage (or charge) corresponding to both the data signal and the threshold voltage of the first transistor T1.

[0138] Despite Figure 10 In the present disclosure, the transistors included in the DC drive circuit (e.g., first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7) have been shown as being formed of P-type transistors, but this disclosure is not limited thereto. For example, at least one of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7 may be changed to N-type transistors.

[0139] Figure 11 It is shown that it includes Figure 8 A plan view of an example of pixels in a display device. Figure 12 It shows along Figure 11 A cross-sectional view of pixels intercepted by line A-A'.

[0140] For ease of explanation, each electrode will be simplified and shown below as being formed of a single electrode layer, but this disclosure is not limited thereto. Each electrode may be formed of multiple electrode layers. In some embodiments of this disclosure, the phrase "components at the same layer (or formed and / or disposed at the same layer (or on the same layer))" may mean that the components are formed by the same process and are made of the same material.

[0141] Although for the sake of explanation, Figure 11 Multiple light-emitting elements (LDs) are shown aligned in a first direction DR1, but the alignment direction of the LDs is not limited to this. For example, some of the LDs can be aligned in a direction diagonally opposite to the first direction DR1.

[0142] Reference Figure 11 and Figure 12According to some embodiments of this disclosure, the pixel PXL may include a first circuit portion PCL1, a second circuit portion PCL2, and an emitter portion DPL disposed on a substrate SUB. In some embodiments, the first circuit portion PCL1 and the second circuit portion PCL2 may be disposed on the substrate SUB at positions spaced apart from each other in a first direction DR1. The emitter portion DPL may be disposed in the space defined between the first circuit portion PCL1 and the second circuit portion PCL2. Therefore, the first circuit portion PCL1, the second circuit portion PCL2, and the emitter portion DPL may be horizontally disposed on the substrate SUB along a second direction DR2 intersecting the first direction DR1.

[0143] The first circuit portion PCL1 and the second circuit portion PCL2 may each include multiple layers. For example, the first circuit portion PCL1 and the second circuit portion PCL2 may each include a buffer layer BF, a gate insulating layer GI, a first interlayer insulating layer ILD1 and a second interlayer insulating layer ILD2 sequentially disposed on a substrate SUB.

[0144] The first circuit portion PCL1 and the second circuit portion PCL2 may include driving circuitry constituting pixel PXL (e.g., Figure 9A The driving circuit (DC) comprises multiple circuit elements. For example, the first circuit portion PCL1 may include a driving transistor TFT configured to provide a driving signal. The second circuit portion PCL2 may include a first conductive line MTL1 and a second conductive line MTL2 configured to provide a power supply signal. Here, the driving transistor TFT may be... Figure 9A The first transistor M1 is included, but this disclosure is not limited thereto.

[0145] The driving transistor TFT of the first circuit part PCL1 may include a bottom electrode layer BML, an active layer ACT, a gate electrode GE, a first transistor electrode TET1, a second transistor electrode TET2, a third transistor electrode TET3, and a fourth transistor electrode TET4.

[0146] The buffer layer BF prevents impurities from diffusing into the circuit elements included in the first circuit portion PCL1 and the second circuit portion PCL2. The buffer layer BF can be formed as a single layer or multiple layers. When the buffer layer BF is formed as multiple layers, the individual layers can be formed from the same material or different materials. Depending on the material or process conditions of the substrate SUB, the buffer layer BF may be omitted.

[0147] A bottom electrode layer (BML) may be formed between the substrate (SUB) and the buffer layer (BF). The bottom electrode layer (BML) may include metal and overlap at least a portion of the active layer (ACT) on the third-direction DR3. Depending on the process conditions, the bottom electrode layer (BML) may be omitted.

[0148] The active layer ACT can be disposed between the buffer layer BF and the gate insulating layer GI. If the pixel circuit layer does not include the buffer layer BF, the active layer ACT can be disposed between the substrate SUB and the gate insulating layer GI. The active layer ACT may include a first region contacting the first transistor electrode TET1, a second region connected to the second transistor electrode TET2, and a channel region disposed between the first and second regions. One of the first and second regions can be a source region, and the other can be a drain region.

[0149] The active layer ACT can be a semiconductor pattern formed from polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. The channel region of the active layer ACT can be an intrinsic semiconductor, which is an undoped semiconductor pattern. Each of the first and second regions of the active layer ACT can be a semiconductor pattern doped with impurities (e.g., a predetermined impurity).

[0150] The gate electrode GE can be disposed between the gate insulating layer GI and the first interlayer insulating layer ILD1 and overlap with at least a portion of the active layer ACT. The gate electrode GE can be insulated from the active layer ACT through the gate insulating layer GI.

[0151] The first transistor electrode TET1 and the second transistor electrode TET2 can be disposed on the first interlayer insulating layer ILD1. The first transistor electrode TET1 and the second transistor electrode TET2 can be electrically connected to the active layer ACT. For example, the first transistor electrode TET1 and the second transistor electrode TET2 can contact the first region and the second region of the active layer ACT, respectively, through contact holes passing through the gate insulating layer GI and the first interlayer insulating layer ILD1.

[0152] In some implementations, the first transistor electrode TET1 and the second transistor electrode TET2 can be formed in parallel (or simultaneously) using the same process.

[0153] The third transistor electrode TET3 and the fourth transistor electrode TET4 can be disposed on the second interlayer insulating layer ILD2. The third transistor electrode TET3 and the fourth transistor electrode TET4 can respectively contact the first transistor electrode TET1 and the second transistor electrode TET2 through contact holes passing through the second interlayer insulating layer ILD2.

[0154] In other words, the third transistor electrode TET3 can be electrically connected to the first region of the active layer ACT via the first transistor electrode TET1. The fourth transistor electrode TET4 can be connected to the second region of the active layer ACT via the second transistor electrode TET2.

[0155] In some implementations, the third transistor electrode TET3 and the fourth transistor electrode TET4 can be formed in parallel using the same process (e.g., simultaneously).

[0156] In addition, the first circuit portion PCL1 may include a first electrode RFE1 and a third electrode CTE1 connected to the driving transistor TFT.

[0157] The first electrode RFE1 can be connected to the third transistor electrode TET3. In some embodiments, the first electrode RFE1 can be integrally connected to the third transistor electrode TET3. In other words, the first electrode RFE1 can be formed on the same layer as the third transistor electrode TET3 and formed in parallel with it (e.g., simultaneously). However, this disclosure is not limited to the foregoing structure. In some embodiments, the first electrode RFE1 can be integrally formed with the first transistor electrode TET1 and / or the third transistor electrode TET3.

[0158] A first insulating layer INS1 may be disposed on the first electrode RFE1, the third transistor electrode TET3, and / or the fourth transistor electrode TET4. The first insulating layer INS1 may include a first opening OP1 through which a portion of the first electrode RFE1 is exposed. The third electrode CTE1 may be disposed on the first insulating layer INS1 and may contact the first electrode RFE1 through the first opening OP1.

[0159] The second circuit section PCL2 may include a first conductive line MTL1 and a second conductive line MTL2.

[0160] The first conductive line MTL1 can be disposed between the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2. The first conductive line MTL1 can be connected to a driving power supply, for example, a second driving power supply. Figure 9A (VSS). In some embodiments, the first conductive line MTL1 can be formed in parallel (e.g., simultaneously) using the same process as the first transistor electrode TET1 and the second transistor electrode TET2 of the first circuit portion PCL1.

[0161] The second conductive line MTL2 can be disposed on the second interlayer insulating layer ILD2. The second conductive line MTL2 can contact the first conductive line MTL1 through a contact hole passing through the second interlayer insulating layer ILD2. In some embodiments, the second conductive line MTL2 can be formed in parallel (e.g., simultaneously) using the same process as the third transistor electrode TET3 and the fourth transistor electrode TET4 of the first circuit portion PCL1.

[0162] In addition, the second circuit portion PCL2 may include a second electrode RFE2 and a fourth electrode CTE2 connected to the second conductive line MTL2.

[0163] The second electrode RFE2 can be integrally formed with the second conductive line MTL2. In other words, the second electrode RFE2 can be formed on the same layer as the second conductive line MTL2, and formed in parallel with it (or simultaneously). The first electrode RFE1 and the second electrode RFE2 can be formed in parallel (e.g., simultaneously) using the same process. In other words, the third transistor electrode TET3, the fourth transistor electrode TET4, the first electrode RFE1, the second conductive line MTL2, and the second electrode RFE2 can be formed simultaneously (e.g., in parallel or substantially simultaneously) on the same layer. However, this disclosure is not limited to the foregoing structure. In some embodiments, the second electrode RFE2 can be integrally formed with the first conductive line MTL1.

[0164] A first insulating layer INS1 may be disposed on the second electrode RFE2 and the second conductive line MTL2. The first insulating layer INS1 may include a second opening OP2 through which a portion of the second electrode RFE2 is exposed. A fourth electrode CTE2 may be disposed on the first insulating layer INS1 and may contact the second electrode RFE2 through the second opening OP2.

[0165] The emitting part DPL may include a first electrode RFE1, a second electrode RFE2, a first insulating layer INS1, a light-emitting element LD, a fixing layer INSA, a third electrode CTE1, a fourth electrode CTE2, and a second insulating layer INS2.

[0166] The first electrode RFE1 of the first circuit portion PCL1 and the second electrode RFE2 of the second circuit portion PCL2 can extend toward the emitter portion DPL. The first electrode RFE1 and the second electrode RFE2 can each extend toward the emitter portion DPL along the side surfaces of the buffer layer BF, the gate insulating layer GI, the first interlayer insulating layer ILD1, and the second interlayer insulating layer ILD2. At least a portion of each of the first electrode RFE1 and the second electrode RFE2 can contact the substrate SUB.

[0167] For example, in the side surfaces of the buffer layer BF, gate insulating layer GI, first interlayer insulating layer ILD1, and second interlayer insulating layer ILD2, their side surfaces adjacent to the emitter portion DPL can be aligned with each other to form a single side surface. The side surface can be tilted relative to the substrate SUB at an angle (e.g., a predetermined angle). The first electrode RFE1 and the second electrode RFE2 can each be disposed along this side surface with a uniformly thick thickness and corresponding to the shape of the side surface. In a plan view, the first electrode RFE1 and the second electrode RFE2 can extend in a second direction DR2.

[0168] The first electrode RFE1 and the second electrode RFE2 can be formed of conductive materials. For example, the first electrode RFE1 and the second electrode RFE2 can include metals or alloys thereof such as Al, Mg, Ag, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti. In some embodiments, the first electrode RFE1 and the second electrode RFE2 can include transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO).

[0169] The materials of the first electrode RFE1 and the second electrode RFE2 are not limited to those described above. For example, as those skilled in the art will understand, the first electrode RFE1 and the second electrode RFE2 can be made of a conductive material (e.g., a metal) having a suitable reflectivity (e.g., a predetermined reflectivity). When the first electrode RFE1 and the second electrode RFE2 are made of a conductive material (e.g., a metal) having a suitable reflectivity (e.g., a predetermined reflectivity), as those skilled in the art will understand, light emitted from opposite ends of the light-emitting element LD, which will be explained below, can be reflected by the first electrode RFE1 and the second electrode RFE2, and then travel in the display direction (e.g., the third direction DR3).

[0170] As described above, the first electrode RFE1 and the second electrode RFE2 can each have a shape corresponding to the shape of the respective side surface formed by the buffer layer BF, the gate insulating layer GI, the first interlayer insulating layer ILD1, and the second interlayer insulating layer ILD2. Light emitted from the first and second ends of the light-emitting element LD can be reflected by the first electrode RFE1 and the second electrode RFE2, and thus travels more efficiently on the third-direction DR3. Therefore, the light output efficiency of the display device 1000 can be improved.

[0171] One of the first electrode RFE1 and the second electrode RFE2 can be an anode electrode, and the other of the first electrode RFE1 and the second electrode RFE2 can be a cathode electrode. For example, the first electrode RFE1 can be an anode electrode, and the second electrode RFE2 can be a cathode electrode. However, this disclosure is not limited to the foregoing, and the opposite is also possible, where the first electrode RFE1 can be a cathode electrode, and the second electrode RFE2 can be an anode electrode.

[0172] The first electrode RFE1 and the second electrode RFE2 can provide a driving signal (or driving current) to the light-emitting element LD in response to the scan signal and the data signal. The light-emitting element LD can emit light with a brightness corresponding to the provided driving signal.

[0173] For example, besides Figure 12 In addition, it also refers to Figure 9A The first electrode RFE1 and the second electrode RFE2 can each be electrically connected to either the driving circuit DC or the second driving power supply VSS via separate connecting lines or connecting components. For example, the first electrode RFE1 can be electrically connected to the driving circuit DC, and the second electrode RFE2 can be electrically connected to the second driving power supply VSS. Therefore, the first electrode RFE1 and the second electrode RFE2 can provide driving signals to the light-emitting element LD.

[0174] The first insulating layer INS1 can be disposed on the first electrode RFE1 and the second electrode RFE2. The light-emitting element LD can be disposed on the first insulating layer INS1.

[0175] As described above, the first insulating layer INS1 can be disposed on the second interlayer insulating layer ILD2 of the first circuit portion PCL1 and the second circuit portion PCL2. The first insulating layer INS1 can be disposed on the entire surface of the substrate SUB and cover the third transistor electrode TET3, the fourth transistor electrode TET4, the second conductive line MTL2, the first electrode RFE1, and the second electrode RFE2, and may include a first opening OP1 exposing a portion of the first electrode RFE1 and a second opening OP2 exposing a portion of the second electrode RFE2. In some embodiments, the first insulating layer INS1 can be formed by an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material.

[0176] In some embodiments, the first insulating layer INS1 may contact the substrate SUB in the opening region OA, where the substrate SUB is exposed in the emitter portion DPL between the first electrode RFE1 and the second electrode RFE2, which are spaced apart from each other.

[0177] The light-emitting element LD can be disposed in the space defined between the first circuit portion PCL1 and the second circuit portion PCL2. In a plan view, the light-emitting element LD can be disposed between the first electrode RFE1 and the second electrode RFE2.

[0178] The light-emitting element (LD) can be prepared in the form of a dispersion in a solution (e.g., a predetermined solution) and supplied between the first circuit portion PCL1 and the second circuit portion PCL2 by an inkjet printing method or the like. For example, the LD can be mixed with a volatile solvent and dropped onto the first insulating layer INS1 in the emitting portion DPL. The dropped LD can be self-aligned by an electric field formed between the first electrode RFE1 and the second electrode RFE2, and is configured to have uniform directionality. For example, the first end of the LD can be positioned adjacent to the first electrode RFE1, and its second end can be positioned adjacent to the second electrode RFE2, such that the longitudinal direction of the LD can be parallel to the first direction DR1. The LD can be arranged along the second direction DR2.

[0179] A fixing layer INSA can be disposed on the light-emitting element LD to stably support the light-emitting element LD and fix it to the first insulating layer INS1. In some embodiments, the fixing layer INSA can be an inorganic insulating layer comprising inorganic materials. The fixing layer INSA can cover at least a portion of the outer peripheral surface (e.g., the outer circumferential surface) of each light-emitting element LD and can be formed such that the first end and the second end of the light-emitting element LD are exposed. Therefore, the fixing layer INSA can prevent the light-emitting element LD from being removed from the substrate SUB. Depending on the process conditions of the display device 1000, the fixing layer INSA can be omitted.

[0180] The third electrode CTE1 and the fourth electrode CTE2 can be disposed on the first insulating layer INS1 and the light-emitting element LD. The third electrode CTE1 of the first circuit portion PCL1 and the fourth electrode CTE2 of the second circuit portion PCL2 can extend toward the emitting portion DPL.

[0181] The third electrode CTE1 and the fourth electrode CTE2 can each contact one of the opposite ends of each of the light-emitting elements LD. For example, the third electrode CTE1 can contact the first end of the light-emitting element LD, and the fourth electrode CTE2 can contact the second end of the light-emitting element LD.

[0182] In the plan view, the third electrode CTE1 may cover at least a portion of the first electrode RFE1 and may extend in the second direction DR2. The third electrode CTE1 may contact the first electrode RFE1 through the first opening OP1 of the first insulating layer INS1. The third electrode CTE1 may be electrically connected to the first end of the light-emitting element LD (e.g., the second semiconductor layer). Figure 213)) and the first electrode RFE1.

[0183] In the plan view, the fourth electrode CTE2 may cover at least a portion of the second electrode RFE2 and extend in the second direction DR2. The fourth electrode CTE2 may contact the second electrode RFE2 through the second opening OP2 of the first insulating layer INS1. The fourth electrode CTE2 may be electrically connected to the second terminal of the light-emitting element LD (e.g., ...). Figure 2 (11) First semiconductor layer and second electrode RFE2.

[0184] The third electrode CTE1 and the fourth electrode CTE2 can each be formed of a transparent conductive material. For example, transparent conductive materials may include ITO, IZO, ITZO, etc. When the third electrode CTE1 and the fourth electrode CTE2 are formed of transparent conductive materials, the light loss of light emitted from the light-emitting element LD can be reduced when light travels along the third direction DR3. However, the materials of the third electrode CTE1 and the fourth electrode CTE2 are not limited to the materials mentioned above.

[0185] In some embodiments, a second insulating layer INS2 may be disposed between the third electrode CTE1 and the fourth electrode CTE2. For example, the second insulating layer INS2 may comprise an inorganic insulating layer formed of an inorganic material. The second insulating layer INS2 may be configured to cover one of the third electrode CTE1 and the fourth electrode CTE2. The other electrode may be disposed on the second insulating layer INS2. For example, the second insulating layer INS2 may be disposed on the first circuit portion PCL1 and the transmitting portion DPL and cover the third electrode CTE1. The fourth electrode CTE2 may be disposed on the second insulating layer INS2 in the transmitting portion DPL. In other words, the third electrode CTE1 and the fourth electrode CTE2 can be electrically isolated from each other through the second insulating layer INS2.

[0186] However, the arrangement of the third electrode CTE1 and the fourth electrode CTE2 is not limited to this. In some embodiments, the third electrode CTE1 and the fourth electrode CTE2 may be disposed in the same layer.

[0187] The third insulating layer INS3 can be disposed over the entire area of ​​the first circuit portion PCL1, the second circuit portion PCL2, and the emitting portion DPL. The third insulating layer INS3 can also be used as an encapsulation layer to prevent the third electrode CTE1, the fourth electrode CTE2, and the light-emitting element LD from being damaged during the manufacturing process of the display device 1000, and to prevent oxygen and / or water from penetrating therein.

[0188] The third insulating layer INS3 may be formed of an inorganic insulating layer comprising inorganic materials. The third insulating layer INS3 may be formed as a single layer, but this disclosure is not limited thereto. The third insulating layer INS3 may include a multilayer structure. In the case where the third insulating layer INS3 includes a multilayer structure, it may further include an organic insulating layer containing organic materials. The third insulating layer INS3 may include a multilayer structure in which organic insulating layers and inorganic insulating layers are alternately disposed.

[0189] Although not shown, the display device 1000 may also include a barrier layer configured to surround the pixel PXL. The barrier layer may be a pixel defining layer configured to define an emission area. The barrier layer may include at least one light-shielding material and / or a reflective material, and thus prevent light leakage between adjacent pixels. Furthermore, the barrier layer can prevent the solution including the light-emitting element LD from leaking into adjacent pixels during the process of aligning the light-emitting element LD. Depending on the process conditions of the display device 1000, the barrier layer may be omitted.

[0190] As described above, the display device 1000 may include a first circuit section PCL1, a second circuit section PCL2, and an emission section DPL.

[0191] The buffer layer BF, gate insulating layer GI, first interlayer insulating layer ILD1, and second interlayer insulating layer ILD2 of the first circuit portion PCL1 and the second circuit portion PCL2 can form a space for arranging the light-emitting element LD in the emitting portion DPL. Furthermore, the first circuit portion PCL1 and the second circuit portion PCL2 can be used as partition walls by first electrodes RFE1 and second electrodes RFE2 disposed along the side surfaces of the layers to reflect light emitted from the light-emitting element LD on the third-direction DR3. Therefore, a separate partition wall for reflecting light emitted from the light-emitting element LD can be omitted, thereby reducing the manufacturing cost of the display device 1000.

[0192] Furthermore, since the third transistor electrode TET3 of the first circuit portion PCL1 and the first electrode RFE1 are integrally formed, and the second conductive line MTL2 and the second electrode RFE2 of the second circuit portion PCL2 are integrally formed, the separate processes for forming the first electrode RFE1 and the second electrode RFE2 can be omitted. Therefore, the manufacturing process of the display device 1000 can be simplified, and the manufacturing cost of the display device 1000 can be reduced.

[0193] Furthermore, since the first circuit portion PCL1, the second circuit portion PCL2, and the emitter portion DPL can be horizontally arranged (e.g., horizontally arranged relative to the substrate SUB), a thin display device can be provided.

[0194] In the following description, embodiments of the display device will be described. In the embodiments described below, the same reference numerals are used to denote the same components as those in the embodiments described above, and their descriptions will be omitted or simplified, with the focus on their differences.

[0195] Figures 13 to 15 It is a cross-sectional view of the corresponding pixels included in the display device according to various embodiments, and is corresponding to Figure 11 A sectional view of line A-A'.

[0196] Figure 13 Exemplary implementation methods and Figure 12 The difference in the exemplary implementation is that the pixel PXLa includes a fourth electrode CTE2a disposed in the same layer as the third electrode CTE1 and formed in parallel with (e.g., simultaneously with) the third electrode CTE1.

[0197] Reference Figure 13 The fourth electrode CTE2a of the second circuit portion PCL2 can contact the second electrode RFE2 through the second opening OP2 of the first insulating layer INS1. The fourth electrode CTE2a can be disposed on the same layer as the third electrode CTE1 and formed in parallel with the third electrode CTE1 by the same process (e.g., formed simultaneously). The fourth electrode CTE2a can extend along the surface of the first insulating layer INS1 to the emitting portion DPL and contact the second end of the light-emitting element LD.

[0198] As described above, when the third electrode CTE1 and the fourth electrode CTE2a are formed in parallel (e.g., simultaneously), the second insulating layer used to electrically isolate the third electrode CTE1 from the fourth electrode CTE2a can be omitted. Figure 12 The INS2 can simplify the manufacturing process of the display device 1000 and reduce the manufacturing cost of the display device 1000.

[0199] and Figure 12 The configuration of the fixing layer INSA differs; in this embodiment, the fixing layer INSAa can be an organic insulating layer comprising organic materials. The thickness of the fixing layer INSAa can be greater than [missing information]. Figure 12 The thickness of the fixing layer INSA. Therefore, in the process of forming the third electrode CTE1 and the fourth electrode CTE2a in parallel (e.g., simultaneously), the fixing layer INSAa can prevent short circuits between the third electrode CTE1 and the fourth electrode CTE2a, and can stably fix the light-emitting element LD in the correct position.

[0200] Figure 14 Implementation methods and Figure 12The difference in the implementation is that the pixel PXLb includes a first electrode RFE1b integrally formed with the first transistor electrode TET1b and a second electrode RFE2b integrally formed with the first conductive line MTL1b.

[0201] Reference Figure 14 The first electrode RFE1b of the first circuit portion PCL1 can be integrally formed with the first transistor electrode TET1b. The second electrode RFE2b of the second circuit portion PCL2 can be integrally formed with the first conductive line MTL1b. As described above, the first transistor electrode TET1b and the first conductive line MTL1b can be disposed in the same layer and formed simultaneously (or substantially simultaneously) by the same process, and the first electrode RFE1b and the second electrode RFE2b integrally formed with them can also be formed simultaneously by the same process.

[0202] In some embodiments, the third transistor electrode TET3, the fourth transistor electrode TET4, the second conductive line MTL2, and the second interlayer insulating layer ILD2 can be omitted. In this case, the third electrode CTE1 can contact the first transistor electrode TET1b (or the first electrode RFE1b) through the first opening OP1 of the first insulating layer INS1, and the fourth electrode CTE2c can contact the first conductive line MTL1b (or the second electrode RFE2b) through the second opening OP2 of the first insulating layer INS1.

[0203] Figure 15 Exemplary implementation methods and Figure 14 The difference in the exemplary implementation is that the pixel PXLc includes a fourth electrode CTE2c disposed on the same layer as the third electrode CTE1 and formed in parallel with (e.g., simultaneously with) the third electrode CTE1.

[0204] Reference Figure 15 The first electrode RFE1c of the first circuit portion PCL1 can be integrally formed with the first transistor electrode TET1c. The second electrode RFE2c of the second circuit portion PCL2 can be integrally formed with the first conductive line MTL1c.

[0205] The fourth electrode CTE2c of the second circuit section PCL2 can be disposed on the same layer as the third electrode CTE1 and formed in parallel with the third electrode CTE1 by the same process (e.g., formed simultaneously). The fourth electrode CTE2c can extend along the surface of the first insulating layer INS1 to the emitting section DPL and contact the second end of the light-emitting element LD.

[0206] As referenced above Figure 13As described, in the case where the third electrode CTE1 and the fourth electrode CTE2c are formed in parallel (e.g., simultaneously), the second insulating layer used to electrically isolate the third electrode CTE1 from the fourth electrode CTE2c can be omitted. Figure 12 The INS2 can simplify the manufacturing process of the display device 1000 and reduce the manufacturing cost of the display device 1000.

[0207] and Figure 12 The configuration of the fixing layer INSA differs from that in this embodiment; in this case, the fixing layer INSA can be an organic insulating layer comprising organic materials. The thickness of the fixing layer INSA can be greater than [missing information]. Figure 12 The thickness of the INSA fixing layer.

[0208] Figure 16 This is a cross-sectional view of pixels included in a display device according to one or more exemplary embodiments of this disclosure, and is corresponding to... Figure 11 A sectional view of line A-A'. Figure 16 Exemplary implementation methods and Figure 12 The exemplary implementation differs in that the pixel PXLd also includes a wavelength conversion layer (WCL) and a color filter layer (CFL), and the other components of the pixel PXLd are similar to those of the other components. Figure 12 The components of the implementation methods are substantially equivalent or similar.

[0209] refer to Figure 16 The pixel PXLd may also include a wavelength conversion layer (WCL) and a color filter layer (CFL).

[0210] The wavelength conversion layer (WCL) can be disposed on the third insulating layer (INS3). The wavelength conversion layer (WCL) may include a base layer (BR) and wavelength conversion particles (QD) and scattering particles (SCT) dispersed in the base layer (BR).

[0211] The base layer BR is not particularly limited, as long as it is formed of a material with high transmittance and excellent dispersion characteristics for wavelength conversion particles (QD) and scattering particles (SCT). For example, the base layer BR can include organic materials such as epoxy resin, acrylic resin, cardo resin, or imide resin.

[0212] Wavelength conversion particles (QDs) can convert the peak wavelength of incident light into different specific peak wavelengths. In other words, QDs can convert the color of incident light into different colors.

[0213] For example, when the light-emitting element LD emits blue light, the wavelength conversion particle QD can convert the blue light provided by the light-emitting element LD into light of different colors, and emit light of different colors from the pixel PXLd. For example, the wavelength conversion particle QD can convert the blue light provided by the light-emitting element LD into red or green light, and emit red or green light from the pixel PXLd.

[0214] Examples of wavelength-converting particles (QDs) may include quantum dots, quantum rods, or fluorescent materials. A quantum dot can be a particulate material that emits light of a specific wavelength as electrons transition from the conduction band to the valence band. In the following description, wavelength-converting particles (QDs) will be referred to as quantum dots, but this disclosure is not limited thereto.

[0215] Quantum dots can be semiconductor nanocrystal materials. Depending on their composition and size, quantum dots can have specific band gaps and thus absorb incident light and then emit light with an intrinsic wavelength. Examples of semiconductor nanocrystals containing quantum dots can include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI compound nanocrystals, and combinations thereof.

[0216] Examples of group IV nanocrystals may include silicon (Si), germanium (Ge), and binary compounds such as silicon carbide (SiC) and silicon-germanium (SiGe), but this disclosure is not limited thereto.

[0217] Examples of II-VI group compound nanocrystals can include binary, ternary, and quaternary compounds. Binary compounds include CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and mixtures thereof. Ternary compounds include CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnSeS, CdSeTe, CdSTe, and CdZnSeS. The following compounds are included: nS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof, and quaternary compounds such as HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof. However, this disclosure is not limited thereto.

[0218] Examples of III-V group compound nanocrystals may include binary, ternary, and quaternary compounds. Binary compounds include GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof. Ternary compounds include GaP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InNP, InNAs, InNSb, InPAs, InPSb, and mixtures thereof. Quaternary compounds include GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and mixtures thereof. However, this disclosure is not limited thereto.

[0219] Examples of group IV-VI compound nanocrystals may include binary, ternary, and quaternary compounds, such as SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof; ternary compounds such as SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and mixtures thereof; and quaternary compounds such as SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof. However, this disclosure is not limited thereto.

[0220] Quantum dots can have any shape commonly used in the art and are not particularly limited thereto. For example, spherical, pyramidal, multi-armed, or cubic nanoparticles, nanotubes, nanowires, nanofibers, and nanoplate particles can be used. Binary, ternary, or quaternary compounds can exist in the particles at substantially uniform concentrations or can exist in the same particles at different concentration distributions.

[0221] Quantum dots can have a core-shell structure, comprising a core having the aforementioned nanocrystals and a shell surrounding the core. The interface between the core and shell can have a concentration gradient, wherein the concentration of the element present in the shell decreases from the surface of the particle to the center of the particle. The shell of the quantum dot can serve as a protective layer to prevent chemical changes in the core, thereby preserving semiconductor properties, and / or can serve as a charging layer for assigning electrophoretic properties to the quantum dot. The shell can have a monolayer or multilayer structure. Examples of shells for quantum dots may include metal or nonmetal oxides, semiconductor compounds, or combinations thereof.

[0222] For example, although examples of metal or nonmetal oxides may include binary or ternary compounds, such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4 and NiO, and ternary compounds such as MgAl2O4, CoFe2O4, NiFe2O4 and CoMn2O4, this disclosure is not limited thereto.

[0223] Furthermore, although examples of semiconductor compounds may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InSb, AlAs, AlP, and AlSb, this disclosure is not limited thereto.

[0224] The light emitted from the quantum dots can have a full width at half maximum (FWHM) of an emission wavelength spectrum of approximately 45 nm or less. This improves the purity and reproducibility of colors displayed by the display device 1000. Furthermore, the light emitted from the quantum dots can be emitted in all directions, regardless of the direction of the incident light. Therefore, the side visibility of the display device 1000 can be improved.

[0225] The scattering particles (SCTs) can have a refractive index different from that of the wavelength conversion layer (WCL) and form an optical interface together with the base layer (BR). The material of the scattering particles (SCTs) is not particularly limited, as long as they can scatter at least some of the transmitted light. For example, the scattering particles (SCTs) can be particles formed from materials such as titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), tin oxide (SnO2), or silicon dioxide.

[0226] Scattering particles (SCTs) can scatter light in random directions without substantially altering the wavelength of light passing through the base layer (BR), regardless of the direction of the incident light. Therefore, the side visibility of the display device 1000 can be improved.

[0227] A first capping layer CPL1 can be disposed on the wavelength conversion layer WCL. The first capping layer CPL1 can be an inorganic insulating layer formed of inorganic material. The first capping layer CPL1 can serve as an encapsulation layer covering the entire surface of the wavelength conversion layer WCL, and thus prevents oxygen and / or water from penetrating into the wavelength conversion layer WCL from the outside. Therefore, the wavelength conversion layer WCL can be encapsulated by a third insulating layer INS3 and the first capping layer CPL1.

[0228] A color filter layer CFL can be disposed on the first capping layer CPL1. The color filter layer CFL can be an absorptive filter configured to allow light of a specific color to pass through it and absorb light of other colors and block the propagation of light of other colors.

[0229] A second capping layer CPL2 can be disposed on the color filter layer CFL. The second capping layer CPL2 can be an inorganic insulating layer formed of inorganic material. The second capping layer CPL2 can serve as an encapsulation layer covering the entire surface of the color filter layer CFL, and thus prevents oxygen and / or water from penetrating into the color filter layer CFL from the outside. Therefore, the color filter layer CFL can be encapsulated by a first capping layer CPL1 and a second capping layer CPL2.

[0230] In some embodiments, at least one of the wavelength conversion layer WCL, the first capping layer CPL1, and the second capping layer CPL2 may be omitted.

[0231] exist Figure 16 In some embodiments, a structure is shown in which the wavelength conversion layer WCL and the color filter layer CFL are formed directly on the substrate SUB, but this disclosure is not limited thereto. In some embodiments, the wavelength conversion layer WCL and the color filter layer CFL may be formed on a separate substrate different from the substrate SUB on which the light-emitting element LD is disposed. In this case, the substrate on which the wavelength conversion layer WCL and the color filter layer CFL are formed may face the substrate SUB on which the light-emitting element LD is disposed.

[0232] In a display device according to an exemplary embodiment of the present disclosure, the circuit layer and the emitting portion are disposed horizontally on the substrate, which simplifies the manufacturing process and enables the manufacture of a thin display device.

[0233] In a display device according to an exemplary embodiment of the present disclosure, during the process of forming a circuit layer and an emitting portion on a substrate, some components of the circuit layer and the emitting portion can be formed in parallel (or simultaneously) during the same process, thereby reducing the cost required to manufacture the display device.

[0234] The effects of this disclosure are not limited to the foregoing, and various other effects are anticipated herein.

[0235] Exemplary embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and is not intended to be limiting. In some instances, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments at the time of filing this application, unless specifically stated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims and their equivalents.

Claims

1. A display device, including: Substrate; A first circuit portion and a second circuit portion are on the substrate and spaced apart from each other in a first direction; as well as The emitting portion is located between the first circuit portion and the second circuit portion, and is situated in a direction parallel to the substrate. The first circuit portion includes a first electrode extending to the emitting portion and a driving transistor located on the substrate. The second circuit portion includes a second electrode extending to the transmitting portion, and The emitting portion includes a light-emitting element located between the first electrode and the second electrode; The display device further includes a first insulating layer that contacts the light-emitting element and the substrate located below the driving transistor.

2. The display device according to claim 1, wherein, At least a portion of the first insulating layer is on the first electrode, and at least another portion of the first insulating layer is on the second electrode. The first insulating layer is located between the substrate and the light-emitting element.

3. The display device according to claim 2, in, The first circuit portion includes a third electrode disposed on the first electrode, at least a portion of the third electrode being in contact with the first end of the light-emitting element, and The second circuit portion includes a fourth electrode disposed on the second electrode, at least a portion of which is in contact with the second end of the light-emitting element.

4. The display device according to claim 3, in, The first insulating layer includes a first opening and a second opening, a portion of the first electrode being exposed through the first opening, and a portion of the second electrode being exposed through the second opening. The third electrode contacts the first electrode through the first opening, and The fourth electrode is in contact with the second electrode through the second opening.

5. The display device according to claim 3, further comprising a second insulating layer, wherein, At least a portion of the second insulating layer is on the third electrode, and at least another portion of the second insulating layer is on the light-emitting element. The fourth electrode is located on the second insulating layer.

6. The display device according to claim 3, wherein, The third electrode and the fourth electrode are formed in parallel on the same layer.

7. The display device according to claim 3, wherein, Each of the third electrode and the fourth electrode comprises a transparent conductive oxide.

8. The display device of claim 3, further comprising a fixing layer surrounding at least a portion of the outer peripheral surface of the light-emitting element and exposing the first end and the second end of the light-emitting element. in, The fixing layer is located between the light-emitting element and the third electrode.

9. The display device according to claim 2, in, The driving transistor includes: An active layer is located on the substrate. Gate electrode, on the active layer; and The first transistor electrode and the second transistor electrode are located above the gate electrode and in contact with the active layer; In this embodiment, a portion of the first electrode is formed on the first transistor electrode or the first electrode is integrally formed with the first transistor electrode, and the driving transistor is electrically connected to the light-emitting element.

10. The display device according to claim 9, wherein the driving transistor further comprises a third transistor electrode, the third transistor electrode being on the first transistor electrode and electrically connected to the first transistor electrode through a contact hole. in, The first electrode and the third transistor electrode are integrally formed.

11. The display device according to claim 9, wherein the driving transistor further comprises a third transistor electrode, the third transistor electrode being on the first transistor electrode and electrically connected to the first transistor electrode through a contact hole.

12. The display device according to claim 9, wherein, The driving transistor also includes a bottom electrode layer between the substrate and the active layer.

13. The display device according to claim 1, wherein, The first electrode and the second electrode each comprise a metal having a predetermined reflectivity.

14. The display device according to claim 1, further comprising a wavelength conversion layer on the light-emitting element, in, The wavelength conversion layer includes wavelength conversion particles and scattering particles, and The wavelength conversion particles include quantum dots.

15. A display device, including: Substrate; A first electrode and a second electrode are on the substrate, the first electrode and the second electrode are in the same layer and spaced apart from each other; A first insulating layer is provided on the first electrode and the second electrode; A light-emitting element is located on the first insulating layer and between the first electrode and the second electrode; as well as A driving transistor is located between the substrate and a portion of the first electrode and is electrically connected to the light-emitting element. The first insulating layer is located between the substrate and the light-emitting element, and is in contact with the substrate exposed between the first electrode and the second electrode.

16. The display device according to claim 15, further comprising: The third electrode is electrically connected to the first electrode and the first end of the light-emitting element; as well as The fourth electrode is electrically connected to the second electrode and the second end of the light-emitting element.

17. The display device according to claim 16, in, The first insulating layer includes a first opening and a second opening, wherein a portion of the first electrode is exposed through the first opening, and a portion of the second electrode is exposed through the second opening. The third electrode contacts the first electrode through the first opening, and The fourth electrode is in contact with the second electrode through the second opening.

18. The display device according to claim 16, wherein, The third electrode and the fourth electrode are formed in parallel on the same layer.

19. The display device of claim 16, further comprising a second insulating layer on the third electrode. in, The fourth electrode is on the second insulating layer.

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