Silicon carbide packaging structure and packaging method

Abstract

The present invention relates to the field of semiconductor technology, and more specifically to a silicon carbide packaging structure and packaging method. The structure is manufactured by the method and includes a substrate and a semiconductor chip. The semiconductor chip is located in the middle of the substrate. A SiC packaging shell is provided in the middle with a groove-shaped portion and is inverted on the upper surface of the semiconductor chip. The SiC packaging shell is provided with an electrode connection area that connects the inner and outer sides of the SiC packaging shell. The electrode connection area is provided with an electrode area protrusion of a set height on the inner side of the SiC packaging shell. The electrode area protrusion is welded to the electrode area on the upper surface of the semiconductor chip. The SiC packaging shell is welded to the connection between the SiC packaging shell and the substrate. The electrode connection area is welded to the outer surface of the SiC packaging shell. The present invention can further reduce the volume of the packaging shell, reduce thermal stress, and improve device reliability. At the same time, it improves thermal conductivity to meet the heat dissipation requirements of silicon carbide devices. In addition, the structure also has a certain degree of radiation resistance, expanding its application in the space field.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon carbide packaging structure and a packaging method. Background Art

[0002] Semiconductors are materials with electrical conductivity intermediate between that of conductors and insulators. Semiconductor materials are a class of electronic materials exhibiting semiconductor properties and can be used to fabricate semiconductor devices and integrated circuits. Currently, semiconductor materials have reached the third generation, primarily including SiC, GaN, and diamond. Compared to first- and second-generation semiconductor materials, third-generation semiconductor materials offer advantages such as high thermal conductivity, high breakdown field strength, high saturated electron drift velocity, and high bonding energy. They can meet the new requirements of modern electronics for high temperature, high power, high voltage, high frequency, and radiation resistance. They are the most promising materials in the semiconductor field, with significant application prospects in defense, aviation, and aerospace. They can reduce energy loss by over 50% and device size by up to 75% in a wide range of industries, including broadband communications, solar energy, automotive manufacturing, semiconductor lighting, and smart grids, marking a milestone in the development of human science and technology.

[0003] The current radiation-resistant packaging is still based on the silicon-based device design of the first generation of semiconductors and has not yet been specifically optimized for SiC devices. On the other hand, the current radiation-resistant packaging only considers the improvement of radiation resistance without considering the heat dissipation capacity of the device. The thermal expansion coefficient of SiC is 6.58*10 -6 , the thermal expansion coefficient of silicon is 2.62*10 -6 When the chip area is equal, the edge stress of a SiC chip is about 2.5 times that of a silicon-based chip. In addition, because SiC has a higher power density than silicon, the actual edge stress of a SiC chip is even greater. Therefore, it is extremely necessary to consider the heat dissipation of the package and the matching of the thermal expansion coefficient.

[0004] Patent publication number CN112786569A discloses a radiation-resistant structure of ceramic and plastic packaging. Organic polymer materials are selected and the radiation-resistant performance of the organic material coating is enhanced by doping with inorganic non-metallic materials. The inner and outer surfaces of the circuit are covered by coating to strengthen the overall radiation-resistant performance of the circuit, such as resistance to electron radiation and gamma ray radiation.

[0005] Patent publication number CN113078120A discloses a novel radiation-resistant ceramic package structure. The ceramic shell is formed by mechanically blending an inorganic non-metallic material into the base material of the ceramic shell and sintering it. The semiconductor chip is located within the radiation-resistant ceramic shell, and the cover plate is assembled with the radiation-resistant ceramic shell through a capping process. This method, which enhances the radiation resistance of the ceramic shell base material while maintaining its physical properties, can be implemented in most ceramic packaged circuits. The radiation-resistant ceramic shell is produced through mechanical blending, and this doping method is applicable to all ceramic packaging materials, including traditional ceramic materials such as Al2O3, AlN, and LTCC.

[0006] The above patent still has the following problems:

[0007] 1. The existing ceramic packaging anti-radiation technology contains the device inside, and it is impossible to further reduce the size of the packaging shell.

[0008] 2. The thermal expansion coefficient of existing ceramic packages is still different from that of chips. During long-term use, the package shell will still generate large thermal stress, affecting the reliability of the device.

[0009] 3. The thermal conductivity of existing ceramic packages is still relatively low and is insufficient to meet the heat dissipation requirements of silicon carbide devices. Summary of the Invention

[0010] One of the objectives of the present invention is to provide a silicon carbide packaging structure that can solve the above-mentioned technical problems.

[0011] To achieve the above objectives, a silicon carbide packaging structure is provided, comprising a substrate and a semiconductor chip, the semiconductor chip being located in the middle of the substrate, and a SiC packaging housing having a groove-shaped center portion and being inverted on the upper surface of the semiconductor chip. The SiC packaging housing is provided with an electrode connection area communicating the inner and outer side surfaces of the SiC packaging housing. The electrode connection area is provided with an electrode area protrusion of a predetermined height on the inner side surface of the SiC packaging housing, the electrode area protrusion being welded to the electrode area on the upper surface of the semiconductor chip, the SiC packaging housing being welded at the connection between the SiC packaging housing and the substrate, and a lead electrode being welded to the electrode connection area on the outer side surface of the SiC packaging housing.

[0012] Principles and advantages:

[0013] 1. The setting of the SiC package shell. Since the middle part is grooved and inverted on the upper surface of the semiconductor chip, the size of the SiC package shell can be close to that of the semiconductor chip, so that the overall size matches the semiconductor chip, reducing redundant volume and further reducing the volume of the package shell. Not only does it not increase the size of the device, but it also has little impact on the overall quality.

[0014] 2. The electrode connection area and electrode area protrusions are integrally formed using an etching process. This ensures excellent electrical conductivity and, due to the further reduction in package size, allows the SiC package to be closer to the semiconductor chip. Furthermore, the SiC package is made of silicon carbide, the same material as the SiC chip, with the same thermal expansion coefficient and a thermal conductivity exceeding that of pure copper. This inherently good thermal conductivity reduces the overall thermal resistance of the device, minimizing thermal stress on the package during long-term use, thereby improving device thermal reliability and extending its lifespan.

[0015] 3. The structural design of the present invention can match the ceramic packaging, plastic packaging process and packaging shape of current devices; it is also compatible with other ceramic / plastic radiation-resistant processes; and it is also compatible with press-fit interconnection processes.

[0016] Furthermore, an anti-radiation protective metal plate is welded on the lead-out electrode.

[0017] The installation of anti-radiation protective metal plates can prevent radiation effects.

[0018] Furthermore, the anti-radiation protective metal plate is a high-order metal plate with a thickness of 0.5-5 mm.

[0019] The high-order metal plate and the setting of a thickness of 0.5-5 mm can make the radiation protection metal plate have a better radiation protection effect.

[0020] Furthermore, the electrode connection area is an AlSiC / CuSiC composite structure, and the substrate material is AlSiC / CuSiC.

[0021] AlSiC / CuSiC as electrode connection material has good weldability and is very suitable for current mainstream welding processes.

[0022] Furthermore, the substrate has a thickness of 0.5-10 mm. When the substrate thickness is less than 0.5 mm, its radiation resistance is relatively weak, while when the thickness is greater than 10 mm, the substrate has a significant impact on the device volume. In practical applications, the substrate thickness should be reduced while still meeting the radiation resistance requirement to minimize the impact on the final volume and mass.

[0023] Furthermore, the height of the electrode area protrusion is set to 10μm-1mm, the bottom shell thickness of the SiC package shell is 0.5-7mm, and the sidewall thickness of the SiC package shell is 0.5-5mm. When the electrode area protrusion height is 10μm-1mm, it is connected to the chip electrode through welding. If solder paste overflows, the excess will adhere to the area around the protrusion, reducing the risk of chip short circuits. At the same time, the chip and shell are closely connected, ensuring the shell's protection, heat dissipation, and electrical conductivity.

[0024] Furthermore, the vertical cross-section of the electrode connection area is in the shape of a long strip or an L shape, so as to be adapted to different use environments.

[0025] One of the objectives of the present invention is to provide a packaging method for a silicon carbide packaging structure, wherein the structure is used for manufacturing the method, and specifically comprises the following steps:

[0026] A metal material is infiltrated into the SiC crystal corresponding to the electrode area of ​​the semiconductor chip using an infiltration process to form an electrode connection area connecting the two sides of the SiC package shell;

[0027] Etching is performed on one side of the SiC crystal where the electrode connection area is located to form a SiC package shell with a groove in the middle; and the electrode connection area in the groove is retained at a predetermined height to form an electrode area protrusion;

[0028] The SiC package shell is placed upside down on the semiconductor chip arranged on the substrate, and the electrode area protrusion is welded to the electrode area on the upper surface of the semiconductor chip, and the connection between the SiC package shell and the substrate is welded;

[0029] The lead-out electrodes are arranged on the electrode connection area on the outer side of the SiC package shell by using an aluminum ribbon / copper ribbon bonding process.

[0030] Principles and advantages:

[0031] 1. Compared to existing ceramic firing methods, while both can enclose semiconductor chips, SiC packaging is etched from SiC crystals. The size of the SiC packaging can be made closer to the semiconductor chip, further reducing the package volume. This not only does not increase the device's external size, but also has a minimal impact on overall quality. Therefore, SiC packaging is superior to ceramic packaging devices.

[0032] 2. The electrode connection area and the electrode area protrusion are integrally formed by an etching process. On the one hand, this can ensure good electrical conductivity. On the other hand, based on the further reduction of the package shell volume, the inner side of the SiC package shell can be brought closer to the semiconductor chip. In addition, the SiC package shell is made of silicon carbide material, which makes the thermal expansion coefficient (CTE) of the SiC package shell closer to that of the semiconductor chip and substrate. Therefore, the thermal conductivity of the device can be greatly improved. Moreover, the package shell will not generate large thermal stress, and the thermal reliability is enhanced.

[0033] 3. The structural design of the present invention can match the ceramic packaging, plastic packaging process and packaging shape of current devices; it is also compatible with other ceramic / plastic radiation-resistant processes; and it is also compatible with press-fit interconnection processes.

[0034] Furthermore, the method further comprises the following steps:

[0035] An anti-radiation protective metal plate is welded on the lead-out electrode.

[0036] The installation of anti-radiation protective metal plates can prevent radiation effects.

[0037] Furthermore, the electrode connection area is an AlSiC / CuSiC composite structure, the volume fraction of the AlSiC composite structure ranges from 5-25%, and the volume fraction of the CuSiC composite structure ranges from 5-40%, which is the volume fraction of the metal in the entire SiC crystal.

[0038] The electrical conductivity of the AlSiC / CuSiC composite structure in the electrode connection area can be guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a schematic structural diagram of a SiC packaging shell of a silicon carbide packaging structure in Example 1 of the present invention;

[0040] Figure 2 This is a schematic structural diagram of a silicon carbide packaging structure in Example 1;

[0041] Figure 3 This is a schematic structural diagram of a SiC packaging shell of a silicon carbide packaging structure in the second embodiment of the present invention;

[0042] Figure 4 This is a structural schematic diagram of a silicon carbide packaging structure in Example 2. DETAILED DESCRIPTION

[0043] The following is further described in detail through specific implementation methods:

[0044] The reference numerals in the drawings of the specification include: SiC package shell 1, electrode connection area 2, solder layer 3, semiconductor chip 4, substrate 5, lead electrode 6, anti-radiation protection metal plate 7.

[0045] Example 1

[0046] A silicon carbide packaging structure, basically as Figure 1 、 Figure 2 As shown, it includes a substrate 5, a semiconductor chip 4, and a SiC package 1. The semiconductor chip 4 is located in the middle of the substrate 5. In this embodiment, the substrate 5 is made of AlSiC / CuSiC and has a thickness of 0.5-10mm. If it is a module device, a layer of copper or silver with a thickness of 1μm-10mm needs to be grown on the lower surface of the substrate 5 and directly connected to the DBC board (copper-clad ceramic substrate) by welding.

[0047] The SiC package 1 is etched from a block of SiC crystal with a thickness between 1mm and 10mm, and a size no less than 1.1 times the size of the chip to be packaged. After etching, the SiC package 1 has a central groove, which is then flip-flopped onto a substrate 5 and covers the semiconductor chip 4.

[0048] Before the SiC crystal is etched into a finished SiC package shell 1, Figure 1 As shown, the SiC crystal is provided with an electrode connection region 2 connecting the upper and lower sides of the SiC crystal. In this embodiment, Al / Cu is infiltrated into the electrode region corresponding to the semiconductor chip 4 using a vacuum pressure infiltration method to form an AlSiC / CuSiC composite structure (i.e., electrode connection region 2). The vertical cross-section of the AlSiC / CuSiC composite structure is a long strip. The volume fraction of the AlSiC composite structure ranges from 5-25%, and the volume fraction of the CuSiC composite structure ranges from 5-40%. This volume fraction is the volume fraction of the metal in the entire SiC crystal.

[0049] After the SiC crystal is etched into the finished SiC package 1, the electrode connection area 2 leaves an electrode area protrusion of a predetermined height on the inner side of the SiC package 1. The predetermined height of the electrode area protrusion is 10 μm to 1 mm. The bottom of the SiC package 1 is 0.5 to 7 mm thick, and the sidewalls are 0.5 to 5 mm thick.

[0050] A solder layer 3 (printed solder paste) is provided at the connection between the SiC package shell 1 and the substrate 5 for patch welding. A solder layer 3 (printed solder paste) is provided between the electrode area protrusion and the electrode area on the upper surface of the semiconductor chip 4 to achieve welding. The size of the electrode connection area 2 corresponding to the gate is 50-95% of the gate area of ​​the semiconductor chip 4, and the size of the electrode connection area 2 corresponding to the source / drain is 5-99% of the source / drain area of ​​the semiconductor chip 4. The electrode connection area 2 is welded with a lead-out electrode 6 on the outer surface of the SiC package shell 1 through the solder layer 3. In this embodiment, the lead-out electrode 6 is provided by an aluminum strip / copper strip bonding process. A solder layer 3 (printed solder paste) is provided on the lead-out electrode 6 and welded with an anti-radiation protective metal plate 7. The anti-radiation protective metal plate 7 is a high-order metal plate, such as Pb, Ta, etc., with a thickness of 0.5-5 mm.

[0051] A packaging method for a silicon carbide packaging structure, wherein the structure is used for manufacturing the method, specifically comprising the following steps:

[0052] S1. Obtain a SiC crystal and substrate 5 of a predetermined size. The SiC crystal should be between 1mm and 10mm thick and at least 1.1 times the size of the chip to be packaged. Substrate 5 should be made of AlSiC / CuSiC and 0.5-10mm thick. For module devices, a layer of copper or silver (1µm-10mm thick) should be grown on the lower surface of substrate 5 and directly soldered to the DBC board (copper-clad ceramic substrate 5).

[0053] S2. Infiltrating the SiC crystal at the location corresponding to the electrode area of ​​the semiconductor chip 4 with a vacuum pressure infiltration method to form an electrode connection area 2 (AlSiC / CuSiC composite structure) that connects the two sides of the SiC package shell 1; wherein the vertical cross-section of the AlSiC / CuSiC composite structure is a long strip, the volume fraction of the AlSiC composite structure is in the range of 5-25%, and the volume fraction of the CuSiC composite structure is in the range of 5-40%, where the volume fraction is the volume fraction of the metal in the entire SiC crystal;

[0054] S3. Etching (laser etching) is performed on the side of the SiC crystal where the electrode connection area 2 is located to form a SiC package housing 1 with a central groove. The electrode connection area 2 is retained within the groove to a predetermined height to form an electrode area protrusion. The predetermined height of the electrode area protrusion is 10 μm to 1 mm. The bottom of the SiC package housing 1 has a shell thickness of 0.5 to 7 mm, and the sidewalls of the SiC package housing 1 have a shell thickness of 0.5 to 5 mm.

[0055] S4. Place the SiC package shell 1 upside down on the semiconductor chip 4 arranged on the substrate 5, and set a solder layer 3 (printed solder paste) on the electrode area protrusion and the electrode area on the upper surface of the semiconductor chip 4 to achieve welding. Also, set a solder layer 3 (printed solder paste) on the connection between the SiC package shell 1 and the substrate 5 to achieve welding.

[0056] S5. Arrange the lead-out electrode 6 on the electrode connection area 2 on the outer surface of the SiC package shell 1 by using an aluminum ribbon / copper ribbon bonding process.

[0057] S6. Welding an anti-radiation protection metal plate 7 on the lead-out electrode 6. The anti-radiation protection metal plate 7 is a high-order metal plate, such as Pb, Ta, etc., with a thickness of 0.5-5 mm. Specific implementation method:

[0059] Compared to existing ceramic packaging, the SiC package in this solution can also contain the semiconductor chip. However, because the SiC package is etched from SiC crystal, its size can be closer to the semiconductor chip, further reducing the package volume. This not only does not increase the device's external size, but also has a minimal impact on overall quality. Therefore, the SiC package is more effective than ceramic packaging devices.

[0060] By infiltrating the SiC crystal with Al / Cu metal materials using vacuum pressure infiltration, an electrode connection area 2 (an AlSiC / CuSiC composite structure) is formed, connecting the two sides of the SiC package housing 1. Etching is then used to integrally form the electrode connection area 2 and the electrode area protrusion. This ensures good electrical conductivity while also further reducing the package volume, allowing the inner side of the SiC package housing 1 to be closer to the semiconductor chip 4, facilitating heat dissipation. Furthermore, the SiC package housing is made of silicon carbide, which brings the coefficient of thermal expansion (CTE) of the SiC package housing 1 closer to that of the semiconductor chip 4 and substrate 5. The thermal conductivity of the housing is increased by 5-7 times, enhancing thermal reliability.

[0061] Example 2

[0062] The difference between the second embodiment and the first embodiment is that, in the silicon carbide packaging structure, the vertical cross-section of the AlSiC / CuSiC composite structure is L-shaped, such as Figure 3 、 Figure 4 As shown, the end of the electrode connection area 2 on the outer surface of the SiC package 1 is arranged on the side wall of the SiC package 1. At the same time, the lead electrode 6 welded to the end of the electrode connection area 2 is also arranged using an aluminum ribbon / copper ribbon bonding process, and its vertical cross-section is also L-shaped.

[0063] In step S2 of a packaging method for a silicon carbide packaging structure, a powder sintering method is used to infiltrate the metal material Al / Cu on the SiC crystal at a location corresponding to the electrode area of ​​the semiconductor chip 4, thereby forming an electrode connection area 2 (AlSiC / CuSiC composite structure) that connects the two side surfaces of the side wall of the SiC packaging shell 1; wherein the vertical cross-section of the AlSiC / CuSiC composite structure is L-shaped.

[0064] In step S3 , the side surface of the SiC crystal where the electrode connection region 2 is located is subjected to an electrospark etching process.

[0065] The above is only an embodiment of the present invention. Common knowledge such as the known specific structures and characteristics in the scheme is excessively described here. Ordinary technicians in the relevant field are aware of all common technical knowledge in the technical field of the invention before the application date or priority date, can obtain all existing technologies in the field, and have the ability to apply conventional experimental means before that date. Ordinary technicians in the relevant field can improve and implement this scheme in combination with their own abilities under the enlightenment given by this application. Some typical known structures or known methods should not become obstacles for ordinary technicians in the relevant field to implement this application. It should be pointed out that for those skilled in the art, without departing from the structure of the present invention, several variations and improvements can be made, which should also be regarded as the scope of protection of the present invention. These will not affect the effect of the implementation of the present invention and the practicality of the patent. The scope of protection required by this application shall be based on the content of its claims, and the specific implementation methods and other records in the specification can be used to interpret the content of the claims.

Claims

1. A packaging method for a silicon carbide packaging structure, characterized in that: The following steps are involved: A metal material is infiltrated into the SiC crystal corresponding to the electrode area of ​​the semiconductor chip using an infiltration process to form an electrode connection area connecting the two sides of the SiC package shell; Etching is performed on one side of the SiC crystal where the electrode connection area is located to form a SiC package shell with a groove in the middle; and the electrode connection area in the groove is retained at a predetermined height to form an electrode area protrusion; The SiC package shell is placed upside down on the semiconductor chip arranged on the substrate, and the electrode area protrusion is welded to the electrode area on the upper surface of the semiconductor chip, and the connection between the SiC package shell and the substrate is welded; The lead-out electrode is arranged on the electrode connection area on the outer side of the SiC package shell by using an aluminum or copper ribbon bonding process.

2. The packaging method of a silicon carbide packaging structure according to claim 1, wherein: The following steps are also included: An anti-radiation protective metal plate is welded on the lead-out electrode.

3. The packaging method of a silicon carbide packaging structure according to claim 2, wherein: The electrode connection area is an AlSiC / CuSiC composite structure, the volume fraction of the AlSiC composite structure ranges from 5-25%, and the volume fraction of the CuSiC composite structure ranges from 5-40%, which is the volume fraction of the metal in the entire SiC crystal.

4. A silicon carbide packaging structure comprising a substrate and a semiconductor chip, wherein the semiconductor chip is located in the middle of the substrate, characterized in that: A packaging method using a silicon carbide packaging structure according to any one of claims 1 to 3, further comprising a SiC packaging shell having a groove-shaped central portion and being inverted on the upper surface of the semiconductor chip, the SiC packaging shell being provided with an electrode connection area communicating with the inner and outer side surfaces of the SiC packaging shell, the electrode connection area being provided with an electrode area protrusion of a set height on the inner side surface of the SiC packaging shell, the electrode area protrusion being welded to the electrode area on the upper surface of the semiconductor chip, the SiC packaging shell being welded at the connection with the substrate, and the electrode connection area being welded with a lead electrode on the outer side surface of the SiC packaging shell.

5. The silicon carbide packaging structure according to claim 4, characterized in that: An anti-radiation protection metal plate is welded on the lead-out electrode.

6. The silicon carbide packaging structure according to claim 5, characterized in that: The anti-radiation protective metal plate is a high-order metal plate with a thickness of 0.5-5 mm.

7. The silicon carbide packaging structure according to claim 4, characterized in that: The electrode connection area is an AlSiC / CuSiC composite structure, and the substrate material is AlSiC / CuSiC.

8. The silicon carbide packaging structure according to claim 4, characterized in that: The substrate has a thickness of 0.5-10 mm.

9. The silicon carbide packaging structure according to claim 4, characterized in that: The height of the electrode area protrusion is set to 10 μm-1 mm, the shell thickness of the bottom of the SiC packaging shell is 0.5-7 mm, and the shell thickness of the side wall of the SiC packaging shell is 0.5-5 mm.

10. The silicon carbide packaging structure according to claim 4, characterized in that: The vertical cross-section of the electrode connection area is in the shape of a long strip or an L shape.

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