Semiconductor structure, manufacturing method and electronic device
By forming a first sidewall and a second sidewall on both sides of the protruding structure of the DRAM, with an air gap in between, the problems of inconsistent air gap sidewall formation and poor yield are solved, achieving low bit line capacitance and good induction margin, which is suitable for DRAM manufacturing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2020-06-22
- Publication Date
- 2026-05-26
AI Technical Summary
Existing technologies suffer from poor yield due to inconsistencies in the wafer structure and poor patterning of conductive materials during the formation of air gap sidewalls, which affect the bit line capacitance and sensing margin of DRAM.
The method involves forming a first sidewall and a second sidewall on both sides of the protruding structure, with an air gap in the middle. The thickness and height of the air gap are controlled by adjusting the etching process parameters to ensure yield and reduce bit line capacitance.
It achieves low bit line capacitance and good inductance margin, meeting the practical application requirements of DRAM and avoiding electrical short circuits.
Smart Images
Figure CN113903737B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, specifically to a semiconductor structure, manufacturing method, and electronic device. Background Technology
[0002] Data sensing margin is one of the key characteristic parameters of Dynamic Random Access Memory (DRAM). As DRAM device dimensions continue to shrink, bit-line capacitance (CBL) needs to be continuously reduced to ensure that the data sensing margin remains as high as possible compared to the previous generation. The main factors determining the characteristics of CBL are the thickness and dielectric constant of the bit-line sidewalls (spacers). Bit-line sidewalls typically employ a three-layer structure, such as a SiN / oxide / SiN three-layer structure. To further reduce bit-line capacitance, the use of air gaps in the sidewalls has become a technological trend. In recent years, various methods for forming air gap sidewalls have been proposed, but in actual process implementation, problems such as inconsistencies in the air gap sidewall structure within the wafer and poor yield due to conductive material patterning exist. Summary of the Invention
[0003] The purpose of this disclosure is to provide a semiconductor structure, manufacturing method, and electronic device. To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general description, nor is it intended to identify key / important components or describe the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.
[0004] According to one aspect of the present disclosure, a semiconductor structure is provided, comprising:
[0005] Semiconductor substrate;
[0006] Protrusions located on the semiconductor substrate;
[0007] The sidewall stack located on both sides of the protruding structure includes a first sidewall located on the upper part of the sidewall of the protruding structure and a second sidewall located outside the first sidewall, wherein there is an air gap between the protruding structure, the first sidewall and the second sidewall.
[0008] According to another aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:
[0009] A semiconductor substrate is provided, the semiconductor substrate including protrusion structures;
[0010] A sacrificial layer is formed on both sides of the protrusion structure. The sacrificial layer includes a connected vertical portion and a horizontal portion. The vertical portion is located on the sidewall of the protrusion structure, and the horizontal portion is located on the semiconductor substrate.
[0011] A first sidewall is formed above the sacrificial layer;
[0012] A second sidewall is formed outside the first sidewall;
[0013] The sacrificial layer is etched to create an air gap beneath the first sidewall.
[0014] According to another aspect of the present disclosure, an electronic device is provided, including the semiconductor structure described above.
[0015] One aspect of the technical solution provided by the embodiments of this disclosure may include the following beneficial effects:
[0016] The semiconductor structure provided in this disclosure has an air gap between the protruding structure, the first sidewall, and the second sidewall, which can achieve a low bit line capacitance and ensure a good sensing margin during use, thus well meeting the needs of practical applications.
[0017] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description, or some features and advantages may be inferred from the description or determined without question, or may be learned by practicing embodiments of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 A schematic diagram of a semiconductor structure according to an embodiment of the present disclosure is shown;
[0020] Figure 2 A schematic diagram of a semiconductor structure according to another embodiment of the present disclosure is shown;
[0021] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure is shown;
[0022] Figure 4A schematic diagram of a semiconductor substrate and multiple bit lines on the semiconductor substrate is shown according to an embodiment of the present disclosure.
[0023] Figure 5 It shows in Figure 4 A schematic diagram of the structure after an oxide layer is formed on the structure shown;
[0024] Figure 6 It shows in Figure 5 A schematic diagram of the structure after a hard mask material layer has been formed on the structure shown;
[0025] Figure 7 It shows the Figure 6 A schematic diagram of the structure after etching the hard mask material layer;
[0026] Figure 8 It shows the removal Figure 7 A schematic diagram of the structure behind the exposed oxide layer;
[0027] Figure 9 It shows in Figure 8 The diagram shown is a structural schematic after the formation of the first nitride layer.
[0028] Figure 10 It shows the Figure 9 A schematic diagram of the structure after etching the first nitride layer;
[0029] Figure 11 It shows the Figure 10 A schematic diagram of the structure after removing the remaining hard mask material layer;
[0030] Figure 12 It shows the Figure 11 A schematic diagram of the structure after the oxide layer of the structure has been etched and thinned;
[0031] Figure 13 It shows in Figure 12 A schematic diagram of the structure after the formation of the second nitride layer by deposition on the structure;
[0032] Figure 14 It shows the Figure 13 A schematic diagram of the structure after etching the second nitride layer;
[0033] Figure 15 A schematic diagram of the structure after the remaining oxide layer has been removed is shown;
[0034] Figure 16 It shows in Figure 15 A schematic diagram of the structure after the formation of the third nitride layer by deposition.
[0035] Figure 17 It shows in Figure 16A schematic diagram of the structure after multiple unit contact elements are deposited on the structure. Detailed Implementation
[0036] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0037] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0038] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0039] like Figure 1 As shown, one embodiment of this disclosure provides a semiconductor structure, including:
[0040] Semiconductor substrate 1;
[0041] A protrusion structure 2 located on the semiconductor substrate 1; the protrusion structure 2 can be a gate or a bit line;
[0042] The sidewall stack located on both sides of the protruding structure 2 includes a first sidewall 3 located on the upper part of the sidewall of the protruding structure 2 and a second sidewall 4 located outside the first sidewall 3, wherein there is an air gap 5 between the protruding structure 2, the first sidewall 3 and the second sidewall 4.
[0043] In some embodiments, the bottom of the second sidewall 4 is lower than the first sidewall 3, and there is a gap 6 between the bottom of the second sidewall 4 and the semiconductor substrate 1, the gap 6 being the opening of the air gap 5.
[0044] In some implementations, such as Figure 2As shown, the semiconductor structure further includes a third nitride layer 80, which is located outside the second sidewall 4 and on top of the protrusion structure 2. The bottom of the third nitride layer 80 extends into the gap 6 to seal the gap 6.
[0045] In some implementations, such as Figure 2 As shown, the semiconductor structure also includes a unit contact 90, which is disposed between two adjacent protrusions 2, and one end of the unit contact 90 is inserted into the semiconductor substrate 10.
[0046] In some embodiments, the upper end of the first sidewall 3 is flush with the upper end of the protruding structure 2.
[0047] In some embodiments, the protrusion structure 2 can be a gate or a bit line, for example, a bit line of DRAM.
[0048] The semiconductor structure provided in this embodiment has an air gap between the protruding structure, the first sidewall, and the second sidewall, which can achieve a low bit line capacitance. When used (e.g., in the manufacture of DRAM), it can ensure a good sensing margin and can well meet the needs of practical applications.
[0049] This embodiment also provides an electronic device, including the semiconductor structure described above. The electronic device includes a smartphone, computer, tablet computer, wearable smart device, artificial intelligence device, and power bank.
[0050] like Figure 3 As shown, this embodiment also provides a method for manufacturing a semiconductor structure, including:
[0051] S10. A semiconductor substrate is provided, wherein the semiconductor substrate includes a protrusion structure.
[0052] Specifically, the protruding structure can be a bit line, such as Figure 1 As shown, a semiconductor substrate 10 is provided, having a plurality of bit lines 20 on the semiconductor substrate 10. The semiconductor substrate 10 may be made of silicon material.
[0053] S20. A sacrificial layer is formed on both sides of the protruding structure. The sacrificial layer includes a vertical portion and a horizontal portion connected together. The vertical portion is located on the sidewall of the protruding structure, and the horizontal portion is located on the semiconductor substrate.
[0054] In some implementations, forming the sacrificial layer includes:
[0055] S201. An oxide layer is deposited over the entire semiconductor structure.
[0056] For example, such as Figure 4and Figure 5 As shown, an oxide layer 30 is formed on the semiconductor substrate 10 and the plurality of bit lines 20.
[0057] Specifically, in some embodiments, oxide is deposited on the semiconductor substrate 10 and multiple bit lines 20 to form an oxide layer 30.
[0058] like Figure 4 and Figure 5 As shown, a semiconductor substrate 10 and a plurality of spaced bit lines 20 formed on the semiconductor substrate 10 are provided. The semiconductor substrate 10 may be made of silicon. The oxide layer 30 includes a first portion 301 on the semiconductor substrate 10, a second portion 302 on the sidewall of the bit line 20, and a third portion 303 on the upper surface of the bit line 20. The oxide may be made of silicon dioxide. The bit line 20 includes a contact layer 202 and a conductive layer 201 sequentially stacked from the semiconductor substrate 10. The oxide layer 30 covers the semiconductor substrate 10 and the plurality of bit lines 20.
[0059] In addition, the semiconductor substrate 10 may also include a silicon semiconductor substrate, a germanium semiconductor substrate, and / or a silicon-germanium semiconductor substrate, etc., and this disclosure does not impose specific limitations. Bit lines 20 are formed on the semiconductor substrate 10. After the contact material structure layer and the wire material structure layer are formed sequentially, the wire structure material layer and the contact material structure layer are etched respectively to obtain the wire layer 201 and the contact layer 202.
[0060] S202. A dielectric layer is deposited over the entire semiconductor structure, extending beyond the top of the oxide layer.
[0061] The dielectric layer can be a hard mask material layer. For example, such as... Figure 6 As shown, a hard mask material layer 40 is formed on the oxide layer 30. In some embodiments, a hard mask material (SOH, spin-on-hard mask) is coated on the oxide layer 30 to form the hard mask material layer 40.
[0062] S203. The oxide layer and dielectric layer are etched back to below the top of the protrusion structure, and the oxide layer is formed as a sacrificial layer.
[0063] Specifically, such as Figure 7As shown, the hard mask material layer 40 is etched back to expose the upper portion of the oxide layer 30 on the bit line, while retaining a portion of the hard mask material layer 40. The upper portion of the oxide layer 30 covers the upper end face of the bit line 20 and the upper portions of both sidewalls of the bit line 20. The hard mask material layer 40 is etched back to expose the upper portion 3021 of the third location 303 and the second location. The lower portion 3022 of the second location is the unexposed portion of the second location 302. By adjusting the etch back process parameters, the size of the exposed upper portion of the oxide layer 30 can be adjusted, thereby achieving the purpose of adjusting the thickness and height of the air gap sidewall to be formed.
[0064] Remove the oxide layer from the exposed bit lines to expose the bit lines.
[0065] In some embodiments, the third portion 303 of the oxide layer 30 and the upper portion 3021 of the exposed second portion are removed by a wet etching method or a dry etching method, such as... Figure 8 As shown.
[0066] S30, A first sidewall is formed above the sacrificial layer.
[0067] In some embodiments, forming the first sidewall includes:
[0068] S301. A nitride layer is deposited on the protruding structure, the sacrificial layer, and the dielectric layer.
[0069] For example, such as Figure 9 As shown, a first nitride layer is deposited to form a first nitride layer; wherein the first nitride layer covers the upper surface of the hard mask material layer, the upper end face of the oxide layer, and the upper portion of the bit line.
[0070] In some embodiments, the material of the first nitride layer 50 may be a nitride such as SiN, SiCN, SiBN, or SiON;
[0071] Specifically, silicon nitride is deposited on the oxide layer 30 and the hard mask material layer 40 to form a first nitride layer 50. The first nitride layer 50 includes a first portion 501 of the first nitride layer above the bit line 20, a second portion 502 of the first nitride layer on the sidewall of the bit line 20, and a third portion 503 of the first nitride layer on the hard mask material layer 40. The thickness of the first nitride layer 50 is less than or equal to the thickness of the oxide layer 30.
[0072] S302, The nitride layer is etched to form a first sidewall located on the sidewall of the protruding structure.
[0073] For example, such as Figure 10As shown, the first nitride layer 50 is selectively etched to remove the first nitride layer 50 located on the hard mask material layer 40 and the top surface of the bit line, while retaining the first nitride layer 50 on the sidewall of the bit line.
[0074] In some embodiments, the first nitride layer 50 is etched to remove the first portion 501 and the third portion 503 of the first nitride layer, exposing the upper end face of the bit line 20 and the hard mask material layer 40 below the third portion 503 of the first nitride layer, and the remaining second portion 502 of the first nitride layer forms the first sidewall.
[0075] Then, the remaining portion of the hard mask material layer 40 is removed, such as... Figure 11 As shown.
[0076] In some implementations, the remaining hard mask material layer 40 is removed by an ashing process.
[0077] S40. A second sidewall is formed outside the first sidewall.
[0078] In some embodiments, forming the second sidewall includes:
[0079] S401, A nitride layer is deposited on the sacrificial layer and the first sidewall.
[0080] For example, such as Figure 13 As shown, a second nitride layer 60 is deposited; wherein the second nitride layer 60 covers the top surface of the oxide layer 30, the first nitride layer 50 and the bit line 20.
[0081] The second nitride layer 60 can also be called the outer SiN spacer.
[0082] The material of the first nitride layer 50 can be nitrides such as SiN, SiCN, SiBN, and SiON.
[0083] Specifically, a second nitride layer 60 can be formed by depositing silicon nitride, and the second nitride layer 60 serves as the outer frame of the air gap.
[0084] The second nitride layer 60 includes a first portion 601 of the second nitride layer on the remaining oxide layer 301', a second portion 602 of the second nitride layer on the lower portion 3022 of the second location and the second portion 502 of the first nitride layer, and a third portion 603 of the second nitride layer on the upper end face of the bit line 20.
[0085] S402, Etch the nitride layer to form a second sidewall located between the sacrificial layer and the first sidewall.
[0086] For example, such as Figure 14 As shown, the second nitride layer is selectively etched to remove the second nitride layer located on the top surface of the thin oxide layer and the bit line 20, while retaining the second nitride layer on the sidewall of the bit line.
[0087] In some embodiments, the first portion 601 of the second nitride layer 60 and the third portion 603 of the second nitride layer 60 are etched to expose the remaining oxide layer 301' and the upper end face of the bit line 20.
[0088] S50. Etch the sacrificial layer to form an air gap under the first sidewall.
[0089] For example, such as Figure 15 As shown, a thin oxide layer on the semiconductor substrate and a remaining oxide layer located on the bit line sidewall are removed to form an opening 701 and an air gap 70. Specifically, the remaining oxide layer 301' is removed by wet etching or dry etching to form the air gap 70.
[0090] In some embodiments, before forming the second sidewall outside the first sidewall, the method further includes:
[0091] S30', Etching and thinning the horizontal portion.
[0092] For example, the oxide layer 30 on the semiconductor substrate 10 is etched and thinned to form a thin oxide layer. In some embodiments, the first portion 301 is etched and thinned to obtain the remaining oxide layer 301', such as... Figure 12 As shown. This is to facilitate sealing the air gap opening after it is formed. By etching to thin the oxide layer on the semiconductor substrate 10, the thickness of the portion covering the oxide layer is less than that on the sidewall of the bit line 20, so that the thickness of the subsequently formed air gap opening is less than the thickness of the air gap, which facilitates sealing.
[0093] In some embodiments, the method further includes:
[0094] S60. A nitride layer is deposited on the semiconductor substrate and the second sidewall to seal the bottom opening of the air gap.
[0095] For example, such as Figure 16As shown, a third nitride layer 80 is deposited to seal the opening 701, forming an air gap sidewall. Specifically, a third nitride layer 80 is deposited to cover the semiconductor substrate 10, the second portion 602 of the second nitride layer, and the upper surface of the bit line 20, thereby blocking the opening 701 of the air gap 70. Care must be taken to prevent SiN from entering the air gap; the sealed air gap then becomes the air gap sidewall. The material of the third nitride layer can be nitrides such as SiN, SiCN, SiBN, or SiON. In this embodiment, the opening 701 of the air gap 70 is located at the bottom of the air gap 70, between the second portion 602 of the second nitride layer and the semiconductor substrate 10. The opening 701 faces outwards, and its thickness is less than the thickness of the air gap 70, thus facilitating the sealing process.
[0096] S70. Etch the nitride layer to form a third sidewall located on the second sidewall.
[0097] Specifically, the portion of the third nitride layer located on the semiconductor substrate is etched downward along the sidewall of the third nitride layer in a direction perpendicular to the semiconductor substrate to expose the semiconductor substrate, and the sidewall of the third nitride layer forms the third sidewall.
[0098] In some embodiments, the method further includes:
[0099] S80. A trench is formed on the semiconductor substrate between two adjacent protrusion structures;
[0100] Specifically, the exposed portion of the semiconductor substrate is etched to form trenches on the semiconductor substrate.
[0101] S90. A unit contact is deposited in the trench, wherein the top surface of the unit contact is higher than the semiconductor substrate and lower than the top surface of the third sidewall.
[0102] The semiconductor structure manufacturing method provided in this embodiment can adjust the size of the exposed oxide layer by adjusting the etching process parameters, thereby adjusting the thickness and height of the air gap sidewall to be formed; the formed air gap opening is located at the bottom of the air gap, the opening direction is outward, and the thickness of the opening is less than the thickness of the air gap, so the sealing process is easy to operate.
[0103] Polycrystalline silicon is deposited in the trench to form unit contacts, the upper end of which is higher than the upper end of the semiconductor substrate and lower than the upper end of the sidewall of the third nitride layer.
[0104] like Figure 17As shown, each of the unit contact members 90 is disposed between two adjacent bit line structures, and one end of the unit contact member 90 is inserted into the semiconductor substrate; the bit line structure includes the bit line 20, the first nitride layer 50, the air gap sidewall, the second nitride layer 60 and the third nitride layer 80.
[0105] like Figure 17 As shown, this embodiment also provides a semiconductor structure, including:
[0106] Semiconductor substrate 10:
[0107] Multiple bit line structures are spaced apart on the semiconductor substrate 10;
[0108] Multiple unit contacts 90 are provided, each of which is disposed between two adjacent bit line structures, and one end of the unit contact 90 is inserted into the semiconductor substrate 10.
[0109] The bitline structure includes:
[0110] Bit line 20;
[0111] The first nitride layer 50 is located on both sides of the upper part of the bit line 20;
[0112] Air gap sidewalls are located on both sides of the lower part of the bit line 20 and below the first nitride layer 50.
[0113] The second nitride layer 60 is located outside the first nitride layer 50 and the air gap sidewall;
[0114] A third nitride layer 80 covers the second nitride layer 60 and the upper surface of the bit line 20.
[0115] The beneficial technical effects achieved by the manufacturing method of the air-gap spacer provided in this disclosure include: First, by adjusting the etching process parameters, the size of the exposed oxide layer can be adjusted, thereby achieving the purpose of adjusting the thickness and height of the air-gap spacer to be formed; Second, the opening is located at the bottom of the air gap, the opening direction is outward, and the thickness of the opening is less than the thickness of the air gap, so the sealing process is easy to operate; Third, during the formation of the air gap, no conductive material is exposed, avoiding the adverse phenomenon of electrical short circuit.
[0116] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0117] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A semiconductor structure, characterized in that, include: Semiconductor substrate; Protrusions located on the semiconductor substrate; The sidewall stack located on both sides of the protruding structure includes a first sidewall located on the upper part of the sidewall of the protruding structure and a second sidewall located outside the first sidewall, wherein there is an air gap between the protruding structure, the first sidewall and the second sidewall; The bottom of the second sidewall is lower than that of the first sidewall, and there is a gap between the bottom of the second sidewall and the semiconductor substrate; The semiconductor structure further includes a nitride layer located outside the second sidewall and on top of the protrusion structure, with the bottom of the nitride layer extending into the gap to seal it.
2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a unit contact, which is disposed between two adjacent protrusions, with one end of the unit contact inserted into the semiconductor substrate.
3. The semiconductor structure according to claim 1, characterized in that, The upper end of the first sidewall is flush with the upper end of the protruding structure.
4. The semiconductor structure according to claim 1, characterized in that, The protruding structure is a gate or a bit line.
5. The semiconductor structure according to claim 4, characterized in that, The protruding structure is a bit line of DRAM.
6. A method for manufacturing a semiconductor structure as described in any one of claims 1-5, comprising: A semiconductor substrate is provided, the semiconductor substrate including protrusion structures; A sacrificial layer is formed on both sides of the protrusion structure. The sacrificial layer includes a connected vertical portion and a horizontal portion. The vertical portion is located on the sidewall of the protrusion structure, and the horizontal portion is located on the semiconductor substrate. A first sidewall is formed above the sacrificial layer; A second sidewall is formed outside the first sidewall; The sacrificial layer is etched to create an air gap beneath the first sidewall.
7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, The formation of the sacrificial layer includes: An oxide layer is deposited over the entire semiconductor structure; A dielectric layer is deposited over the entire semiconductor structure, extending beyond the top of the oxide layer; The oxide layer and dielectric layer are etched back to below the top of the protrusion structure, with the oxide layer forming a sacrificial layer.
8. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, The formation of the first sidewall includes: A nitride layer is deposited on the protruding structure, the sacrificial layer, and the dielectric layer; The nitride layer is etched to form a first sidewall located on the sidewall of the protruding structure.
9. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, Before forming the second sidewall outside the first sidewall, the method further includes: The horizontal portion is thinned by etching.
10. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, The formation of the second sidewall includes: Nitride layers are deposited on the sacrificial layer and the first sidewall; The nitride layer is etched to form a second sidewall located between the sacrificial layer and the first sidewall.
11. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, The method further includes: A nitride layer is deposited on the semiconductor substrate and the second sidewall to seal the bottom opening of the air gap; The nitride layer is etched to form a third sidewall located on the second sidewall.
12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that, The method further includes: A trench is formed on the semiconductor substrate between two adjacent protrusion structures; A unit contact is deposited within the trench, the top surface of which is higher than the semiconductor substrate and lower than the top surface of the third sidewall.
13. An electronic device comprising a semiconductor structure as claimed in any one of claims 1 to 5.
14. The electronic device according to claim 13, including a smartphone, a computer, a wearable smart device, an artificial intelligence device, and a power bank.