Temperature compensation system and method for full differential hysteretic comparator with resistive load

Abstract

The application provides a full-differential hysteresis comparator temperature compensation system and method with resistance as a load, and belongs to the field of hysteresis comparators.The application provides a full-differential hysteresis comparator temperature compensation system and method with resistance as a load, and provides a method for calculating the temperature coefficient of each end of a differential amplifier with a smaller load when the temperature coefficient of each type of unit resistance meets a linear constraint condition in the application.Meanwhile, the application provides a method for using two or more types of resistances through a series / parallel connection mode, adjusting the proportion of different types of unit resistances, and finally obtaining an ideal temperature coefficient of the load resistance.The application overcomes the defect that the resistance value of the load resistance of the hysteresis comparator structure follows the temperature change, solves the disadvantage that the open-loop gain of the hysteresis comparator changes with the temperature due to the problem, improves the signal processing rate of the comparator, improves the overall performance of the comparator, and makes the output result closer to the ideal effect.

Description

Technical Field

[0001] This invention belongs to the field of hysteresis comparators, specifically relating to a temperature compensation system and method for a fully differential hysteresis comparator with a resistor as the load. Background Technology

[0002] Hysteresis comparators are common circuits in integrated circuits. Their strong anti-interference capability and fast state transition rate make them widely used in the design of front-end particle detection circuits. Fully differential hysteresis comparators with resistor loads possess several of the key characteristics of hysteresis comparators. First, the resistor load allows for a faster signal transmission rate; second, the fully differential input characteristic improves the noise performance of the output signal. Due to these advantages, this type of hysteresis comparator is widely used in front-end particle detection circuits.

[0003] Reference [1] (Reference [1] Zhou Yangfan, Li Qiuju, Liu Peng, Fan Lei, Xu Wei, Tao Ye, Li Zhenjie, Anultrafast front-end ASIC for APD array detectors in X-ray time-resolved experiments[J]. Chinese Physics C, 2017, 41(06): 138-145.) discloses a hysteresis comparator circuit. Figure 1 As shown, this hysteresis comparator circuit mainly consists of four identical low-gain, high-bandwidth differential amplifier circuits and a hysteresis circuit. Each differential amplifier stage uses two NMOS transistors as input transistors and one NMOS transistor as its tail current transistor. The differential amplifier uses two resistors of equal value as loads, and a diode-connected transistor clamps the output voltage of the differential amplifier, thereby reducing the output detuning recovery time under large signal input conditions, further improving the output voltage slew rate of this hysteresis comparator. Furthermore, the hysteresis circuit module includes three NMOS transistors, similar in structure to the differential amplifiers. Two of these NMOS transistors are used as signal input transistors, and the third as the tail current transistor. A positive feedback loop is used to introduce the hysteresis signal into the comparator circuit to improve the circuit's noise immunity.

[0004] This hysteresis comparator circuit has a simple structure, small area, and simultaneously possesses good noise immunity and a fast signal transmission rate. However, in actual CMOS manufacturing processes, since the load of each stage differential amplifier of the comparator is a temperature-sensitive POLY resistor, and the resistor type is generally the same, the load resistor here is defined as R. DTherefore, the load at each end of the differential amplifier can be expressed as:

[0005] R = R D (1)

[0006] Since the load resistor has a relatively large temperature coefficient, the temperature coefficient of the load at each end of the differential amplifier can be represented by equation (2).

[0007]

[0008] As can be seen from equation (2), the temperature coefficient of the comparator load is the same as that of the actual POLY resistor used. Therefore, its actual resistance value will change continuously with the temperature. Thus, the hysteresis comparator of this structure also has disadvantages: the load resistance value will change with the temperature, which will cause the open-loop gain of the entire hysteresis comparator to change with the temperature, thereby affecting the signal processing rate of the comparator, thus affecting the overall performance of the comparator, and ultimately failing to obtain the ideal output result. Summary of the Invention

[0009] To overcome the shortcomings of the prior art, the present invention provides a method for temperature compensation of a fully differential hysteresis comparator with a resistor as the load.

[0010] To achieve the above objectives, the present invention provides the following technical solution:

[0011] A temperature compensation system for a fully differential hysteresis comparator with a resistive load includes four differential amplifier circuits connected in stages and a hysteresis circuit connected to the four differential amplifier circuits in the form of a positive feedback loop.

[0012] The differential amplifier circuit includes:

[0013] Two first NMOS transistors, whose gates serve as the input terminals of the differential amplifier circuit;

[0014] Two transistors are used to clamp the output voltage of the differential amplifier circuit; both are composed of diodes connected together, and the source and drain of each transistor are connected as the output terminal of the differential amplifier circuit. The gates of the two transistors are respectively connected to the drains of the two first NMOS transistors.

[0015] The second NMOS transistor serves as the tail current transistor of the differential amplifier circuit; its source is grounded, its drain is connected to the source of the two first NMOS transistors, and its gate is connected to an external voltage.

[0016] Two load resistors serve as the load for the differential amplifier circuit, each of which is composed of two or more unit resistors with different temperature coefficients connected in series or in parallel.

[0017] The hysteresis circuit includes:

[0018] Two third NMOS transistors have their gates connected to the outputs of four progressively connected differential amplifier circuits, and their drains are the output terminals.

[0019] The fourth NMOS transistor serves as the tail current transistor of the hysteresis circuit; its source is grounded, its drain is connected to the source of the two third NMOS transistors, and its gate is connected to an external voltage.

[0020] A method for temperature compensation of a fully differential hysteresis comparator with a resistive load includes the following steps:

[0021] The resistance value and temperature coefficient of the load resistor are expressed in terms of unit resistance, resulting in the resistance value expression and temperature coefficient expression.

[0022] The resistance value of the load resistor is determined according to the resistance value expression and the temperature coefficient expression;

[0023] Setting the temperature coefficient expression to zero, the temperature coefficient KT for each type of unit resistance is obtained based on the linear constraint relationship. R1 KT R2 ,…,KT RN The KT RN This represents the temperature coefficient of the Nth unit resistance;

[0024] The proportion of different types of unit resistance is determined based on the value of the temperature coefficient.

[0025] Preferred,

[0026] The resistance value of the load resistor is expressed as follows:

[0027] R = R1 + R2 + ... + R N

[0028] The temperature coefficient of the load resistor is expressed as:

[0029]

[0030] Where R represents the resistance value of the load resistor, R N This represents the resistance value of the Nth unit resistor.

[0031] Preferred,

[0032] The resistance value of the load resistor is expressed as follows:

[0033]

[0034] The temperature coefficient of the load resistor is expressed as:

[0035]

[0036] Where R represents the resistance value of the load resistor, R N This represents the resistance value of the Nth unit resistor.

[0037] The method for temperature compensation of a fully differential hysteresis comparator with a resistor as the load provided by this invention has the following beneficial effects: This application overcomes the defect that the load resistor value of the hysteresis comparator structure changes with temperature, solves the drawback that the open-loop gain of the hysteresis comparator changes with temperature due to this problem, improves the signal processing speed of the comparator, improves the overall performance of the comparator, and makes the output result closer to the ideal effect. Attached Figure Description

[0038] To more clearly illustrate the embodiments and design schemes of the present invention, the accompanying drawings required for this embodiment will be briefly described below. The drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of the circuit structure of the hysteresis comparator proposed in the background art reference [1] of this invention;

[0040] Figure 2 This is a circuit diagram of the hysteresis comparator for temperature compensation of load resistance proposed in Embodiment 1 of the present invention;

[0041] Figure 3 This is a circuit structure diagram of the differential amplifier circuit proposed in Embodiment 1 of the present invention;

[0042] Figure 4 This is a circuit structure diagram of the hysteresis circuit proposed in Embodiment 1 of the present invention. Detailed Implementation

[0043] To enable those skilled in the art to better understand and implement the technical solutions of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and should not be construed as limiting the scope of protection of the present invention.

[0044] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances. In the description of this invention, unless otherwise stated, "a plurality of" means two or more, which will not be elaborated further here.

[0045] Example 1

[0046] This invention provides a method for temperature compensation of a fully differential hysteresis comparator with a resistive load, specifically as follows: Figure 2 The diagram shown is a circuit structure diagram of the hysteresis comparator proposed in this invention, which includes four differential amplifier circuits connected in stages and a hysteresis circuit connected to the four differential amplifier circuits in the form of a positive feedback loop.

[0047] Specifically, such as Figure 3 As shown, the differential amplifier circuit includes: two first NMOS transistors, whose gates serve as the input terminals of the differential amplifier circuit; two transistors used to clamp the output voltage of the differential amplifier circuit; both are composed of diodes connected together, with the source and drain of each transistor connected as the output terminal of the differential amplifier circuit, and the gates of the two transistors respectively connected to the drains of the two first NMOS transistors; a second NMOS transistor, serving as the tail current transistor of the differential amplifier circuit; its source is grounded, its drain is connected to the source of the two first NMOS transistors, and its gate is externally connected to a voltage; and two load resistors, serving as the load of the differential amplifier circuit, each load resistor being composed of two or more unit resistors with different temperature coefficients connected in series or parallel.

[0048] Specifically, such as Figure 4 As shown, the hysteresis circuit includes: two third NMOS transistors, whose gates are respectively connected to the output terminals of four differential amplifier circuits connected in stages, and whose drains are the output terminals; a fourth NMOS transistor serves as the tail current transistor of the hysteresis circuit, whose source is grounded, whose drain is connected to the source terminals of the two third NMOS transistors, and whose gate is connected to an external voltage.

[0049] and Figure 1 In contrast, this invention uses two or more types (with different temperature coefficients) of unit resistors in series / parallel connection to achieve R in equation (1). D The constraints satisfied by the resistance values ​​of different types of unit resistors and the temperature coefficient of the load at each end of the improved differential amplifier are expressed as follows:

[0050] R = R1 + R2 + ... + R N

[0051]

[0052]

[0053]

[0054] By setting the formula representing the temperature coefficient of the load to zero, a linear constraint relationship is found between the temperature coefficients of various types of unit resistors. Then, within the achievable temperature coefficient range of each type of unit resistor, simulation verification is used to find the temperature coefficient KT of each type of resistor that minimizes the formula result of the load temperature coefficient. R1 KT R2 ,…,KT RN Subsequently, while satisfying the constraints of the unit resistance formula for each type of unit resistance, the proportion of each type of unit resistance in the load resistance R is adjusted so that each type of unit resistance has a temperature coefficient KT obtained by setting the formula representing the temperature coefficient of the load to zero. R1 KT R2 ,…,KT RN Ultimately, the above scheme achieves the goal of temperature compensation for a fully differential hysteresis comparator with a resistive load by adjusting the temperature coefficient of the differential amplifier's load resistor.

[0055] The specific implementation steps are as follows:

[0056] First step, according to Figure 1 The design of the medium hysteresis comparator is based on relevant design specifications, such as overall gain, small signal bandwidth, and output voltage slew rate, and the value of the load resistor R is determined under room temperature conditions (300K).

[0057] The second step, according to Figure 2 The design of the medium hysteresis comparator uses two or more types of unit resistors in series / parallel connection to realize the load resistance R. The limiting relationship between the various types of unit resistors is based on the resistance value formula of the unit resistor, so that the temperature coefficient of the total load resistance R is related to the temperature coefficient of each type of unit resistor according to the formula of the load temperature coefficient.

[0058] The third step is to obtain the linear constraint relationship between the temperature coefficients of various types of unit resistances, under the condition that the formula for the temperature coefficient of the load is equal to zero.

[0059] The fourth step is to find, through simulation verification, the temperature coefficient KT of each type of unit resistance that minimizes the temperature coefficient of the load within the achievable temperature coefficient range for each type of unit resistance. R1 KT R2 ,…,KT RN .

[0060] The fifth step involves adjusting the proportion of each type of unit resistor in the load resistance R while satisfying the limiting relationships of the unit resistance formula. This ensures that each type of unit resistor possesses the temperature coefficient KT obtained by setting the temperature coefficient of the load formula to zero.R1 KT R2 ,…,KT RN .

[0061] The above embodiments are merely preferred embodiments of the present invention, and the scope of protection of the present invention is not limited thereto. Any simple changes or equivalent substitutions of the technical solutions that can be obviously obtained by those skilled in the art within the scope of the technology disclosed in the present invention shall fall within the scope of protection of the present invention.

Claims

1. A temperature compensation system for a fully differential hysteresis comparator with a resistive load, characterized in that, It includes four differential amplifier circuits connected in stages, and a hysteresis circuit connected to the four differential amplifier circuits in the form of a positive feedback loop; The differential amplifier circuit includes: Two first NMOS transistors, whose gates serve as the input terminals of the differential amplifier circuit; Two transistors are used to clamp the output voltage of the differential amplifier circuit; both are composed of diodes connected together, and the source and drain of each transistor are connected as the output terminal of the differential amplifier circuit. The gates of the two transistors are respectively connected to the drains of the two first NMOS transistors. The second NMOS transistor serves as the tail current transistor of the differential amplifier circuit; its source is grounded, its drain is connected to the source of the two first NMOS transistors, and its gate is connected to an external voltage. Two load resistors serve as the load for the differential amplifier circuit, each of which is composed of two or more unit resistors with different temperature coefficients connected in series or in parallel. The hysteresis circuit includes: Two third NMOS transistors have their gates connected to the outputs of four progressively connected differential amplifier circuits, and their drains are the output terminals. The fourth NMOS transistor serves as the tail current transistor of the hysteresis circuit; its source is grounded, its drain is connected to the source of the two third NMOS transistors, and its gate is connected to an external voltage.

2. The compensation method for the temperature compensation system of a fully differential hysteresis comparator with a resistive load as described in claim 1, characterized in that, Includes the following steps: The resistance value and temperature coefficient of the load resistor are expressed in terms of unit resistance, resulting in the resistance value expression and temperature coefficient expression. The resistance value of the load resistor is expressed as: The temperature coefficient of the load resistor is expressed as: in, This indicates the resistance value of the load resistor. This represents the resistance value of the Nth unit resistor; The resistance value of the load resistor is determined according to the resistance value expression and the temperature coefficient expression; Setting the temperature coefficient expression to zero, the temperature coefficients of various types of unit resistances are obtained based on the linear constraint relationship. The This represents the temperature coefficient of the Nth unit resistance; The proportion of different types of unit resistance is determined based on the value of the temperature coefficient.

3. The compensation method for the temperature compensation system of a fully differential hysteresis comparator with a resistive load as described in claim 2, characterized in that, The resistance value of the load resistor is expressed as: The temperature coefficient of the load resistor is expressed as: in, This indicates the resistance value of the load resistor. This represents the resistance value of the Nth unit resistor.

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