Quantum circuit simulation

Abstract

This invention provides an embodiment for simulating quantum circuits. Specifically, it receives indications of subsets of input and output qubits of the quantum circuit. The indicated subset corresponds to an amplitude tensor of the quantum circuit to be determined, wherein the amplitude tensor includes the amplitudes of different state combinations of the qubits in the indicated subset. Using a tensor network of the quantum circuit and a restricted maximum cardinality search (RMCS), the elimination order of intermediate qubits within the quantum circuit is determined. The amplitude tensor is determined by sequentially deleting the indices of the tensor network corresponding to the intermediate qubits according to the elimination order.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of quantum circuit simulation. Background Technology

[0002] Recently, several companies have developed various types of quantum computers. However, quantum computers are still not commercially available. Quantum computer simulators can provide an efficient platform for developing quantum algorithms and verifying upcoming quantum processors.

[0003] However, in practice, simulating quantum computers and quantum circuits is typically a highly complex task, requiring a significant amount of memory. The complexity increases with the number of qubits processed in the simulation.

[0004] There are different methods for simulating quantum circuits. Some of these methods are listed below and further mentioned in the description:

[0005] [1] H. De Raedt et al., “Massively parallel quantum computer simulator, eleven years later”, Communications in Computer Physics, Vol. 237, pp. 47-61, 2019, arXiv:1805.04708v2[quant-ph].

[0006] [2] IL Markov and Y. Shi, “Simulating quantum computing by contracting tensor networks”, SIAM Journal of Computing, Vol. 38, No. 3, pp. 963-981, January 2005, arXiv:quant-ph / 0511069v7.

[0007] [3] S. Boixo, SVIsakov, VNSmelyanskiy and H. Neven, “Simulation of low-depth quantum circuits as complex undirected graphical models”, December 2017, arXiv:1712.05384v2[quant-ph].

[0008] [4] J. Chen, F. Zhang, C. Huang, M. Newman and Y. Shi, “Classical Simulation of Intermediate-Size Quantum Circuits”, May 2018, arXiv:1802.06952v3[quant-ph].

[0009] [5] RETarjan and M. Yannakakis, “Simple Linear Time Algorithm To Test Chordality of Graph, Test Acyclicity Of Hypergraphs, And Selectively Reduce Acyclic Hypergraphs”, SIAM J. Comput., Vol. 13, No. 3, pp. 566-579, 1984. Summary of the Invention

[0010] The above methods may still suffer from high complexity and low flexibility in selecting results to be simulated.

[0011] This invention is defined by the independent claims. Some advantageous embodiments are the subject of the dependent claims.

[0012] According to a first aspect, the present invention relates to a decoding apparatus for simulating a quantum circuit. The apparatus includes processing circuitry. The processing circuitry is configured to: receive indications of a subset of input and output qubits of the quantum circuit, the indicated subset corresponding to an amplitude tensor of the quantum circuit to be determined, the amplitude tensor including the amplitudes of different state combinations of the qubits in the indicated subset; determine an elimination order of intermediate qubits within the quantum circuit using a tensor network of the quantum circuit and a restricted maximum cardinality search (RMCS); and determine the amplitude tensor by sequentially deleting indices of the tensor network corresponding to the intermediate qubits according to the elimination order.

[0013] Using RMCS, the optimal / optimized elimination sequence can be determined for arbitrary amplitude subsets. This can reduce the computational cost and memory requirements of analog quantum circuits.

[0014] According to the first aspect or the first aspect itself, in a first possible implementation of the device, the elimination order is determined iteratively in reverse order by selecting an intermediate qubit from the intermediate qubits in each step of the iteration, wherein the intermediate qubit: (i) was not selected in any previous step of the iteration; (ii) corresponds to a vertex in the chord graph representing the tensor network, the vertex being adjacent to a maximum number of vertices corresponding to: (a) the intermediate qubit selected in any previous step of the iteration, or (b) the qubit in the indicator subset.

[0015] According to the first implementation of the first aspect or the first aspect itself, in one possible implementation of the device, each intermediate qubit uniquely corresponds to a corresponding index of the tensor, each qubit in the indicator subset uniquely corresponds to a corresponding index of the tensor, and each index of the tensor uniquely corresponds to an input qubit, an output qubit, or an intermediate qubit; and / or there is a one-to-one correspondence between the vertices of the chord graph and the indices corresponding to the intermediate qubits or the qubits in the indicator subset.

[0016] According to the second implementation of the first aspect or the first aspect itself, in one possible implementation of the device, the chord graph representing the tensor network is a chord graph completion of a non-chord graph, the non-chord graph representing the tensor network having a minimized maximal clique in the chord graph completion of the non-chord graph.

[0017] According to the above implementation or the first aspect itself, in one possible implementation of the device, the chord graph is obtained from the non-chord graph representing the tensor network using an optimized elimination order of the vertices of the non-chord graph, wherein the chord graph is obtained by adding edges to the non-chord graph such that for each vertex, all neighbors of the vertex that are later than the vertex in the optimized elimination order are a clique in the chord graph.

[0018] According to the above implementation or the first aspect itself, in one possible implementation of the device, for each quantum gate of the quantum circuit, there exists a tensor of the tensor network, and for each quantum bit of the quantum gate that is an intermediate quantum bit or in the indicator subset, the tensor has an index corresponding to the quantum bit; for each quantum gate of the quantum circuit, the vertex of the nonstring graph corresponding to the quantum bit of the quantum gate is a clique.

[0019] According to the above implementation or the first aspect itself, in one possible implementation of the device, determining the elimination order of the intermediate qubits includes determining the optimized elimination order.

[0020] According to the above implementation or the first aspect itself, in one possible implementation of the device, the optimized elimination order of the vertices of the non-chord graph representing the tensor network is determined using an optimization process. The optimization process minimizes the maximum clique of the graph obtained by adding edges to the non-chord graph such that, for each vertex in the graph, all neighbors of the vertex that are later than the vertex in the optimized elimination order are a clique in the graph.

[0021] According to the two implementations described above or the first aspect itself, in one possible implementation of the device, before determining the optimized elimination order, the nonstring graph is modified by adding edges to the nonstring graph such that the vertices of the qubits corresponding to the indicated subset are cliques.

[0022] According to a first implementation of the first aspect or the first aspect itself, in one possible implementation of the apparatus, the processing circuitry is configured to determine, based on the indicator subset, the nonstring graph representing the tensor network such that: (i) there is a one-to-one correspondence between the vertices of the nonstring graph and the indices of the tensors corresponding to intermediate qubits or qubits in the indicator subset; (ii) for each tensor of the tensor network, the vertex of the nonstring graph corresponding to the tensor is a clique.

[0023] According to a first implementation of the first aspect or the first aspect itself, in one possible implementation of the device, the processing circuitry is configured to determine, based on the indication subset, the nonstring graph representing the tensor network by adding the following: (i) for each input or output qubit in the indication subset, a single vertex corresponding to the qubit, and (ii) edges such that for each quantum gate of the quantum circuit, the vertex of the nonstring graph corresponding to the qubit of the quantum gate is a clique, wherein there is a one-to-one correspondence between the vertices of the universal nonstring graph and the intermediate qubits.

[0024] According to a first implementation of the first aspect or the first aspect itself, in one possible implementation of the device, the processing circuitry is configured to determine, based on the indicated subset, the nonstring graph representing the tensor network by deleting, for each input or output qubit not in the indicated subset, all edges connecting vertices corresponding to the qubits, and all vertices corresponding to the qubits; wherein there is a one-to-one correspondence between the vertices of the general nonstring graph and the qubits of the quantum circuit, wherein each qubit of the quantum circuit is an input qubit, an output qubit, or an intermediate qubit.

[0025] According to any of the above-described implementations of the first aspect or the first aspect itself, in one possible implementation of the device, the processing circuitry is configured to delete from the tensor of the tensor network an index corresponding to: (i) an input qubit not in the indicator subset, or (ii) an output qubit not in the indicator subset, before deleting the index corresponding to the intermediate qubit.

[0026] According to any of the above-described implementations of the first aspect or the first aspect itself, in one possible implementation of the device, the index corresponding to an input qubit not in the indicator subset or an output qubit not in the indicator subset is removed from the tensor network by setting the index to a corresponding predetermined value; and / or the index corresponding to the intermediate qubit is removed from the tensor network by shrinking.

[0027] According to a second aspect, the present invention relates to a method for simulating a quantum circuit. The method includes the steps of: receiving an indication of a subset of input and output qubits of the quantum circuit, the indicated subset corresponding to an amplitude tensor of the quantum circuit to be determined, the amplitude tensor including the amplitudes of different state combinations of the qubits in the indicated subset; determining an elimination order of intermediate qubits within the quantum circuit using a tensor network of the quantum circuit and a restricted maximum cardinality search (RMCS); and determining the amplitude tensor by sequentially deleting indices of the tensor network corresponding to the intermediate qubits according to the elimination order.

[0028] According to the second aspect itself, in a first possible implementation of the method, the elimination order is determined iteratively in reverse order by selecting one intermediate qubit from the intermediate qubits in each step of the iteration, wherein the intermediate qubit: (i) was not selected in any previous step of the iteration; (ii) corresponds to a vertex in the chord graph representing the tensor network, the vertex being adjacent to a maximum number of vertices corresponding to: (a) the intermediate qubit selected in any previous step of the iteration, or (b) the qubit in the indicator subset.

[0029] According to the first implementation of the second aspect or the second aspect itself, in one possible implementation of the method, each intermediate qubit uniquely corresponds to a corresponding index of the tensor, each qubit in the indicator subset uniquely corresponds to a corresponding index of the tensor, and each index of the tensor uniquely corresponds to an input qubit, an output qubit, or an intermediate qubit; and / or there is a one-to-one correspondence between the vertices of the chord graph and the indices corresponding to the intermediate qubits or the qubits in the indicator subset.

[0030] According to a second implementation of the second aspect or the second aspect itself, in one possible implementation of the method, the chord graph representing the tensor network is a chord graph completion of a non-chord graph, the non-chord graph representing the tensor network having a minimized maximal clique in the chord graph completion of the non-chord graph.

[0031] According to the above implementation or the second aspect itself, in one possible implementation of the method, the chord graph is obtained from the non-chord graph representing the tensor network using an optimized elimination order of the vertices of the non-chord graph, wherein the chord graph is obtained by adding edges to the non-chord graph such that for each vertex, all neighbors of the vertex that are later than the vertex in the optimized elimination order are a clique in the chord graph.

[0032] According to the above implementation or the second aspect itself, in one possible implementation of the method, for each quantum gate of the quantum circuit, there exists a tensor of the tensor network, and for each quantum bit of the quantum gate that is an intermediate quantum bit or in the indicator subset, the tensor has an index corresponding to the quantum bit; for each quantum gate of the quantum circuit, the vertex of the nonstring graph corresponding to the quantum bit of the quantum gate is a clique.

[0033] According to the above implementation or the second aspect itself, in one possible implementation of the method, determining the elimination order of the intermediate qubits includes determining the optimized elimination order.

[0034] According to the above implementation or the second aspect itself, in one possible implementation of the method, the optimized elimination order of the vertices of the non-chord graph representing the tensor network is determined using an optimization process. The optimization process minimizes the maximum clique of the graph obtained by adding edges to the non-chord graph such that, for each vertex in the graph, all neighbors of the vertex that are later than the vertex in the optimized elimination order are a clique in the graph.

[0035] According to the two implementations described above or the second aspect itself, in one possible implementation of the method, before determining the optimized elimination order, the nonstring graph is modified by adding edges to the nonstring graph such that the vertices corresponding to the indicated subset of qubits are cliques.

[0036] According to the first implementation of the second aspect or the second aspect itself, in one possible implementation of the method, the method includes the steps of: determining the nonstring graph representing the tensor network based on the indicator subset, such that: (i) there is a one-to-one correspondence between the vertices of the nonstring graph and the indices of the tensors corresponding to intermediate qubits or qubits in the indicator subset; (ii) for each tensor of the tensor network, the vertex of the nonstring graph corresponding to the tensor is a clique.

[0037] According to the first implementation of the second aspect or the second aspect itself, in one possible implementation of the method, the method includes the following steps: determining the nonstring graph representing the tensor network based on the indicator subset by adding the following items: (i) a single vertex corresponding to each input or output qubit in the indicator subset, and (ii) edges such that for each quantum gate of the quantum circuit, the vertex of the nonstring graph corresponding to the qubit of the quantum gate is a clique, wherein there is a one-to-one correspondence between the vertex of the universal nonstring graph and the intermediate qubit.

[0038] According to the first implementation of the second aspect or the second aspect itself, in one possible implementation of the method, the method includes the following steps: determining the nonstring graph representing the tensor network based on the indicator subset by deleting the following items for each input or output qubit not in the indicator subset: all edges connecting vertices corresponding to the qubits, and all vertices corresponding to the qubits; wherein there is a one-to-one correspondence between the vertices of the general nonstring graph and the qubits of the quantum circuit, wherein each qubit of the quantum circuit is an input qubit, an output qubit, or an intermediate qubit.

[0039] According to any of the above-described implementations of the second aspect or the second aspect itself, in one possible implementation of the method, the method includes the step of: deleting from the tensor of the tensor network an index corresponding to: (i) an input qubit not in the indicator subset, or (ii) an output qubit not in the indicator subset, before deleting the index corresponding to the intermediate qubit.

[0040] According to any of the above-described implementations of the second aspect or the second aspect itself, in one possible implementation of the method, the index corresponding to an input qubit not in the indicator subset or an output qubit not in the indicator subset is removed from the tensor network by setting the index to a corresponding predetermined value; and / or the index corresponding to the intermediate qubit is removed from the tensor network by shrinking.

[0041] The advantages of the method provided in the second aspect are the same as the advantages of the corresponding implementation of the device provided in the first aspect.

[0042] According to a third aspect, the present invention relates to a computer program product comprising instructions stored on a non-transitory storage medium. When executed in one or more processors, the computer program product performs the methods provided in the first or second aspect or any possible embodiment of the first or second aspect.

[0043] The following figures and description illustrate one or more embodiments in detail. Other features, objects, and advantages will be apparent from the specification, figures, and claims. Attached Figure Description

[0044] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the drawings:

[0045] Figure 1 It is a tensor network A represented using a traditional graphical tensor network. ij B jk C iklGraphical representation;

[0046] Figure 2 It is a tensor network A represented using an alternative graphical tensor network. ij B jk C ikl Graphical representation;

[0047] Figure 3 It is a shrinking tensor network A ii B jk C ikl The index k and the formation of a new tensor D ijl Graphical representation;

[0048] Figure 4 (a)-(g) are graphical representations of a fully contracted tensor network using the elimination order π = [kjilmn];

[0049] Figure 5 (a)-(g) are complete contractions using the elimination sequence π=[kjilmn]. Figure 4 (a) is a graphical representation of the tensor network, highlighting the largest clique corresponding to a single intermediate tensor;

[0050] Figure 6 (a)-(g) are complete contractions using the elimination sequence π=[kjilmn]. Figure 4 (a) is a graphical representation of the tensor network, highlighting the largest clique corresponding to a single intermediate tensor;

[0051] Figure 7 This is a schematic diagram of an exemplary quantum circuit;

[0052] Figure 8 (a)-(d) show exemplary graphical representations of different quantum gates;

[0053] Figure 9 yes Figure 7 A graphical representation of an exemplary quantum circuit;

[0054] Figure 10 This is a block diagram for implementing an example of a quantum circuit simulator in an embodiment of the present invention;

[0055] Figure 11 (a)-(f) are graphical representations of chord diagrams generated based on the graph and the elimination order π=[ijklmn];

[0056] Figure 12 (a)-(g) are based on the chord diagram. and vertex subset (These vertices are cliques) Construct a perfect elimination order The graphical representation of it has its vertex C at the end;

[0057] Figure 13 It can be executed according to the chord diagram. and vertex subset (These vertices are cliques) to achieve the perfect elimination order A flowchart of exemplary steps;

[0058] Figure 14 It is possible to perform the operation to obtain the chord diagram based on the graph G = (V, E) and the elimination order π: V → {1, ..., |V|}. A flowchart of exemplary steps;

[0059] Figure 15 It can be used as Figure 14 A flowchart of an exemplary step performed as a part of an exemplary step;

[0060] Figure 16 It can be used as Figure 14 and / or Figure 15 A flowchart of an exemplary step performed as a part of an exemplary step;

[0061] Figure 17 It can be made by Figure 10 The flowchart illustrates the exemplary steps performed by the exemplary quantum circuit simulator.

[0062] In the following text, the same reference numerals refer to the same or at least functionally equivalent features. Detailed Implementation

[0063] In the following description, reference is made to the accompanying drawings, which form part of this invention and illustrate specific aspects of embodiments of the invention or from which specific aspects of embodiments of the invention may be used. It should be understood that embodiments of the invention may be used in other aspects and may include structural or logical variations not depicted in the drawings. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of the invention is defined by the appended claims.

[0064] For example, it should be understood that the disclosure relating to the described method can also apply to the corresponding device or system for performing the method, and vice versa. For example, if one or more specific method steps are described, the corresponding device may include one or more units (in other words, modules or circuits) (e.g., functional units) to perform the described one or more method steps (e.g., one unit performs one or more steps, or multiple units perform one or more of a plurality of steps respectively), even if the one or more units are not explicitly described or illustrated in the drawings. On the other hand, for example, if a specific apparatus is described according to one or more units (e.g., functional units), the corresponding method may include a step to implement the function of one or more units (e.g., one step implements the function of one or more units, or multiple steps implement the function of one or more of a plurality of units respectively), even if the one or more steps are not explicitly described or illustrated in the drawings. Furthermore, it should be understood that, unless otherwise stated, features of the various exemplary embodiments and / or aspects described herein can be combined with each other.

[0065] This invention focuses on the efficient simulation of quantum circuits (digital quantum computers). The task of quantum circuit simulation is essential for the development of quantum algorithms and the verification and validation of upcoming quantum processors.

[0066] Quantum computers operate based on the states of a collection (e.g., multiple, a system, or a group) of two-state quantum systems (also called qubits). Unlike ordinary bits, which can only be assumed to have two values, i.e., in state "0" or "1", the states of qubits are vectors in a two-dimensional complex vector space. It is convenient to represent the general state of a qubit as a linear combination (or superposition) of two computational ground states (denoted as |0> and |1>), which form an orthogonal basis of the vector space, i.e., satisfying the conditions <1|0>=<0|1>=0 and <0|0>=<1|1>=1. It should be noted that these conditions allow for free choice of computational ground states. For example, two states... and This also forms an orthogonal basis, which can also be used to describe the state of a qubit. The computational state is represented as a vector. and Then, the state of any qubit can be written as

[0067]

[0068] Here, α is the amplitude of state |0>, and β is the amplitude of state |1>. In other words, a qubit can be a linear combination of states |0> and |1>. If state |φ> satisfies the normalization condition <φ|φ>=|α| 2 +|β| 2If |α| = 1, then the result of a measurement performed on a qubit (e.g., a measurement of electron spin) is 0, with a probability of |α|. 2 , or 1, with a probability of |β| 2 .

[0069] The state of a system with N qubits |ψ> is determined by 2 N A specified amplitude, or in other words, 2. N A vector in a dimensional vector space. Similar to the above, the computational ground state of an N-qubit system can be written in the following form:

[0070]

[0071] in, The outer product of vectors representing individual qubits, index i i We can assume values ​​of 0 and 1. Therefore, the state of any system with N qubits can be written as...

[0072]

[0073] As can be seen from the above, given a basis |i1, ...,i... N >,|ψ> corresponds to having N (inverse) indices i1,...,i N (N, 0) type tensor of (order / degree / rank N) Each index can be assumed to have two distinct values, such as 0 or 1. Tensor The entries, i.e., tensors The corresponding value assumed for a combination of N index values ​​is the magnitude of the state |ψ>. Based on the index values ​​and the basis used to describe the tensor, each magnitude corresponds to a specific state of the system and indicates the probability of observing the system in that specific state. In other words, for indices x1, ..., x... N Each combination of values, where Amplitude Tensor amplitude The absolute square is the value observed when measuring a system in state |ψ>, where the amplitude is... The corresponding computational ground state (i.e., in state |x1, ..., x) N The probability of observing a system in state |x1, ..., x2. N The probability of > is

[0074] For example, we assume a 4-qubit state |ψ> and are interested in the probability of observing the qubit string b = 0001, that is, the probability of observing the first, second, third, and fourth qubits in states |0>, |0>, |0>, and |1>, respectively. In other words, we are interested in the probability |ψ> of finding a 4-qubit system in the following states. 0001 | 2 :

[0075]

[0076] Then, the tensor corresponding to state |0001> (or qubit string b) and with index values ​​i1=i2=i3=0, i4=1 The magnitude of the entries ψ 0001 It can be calculated as follows:

[0077] ψ 0001 = <e 0001 |ψ>,

[0078] It is a vector |e 0001 The inner product between > and |ψ>.

[0079] In terms of quantum programming, the operation of a quantum circuit can be represented as the effect of the circuit matrix C (usually a unitary matrix) on the initial state |φ> of the quantum circuit:

[0080] |ψ>=C|φ>,

[0081] Then measure the final state |ψ> of the quantum circuit.

[0082] To simulate quantum computing, tensors are typically computed / determined. Or entries for vectors |ψ>. There are different approaches in this regard.

[0083] In the first method (full-state method), all magnitudes of |ψ> are obtained at once by applying a sparse linear transformation to the magnitude vector |ψ> (full-state simulation, [1]):

[0084] |ψ>=C|φ>=C d ·C d-1 ·…·C1|φ>

[0085] Here, the entire circuit matrix C is expanded into a (unitary) matrix Cu. j The product of operations is represented by the operation, each operation being performed in the corresponding (clock) cycle of the circuit j∈[1,..,d]. However, as in [1], applying the gate directly to the full state vector is difficult to optimize. Furthermore, such programs require a large amount of RAM, which limits the maximum circuit size on modern hardware to around 50 qubits. Most older programs are based on sparse matrices C. kSequential application of state vectors (e.g., initial state vector |φ>).

[0086] In the second method (single-amplitude method), each amplitude is calculated one by one by evaluating the vector-matrix-vector product (e.g., evaluating the matrix elements of C):

[0087] σ k = <e k |ψ>= <e k |C d ·C d-1 …C1|φ>

[0088] Sparse matrix C i It is the outer product of a single-qubit or two-qubit gate. To utilize C... i The internal structure of the circuit can be more conveniently represented as a type (N, N) tensor acting on |φ> (with N inverse and N covariant indices, thus a rank of 2N). Similar to the state vector |ψ>, the circuit matrix can be written as...

[0089]

[0090] Here, it is assumed that the summation is performed on the same index, and |·><·| represents the outer product.

[0091] Evaluation of a single amplitude, for example, calculating One of them is equivalent to the shrinking (e.g., complete shrinking) of a tensor network [2], [3]. In other words, tensor and / or This can be obtained by shrinking tensor networks. Typically, tensor networks can be used to describe quantum circuits and / or compute entries for amplitude tensors in quantum circuits. Tensor networks usually consist of expressions for one or more tensors, such as A... ij ·B jk ·C ikl Each tensor has a corresponding set of indices. Typically, each distinct index (in the example, i, j, k, and l) may appear on more than one tensor in the tensor network. Depending on the context, the contraction of all (distinct) indices can be implicitly understood or explicitly indicated by ∑. ijk A ij ·B jk ·C ikl In this invention, the summation of indices is also referred to as the shrinking of the indices. Therefore, compared to the common tensor shrinking which performs the summation of indices that appear exactly twice, in this invention, the shrunken indices can also appear only once or more times in the tensor network.

[0092] Such code (implementations) based on tensor network graphs are more flexible and can exceed the 50-qubit limit. However, their problem is inefficient handling of diagonal matrices and higher-order tensors. In particular, in traditional tensor representations, the representation of diagonal tensors is indistinguishable, such as controlled Z-gates. Off-diagonal tensors Here, the diagonal tensor is one of them. The tensor, that is, in

[0093]

[0094] Therefore, it can be represented by a diagonal matrix acting on an N-qubit system.

[0095] Furthermore, it is more difficult to tune tensor network graph-based programs to make efficient use of modern parallel hardware.

[0096] The corresponding tensor network can be obtained from any quantum circuit, as shown below. First, the quantum circuit is represented using single-qubit and two-qubit gates, such as Hadamard gates, controlled X gates (cX, also known as controlled NOT gates, CNOT), and π / 8 gates, which always achieves arbitrary precision. However, it should be noted that this is merely an illustrative example, and the invention is not limited to a specific set of gates used to describe quantum circuits. Generally, any set of gates, even n-qubit gates with arbitrary n (especially gates where n > 2), can be used to describe quantum circuits and achieve the advantages of this invention.

[0097] Then, the individual single-qubit and two-qubit gates are represented as

[0098] (Diagonal single-qubit gate)

[0099] (Off-diagonal single-qubit gate)

[0100] (Diagonal two-qubit gate), and

[0101] (Off-diagonal two-qubit gate)

[0102] Among them, usually It can be represented as a unitary matrix and depends on the specific quantum gate. Therefore, typically, for each quantum gate of a quantum circuit, there may exist a tensor of the (unshrunken) tensor network. Generally, there may be a one-to-one correspondence between the quantum gate and the tensor of the tensor network (initially, i.e., before shrinking). However, after shrinking the index, new tensors obtained from more than one tensor of the unshrunken tensor network can correspond to more than one quantum gate.

[0103] Furthermore, as can be seen from the above formula, even diagonal quantum gates introduce new variables / qubit states. However, using the orthogonality of the computational basis, these qubit states can be immediately removed from the tensor expression of the quantum circuit. These qubit states are referred to as non-unique qubit states, as explained further below. For example, a diagonal single-qubit gate U... d1 Followed by an off-diagonal single-qubit gate U n1 It can be simplified to

[0104]

[0105] in It can be considered to correspond to U d1 and U n1 Door.

[0106] Then, according to the following formula, the circuit tensor of a quantum circuit operating with N qubits is... It can be written as a Boolean variable. The sum of the two Boolean variables is assumed to have values ​​of 0 and 1.

[0107]

[0108] Here, we can assume that non-unique qubit states may have been removed, that is, only the variables corresponding to unique qubit states are considered. Summation (otherwise, some functions ψ1 would include increment functions) It also sums the states of non-unique qubits.

[0109] It should be noted that N can also be the number of output qubits in the circuit, and the number of input qubits can be the same as the number of output qubits. Furthermore, for each Boolean variable... The subscript k enumerates the qubits (e.g., enumerates...). Figure 7 In the context of world lines (horizontal lines; vertical lines are lines between two points), the superscript l enumerates lines along world lines (e.g., along qubit lines in the graphical representation of quantum circuits, such as...). Figure 7 (As shown) introduces a new variable. In other words, for all k∈{1, 2, ..., N}, the variable... This corresponds to the k-th qubit. Specifically, according to the amplitude... Corresponding to the initial / input state and final / output state The fact that the k-th qubit exists means that for each qubit, there are two corresponding Kroncker increments. and and tensor ψ j middle and The value is correct. It should also be noted that typically d1, ..., d... N They can be different from each other. Furthermore, the remaining variables... l∈{1, 2, ..., d} k -1 corresponds to the (unique) intermediate qubit state.

[0110] This is also Figure 7 As shown below, a more detailed explanation will follow. However, it should be noted that... Figure 7 The non-unique qubit state and the unique qubit state are shown.

[0111] In the above text, we assumed that all labels having the same subscript i... The horizontal lines all correspond to a single / identical qubit. In other words, the state is considered to be... The l-th state corresponding to a k-qubit (e.g., and These are the input and output states of the first quantum bit, respectively.

[0112] However, in this invention, the input state of the k-th qubit... The output state of the k-th qubit The intermediate state of the k-th qubit l∈{1, 2, ..., d} k -1} are called mutually distinct qubits. In particular, we usually adopt the view that: in the above formula, for Other variables l∈{1, 2, ..., d} k The value of -1 corresponds to the intermediate qubit. As explained further below, this is merely a matter of terminology.

[0113] Furthermore, in the above formula, the functions ψ1, ..., ψ μ Each function in the list is a function and One of them, therefore depending on one, two, or four Boolean variables. Then, the function can be based on... and Rewritten as a tensor. It should also be noted that, typically, the input and output can also be referred to as external qubits.

[0114] In particular, diagonal single-qubit gates, off-diagonal single-qubit gates, diagonal two-qubit gates, and off-diagonal two-qubit gates are represented as tensors of rank 1, 2, 2, and 4, respectively. It should also be noted that, since at this point, the computation of the magnitude tensor (or one or more specific magnitudes of the tensor) is merely a matter of complex number multiplication and addition, there is no need to distinguish between the upper and lower indices of the tensor (e.g., it can be written as...). Instead It should also be noted that, in order to obtain the amplitude... One possibility is that a complete shrinkage of the tensor network must be performed, i.e., the sum of all Boolean variables / tensor indices. Typically, magnitude expressions (e.g., tensor networks) can also be constructed using known techniques, such as those described in [3] and [4].

[0115] Finally, some codes based on graphical models (e.g., graphical models of tensor networks corresponding to a given quantum circuit) overcome the previous problems. These codes utilize tensor network graphs for optimization evaluation. In other words, in these graphical models, the tensor network is represented as a graph, preferably undirected and / or simple graphs, which will be discussed in detail below. Figures 1 to 3 To explain.

[0116] Figure 1 The tensor network ∑ is shown. ijk A ij ·B jk ·C ikl The first graphical representation (also referred to here as the traditional representation). As can be seen, in this representation, nodes represent multidimensional arrays, and edges represent indices of the multidimensional arrays. Vectors, matrices, and higher-order tensors are represented by nodes with 1, 2, and more edges, respectively. Connecting edges represent contractions (summations) over their respective indices.

[0117] In other words, in a traditional representation / graph, vertices representing tensors with a common index are connected by edges. Furthermore, for each tensor in a tensor network, there may be a vertex in the corresponding traditional graph. Typically, there is a one-to-one correspondence between vertices and tensors. However, for an index in a tensor network, there may be multiple corresponding edges. For example, if an index appears on three tensors, there are three edges connecting the vertices corresponding to those three tensors. Moreover, every two vertices corresponding to a tensor with a shared index are connected by an edge. Therefore, a tensor with a shared index corresponds to a clique (fully connected subgraph) in the traditional graph.

[0118] It should be noted that, generally, "a subset of vertices is / forms a clique" means that each vertex of the subset is connected to every other vertex in the subset. It should also be noted that in the expression "two vertices connected," the terms "connected," "joined," or "stitched" are used interchangeably. Furthermore, the terms "node" and "vertex" are used interchangeably. Additionally, a "neighbor" of a first vertex is another second vertex that shares a common edge with the first vertex; while a vertex adjacent to a first vertex is a neighbor of the first vertex.

[0119] exist Figure 1 In the traditional Chinese representation of the diagram, due to the example expression ∑ ijk A ij ·B jk ·C ikl There are three tensors (A, B, and C) in the graph, therefore there are three vertices, each corresponding to a specific tensor within the graph. Furthermore, since tensors A and B share index j, the vertices corresponding to tensors A and B are connected by edges corresponding to index j. Similarly, since tensors A and C share index i, the vertices corresponding to tensors A and C are connected by edges corresponding to index i. Finally, since tensors B and C share index k, the vertices corresponding to tensors B and C are connected by edges corresponding to index k.

[0120] Figure 2 The same example expression ∑ is shown. ijk A ij ·B jk ·C ikl The different graphical representations used in [3] (also referred to here as graphical models) are also used. In this representation, (unique) indices are represented by nodes, and tensors are represented by cliques (fully connected subgraphs).

[0121] In other words, in the graph representation, vertices with indices in a common tensor are connected by edges. Furthermore, for each unique index in the tensor network, there may be a corresponding vertex in the graph representation. Typically, there is a one-to-one correspondence between vertices and unique indices.

[0122] It's important to note that the term "unique index" refers to indices that are distinct from each other. That is, multiple tensors may share a common index, but an index appearing on multiple tensors counts as a single unique index. For example, in the example expression ∑... ijk A ij ·B jk ·C ikl It has four unique indices i, j, k, and l. Typically, the term "unique" can be omitted here if it is known from the context.

[0123] However, there is typically no one-to-one correspondence between tensors and graph edges. In other words, for a tensor in a tensor network, there can be multiple corresponding edges. For example, if a tensor has more than three distinct indices, then each pair of vertices corresponding to those distinct indices will have an edge. All of these edges correspond to the tensor (and vice versa). Therefore, each tensor corresponds to a clique (fully connected subgraph) in the graph model.

[0124] exist Figure 2 In the illustration of the graphical model, due to the example expression ∑ ijk A ij ·B jk ·C ikl There are four unique indices (i, j, k, and l) in the graph, therefore there are four vertices, each corresponding to a specific index. Furthermore, since tensor A has indices i and j, the vertices corresponding to indices i and j are connected by edges corresponding to tensor A. Similarly, since tensor B has indices j and k, the vertices corresponding to indices j and k are connected by edges corresponding to tensor B. Finally, since tensor C has indices i, k, and l, the vertices corresponding to indices i, k, and l form a clique, and all edges of the clique correspond to tensor C. In other words, the edges connecting vertices corresponding to indices i and k, the edges connecting vertices corresponding to indices k and l, and the edges connecting vertices corresponding to indices i and l all correspond to tensor C. Therefore, in the graph, tensor C is represented by all three edges.

[0125] Then, a graphical model was used.

[0126] The shrinking of the index corresponds to deleting a node from the graph and introducing connections between all its neighbors. This is in Figure 3 As shown in the image. More specifically, Figure 3 Example expression ∑ is shown ijk A ij ·B jk Ci kl The shrinkage of index k. Specifically, Figure 3 The diagram on the left shows the corresponding example expression ∑ ijk A ij ·B jk Ci kl The (unshrunken) plot, with the shrunken plot obtained by shrinking index k shown on the right.

[0127] It should be noted that, typically, shrinking a tensor network refers to deleting one or more indices by performing one or more summations. Similarly, shrinking a tensor network index refers to deleting an index by summing the indices. For example, in the example expression ∑ ijk A ij ·B jk Cikl In this context, the contraction of index k corresponds to summing over k:

[0128]

[0129] From shrinking tensor networks ∑ ij A ij ·D ijl As can be seen, there is no index k.

[0130] New tensor D ijl Explicitly given as D ijl =∑ k B jk ·C ikl Typically, shrinking an index can create a new tensor. Therefore, all tensors sharing a shrinking index can be merged into a new tensor. Conversely, shrinking can also typically remove all tensors from a tensor network with a shrinking index. In other words, these tensors will not appear in the shrunk tensor network.

[0131] A new clique represents a new tensor formed after shrinking its respective indices. In other words, in a shrinking tensor network, there is a new tensor where "new" means that no identical tensors existed in the tensor network before the shrinking. The indices of the new tensor correspond to the vertices of the neighbors of the vertex corresponding to the shrinking index.

[0132] For example, in Figure 3 As can be seen in the example shown, the new clique is formed by vertices i, j, and l, where all edges between these indices correspond to the new tensor D. Typically, all neighbors of the removed node can become a clique in the shrinking graph (e.g., if they are not already).

[0133] Typically, for the amplitude expression σ k = <e k |ψ>= <e k |C d ·C d-1 The evaluation of ...C1|φ> is equivalent to the complete shrinkage of the corresponding tensor network. In terms of the graph, this corresponds to eliminating all nodes in the graph. For example, as shown in [2], the optimal shrinkage sequence can be computed by tree decomposition of the expression graph. The dimension of the largest intermediate tensor is given by the tree width. Therefore, the tree width corresponds to the quality of the scheme (elimination sequence).

[0134] In the following text, now combined Figure 4 The following example expression illustrates the use of a graphical model in analyzing the shrinkage of a full tensor network:

[0135]

[0136] The complete shrinking of this tensor network can be performed through the following steps.

[0137]

[0138]

[0139]

[0140]

[0141]

[0142]

[0143] Specifically, in steps (1), (2), (3), (4), (5), and (6), indices i, j, k, l, m, and n are shrunk, respectively. Furthermore, the graphs obtained after steps (1), (2), (3), (4), (5), and (6) are respectively... Figure 4 As shown in (b), (c), (d), (e), (f), and (g), Figure 4 a) shows the original / unshrunken graph. In each step, the intermediate (tensor network) expression is summed over a single variable (index), which is removed from the tensor network, and the corresponding node is removed from the graph. The clique in the graphical model is the intermediate tensor T in the shrinking sequence. In other words, a new tensor T can be formed in each step of the elimination process. If such a new tensor T has an index that shrinks in the next step of the elimination sequence, then the new tensor is called an intermediate tensor.

[0144] However, the numerical cost of the operation depends critically on the size of the intermediate product, or the size of the maximal clique in the graphical model. For example, to evaluate an intermediate tensor T using K variables / indices of size L (e.g., assuming L distinct values ​​when performing a summation), it might require L... K+1 This is a multiplication (e.g., when two tensors are combined into an intermediate tensor). Furthermore, the resulting intermediate tensor will have L... K There are 10 entries. Furthermore, a virtual tensor of rank K+1 can be formed. Here and below, the term "virtual tensor" refers to a tensor that can be built into computer memory during the index shrinking process. More generally, the term "virtual tensor" refers to the computational cost and memory requirements required to perform the shrinking step.

[0145] For example, in step (1) above, for an intermediate tensor with three indices of size 2... Evaluate. This may require 2. 4 = 16 times multiplied and sum of 2 3 =8 additions. This can be achieved by first constructing / computing a virtual tensor of size 4. This is implemented by... Here, each of the 16 entries in the virtual tensor corresponds to the result of a multiplication. Then, the virtual tensor can be... shrink.

[0146] Different contraction sequences may lead to different intermediate products (but the result is the same). In particular, the computational complexity (e.g., in terms of the memory / RAM required to perform the calculations) depends critically on the size of the largest clique in the intermediate graph. Therefore, the analysis of tensor network graphs can be used for efficient simulation of quantum circuits.

[0147] It should be noted that the terms "intermediate graph" and "intermediate tensor network" in the elimination order refer to those graphs / tensor networks obtained after performing the elimination according to the elimination order, the first or more shrinkages in the two or more shrinkages, but not all shrinkages. Intermediate graphs do not include the original / unshrinked graph and the final graph. For example, in Figure 4 In the diagram, figures (b), (c), (d), (e), and (f) are intermediate diagrams. It should also be noted that the terms "node order," "shrinking order," "shrinking sequence," "elimination order," "shrinking sequence," and "shrinking sequence" are used interchangeably. Furthermore, aside from external qubits that may have been removed from the tensor network / graphical model representing the quantum circuit, there is generally a one-to-one correspondence between qubits, unique indices, and vertices. Therefore, the elimination order of qubits corresponds to the elimination order of vertices and the shrinking order of indices (and vice versa). Thus, the terms "qubit elimination sequence," "index elimination sequence," and "vertices elimination sequence" are used interchangeably.

[0148] It should also be noted that, typically, each vertex / index appears only once in the elimination order. Therefore, generally, a subset of vertices V of a graph G(V, E) with vertices V and edges E is considered. The elimination order is bijective π: C → {1, 2, ..., |C|}. Alternatively, π can be viewed as a set of vertex and index pairs: Where C = {c1, c2, ..., c} |C| Furthermore, the index set I = {i1, i2, ..., i} can be defined as follows: |I| The elimination order of the indices of} (in the form π: I→{1, 2, ..., |I|}) is expressed as π=[π -1 (1)π -1 (2)…π -1 (|I|)](For example, this expression can be read as π = [jlmikn]). Furthermore, it should be noted that the graph here is typically a set of vertices V = {v1, v2, ..., v...} |V|} and the edge set E = {e1, e2, ..., e |E| An ordered pair G(V, E) of the graph, where each edge corresponds to a pair of vertices in the graph.

[0149] Typically, the shrinking of two or more indices can be performed in any order. That is, regardless of the order, the same tensor network and the same graphical model will be obtained after shrinking all two or more indices. In short, any order will produce the same result. However, the intermediate graphs and tensor networks often depend on the order in which the shrinking is performed.

[0150] In other words, different elimination sequences lead to intermediate products of different dimensions, for example, intermediate tensors with different ranks and / or different intermediate graphs. This is in Figure 5 and Figure 6 The diagram shows two different elimination orders. More specifically, Figure 5 Corresponding to the elimination sequence π = [ijklmn], the steps are the same as... Figure 4 same, Figure 6 This corresponds to the elimination sequence π = [kjilmn].

[0151] exist Figure 5 and Figure 6 In the diagram, the clique corresponding to the largest intermediate product (e.g., the largest intermediate tensor) is highlighted by a shaded region. In other words, the shaded region highlights the vertex corresponding to the index of the (newly formed) intermediate tensor with the largest rank among the intermediate tensors in the corresponding elimination sequence. More specifically, Figure 5 The set highlighted in (b) corresponds to the tensor formed in step (1) above. Similarly, Figure 6 The set highlighted in (b) corresponds to the new tensor formed in the first step of eliminating the sequence π = [kjilmn].

[0152] Since the maximum rank of an intermediate tensor corresponds to (e.g., equal to) the maximum size of the clique corresponding to a single intermediate tensor, the maximum size of the clique corresponding to a single intermediate tensor in the elimination sequence is closely related to the computational complexity of the elimination sequence.

[0153] For example, suppose the contraction occurs once in each of the three initial tensors of ranks r1, r2, and r3. The resulting tensor might be an intermediate tensor with rank r = r1 + r2 + r3 - 3. However, although only... A complex number is used to describe all three initial tensors, but the resulting tensors require... The plural form usually has more than the original form. A plural number.

[0154] Therefore, the variable / index elimination sequence corresponding to the minimum computational complexity contains the intermediate tensor with the minimum possible maximum rank. In a graphical model, the elimination sequence corresponding to the minimum possible intermediate tensor can be computed based on the tree decomposition of the initial graph (e.g., based on the graph corresponding to the unshrunken tensor network).

[0155] The tree decomposition of graph G can be expressed as finding the count of nodes with the smallest maximum clique (or maximum tree width) in the elimination sequence. As described below, such an elimination sequence can be used to construct a chord graph from the initial graph, which has the smallest tree width (or smallest maximum clique) among the chord graphs that can be constructed from the initial graph.

[0156] It should be noted that, strictly speaking, only the elimination sequence corresponding to the minimum possible intermediate tensor and / or the minimum possible tree width of the resulting chord graph is the optimal elimination sequence. In other words, strictly speaking, among all elimination sequences that eliminate the same two or more nodes in a given graph, the optimal elimination order minimizes the maximum clique in the intermediate graph (e.g., corresponding to a single intermediate tensor). Typically, there may be more than one optimal elimination order to minimize the maximum rank of the intermediate tensor.

[0157] However, especially considering that finding the optimal elimination order is an NP-hard problem, in practical applications, the optimal elimination order is often not the truly optimal elimination order, but only an approximation. In this invention, such an approximation is also referred to as an optimized elimination order. Typically, the optimized elimination sequence can be the result of some kind of (e.g., heuristic) optimization process, and does not necessarily actually minimize the maximum clique and / or minimize the maximum intermediate tensor in the resulting chord graph. Therefore, the chord graph constructed using the optimized elimination sequence can only have substantially the minimum tree width, or in other words, can only have the minimum tree width. However, in some embodiments, the optimized elimination order is the optimal elimination order. In other words, the optimization process used to determine the optimized elimination order can be the process that determines the optimal elimination order.

[0158] Now for reference Figures 7 to 9 This will illustrate the construction of a graphical model of a quantum circuit.

[0159] Figure 7 An exemplary 4-qubit quantum circuit 700 is shown. It can be seen that after each quantum gate, the corresponding qubit lines (i.e., horizontal lines; vertical lines are lines between two points) are labeled with different symbols. The tag (index increased by 1). It should be noted that... Figure 7 The time order of operations is from right to left (the later the time, the higher the index).

[0160] Specifically, it is expressed as and Each line corresponds to one of the four input qubits of the quantum circuit 700, and is represented as... and Each line corresponds to one of the four output qubits of the quantum circuit 700.

[0161] The remaining qubit lines (horizontal lines) correspond to intermediate qubits. Generally, the term "intermediate qubit" or "internal qubit" refers to a two-state quantum system used to describe a quantum circuit that does not correspond to either an input qubit or an output qubit (state). In other words, an intermediate qubit is a qubit (e.g., a virtual qubit) between two (off-diagonal) quantum gates in a quantum circuit (or within it). However, only off-diagonal quantum gates can introduce new, unique qubit states, thus introducing new intermediate qubits. In other words, if a given qubit is in state |0> or |1> before a diagonal quantum gate, then that given qubit is in the same state after the diagonal quantum gate (only the phase of that state may have changed). Therefore, if two indices... and Corresponding to the same qubit state.

[0162] For example, in Figure 7 In the middle, marked as The line corresponds to the one marked as The same intermediate qubit as the line is labeled as and The line corresponds to the one marked as The same intermediate qubit as the line. Similarly, the line and Corresponding to and marked as The same intermediate qubits are connected in the same way, and so on.

[0163] Furthermore, the box marked H represents the Hadamard gate, which is an off-diagonal single-qubit gate; the box marked X... 1 / 2 The box represents X 1 / 2 The gate is an off-diagonal single-qubit gate; denoted as y. 1 / 2 The box represents Y 1 / 2 The gate is an off-diagonal single-qubit gate; and the box labeled T represents the T-gate (also known as the π / 8 gate), which is a diagonal single-qubit gate.

[0164] Finally, each pair of points connected by a vertical line (labeled cZ) represents a controlled Z-gate, which is a diagonal two-qubit gate. The two qubit lines connected by the cZ gate are the qubits to which the cZ gate operates. Here, one of these qubits (e.g., the upper qubit) is the control qubit, and the other qubit is the target qubit to which the Z-operation can be performed based on the state of the control qubit.

[0165] Figure 8 (a) through (d) illustrate exemplary representations of a diagonal single-qubit gate, an off-diagonal qubit gate, a diagonal qubit gate, and an off-diagonal two-qubit gate, respectively. Therefore, Figure 8 (a) to (d) correspond to the generic expression U mentioned above, respectively. d1 U n1 U d2 and U n2 . Figure 8 The corresponding left side shows an exemplary representation that can be used for quantum circuit schematics, while the corresponding right side shows an exemplary representation that can be used for graphical models.

[0166] As can be seen, in the graphical model, the qubits of a quantum gate are represented as vertices, and the vertices corresponding to the qubits of a quantum gate are represented as a clique. For example... Figure 8 As shown, corresponding to quantum gate U xx The (all) edges of the clique correspond to the tensor of the quantum gate. In other words, typically, for each quantum gate of a quantum circuit, the vertices of the nonstring graph corresponding to the qubit of that quantum gate form a clique.

[0167] It should be noted that, correspondingly, for each quantum gate of a quantum circuit, there can exist a corresponding tensor of a tensor network. For each qubit in the quantum gate that serves as an intermediate qubit or in an indicator subset (as an indicator qubit), the tensor can have an index corresponding to that qubit. This invention is not limited to any particular quantum gate representation. Quantum circuits can generally be represented by basic gates and composite gates comprising one or more basic gates.

[0168] Figure 9 It shows the corresponding Figure 7 The diagram shows a graphical model of a quantum circuit. It can be seen that each non-equivalent qubit state has a vertex. In other words, each (unique) qubit in a quantum circuit has a vertex. It should be noted that the term "qubit of a quantum circuit" usually refers to the input qubit, output qubit, and intermediate qubits (within the quantum circuit).

[0169] As mentioned above, graphical models offer a more economical representation of angular quantities and reduce computation in terms of evaluating expressions. However, to date, graphical model-based methods have primarily been applied to evaluating single magnitudes at a time.

[0170] In view of the above, the object of the present invention is to efficiently evaluate / compute any sub-tensor (e.g., any subset of entries / amplitudes) of the amplitude tensor of the circuit matrix of a quantum circuit based on a graphical model.

[0171] It should be noted that the term "subtensor" typically refers to a tensor from which data can be extracted by setting the index of the corresponding tensor to 0 or 1. or A tensor obtained from a quantum circuit. Therefore, for each index set in this way, the state of a specific input or output qubit of the quantum circuit is specified. Thus, in other words, the entries of a sub-tensor of a tensor are subsets of the entries of the tensor.

[0172] It should also be noted that if the initial state |φ> corresponding to |ψ> is a basis vector for computing the basis, then Actually, it's a circuit tensor. The subtensor of the quantum bit system. Therefore, this invention is particularly helpful for efficiently computing the corresponding magnitude tensor given the initial state |φ> of the quantum bit system. Any subtensor (|φ>).

[0173] Therefore, according to a first embodiment, an apparatus for simulating a quantum circuit is provided. The apparatus further includes processing circuitry for receiving an indication of a subset of qubits, the qubits being the input and output qubits of the quantum circuit. The indication subset corresponds to an amplitude tensor of the quantum circuit to be determined, wherein the amplitude tensor includes the amplitudes of different state combinations of the qubits in the indication subset. The processing circuitry is further configured to determine an optimal elimination order of intermediate qubits within the quantum circuit using a tensor network of the quantum circuit and a restricted maximum cardinality search (RMCS). Furthermore, the processing circuitry is configured to determine the amplitude tensor by sequentially deleting the indices of the tensors of the tensor network corresponding to the intermediate qubits from the tensor network according to the elimination order.

[0174] Furthermore, according to a second embodiment, a method for simulating a quantum circuit is provided. The method includes the steps of: receiving an indication of a subset of input and output qubits of a quantum circuit, the indicated subset corresponding to an amplitude tensor of the quantum circuit to be determined, the amplitude tensor including the amplitudes of different state combinations of the qubits of the indicated subset. Furthermore, the method includes the step of: determining an elimination order of intermediate qubits within the quantum circuit using a tensor network of the quantum circuit and a restricted maximum cardinality search (RMCS). Furthermore, the method includes the step of: determining the amplitude tensor by sequentially deleting the indices of the tensor network corresponding to the intermediate qubits from the tensor network according to the elimination order.

[0175] Furthermore, according to a third embodiment, a computer program product is provided, including instructions stored on a non-transitory storage medium. When the computer program is executed in one or more processors, it performs the method described according to a second embodiment.

[0176] Figure 10 An exemplary implementation of such a device 1000 is shown, which includes processing circuitry 1050. Processing circuitry 1050 may include a functional portion 1060 for simulating quantum circuitry.

[0177] A device can simulate a subset of the amplitude of a quantum circuit, for example, by partially shrinking a tensor network. Here, the simulation can represent the computation of a quantum circuit (e.g., the circuit tensor described above). ( ) one or more entries of the magnitude tensor.

[0178] In this implementation, the amplitude tensor can be the circuit tensor of a quantum circuit. The sub-tensor of the quantum circuit can be determined by partially shrinking the tensor network of the quantum circuit (in other words, the tensor network representing the quantum circuit).

[0179] If multiple amplitude senses of a circuit tensor are determined at once (e.g., in combination), such partial contractions occur during circuit simulation.

[0180] For example, considering a 4-qubit quantum circuit, one might be interested in calculating the probabilities / amplitudes of qubit strings b1 = 0001 and b2 = 1001 (with a different first qubit) in a single pass of the simulator (used). In other words, the interest lies in determining the amplitudes of the output qubits in states 0, 0, 0, and 1, and in determining the amplitudes of the output qubits in states 1, 0, 0, and 1. It should also be noted that in this example, the indicator subset includes a single qubit, i.e., the first qubit. The basis vectors corresponding to the two qubit strings are:

[0181]

[0182]

[0183] Then, vector e can be processed column by column. 0001 and e 1001 Stack them into a matrix, then combine the two vectors into a single expression:

[0184]

[0185] The amplitudes of b1 and b2 can be calculated similarly to the single-amplitude method:

[0186] σ λ =[σ 1001 σ0001 ]= <E λ |C|ψ>.

[0187] Here, the index λ represents the amplitude addressed in the two amplitudes. The above expression is equivalent to a partial contraction of the tensor network (summing over all indices except λ). This parameter can be followed to include all qubit strings that differ by 2, 3, or more qubits, up to all qubits in the circuit. Any subset of amplitudes can be computed in a similar manner, up to the complete state.

[0188] Typically, one might focus on determining an amplitude tensor (and vice versa) that corresponds to an arbitrary subset (e.g., an indicator subset) of the input qubits and / or output qubits. This amplitude tensor corresponds to the indicator subset as described below.

[0189] Here, it should be noted that, generally, (i) the terms “amplitude tensor corresponding to the indicator subset”, “amplitude tensor belongs to the subset” and “subset tensor” are used interchangeably; (ii) qubits in the indicator subset are also called indicator qubits; (iii) input qubits and output qubits that are not in the indicator subset are also called complementary qubits; and (iv) a set of complementary qubits is also called a complementary subset.

[0190] Typically, it is assumed that the index of a subset of tensors with values ​​of 0 and 1 can correspond one-to-one with the indicated qubit.

[0191] Furthermore, the subset tensor can correspond to a specific state of the complementary qubit. Typically, for each complementary qubit, this specific state can be predefined, predetermined, or indicated (e.g., along with an indicator subset). For example, the subset tensor can correspond to an input state where all input qubits are in the |0> state. The entries of the subset tensor can be amplitudes corresponding to the specific states of the complementary qubits. Furthermore, for each combination of index values, the corresponding entry of the subset tensor can be an amplitude corresponding to: (i) the complementary qubit in the corresponding specific state, and (ii) the indicator qubit in the state corresponding to the combination of index values. The subset tensor can be a circuit tensor. The subtensors and / or can be represented by each index (index i1, ..., i) corresponding to the complementary qubits according to the specific state of the corresponding complementary qubits. N and j1, ..., j N One of the states is set to 0 or 1 to obtain the qubit from the circuit tensor. For example, in the example above, when the specific state of all input qubits is the |0> state, it is possible

[0192] The advantage of using RMCS to determine the elimination order of intermediate qubits (or the shrinking order of tensor network indices) is that any subset of amplitudes from a single amplitude to the full state vector can be evaluated with minimal / minimized possible requirements in terms of memory and / or processor cycles of a single processor. In other words, the quantum circuit simulator according to the invention simulates multiple amplitudes in a single pass of the algorithm (e.g., jointly). Thus, a novel feature of the simulator is the ability to solve for any subset of amplitudes (up to the full state vector) in a single pass. Furthermore, this approach is readily parallelizable [4].

[0193] Typically, multiple magnitudes can be solved by partially shrinking the corresponding tensor network (instead of summing all variables in the expression). However, compared to single-magnitude methods, it is currently unknown how to choose a suitable summation order to achieve minimum / minimized computational cost, and no multi-magnitude / full-state simulator has been created.

[0194] More specifically, if during tensor network shrinkage, the process stops before summing all variables in the sequence, the result will be partial shrinkage of the network. Suppose in the example above, the optimized elimination sequence is found to be π = [ijklmn], i.e. Figure 5 The elimination sequence is shown.

[0195] It should be noted that the optimized elimination sequence π = [ijklmn] is not the optimal elimination sequence, i.e., it has the minimum possible intermediate tensor. For example, the elimination sequence μ = [jiklmn] has no intermediate tensor with rank 3, so its complexity is lower than that of calculating the rank 3 tensor in step (1). The elimination sequence is π = [ijklmn].

[0196] If the sequence π = [ijklmn] is followed and all variables before [mn] in the expression are shrunk, the result is a partial shrinkage of the tensor network:

[0197]

[0198] However, to perform arbitrary partial shrinkage, the elimination sequence needs to be transformed without increasing the size of the intermediate products. That is, if a set of variables needs to be excluded from the summation, a new elimination sequence needs to be found to place this set of variables at the end.

[0199] In other words, we might focus only on the amplitude corresponding to a specific external (input / output), for example, the k-th qubit in state |0> or |1>. These external qubits correspond to (e.g., are) complementary qubits. Then, we can use the formula...

[0200]

[0201] The index i corresponding to the k-th external qubit k or j k Set to a value of 0 or 1, corresponding to the stated state. Since each index of the external qubit has a Dirac delta function (or, more precisely, Kronecker-delta), the corresponding Boolean variable... or Summation becomes simple because it corresponds to setting the corresponding Boolean variable in the tensor network to 0 or 1 (thus removing the index as a degree of freedom). Furthermore, the vertices corresponding to such qubits can be removed from the graphical model.

[0202] Therefore, typically, indices corresponding to input qubits or output qubits not in the indicator subset are removed from the tensor network by setting the index to the corresponding predetermined value. Furthermore, indices corresponding to intermediate qubits can be removed from the tensor network by shrinking. Advantageously, indices corresponding to complementary qubits are removed from the tensor network before removing the indices corresponding to intermediate qubits.

[0203] In principle, the indices / vertices of complementary qubits can be deleted at any time. However, it is advantageous to delete them as early as possible, as this reduces the complexity of further operations. Alternatively, a tensor network and / or graphical model can be constructed after the set of complementary qubits is known. In this case, it is not necessary to first introduce the indices / vertices corresponding to the complementary qubits.

[0204] In any case, it is advantageous that the graph tensor network on which the optimized elimination order is determined by RMCS is based has no vertex indices corresponding to complementary qubits.

[0205] Therefore, typically, each intermediate qubit can uniquely correspond to a corresponding index of the tensor. Furthermore, each qubit in the indicator subset can uniquely correspond to a corresponding (unique) index of the tensor, and each index of the tensor can uniquely correspond to an input qubit, an output qubit, or an intermediate qubit.

[0206] As described below, "each A uniquely corresponds to B" means that two different A's will not correspond to the same B. It should also be noted that if the indices of complementary qubits are not removed from the tensor network, a one-to-one correspondence can exist between the qubits (internal and external) of the quantum circuit and the unique indices of the tensor network.

[0207] On the other hand, if the index of the complementary qubit has been removed from the tensor network, there may be a one-to-one correspondence between the non-complementary qubit (i.e., the indicator or internal qubit) and the unique index of the tensor network.

[0208] Furthermore, there is typically a one-to-one correspondence between the vertices of a graph representing a tensor network (of a quantum circuit) and the indices of the tensors corresponding to the intermediate qubits or the qubits in the indicator subset.

[0209] It should be noted that this is particularly possible if the vertex corresponding to the complementary qubit has been removed from the graph. Furthermore, if the index corresponding to the complementary qubit has been removed from the tensor network, a one-to-one correspondence may exist between the unique index and the vertex. It should also be noted that if the index corresponding to the complementary qubit has not been removed from the tensor network, and the vertex corresponding to the complementary qubit has not been removed from the graph, a one-to-one correspondence may also exist between the vertex and the index.

[0210] It should also be noted that, advantageously, complementary qubits are removed from the graphical model / tensor network before determining the optimal elimination order of complementary qubits.

[0211] Furthermore, typically, if the index corresponding to the complementary qubit is not removed from the tensor network representing the quantum circuit, a one-to-one correspondence may exist between the unique index of the tensor network and the qubit of the quantum circuit. For example, Figure 9 The vertices of the graph and Figure 7 There is a one-to-one correspondence between the qubits of the quantum circuit shown. On the other hand, if the index corresponding to the complementary qubit has been removed from the tensor network (or was not included in the tensor network in the first place), then there may be a one-to-one correspondence between the unique index of the tensor network and the qubit of the quantum circuit corresponding to the indicated qubit or internal qubit.

[0212] In summary, for indicated qubits, the magnitudes of their states |0> and |1> are typically of interest. Therefore, the index / vertices of the indicated qubits cannot be removed from the tensor network / graphical model (in particular, because one of the two states of the indicated qubit must be chosen to solve for the corresponding Kronecker-Dirac equation). Thus, to calculate the magnitudes... One or more of the internal qubits are shrunk, but all internal qubits are not shrunk. However, the indicated qubits still appear as degrees of freedom in the tensor network, thus affecting computational complexity.

[0213] Therefore, when determining the optimal elimination sequence for the internal qubits—that is, the elimination sequence that minimizes (in a sense) computational resources and / or memory requirements—the indicated qubits must be taken into account. This can be accomplished by determining the optimal elimination order for both the internal and indicated qubits, which is constrained by the position of the indicated qubit at the end of the elimination sequence.

[0214] According to the present invention, the optimal / optimized elimination sequence for any amplitude subset can be obtained using RMCS. One method for obtaining the elimination sequence based on RMCS is a chord graph-based algorithm, which is explained further below.

[0215] In this regard, it's important to clarify that, generally speaking: a chord graph is a graph in which every cycle with four or more vertices has a chord; a chord is an edge that is not part of a cycle but connects two vertices of the cycle; a cycle is a non-empty sequence of mutually distinct edges connecting a sequence of vertices, where the only repeated vertices in the sequence are the first and last vertices (in other words, the first and last vertices of the sequence are the same, and all other vertices are distinct and different from the first / last vertex). In other words, a chord graph is a graph that does not contain cycles with more than 3 nodes.

[0216] The elimination order can be determined iteratively in reverse order. This can be done by selecting, at each step of the iteration, an intermediate qubit that was not selected in any previous step of the iteration. In the string diagram representing the tensor network, the selected intermediate qubit also corresponds to a vertex that is adjacent to the intermediate qubit selected in any previous step of the iteration, or the vertex indicating the maximum number of vertices corresponding to the qubits in the subset.

[0217] In this way, given a chord diagram and the (indicator) subset of nodes (As input) it is possible to establish a perfect elimination order as long as a clique exists in C (e.g., nodes in C form / are a clique). So that S is in At the end of the text. It should be noted here that a perfect elimination order is generally an elimination order in which the neighbors of the vertex with the higher number (e.g., later than the vertex being eliminated) form a clique for each vertex. Typically, a graph has a perfect elimination order if and only if it is a chord graph.

[0218] Furthermore, due to the elimination order It is a string diagram The perfect elimination order, if If the largest clique in the sequence has a size of K+1, then it appears in the elimination sequence. The maximum rank of the intermediate tensor in the chord graph is K. In other words, if the chord graph... If the largest clique in the sequence has a size K, then the order of the largest virtual tensor in the elimination sequence is also K.

[0219] Now refer to the pseudocode description below to build the 1070 elimination order using RMCS. Exemplary implementation:

[0220]

[0221] As can be seen, for each node in graph H, a counter (represented as cardinality(v) in pseudocode) is introduced to store the number of neighbors that the node has enumerated.

[0222] First, all nodes in C are enumerated in arbitrary order, and the counters on all their neighbors are updated (lines 2 and 3). In other words, lines 2 through 4 of the pseudocode initialize the function cardinality(v) by setting the value of the function to 0 for each node: V → {0, 1, 2, 3, ...}. Furthermore, according to line 5, the indicator subset C of the nodes is removed from the set of vertices V.

[0223] Then, there exists a loop with a loop variable `i` that executes lines 7 through 16, a total of |V| times (because, according to line 6, `i` runs from `i = |V|` to `i = 1`, running once for each vertex of H). During each execution of the `i` loop, a vertex of H is selected / picked (executed in line 8 or 10). Since the selected vertex is also removed from the corresponding set (lines 8 and 11), it is impossible to select a vertex twice; therefore, each vertex is selected only once.

[0224] Based on lines 7 and 8, nodes in subset C are selected first. In other words, the i-loop must execute |C| times before selecting any other nodes, and each node in subset C is selected only once. Due to the sequence... They are constructed in reverse order, so these nodes will be located in the sequence. The end of.

[0225] Based on lines 9 through 12, select the node with the maximum number of enumerated neighbors (in other words, the maximum cardinality) and assign it the next number. Typically, connections can be arbitrarily broken. In other words, if two or more vertices have the same cardinality, any one of those two or more vertices can be selected.

[0226] According to line 13, the node selected in the current execution of the loop (line 8 or line 10) will be added to the elimination order. In (in) (the i-th position).

[0227] Based on lines 14 through 16, update the counters on all neighboring nodes. In other words, nodes that have not yet been selected (e.g., not yet added to) The counter / base of the selected vertex's neighbors is incremented by 1.

[0228] Elimination order It will be a chord graph with a subset C at the end. The perfect elimination order.

[0229] The algorithm described graphically is as follows: Figure 12 As shown. Figure 12 As shown in the shaded ellipse in the first two figures of (a) and (b), in this example, the subset 1200 consisting of the two upper vertices is the indicator subset C. Figure 12 All figures (a) through (g) show the same chord diagram. As a subset C, it serves as the input to the process. The goal is to construct... Elimination order This is so that nodes in the vertex indicator subset are placed at the end.

[0230] Figure 12 The letters in the vertices shown in (a) are Figure 12 In the following description, "vertices" are used to refer to vertices. It should be noted that each of steps S1210, S1220, S1230, S1240, S1250, and S1260 can correspond to one execution of the above pseudocode loop. Furthermore, in Figure 12 In the diagram, white numbers on a black background indicate the assigned position of the corresponding vertex in the elimination sequence, while black numbers on a white background indicate the current cardinality of the corresponding vertex.

[0231] Specifically, in step S1210, vertex i is selected. It should be noted that the selection of vertex i in step S1210 is arbitrary. Alternatively, vertex j can be selected instead of vertex i, which will produce a perfect elimination sequence where vertices i and j are also at the end. An elimination sequence is then assigned to vertex i. The cardinality of the 6th position in the matrix is ​​increased by 1 for its unselected neighbors (i.e., vertex jkl).

[0232] In step S1220, since vertex j is the only vertex in the indicator subset that has not yet been selected, vertex j is selected. An elimination sequence is then assigned to vertex j. The cardinality of the 5th position in the matrix is ​​increased by 1 for its unselected neighbors (i.e., vertex kl).

[0233] In step S1230, since vertex k has the largest cardinality of 2 among the unselected vertices (i.e., vertices klmn), vertex k is selected. An elimination sequence is assigned to vertex k. The cardinality of the fourth position in the equation is increased by 1 for its unselected neighbors (i.e., vertices lm). It should be noted that in this step, it is also possible to choose vertex l, which has the same maximum cardinality of 2 as vertex k, instead of vertex k. In this case, the cardinality of all remaining vertices kmn is increased by 1.

[0234] In step S1240, vertex l is selected because it is the only vertex with the largest cardinal number 3 among the vertices that have not yet been selected (i.e., vertices lmn). An elimination sequence is then assigned to vertex l. At the third position in the equation, the cardinality of the unselected neighbors of vertex l (i.e., vertex mn) is increased by 1.

[0235] In step S1250, since vertex m is the only vertex with the largest cardinal number 2 among the unselected vertices (i.e., vertices m and n), vertex m is selected, and an elimination sequence is assigned to vertex m. The second position in the equation, and the cardinality of the unselected neighbors of vertex l (i.e., vertex n) is increased by 1.

[0236] In step S1260, the only remaining vertex, vertex n, is selected and an elimination sequence is assigned to it. The first position in the sequence. Therefore, a total of the eliminated sequences were obtained.

[0237] Now combine Figure 13 Description of using RMCS to build 1370 elimination order Another exemplary implementation.

[0238] As before, Figure 13 The input to the process is a chord diagram. and vertex subset The output of this process is a sequence of eliminated vertices. Therefore, it can be used to obtain the elimination sequence of the internal qubits of a quantum circuit, which is optimized for joint calculation of the magnitude corresponding to the indicator subset C.

[0239] First, in step S1310, the loop variable is set to i = |V| - |C|, and a set including all vertices that still must be selected is introduced. It should be noted that, typically, i can be... The replacement is therefore introduced only for clarity.

[0240] In step S1320, for all vertices that still need to be selected ( For all w), update the cardinality of the vertices to . Where N(w) is the set of neighbors of w, and ∧ represents logical AND. That is, the cardinality of vertex w is set to the number of non-necessary neighbors of that vertex, which is the number of neighbors already selected in the subset C or in the previous execution of the loop. It should be noted that if i ≠ |V| - |C|, the cardinality of all vertices that still need to be selected, as well as the cardinality of the unselected neighbors of the vertex, can be updated by incrementing (e.g., by 1). For example, for all We can set c(w) = c(w) + 1.

[0241] In step S1340, (arbitrarily) select the vertex v with the largest cardinality among the vertices that still need to be selected. In this step, the mathematical expression for the set of vertices from which vertex v is selected is given as follows: in, It is a mathematical expression for "all".

[0242] It should be noted that steps S1320 and S1340 can be performed directly from the set. Choose vertex v to combine.

[0243] In step S1350, the selected vertex is added to the i-th position in the elimination sequence.

[0244] In step S1360, it is checked whether all vertices in H that are not in the indicated subset (i.e., included in the elimination order) have been selected. In this example, this is done by checking if i = 1. Alternatively, for example, a condition could be checked. If i = 1 ("Yes" in S1360), then the process eliminates the current sequence. This concludes the output. It should be noted that the elimination sequence can be achieved by adding vertices of C in any order to the end of π. Obtain the perfect elimination order of all vertices of H. Otherwise ("No" in S1360), after executing step S1380, decrement the loop variable i (i = i-1) and remove the currently selected vertex from the set of vertices that must be selected. Use the updated loop variable i and vertex set Repeat steps S1320, S1340, S1350, and S1360.

[0245] The above process requires inputting a diagram. It is a string diagram. However, the graphical model, representing the initial diagram G = (V, E) of a quantum circuit, may not be string-like a priori. For example, Figure 9The diagram of quantum circuit 700 shown is not a string diagram.

[0246] Generally, any graph can be transformed into a chord graph by adding edges. To obtain a chord graph from G = (V, E). It may be necessary to add edges to graph G, which is also known as the chord graph completion of G. Therefore, as already noted, although the vertices of graph G and its chord graph completion H are the same, the vertices of G are typically only a subset of the vertices of its chord graph completion H, i.e. Typically, the chord graph completion of a non-chord graph is not unique. In particular, different chord graph completions of the same non-chord graph may have different tree widths (e.g., there are always various completions by connecting each vertex to the others).

[0247] Therefore, it is advantageous that the chord graph representing the tensor network is the chord graph completion of the non-chord graph, which represents the tensor network having a minimum / minimized maximal clique in the chord graph completion of the non-chord graph.

[0248] In particular, it is advantageous to obtain a chord graph representing a tensor network from a non-chord graph using an optimized elimination order of the non-chord graph vertices. Specifically, the chord graph can be obtained by adding edges to the non-chord graph such that for each vertex, all neighbors of vertices later than that vertex in the optimized elimination order form a clique.

[0249] This chord graph construction ensures that the complexity of finding the perfect elimination order is not changed. When a vertex is removed from the graph, the same edge is added. This process does not change the tree width due to the construction, because the edges are introduced anyway during elimination.

[0250] Generally, any elimination sequence π can be used to construct a chord graph H from a given graph G, which is also called a filled graph of G relative to π. For example, this can be done by following the elimination sequence π, but instead of eliminating nodes and connecting their neighbors to the clique, only connecting the nodes' later neighbors in the elimination sequence π. It should be noted that this operation adds essentially the same edges to the graph as the original node elimination π, but the nodes are not removed from the graph. It should also be noted that by adding these edges to the graph, a chord graph is formed, and the elimination sequence π will be a perfect elimination sequence for the resulting chord graph. For example, this can be done using the pseudocode shown below:

[0251]

[0252] In particular, according to line 2 of the pseudocode, all edges of the input graph are also provided to the output graph H.

[0253] Between lines 4 and 13 of the pseudocode, there is a loop with a loop variable `i` that runs from `i = 1` to `i = |V|` according to line 3. In other words, the loop is executed once for each vertex in the elimination sequence. The following steps are performed during one execution of the loop. It should be noted that in the last two executions of the `i` loop, no edges are added to the graph H. In other words, the loop variable `i` can run only from `i = 1` to `i = |V| - 2` without changing the output graph H.

[0254] In line 4 of the pseudocode, the next node in the elimination sequence is determined (hereafter referred to as the current node). Furthermore, according to line 5, an auxiliary set U is defined and initialized / reset to an empty set.

[0255] Then, according to lines 6 through 10 of the pseudocode, all neighbors of the current node that are later than the current node in the elimination sequence (line 7) (line 6) are included in the auxiliary set of vertex U (line 8).

[0256] Subsequently, according to lines 11 through 13 of the pseudocode, the vertices in U are made into a clique. More specifically, for each pair of (distinct) vertices (line 11), the edge set of H is ensured. Including edges.

[0257] The obtained graph (After executing loop |V| times) is a chord graph. Furthermore, if the rank of the largest intermediate tensor in the elimination sequence π is K, then the corresponding chord graph... The largest clique in the sequence π is K+1. In other words, if the order of the largest dummy tensor in the eliminated sequence π is K, then the largest clique in the corresponding chord graph is also K.

[0258] It should also be noted that, therefore, eliminating sequence π and The order of the largest virtual tensor is the same, therefore the elimination sequence π and The computational complexity is the same. In other words, due to the constructed sequence It has the same complexity as the elimination sequence π used to construct the chord graph H, therefore the above explanation... The construction does not increase computational complexity. Therefore, eliminating the sequential π can be viewed as a sequence. The input for construction (along with the non-chord graph G), is a sequence. The computational complexity of the constructed sequence is the same as that of π, and the specified subset of vertices is placed at the end. This is independent of the computational complexity of the sequence π, especially since it holds true regardless of whether the optimized elimination order π is the optimal elimination order. In fact, as mentioned above, since finding the optimal elimination order is an NP-hard problem, in practical applications, π is often not the truly optimal elimination order, but only some approximation (also referred to here as the optimized elimination order). Then, the constructed sequence It will be optimized to the same extent as or as optimally as the elimination order π used to obtain the chord graph H.

[0259] In the following text, combined with Figure 11 The above pseudocode is illustrated using the elimination sequence π = [ijklmn]. This elimination sequence is... Figure 4 The known elimination sequences. More specifically, Figure 11 China follows and Figure 4 The same sequence in the middle.

[0260] Specifically, steps S1110, S1130, S1150, S1170, and S1190 correspond to the first to fifth executions of lines 4 to 13 of the pseudocode, respectively. The last execution of the loop, which can be omitted in any case, is not included. Figure 11 As shown in Figures (a) through (f), vertices in the elimination sequence that are later than the current vertex in the last step are represented by black labels on a white background; other vertices have white indices on a black background.

[0261] In step S1110, it is ensured that the later neighbor of the current vertex i in the elimination sequence (i.e., vertex jkl) is a clique. Because in Figure 11 Since there is no edge connecting vertices j and l in (a), edge 1120 connecting vertices j and l is added. Figure 11 In the figure of (a), thus producing Figure 11 The figure shown in (b) is as follows.

[0262] In step S1130, it is ensured that the current vertex j's later neighbor (i.e., vertex kl) in the elimination sequence is a clique. Because in Figure 11 The graph in (b) already has edges connecting these vertices, so no additional edges need to be added, and therefore... Figure 11 (b) and Figure 11 The diagram shown in (c) is the same.

[0263] In step S1150, it is ensured that the latest neighbor of the current vertex k in the elimination sequence (i.e., vertex lm) is a clique. Because in Figure 11 (c) does not have an edge connecting vertices l and m, therefore add edge 1160 connecting vertices l and m. Figure 11 In the figure of (c), thus producing Figure 11 The figure shown in (d) is a diagram.

[0264] In step S1170, it is ensured that the current vertex l's later neighbor in the elimination sequence (i.e., vertex mn) is a clique. Because in Figure 11 The graph in (d) already has edges connecting these vertices, so no additional edges need to be added, and therefore... Figure 11 (d) and Figure 11The diagram shown in (e) is the same.

[0265] In step S1190, it is ensured that the later neighbor of the current vertex m in the elimination sequence (i.e., vertex n) is a clique. However, as mentioned above, since there is only one vertex later than vertex m in the elimination sequence, no vertex is ever added in this step. Therefore, Figure 11 (e) and Figure 11 The diagram shown in (f) is the same. It can be seen that... Figure 11 The diagram obtained in (f) is a chord diagram.

[0266] Now combine Figure 14 Describe another exemplary implementation of constructing a chord graph H from the graph using the elimination sequence π.

[0267] Steps S1420, S1460 and S1450 essentially implement a frame with a loop variable i, and step S1440 is executed in the i loop.

[0268] Specifically, in step S1420, the loop variable is initialized to i = 1, and all edges of graph G are also provided to the graph.

[0269] In step 1460, check the exit condition of loop i (i = |V| - 2?). If i = |V| - 2 (yes in step 1460), then the construction of the chord graph H is complete. Specifically, the current edge set... It is a string diagram The edges. If i ≠ |V|-2 ("No" in step 1460), the construction of the chord graph continues to step S1450. Therefore, S1440 is performed once for each i ∈ {1, ..., |V|-2}.

[0270] In step S1450, the loop variable is incremented by only 1 (i = i + 1). Then, step S1440 is executed (again).

[0271] In step S1440, the edge is added to the edge set. In the given information, for all the following vertices x and y:

[0272] (a) as the elimination sequence ("x, y∈N((π) -1 The neighbors of the i-th vertex in (i))”)

[0273] (b) mutually distinct vertices (“x≠y”), and

[0274] (c) The i-th vertex in the elimination sequence π (“π(x)>i∧π(y)>i”, where “∧” is usually a logical AND) is eliminated later.

[0275] In the (updated) edge set There is an edge (x, y).

[0276] Figure 15 It shows Figure 14 A more detailed exemplary implementation of step S1440. More specifically, according to Figure 15 Step S1440 may include step S1560, in which an auxiliary subset U is determined, which is the set of neighbors ("w∈N(π)) of the i-th vertex in the elimination sequence. -1 (i))″) and vertices w that are later than the i-th vertex ("π(w)>i"). For example, this step can be implemented as in lines 5 to 10 of the pseudocode above for "constructing a chord graph according to the elimination order", corresponding to Figure 16 The implementation shown.

[0277] Step S1440 may also include step S1580, which is performed after step S1560, in which the edge is added to the edge set. In the (updated) edge set, for all vertices x and y (x, y ∈ U) in the auxiliary subset U that are mutually distinct vertices ("x ≠ y"), the edge set... There is an edge (x, y).

[0278] For example, this step can be implemented as in lines 11 through 13 of the pseudocode above used for “constructing a chord graph according to the elimination order”.

[0279] Using an optimized elimination order, the advantage of obtaining a chord graph H representing a quantum circuit from a nonstring graph G is that chord graph H will have a minimized maximal clique in the chord graph completion of the nonstring graph. In other words, the resulting chord graph H will be the chord graph completion of G with the minimized tree width in the chord graph completion of G.

[0280] Figure 17 Exemplary method steps of a method that can be performed by device 1000 are shown. The process outlined below enables efficient partial tensor network shrinkage to simulate multiple amplitudes of a quantum circuit in a single pass (jointly).

[0281] First, in step S1700, a subset of vertices of graph G can be obtained. Indication. For example, an indication of a subset of qubits can be obtained, said subset being a subset of the external qubits of the quantum circuit. Hereafter, as further explained below, it is assumed that... It is non-chordal and can be called a non-chordal graph.

[0282] Then, in step S1710, a graph G = (V, E1) representing the quantum circuit to be simulated can be obtained / received. Alternatively, the graph G = (V, E1) can be generated / determined, for example, based on a given / received tensor network expression. Or, or additionally, a graph G encoding a tensor network representing the quantum circuit can be created / generated first. Then, an amplitude expression (e.g., a tensor network) can be constructed as described above. Then, a graph G corresponding to the amplitude expression can be constructed using the known algorithms in [3], [4]. The result is a graph G, where nodes represent variables and cliques represent tensors in the tensor network. In particular, since there is a transitive one-to-one correspondence between vertices, indices, and qubits of the quantum circuit, subset C can be interchangeably referred to as a subset of vertices, indices, and qubits.

[0283] Typically, nonstring graphs represent tensor networks. This can be determined based on the indicator subset C. Specifically, the non-chord graph can be determined. Make non-chord graph There is a one-to-one correspondence between the vertices and the indices of the tensors corresponding to the intermediate qubits or the qubits in the indicator subset.

[0284] Furthermore, the non-chord graph can be determined. Such that for each tensor of the tensor network, there is a nonstring graph corresponding to the tensor. The vertex is a clique. In other words, steps S1710 and S1720 can be merged.

[0285] For example, the nonstring graph representing a tensor network can be determined based on the indicator subset C and the general nonstring graph U representing the tensor network. More specifically, for each input or output qubit in the indicator subset C (i.e., for each indicated qubit), a single vertex corresponding to that qubit can be added to the vertices of U. Furthermore, for each indicated qubit, edges can be added such that for each quantum gate of the quantum circuit, the vertices of the nonstring graph corresponding to that quantum gate's qubit form a clique. Moreover, there is a one-to-one correspondence between the vertices and intermediate qubits of the universal nonstring graph U. For example, it consists of vertices and edges entirely within the shaded region. Figure 9 The subgraph is this general graph U, in order to obtain Add the vertices and edges corresponding to the indicated qubits to U.

[0286] Alternatively, it can be based on the indicator subset C, according to the general nonstring graph representing the tensor network. Determine the nonstring graph representing the tensor network. More specifically, for each input or output qubit not in the indicator subset (i.e., for each complementary qubit), all edges connecting the vertices corresponding to the qubit, and all vertices corresponding to the qubit can be accessed from... Deleted. Additionally, the general nonchord diagram... There is a one-to-one correspondence between the vertices of a quantum circuit and the qubits of a quantum circuit, where each qubit of a quantum circuit is either an input qubit, an output qubit, or an intermediate qubit. In other words, There is a one-to-one correspondence between the vertices of a quantum circuit and the qubits of a quantum circuit; the qubits of a quantum circuit are indicative, complementary, and intermediate qubits. For example, Figure 9 The entire diagram shown is this type of general diagram. In order to obtain From Remove vertices and edges corresponding to unindicated (i.e. complementary) qubits.

[0287] For example, in steps S1700 and S1710 above, the quantum circuit can be read, and the user can select the set of (external) qubits requiring all amplitudes. In other words, the user can select the subset C of nodes corresponding to the non-shrinking index. It should also be noted that the order of steps S1700 and S1710 can be interchanged, or the two steps can be performed simultaneously.

[0288] Then, step S1750 is performed, in which the elimination order of the intermediate qubits within the quantum circuit is determined using the tensor network and RMCS of the quantum circuit. Alternatively, the elimination order can be determined. However, there is an indicated set of nodes C at the end. Step S1750 may include steps S1720, S1740, S1760, and S1770. Furthermore, if the graph G = (V, E1) and / or tensor network representing the quantum circuit is determined (or modified) in step S1710, then step S1710 may also be considered as part of step S1750.

[0289] Then, in step S1720, edges can be added to graph G such that the vertices corresponding to the indicated qubits form a clique. In other words, if there is no clique in set C, edges are added to form a clique. The result is a graph in C where nodes have cliques. In other words, cliques are introduced at nodes representing / corresponding to variables that will not be eliminated (if the cliques do not already exist). In other words, advantageously, the non-chord graph is used before determining the optimal elimination order π. Modify the non-chord diagram as follows: Edges are added such that the vertices corresponding to the indicator subsets of qubits form a clique. In the original graph G, a clique connecting the vertices of the target subset C corresponding to the qubits is introduced. This produces the graph... It can have a tree width greater than G. It should be noted that if the vertices corresponding to subset C are already a clique of G, step S1720 can be advantageously omitted. In this case, it can use... Perform the following steps.

[0290] Then, in step S1740, the figure can be determined. The optimization eliminates π. It should be noted that, advantageously, if the graph... If the diagram is already a chord diagram, then this step and the next step (i.e., steps S1740 and S1760) are not executed. In this case, steps S1740 and S1760 can be omitted, and after step S1720, the following steps can be used. Perform step S1770. However, in the following text, it is assumed that... It is a non-chord graph.

[0291] Typically, the elimination order π of the vertices of a nonstring graph representing a tensor network can be determined using an optimization process. This process usually minimizes the maximum clique of the corresponding filled graph. The corresponding filled graph is the nonstring graph with respect to the optimized elimination order π. The filled graph. The filled graph can be derived from the non-chord graph in the following manner. Obtain: Anomalous String Graph Edges are added such that for each vertex in the filled graph, all its neighbors (in the filled graph) that are later than that vertex in the optimized elimination order are a clique in the filled graph. Typically, the filled graph is a chord graph. Therefore, in other words, the optimization process can minimize the maximum clique / tree width of the resulting chord graph / filled graph.

[0292] For example, in step S1740, the elimination order π can be determined by calculating the tree decomposition with the minimum tree width (computationally dense part, NP-hard problem). (Figure) The tree decomposition can be solved using any of the many available algorithms and methods. Therefore, obtaining... The optimized elimination order of vertices π. In other words, determining the (optimized) elimination order of the middle qubits typically involves determining the optimized elimination order of (all) vertices V (e.g., relative to...). The elimination order π is optimized (by edge optimization). It should be noted that the optimized elimination order π corresponds to the elimination order of the indicated qubit and the intermediate qubit.

[0293] Typically, the nonstring graph representing a tensor network can be determined. The optimized elimination order π of the vertices minimizes the maximum intermediate tree width (e.g., for ). Elimination order of all λ, max tw (π)≤max tw (λ)). The maximum width of the intermediate tree in the elimination order λ. tw (λ) is the maximum tree width among the tree widths of the intermediate graph corresponding to the elimination order λ. In other words, according to The tree width of all intermediate graphs obtained from the elimination order λ is equal to or less than max. tw (λ)(max tw (λ) is an integer), and at least one of the intermediate graphs has a tree width max. tw (λ). In particular, each intermediate graph corresponding to the elimination order λ can be derived from the non-chord graph in the following way. The result is achieved by sequentially eliminating the vertices corresponding to the first n qubits in the elimination order λ. In other words, in the order v1, v2, ..., v... n from Delete all vertices v i =λ -1 (i), where i ≤ n. Typically, n can be greater than zero and less than the non-chord graph. The number of vertices |V| is an integer. Furthermore, each vertex v can be eliminated in the following way: i From the non-chord diagram Delete the one corresponding to vertex v i All edges of the endpoints; from the non-chord graph Delete vertex v i ; and to the non-chord graph Add an edge such that vertex v i All of its neighbors are connected.

[0294] However, nodes in set C may not be at the end of π. However, as mentioned above, using π from... The obtained chord diagram It can be used as an intermediate product to transform the elimination order π, giving it a specific set of nodes at the end. It is computationally equivalent if any (elimination) sorting of the chord graph nodes (when vertices are removed sequentially and their neighbors are connected) does not introduce new edges and therefore does not increase the size of the maximum clique. Therefore, according to the order π and The evaluation of tensor network shrinkage is computationally equivalent. In other words, the two perfect elimination orders of the graph are computationally equivalent. Thus, according to the present invention, chord graphs can be used to construct equivalent elimination orders for partial tensor network shrinkage using RMCS. In other words, the order π can be transformed using RMCS. Make the node set C located at The end. This new sorting. It is also perfect because any zero-filling elimination sort of a chord graph has the same complexity. Using a chord graph, the target subset C of vertices can be moved to the end of an elimination order with polynomial complexity. The process according to the invention extends the usual MCS algorithm (e.g., as described in [5]) to facilitate the placement of a specified set of nodes C into a sequence. The end of.

[0295] Therefore, in step S1760, the diagram can be used. Constructing / generating chord graphs with π

[0296] Then, in step S1770, using H and C, the perfect elimination order of the vertices of H corresponding to the middle qubit can be determined. The new elimination order This can be determined using the RMCS algorithm. In terms of computational cost and / or memory, this elimination order is relevant for the indicated (external) qubit. This can correspond to an optimized partial shrinking order of the index; a tensor network representation represents a quantum circuit with computational cost and / or memory. It should also be noted that subset C can be appended / added to the elimination order in any order. Furthermore, the resulting elimination order will be the perfect elimination order of H, V→{1, 2, ..., |V|}, and in this sense, the elimination order... It is called perfect.

[0297] Then, in step S1790, the magnitude tensor corresponding to subset C can be determined. For example, a tensor network can be configured according to the order... (For example, using the bucket elimination algorithm) (partial) shrinkage. Shrinkage terminates when all variables not in set C are eliminated from the tensor network.

[0298] Embodiments, such as apparatus 1000 for simulating quantum circuits, and the functions described herein, such as with reference to apparatus 1000, can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, these functions can be stored as one or more instructions or code in a computer-readable medium or transmitted via a communication medium and executed by a hardware-based processing unit. A computer-readable medium may include a computer-readable storage medium corresponding to a tangible medium (e.g., a data storage medium), or any communication medium that facilitates the transfer of a computer program from one place to another according to a communication protocol, etc. In this way, a computer-readable medium can generally correspond to (1) a non-transitory tangible computer-readable storage medium, or (2) a communication medium such as a signal or carrier wave. A data storage medium can be any available medium accessible via one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementing the techniques described herein. Computer program products may include computer-readable media.

[0299] By way of example and not limitation, such computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Furthermore, any connection may be appropriately referred to as a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote resource using coaxial cable, optical fiber, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the definition of medium includes coaxial cable, optical fiber, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave. However, it should be understood that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transient media, but rather refer to non-transient tangible storage media. The disks and optical discs used herein include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs utilize lasers to reproduce data optically. Combinations of the above items should also be included within the scope of computer-readable media.

[0300] Instructions can be executed by one or more processors, such as digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, as used herein, the term "processor" can refer to any of the foregoing structures or any other structures suitable for implementing the techniques described herein. Furthermore, in some aspects, the various functions described herein can be provided within dedicated hardware and / or software modules for encoding and decoding, or incorporated into a combinational decoder. Moreover, these techniques can be fully implemented in one or more circuit or logic elements.

[0301] The techniques of this invention can be implemented in a variety of devices or apparatuses, including wireless mobile phones, integrated circuits (ICs), or a set of ICs (e.g., chipsets). This invention describes various components, modules, or units to emphasize functional aspects of the apparatus used to perform the disclosed techniques, but these do not necessarily need to be implemented by different hardware units. Rather, as described above, the various units can be combined with suitable software and / or firmware within a codec hardware unit, or provided as a collection of interoperable hardware units including one or more processors as described above.

[0302] This invention provides an embodiment for simulating quantum circuits. Specifically, it receives indications of subsets of input and output qubits of the quantum circuit. The indicated subset corresponds to an amplitude tensor of the quantum circuit to be determined, wherein the amplitude tensor includes the amplitudes of different state combinations of the qubits in the indicated subset. Using a tensor network of the quantum circuit and a restricted maximum cardinality search (RMCS), the elimination order of intermediate qubits within the quantum circuit is determined. The amplitude tensor is determined by sequentially deleting the indices of the tensor network corresponding to the intermediate qubits according to the elimination order.

Claims

1. A device for simulating quantum circuits, characterized in that, The device includes a processing circuit (1050) for: Receive (S1700) an indication of a subset of input and output qubits of the quantum circuit, the indicated subset corresponding to the amplitude tensor of the quantum circuit to be determined (S1790), the amplitude tensor including the amplitude of different state combinations of the qubits of the indicated subset; Using the tensor network of the quantum circuit and the restricted maximum cardinality search (RMCS), the elimination order of intermediate qubits within the quantum circuit is determined (S1750); the elimination order is determined iteratively in reverse order by selecting one intermediate qubit from the intermediate qubits in each step of the iteration (S1770), wherein the intermediate qubit is: • Not selected in any preceding step of the iteration; In the chord graph representing the tensor network, a vertex is adjacent to a maximum number of vertices corresponding to the following: ο The intermediate qubit selected in any preceding step of the iteration, or ο The qubits in the indicated subset; The goal of the RMCS is to construct the elimination order of the chord graph so that nodes in the subset of the indicator of the vertices are placed at the end; The magnitude tensor is determined (S1790) by sequentially deleting the indices of the tensors of the tensor network corresponding to the intermediate qubits from the tensor network according to the elimination order.

2. The apparatus according to claim 1, characterized in that, Each intermediate qubit uniquely corresponds to a corresponding index of the tensor, each qubit in the indicator subset uniquely corresponds to a corresponding index of the tensor, and each index of the tensor uniquely corresponds to an input qubit, an output qubit, or an intermediate qubit; and / or There is a one-to-one correspondence between the vertices of the string diagram and the indices corresponding to the intermediate qubits or the qubits in the indicator subset.

3. The apparatus according to claim 1 or 2, characterized in that, The chord graph of the tensor network is a chord graph completion of a non-chord graph, wherein the non-chord graph represents the tensor network with a minimized maximal clique in the chord graph completion of the non-chord graph.

4. The apparatus according to claim 3, characterized in that, The chord graph is obtained from the non-chord graph representing the tensor network using an optimized elimination order of the vertices of the non-chord graph (S1760), wherein, The chord graph is obtained by adding edges to the non-chord graph such that for each vertex, all neighbors of the vertex that are later than the vertex in the optimized elimination order are a clique in the chord graph.

5. The apparatus according to claim 4, characterized in that, For each quantum gate of the quantum circuit, there exists a tensor of the tensor network, and for each quantum bit of the quantum gate that is an intermediate quantum bit or in the indicator subset, the tensor has an index corresponding to the quantum bit; For each quantum gate of the quantum circuit, the vertex of the nonstring graph corresponding to the qubit of the quantum gate is a clique.

6. The apparatus according to claim 5, characterized in that, Determining the elimination order of the intermediate qubits includes determining (S1740) the optimized elimination order.

7. The apparatus according to claim 6, characterized in that, The elimination order of the vertices of the nonstring graph of the tensor network is determined using an optimization process (S1740), wherein, The optimization process minimizes the maximum clique of a graph obtained by adding edges to the non-chord graph such that for each vertex in the graph, all neighbors of the vertex that are later than the vertex in the optimized elimination order are a clique in the graph.

8. The apparatus according to claim 6 or 7, characterized in that, Before determining the optimized elimination order, the nonstring graph is modified (S1720) by adding edges to the nonstring graph such that the vertices of the qubits corresponding to the indicated subset are cliques.

9. The apparatus according to any one of claims 4-7, characterized in that, The processing circuit (1050) is used for: The nonstring graph representing the tensor network is determined (S1710) based on the indicated subset, such that: • There is a one-to-one correspondence between the vertices of the nonstring graph and the indices of the tensors corresponding to the intermediate qubits or the qubits in the indicator subset; • For each tensor of the tensor network, the vertex of the nonstring graph corresponding to the tensor is a clique.

10. The apparatus according to claim 3, characterized in that, The processing circuit (1050) is used for: The nonstring graph representing the tensor network is determined (S1710) based on the indicated subset, such that: • There is a one-to-one correspondence between the vertices of the nonstring graph and the indices of the tensors corresponding to the intermediate qubits or the qubits in the indicator subset; • For each tensor of the tensor network, the vertex of the nonstring graph corresponding to the tensor is a clique.

11. The apparatus according to claim 8, characterized in that, The processing circuit (1050) is used for: The nonstring graph representing the tensor network is determined (S1710) based on the indicated subset, such that: • There is a one-to-one correspondence between the vertices of the nonstring graph and the indices of the tensors corresponding to the intermediate qubits or the qubits in the indicator subset; • For each tensor of the tensor network, the vertex of the nonstring graph corresponding to the tensor is a clique.

12. The apparatus according to any one of claims 4-7 and 10-11, characterized in that, The processing circuit (1050) is used for: Based on the indicated subset, the non-chord graph representing the tensor network is determined (S1710) by adding the following items: • For each input or output qubit in the indicated subset, corresponding to a single vertex of the qubit, and • An edge, such that for each quantum gate of the quantum circuit, the vertex of the nonstring graph corresponding to the qubit of the quantum gate is a clique, wherein, There is a one-to-one correspondence between the vertices and the intermediate qubits of the general nonstring graph.

13. The apparatus according to claim 3, characterized in that, The processing circuit (1050) is used for: Based on the indicated subset, the non-chord graph representing the tensor network is determined (S1710) by adding the following items: • For each input or output qubit in the indicated subset, corresponding to a single vertex of the qubit, and • An edge, such that for each quantum gate of the quantum circuit, the vertex of the nonstring graph corresponding to the qubit of the quantum gate is a clique, wherein, There is a one-to-one correspondence between the vertices and the intermediate qubits of the general nonstring graph.

14. The apparatus according to claim 8, characterized in that, The processing circuit (1050) is used for: Based on the indicated subset, the non-chord graph representing the tensor network is determined (S1710) by adding the following items: • For each input or output qubit in the indicated subset, corresponding to a single vertex of the qubit, and • An edge, such that for each quantum gate of the quantum circuit, the vertex of the nonstring graph corresponding to the qubit of the quantum gate is a clique, wherein, There is a one-to-one correspondence between the vertices and the intermediate qubits of the general nonstring graph.

15. The apparatus according to claim 9, characterized in that, The processing circuit (1050) is used for: Based on the indicated subset, the non-chord graph representing the tensor network is determined (S1710) by adding the following items: • For each input or output qubit in the indicated subset, corresponding to a single vertex of the qubit, and • An edge, such that for each quantum gate of the quantum circuit, the vertex of the nonstring graph corresponding to the qubit of the quantum gate is a clique, wherein, There is a one-to-one correspondence between the vertices and the intermediate qubits of the general nonstring graph.

16. The apparatus according to any one of claims 4-7 and 10-11, characterized in that, The processing circuit (1050) is used for: Based on the indicated subset, the nonstring graph representing the tensor network is determined (S1710) by deleting the following items for each input or output qubit not in the indicated subset: • Connect all edges corresponding to the vertices of the stated qubit, and • Corresponding to all vertices of the qubit; where, There is a one-to-one correspondence between the vertices of the general nonstring graph and the qubits of the quantum circuit, wherein each qubit of the quantum circuit is an input qubit, an output qubit, or an intermediate qubit.

17. The apparatus according to claim 3, characterized in that, The processing circuit (1050) is used for: Based on the indicated subset, the nonstring graph representing the tensor network is determined (S1710) by deleting the following items for each input or output qubit not in the indicated subset: • Connect all edges corresponding to the vertices of the stated qubit, and • Corresponding to all vertices of the qubit; where, There is a one-to-one correspondence between the vertices of the general nonstring graph and the qubits of the quantum circuit, wherein each qubit of the quantum circuit is an input qubit, an output qubit, or an intermediate qubit.

18. The apparatus according to claim 8, characterized in that, The processing circuit (1050) is used for: Based on the indicated subset, the nonstring graph representing the tensor network is determined (S1710) by deleting the following items for each input or output qubit not in the indicated subset: • Connect all edges corresponding to the vertices of the stated qubit, and • Corresponding to all vertices of the qubit; where, There is a one-to-one correspondence between the vertices of the general nonstring graph and the qubits of the quantum circuit, wherein each qubit of the quantum circuit is an input qubit, an output qubit, or an intermediate qubit.

19. The apparatus according to claim 9, characterized in that, The processing circuit (1050) is used for: Based on the indicated subset, the nonstring graph representing the tensor network is determined (S1710) by deleting the following items for each input or output qubit not in the indicated subset: • Connect all edges corresponding to the vertices of the stated qubit, and • Corresponding to all vertices of the qubit; where, There is a one-to-one correspondence between the vertices of the general nonstring graph and the qubits of the quantum circuit, wherein each qubit of the quantum circuit is an input qubit, an output qubit, or an intermediate qubit.

20. The apparatus according to any one of claims 1-2, 4-7, 10-11, 13-15, and 17-19, characterized in that, The processing circuit (1050) is used for: Before deleting the index corresponding to the intermediate qubit, delete the index corresponding to the following from the tensor of the tensor network: • Input qubits not in the indicated subset, or • Output qubits not in the indicated subset.

21. The apparatus according to claim 3, characterized in that, The processing circuit (1050) is used for: Before deleting the index corresponding to the intermediate qubit, delete the index corresponding to the following from the tensor of the tensor network: • Input qubits not in the indicated subset, or • Output qubits not in the indicated subset.

22. The apparatus according to claim 8, characterized in that, The processing circuit (1050) is used for: Before deleting the index corresponding to the intermediate qubit, delete the index corresponding to the following from the tensor of the tensor network: • Input qubits not in the indicated subset, or • Output qubits not in the indicated subset.

23. The apparatus according to claim 9, characterized in that, The processing circuit (1050) is used for: Before deleting the index corresponding to the intermediate qubit, delete the index corresponding to the following from the tensor of the tensor network: • Input qubits not in the indicated subset, or • Output qubits not in the indicated subset.

24. The apparatus according to claim 12, characterized in that, The processing circuit (1050) is used for: Before deleting the index corresponding to the intermediate qubit, delete the index corresponding to the following from the tensor of the tensor network: • Input qubits not in the indicated subset, or • Output qubits not in the indicated subset.

25. The apparatus according to claim 16, characterized in that, The processing circuit (1050) is used for: Before deleting the index corresponding to the intermediate qubit, delete the index corresponding to the following from the tensor of the tensor network: • Input qubits not in the indicated subset, or • Output qubits not in the indicated subset.

26. The apparatus according to any one of claims 1-2, 4-7, 10-11, 13-15, 17-19, and 21-25, characterized in that, The index corresponding to an input qubit or output qubit not in the indicator subset is removed from the tensor network by setting the index to a corresponding predetermined value; and / or The index corresponding to the intermediate qubit is removed from the tensor network by shrinking.

27. The apparatus according to claim 3, characterized in that, The index corresponding to an input qubit or output qubit not in the indicator subset is removed from the tensor network by setting the index to a corresponding predetermined value; and / or The index corresponding to the intermediate qubit is removed from the tensor network by shrinking.

28. The apparatus according to claim 8, characterized in that, The index corresponding to an input qubit or output qubit not in the indicator subset is removed from the tensor network by setting the index to a corresponding predetermined value; and / or The index corresponding to the intermediate qubit is removed from the tensor network by shrinking.

29. The apparatus according to claim 9, characterized in that, The index corresponding to an input qubit or output qubit not in the indicator subset is removed from the tensor network by setting the index to a corresponding predetermined value; and / or The index corresponding to the intermediate qubit is removed from the tensor network by shrinking.

30. The apparatus according to claim 12, characterized in that, The index corresponding to an input qubit or output qubit not in the indicator subset is removed from the tensor network by setting the index to a corresponding predetermined value; and / or The index corresponding to the intermediate qubit is removed from the tensor network by shrinking.

31. The apparatus according to claim 16, characterized in that, The index corresponding to an input qubit or output qubit not in the indicator subset is removed from the tensor network by setting the index to a corresponding predetermined value; and / or The index corresponding to the intermediate qubit is removed from the tensor network by shrinking.

32. The apparatus according to claim 20, characterized in that, The index corresponding to an input qubit or output qubit not in the indicator subset is removed from the tensor network by setting the index to a corresponding predetermined value; and / or The index corresponding to the intermediate qubit is removed from the tensor network by shrinking.

33. A method for simulating quantum circuits, characterized in that, Includes the following steps: Receive (S1700) an indication of a subset of input and output qubits of the quantum circuit, the indicated subset corresponding to the amplitude tensor of the quantum circuit to be determined (S1790), the amplitude tensor including the amplitude of different state combinations of the qubits of the indicated subset; Using the tensor network of the quantum circuit and the restricted maximum cardinality search (RMCS), the elimination order of intermediate qubits within the quantum circuit is determined (S1750); the elimination order is determined iteratively in reverse order by selecting one intermediate qubit from the intermediate qubits in each step of the iteration (S1770), wherein the intermediate qubit is: • Not selected in any preceding step of the iteration; In the chord graph representing the tensor network, a vertex is adjacent to a maximum number of vertices corresponding to the following: ο The intermediate qubit selected in any preceding step of the iteration, or ο The qubits in the indicated subset; The goal of the RMCS is to construct the elimination order of the chord graph so that nodes in the subset of the indicator of the vertices are placed at the end; The magnitude tensor is determined (S1790) by sequentially deleting the indices of the tensors of the tensor network corresponding to the intermediate qubits from the tensor network according to the elimination order.

34. A computer program product, characterized in that, Includes instructions stored on a non-transitory storage medium, which, when executed in one or more processors, perform the method according to claim 33.

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