Memory device with enhanced esd protection and secure access from tester

Abstract

The present disclosure relates to a memory device comprising: an array of memory cells; a plurality of boundary cells capable of managing serial data and parallel data; a hybrid pad connected to the memory cells by a low speed path, the hybrid pad configured to be contacted by a probe of a tester machine; a high speed pad connected to the boundary cells by a high speed path; a tri-state multiplexer block connected to the memory cells and the boundary cells and configured to receive at least a first input signal and a second input signal to the memory cells and the boundary cells, the tri-state multiplexer block further connected to the hybrid pad; an ESD network connected to the hybrid pad; an enable circuit connected to one of the hybrid pads, configured to receive an external enable signal and to provide an internal enable signal to the tri-state MUX; wherein the enable circuit comprises: a tester presence detector circuit connected to the hybrid pad; and a logic gate having respective input terminals and an output terminal, the respective input terminals connected to the tester presence detector circuit and configured to receive the external enable signal, the output terminal configured to provide the internal enable signal, the tester presence detector circuit configured to provide a presence signal to the logic gate when a tester machine is connected to the hybrid pad. The present disclosure also relates to a system on chip (SoC) component comprising a memory device, i.e. as an embedded device; and a method of implementing enhanced ESD protection and secure access to memory cells.

Description

Technical Field

[0001] This invention relates to memory devices, and more particularly to memory devices with enhanced ESD protection and secure access from a test machine. Background Technology

[0002] Electrostatic discharge (ESD) protection is a critical issue when managing memory devices, especially as recent advancements in memory design have exacerbated ESD-related problems by reducing transistor size and oxide layer thickness.

[0003] However, as the die size of System-on-Chip (SoC) continues to grow and the number of transistors it can accommodate increases, each of which requires ESD protection structures, ESD protection checks consume more runtime and memory areas.

[0004] A system-on-a-chip (SoC) is a semiconductor integrated circuit that integrates all the components of a computer or other electronic system. These components typically include a central processing unit (CPU), memory sections, input / output ports, and auxiliary storage components, all of which reside on a single semiconductor substrate.

[0005] Especially in the automotive sector, there is a need to process SoC devices, which include controllers, memory, and connections to many external sensors and actuators.

[0006] Basically, ESD protection is achieved by providing an alternative path for ESD branch currents, namely through an unenergized device that is typically indicated as an ESD network.

[0007] Typically, an ESD network is provided when ESD is likely to occur. That is, the ESD network is connected to each external or test pad, where the contact probes of the external test equipment are adjacent, and the test process handles high ESD.

[0008] The goal is to address ESD-related issues and provide effective and secure ESD protection for memory devices. Specifically, it involves connecting an ESD network to test pads that enable the memory device to connect to an external test machine, allowing communication with the memory cell only when such a test machine is actually connected to the test pads, and handling different privilege levels and different test modes. Summary of the Invention

[0009] One embodiment of this disclosure provides a memory device comprising: a memory cell array; a plurality of boundary cells capable of managing mixed serial and parallel data pads, the mixed pads being connected to the memory cells via low-speed paths and configured to contact probes of a machine under test; high-speed pads being connected to the boundary cells via high-speed paths; a tri-state multiplexer block being connected to the memory cells and the boundary cells and configured to receive at least a first input signal and a second input signal from the memory cells and the boundary cells, the tri-state multiplexer block also being connected to the mixed pads; and an ESD network connecting... A hybrid pad is connected to the hybrid pad; an enable circuit is connected to one of the hybrid pads and configured to receive an external enable signal and provide an internal enable signal to the tri-state MUX; wherein the enable circuit includes: a tester presence detector circuit connected to the hybrid pad; and a logic gate having corresponding input terminals and output terminals, the corresponding input terminals being connected to the tester presence detector circuit and configured to receive the external enable signal, the output terminals being configured to provide the internal enable signal, and the tester presence detector circuit being configured to provide a presence signal to the logic gate when a tester is connected to the hybrid pad.

[0010] Another embodiment of this disclosure provides a system-on-a-chip (SoC) component including a memory device, the SoC component comprising: an array of memory cells; a plurality of boundary cells capable of managing serial and parallel data; a hybrid pad connected to the memory cells via a low-speed path, the hybrid pad being configured as probe contacts of a machine under test; a high-speed pad connected to the boundary cells via a high-speed path; and a tri-state multiplexer block connected to the memory cells and the boundary cells, and configured to receive at least a first input signal and a second input signal from the memory cells and the boundary cells, the tri-state multiplexer block also being connected to the hybrid pad; E An SD network, the ESD network being connected to the hybrid pads; an enable circuit, the enable circuit being connected to one of the hybrid pads, configured to receive an external enable signal and provide an internal enable signal to the tri-state MUX; wherein the enable circuit includes: a tester presence detector circuit, the tester presence detector circuit being connected to the hybrid pads; and a logic gate, the logic gate having corresponding input terminals and output terminals, the corresponding input terminals being connected to the tester presence detector circuit and configured to receive the external enable signal, the output terminals being configured to provide the internal enable signal, and the tester presence detector circuit being configured to provide a presence signal to the logic gate when a tester is connected to the hybrid pads.

[0011] Another embodiment of this disclosure provides a method for implementing enhanced ESD protection and secure access to memory cells, the method comprising the steps of: detecting the connection of a test machine to a hybrid pad of an ESD-protected memory device including an array of memory cells, the hybrid pad being connected to an ESD network; enabling the generation of an internal enable signal for a tri-state MUX, the tri-state MUX providing input signals from the memory cells to the hybrid pad; and testing the hybrid pad. Attached Figure Description

[0012] Figure 1 A block diagram of a memory device that provides ESD protection for hybrid pads is shown;

[0013] Figure 2 A block diagram of a memory device with enhanced ESD protection and secure access according to an embodiment of the present disclosure is shown;

[0014] Figure 3A and 3B Implementations of alternative embodiments according to this disclosure are shown respectively. Figure 2 Finite state machine (FSM) and associated lookup table for decision sequences of memory devices;

[0015] Figure 4 A block diagram is shown illustrating a method for implementing enhanced ESD protection and secure access to memory cells according to embodiments of the present disclosure. Detailed Implementation

[0016] Referring to these figures, this document discloses a memory device equipped with enhanced ESD protection, pad contact detection, and secure access.

[0017] More specifically, as will be described in detail below, the proposed memory device equipped with enhanced ESD protection, pad contact detection, and secure access is designed to properly protect hybrid pads used for testing purposes, which can be connected to a tester or host device along a low-speed path and alternatively to a high-speed path, so as to allow different test modes to be implemented only for authorized access.

[0018] An example memory device includes:

[0019] -Memory cell array;

[0020] - Multiple boundary cells, which are capable of managing serial and parallel data;

[0021] - Hybrid pads connected to the memory cell via a low-speed path, the hybrid pads being configured to contact the probes of the test machine;

[0022] - High-speed pads, which are connected to the boundary cell via high-speed paths;

[0023] - A tri-state multiplexer block, the tri-state multiplexer block being connected to the memory cell and the boundary cell and configured to receive a first input signal and a second input signal from the memory cell and the boundary cell, the tri-state multiplexer block being also connected to the hybrid pad;

[0024] -ESD network, the ESD network being connected to the hybrid pads;

[0025] - An enable circuit, connected to one of the hybrid pads, is configured to receive an external enable signal and provide an internal enable signal to the tri-state MUX;

[0026] The enable circuit mentioned above includes:

[0027] - The tester has a detector circuitry connected to the hybrid pad; and

[0028] A logic gate having corresponding input and output terminals, the corresponding input terminals being connected to the presence detector circuit of the tester and configured to receive the external enable signal, and the output terminals being configured to provide the internal enable signal.

[0029] The tester presence detector circuit is configured to provide a presence signal to the logic gate when the tester is connected to the hybrid pad. In the context of this disclosure, low speed and high speed have corresponding valences (e.g., low speed is relatively lower than high speed, and high speed is relatively higher than low speed). By way of example only and without limitation, a low-speed path or low-speed pad may be suitable for operation at 133MHz, and a high-speed path or high-speed pad may be suitable for operation at 1GHz or higher.

[0030] In one embodiment, the enable circuit may further include a pull-up circuit connected to the hybrid pad and the tester presence detector circuit.

[0031] Furthermore, the tester's detector circuitry may further include a sequence detection circuit configured to detect the bit sequence applied to the hybrid pads to verify that the tester is an authorized tester or that the test mode is the correct test mode, and to allow corresponding access to the memory cells from the hybrid pads.

[0032] Furthermore, the memory array can receive a specific enable signal to allow direct access to the memory cells by directly connecting the memory cells to the tri-state MUX and thus to the hybrid pads.

[0033] This disclosure also relates to a system-on-a-chip (SoC) component that includes a memory device, specifically as an embedded device.

[0034] This disclosure further relates to a method for implementing enhanced ESD protection and secure access to memory cells, the method comprising the following steps:

[0035] - The connection between the test equipment and the hybrid pads of the memory device with ESD protection, including the memory cell array, is inspected and connected to the ESD network;

[0036] - Enables the generation of an internal enable signal for a tri-state MUX, which provides input signals from the memory cell to the hybrid pad;

[0037] - Test the hybrid pads.

[0038] More specifically, the method may include the step of selecting the input signal from the memory cell by means of a selection signal received by the tri-state MUX.

[0039] The method may further include the steps of connecting memory cells of the memory array to the hybrid pads along a low-speed path by means of a high-voltage buffer when the first input signal is selected by the tri-state MUX, or connecting boundary cells to the hybrid pads along a high-speed path by means of a buffer when the second input signal is selected by the tri-state MUX.

[0040] The detection step may further include detecting the bit sequence applied to the hybrid pad to verify that the test machine is an authorized test machine or the test mode is the correct test mode, and to allow corresponding access to the memory cell from the hybrid pad.

[0041] The system may also provide steps for storing the bit sequence of the hybrid pads and updating the stored bit sequence at the end of each test operation.

[0042] Memory devices with very high parallelism, such as memory chips in SoCs or other stacked configurations, have a large number of pads. Most of these pads are used for internal communication and therefore do not require any ESD protection. These pads are connected to the memory array via high-speed paths, and therefore are often designated as high-speed pads or HS pads. HS pads typically cannot manage analog voltages and are indeed smaller in size.

[0043] The memory device also features test pads for contact with an external test equipment. These test pads are typically larger than the HS pads. The test pads can be input pads, output pads, or input / output pads, and are connected to the memory array via a low-speed path using appropriate buffers. Furthermore, a corresponding ESD network is connected to the ESD-exposed test pads, primarily due to the connection to the test equipment.

[0044] Figure 1 This is a block diagram of an example memory device 100 equipped with ESD protection.

[0045] The ESD-protected memory device 100 includes hybrid pads 101 for testing purposes and high-speed pads 102 for internal communication, as indicated above. As will be explained below, each hybrid pad 101 will be connected to an external test machine and can be connected to the memory block 110 along the low-speed path LS_path and alternatively along the high-speed path HS_path, to allow different test modes to be performed via these hybrid pads 101. Because of its ability to connect to a test machine, the hybrid pads 101 can drive very high capacitive loads and are large enough to allow standard contact probes of the test machine to fall onto the hybrid pads.

[0046] like Figure 1 As shown, the hybrid pad 101 is connected to the memory array 110 along a low-speed path LS_path via a high-voltage or HV buffer 103, which further includes corresponding basic buffers 103A and 103B in an inverter configuration. The HV buffer 103 may also be equipped with a high-voltage switch to manage high voltage. The basic buffers 103A and 103B are driven directly or in an inverted manner by a first enable signal Enable_I / O. The first enable signal Enable_I / O enables I / O data transfer for the hybrid pad 101.

[0047] The hybrid pad 101 is also coupled to an ESD network 105, which enables the ESD-related current Iesd to be deflected toward passive components included therein.

[0048] High-speed pads 102 are connected to memory blocks 110 along the high-speed path HS_path by means of additional buffers 104 with low drive capability. It is noteworthy that buffers 104 are specifically of a reduced size relative to HV buffers 103, and providing such buffers 104 in large quantities for each high-speed pad 102 does not negatively impact the overall size of the memory device 100 with ESD protection. Furthermore, these high-speed pads 102 do not require ESD protection, and therefore, in some embodiments, an ESD network is not provided for the high-speed pads.

[0049] More specifically, high-speed pad 102 is connected to boundary cell 106 coupled to memory block 110. Boundary cell 106 is capable of managing serial input data SIN and output data SOUT, as well as parallel input data PIN and output data POUT, the latter being connected to high-speed pad 102 via buffer 104.

[0050] Memory block 110 includes a subarray 107 of memory cells connected to decoding block 108 and to sense amplifier 109, the decoding block further including column decoders and DMA (direct memory access) paths.

[0051] The ESD-protected memory device 100 further includes a tri-state multiplexer block or MUX 111, which is then connected to the memory block 110 and the boundary cell 106. The tri-state MUX 111 is provided with a first enable signal Enable_I / O that enables I / O data transfer and a selection signal Sel. The tri-state MUX 111 further receives a first input signal IN0 from the memory block 110 and a second input signal IN1 from the boundary cell 106. More specifically, the selection signal Sel controls the tri-state MUX 111 to select between input signals to be provided to the HV buffer 103 and thus to the hybrid pad 101.

[0052] According to an alternative embodiment, the tri-state MUX 111 can receive more than two input signals and provide one of the multiple input signals to the HV buffer 103 based on the selection signal Sel. This may be a case where the memory device has more than two paths to be connected to the hybrid pad 101, specifically considering the basic buffer 103A of the HV buffer 103.

[0053] DMA typically allows a hardware subsystem to access main system memory (random access memory) independently of the central processing unit (CPU). This feature is particularly useful when the CPU cannot keep up with the data transfer rate, or when the CPU needs to perform work while waiting for relatively slow I / O data transfers.

[0054] As this is direct access to memory subarray 107, the DMA path should be carefully controlled. A specific enable signal, Enable_DMA, is provided to decoding block 108 to enable DMA, i.e., direct access to memory subarray 107. Specifically, when DMA is enabled, memory subarray 107 is directly connected to tri-state MUX 111 and a first input signal IN0 is provided to it. It should be noted that, depending on the DMA mode, memory subarray 7 is connected to tri-state MUX 111 via the DMA path included in decoding block 108, which also includes a standard column decoder for connecting the sense amplifier 109 to memory subarray 107. In other respects, the first input signal IN0 is provided by the column decoder included in decoding block 108.

[0055] According to such Figure 2 The embodiment of this disclosure shown has an ESD-protected memory device 100 with an arrangement for checking the connection between the mixed pads and the tester and the true nature of such connection, as will be explained below.

[0056] The ESD-protected memory device 100 includes an enable circuit 120 with enhanced ESD protection, pad contact detection, and secure access. The enable circuit is connected to a hybrid pad 101, receives a first enable signal Enable_I / O, and provides a fourth enable signal Int_Enable_I / O to a tri-state MUX 111 and an HV buffer 103.

[0057] Specifically, the enable circuit 120 includes a pull-up circuit 121 connected to the hybrid pad 101 and the tester presence detector or TPD circuit 122. More specifically, the pull-up circuit 121 includes a pull-up open-gate transistor Mpu, which is inserted between the power supply voltage reference Vdd and the hybrid pad 101 and has a gate terminal connected to the TPD circuit 122 and receiving a control signal PG from the TPD circuit. As will be clarified in the following description, the control signal PG can disconnect or turn off the pull-up open-gate transistor Mpu.

[0058] TPD circuit 122 is then connected to the hybrid pad 101 and receives the test signal Stest from the hybrid pad. TPD circuit 121 further receives a power-on reset (POR) signal and a disable signal TPD_disable. These power-on and disable signals are provided to the ESD-protected memory device 100 from suitable external control circuitry. As will be clarified in the following description, the test signal Stest indicates that a tester is connected to the hybrid pad 101 and is capable of detecting such a tester.

[0059] In addition, the first enable signal Enable_I / O, the DMA enable signal Enable_DMA, and the select signal Sel can be managed via JTAG by setting some internal registers.

[0060] The enable circuit 120 also includes a logic gate 123, namely a NOR gate, which has corresponding input terminals to receive an presence signal Pres and a first enable signal Enable_I / O from the TPD circuit 122, and an output terminal to provide a fourth enable signal Int_Enable_I / O.

[0061] According to another embodiment not shown in the accompanying drawings, the fourth enable signal Int_Enable_I / O can be used as the selection signal Sel. Alternatively, in some embodiments, the test register T-reg can also be used as the selection signal Sel.

[0062] Typically, the voltage at the hybrid pad 101 remains high due to the pull-up gate transistor Mpu connected thereto. Specifically, after the ESD-protected memory device 100 is powered on (pulsed power is supplied to the signal POR), the TPD circuit 122 enables the pull-up gate transistor Mpu and keeps it active until a subsequent event.

[0063] When the tester's contact probes land on the hybrid pad 101, the gate transistor Mpu is pulled up to provide a 0V voltage according to a pre-agreed protocol. It should be noted that due to the ESD network 105 connected to the hybrid pad 101, the contact between the hybrid pad 101 and the tester is free from ESD-related issues.

[0064] After a 0V voltage is provided, the pull-up open-gate transistor Mpu begins to draw current from the mixed pad 101, but this is compensated by a stronger test circuit. This results in a 0V voltage value for the test signal Stest being provided to the TPD circuit 122, which confirms that the test circuit is connected to the mixed pad 101 and generates the presence signal Pres for logic gate 123.

[0065] TPD circuit 122 also generates a suitable control signal PG for the gate terminal of the pull-up gate transistor Mpu, which is therefore turned off so as not to interfere with the testing of the mixed pad 101. More specifically, the pull-up gate transistor Mpu is turned off until the next power cycle (when the power supply signal POR is pulsed) or when the signal TPD_disable is pulsed.

[0066] Appropriately, when the TPD circuit 122 is further turned on by the power supply signal POR, the pull-up gate transistor Mpu is re-turned on and appropriately connected to the hybrid pad 101, ready for further testing operations.

[0067] When I / O data transmission is enabled via the first enable signal Enable_I / O, logic gate 123 generates a corresponding fourth enable signal Int_Enable_I / O for the tri-state MUX 111 and the HV buffer 103. The HV buffer allows either the first input signal IN0 or the second input signal IN1 to be provided to the hybrid pad 101 for testing purposes. Specifically, the provision of the first input signal IN0 or the second input signal IN1 is adjusted by applying a selection signal Sel to the tri-state MUX 111.

[0068] Furthermore, according to an alternative embodiment, the enable circuit 120 further includes a privilege level mechanism to detect not only when a tester is connected to the mixing pad 101, but also whether such a tester is an authorized tester or the test mode is the correct test mode.

[0069] like Figure 3A As shown, the TPD circuit 122 includes a sequence detection circuit 130, which in turn includes a finite state machine (FSM) 131. The sequence detection circuit 130 is enabled by writing an internal non-volatile flag Secure_access_ON.

[0070] The sequence of bits B1...Bn is stored, and the sequence detection circuit 130 enables the TPD circuit 122 by turning off the pull-up gate transistor Mpu only when the correct sequence is detected. Specifically, the finite state machine 131 includes multiple states connected according to the stored bit sequence, such that only the correct bit sequence results in an unlocked state, and any other transitions between states are indicated as errors.

[0071] According to this alternative embodiment, a bit sequence can be stored for each hybrid pad 101, and the bit sequence is equal for all (hardware-coded) ESD-protected memory devices. Specifically, as Figure 3B As shown, the bit sequence is stored in lookup table 132.

[0072] TPD circuit 122 also includes a timer T. When the tester is connected to the hybrid pad 101, timer T is also triggered and sends a signal indicating a possible timeout, i.e., the elapsed time limit, which requires restarting the test program, specifically by disconnecting and reconnecting the tester's contact probes. Otherwise, the test program executes correctly if the correct bit sequence is provided within the time limit.

[0073] According to another alternative embodiment, the bit sequence can be programmed by a test machine, for example, stored in a dedicated flash cell of the memory subarray 107 outside the user address space. In this way, the bit sequence can be changed for each memory device or for a group of memory devices, such as all devices provided to a client.

[0074] Furthermore, in the case of programmable bit sequences, in some embodiments, countermeasures against so-called "response attacks" are implemented by providing, for example, an update to the stored bit sequence stored in lookup table 132 at the end of each test operation. In this case, the same bit sequence cannot be used for subsequent access to the ESD-protected memory device 100 for testing purposes. This feature is particularly useful when the test mode is available to the end client and not just at the factory level.

[0075] Upon power-up, each lookup table 132 is preloaded with the PAD# sequence to be identified.

[0076] according to Figure 3A and 3B In an example embodiment, the current bit sequence used is a bit sequence with tag 0b01. Then, the new bit sequence of pada is written to the next available entry (11), and the current tag is burned (i.e., tag bit 01 replaces tag bit 00).

[0077] In the event of a customer return, the available entries are programmed to 0b10 before the memory device is separated from the rest of the SoC.

[0078] TPD circuit 122 may be a single TPD that is implemented in the memory device and controls the pull-up gate transistors of all hybrid pads 101. In this case, TPD circuit 122 receives a bit sequence from only one pad and enables all hybrid pads if the bit sequence is identified as correct.

[0079] In other respects, the ESD-protected memory device 100 may include a plurality of TPD circuits 122, each TPD circuit being dedicated to a corresponding hybrid pad 101 and controlling the pull-up gate transistor Mpu connected thereto.

[0080] In this case, each TPD circuit 122 receives a bit sequence and enables only one hybrid pad 101 (if the sequence is correct).

[0081] Finally, a multi-pad TPD circuit 122 can be used, which is a single TPD circuit 122 implemented in a memory device that controls all pull-up gate transistors for all mixed pads. In this case, the TPD circuit 122 is able to identify multiple different sequences in parallel (one sequence for each mixed pad).

[0082] This disclosure also relates to system-on-chip (SoC) components including memory devices with ESD protection as embedded devices.

[0083] More specifically, ESD-protected memory devices can be structurally independent and coupled to SoC components, for example, via multiple struts.

[0084] ESD-protected memory devices can implement DMA to reduce the final latency that SoC components may experience when reading data.

[0085] like Figure 4 As depicted in another embodiment of this disclosure, a method 400 for implementing enhanced ESD protection and secure access to memory cells is provided.

[0086] The method includes the following steps:

[0087] - (Step 410) Detect the connection between the tester and the hybrid pad 101 of the ESD-protected memory device 100, the hybrid pad 101 being connected to the ESD network 105.

[0088] - (Step 420) Enable the generation of an internal enable signal Int_Enable_I / O for the tri-state MUX 111, which provides input signals IN0 and IN1 from the memory block 110 of the memory subarray 107 including memory cells to the hybrid pad 101;

[0089] - (Step 430) Test the hybrid pad 101.

[0090] More specifically, the method may further include the step of selecting input signals IN0 and IN1 by means of a tri-state MUX 111 and a selection signal Sel received therefrom.

[0091] As previously indicated, the selection signal Sel can be either the internal enable signal Int_Enable_I / O or the test register T-reg. Furthermore, more than two input signals can be selected, even if not shown in the accompanying drawings.

[0092] Furthermore, the method may include the following step: when the first input signal IN0 is selected, connecting the memory cells of the memory subarray 107 of the memory block 110 to the hybrid pad 101 along the low-speed path LS_path using an HV buffer 103. In other embodiments, the method may include the following step: when the second input signal IN1 is selected, connecting the boundary cells 106 connected to the memory block 110 to the hybrid pad 101 along the high-speed path HS_path using a buffer 104.

[0093] The detection step may further include driving a pull-up gate transistor Mpu, which is connected to a hybrid pad 101 and a TPD circuit 122 that generates an internal enable signal Int_Enable_I / O.

[0094] The detection step may further include detecting the bit sequence applied to the hybrid pad 101 to verify that the test machine is an authorized test machine or the test mode is the correct test mode, and to allow corresponding access to the memory cell from the hybrid pad 101.

[0095] In this case, the method may further include the steps of storing the bit sequence of the mixed pad 101 and updating the stored bit sequence at the end of each test operation.

[0096] In summary, this disclosure provides an ESD-protected memory device that allows protection of hybrid pads for testing purposes and also allows data to be provided to the hybrid pads along a high-speed path, the hybrid pads being able to manage HV without affecting the high-speed path.

[0097] More specifically, by using an ESD-protected memory device according to this disclosure, the implementer can actually choose between the following options:

[0098] 1) Utilize both enhanced ESD protection and pad connection detection features.

[0099] In this configuration, the tester includes a detector circuitry that provides a high-valued control signal PG to turn off the pull-up gate transistor Mpu, which receives this control signal PG at its gate terminal. Furthermore, the internal enable signal Int_Enable_I / O is asserted, indicating that a contact has been detected on the hybrid pads by either the tester or the host device. This is clearly a low-cost implementation for memory devices.

[0100] 2) Utilize enhanced ESD protection, pad connection detection, and secure access features (sequence identification).

[0101] As previously described, the tester has a detector circuitry for providing a high-valued control signal PG to turn off the pull-up gate transistor Mpu, which receives this control signal PG at its gate terminal. However, in this case, the internal enable signal Int_Enable_I / O is asserted, recognizing only the correct bit sequence.

[0102] In addition, the enable circuitry features enhanced ESD protection, pad connection detection, and secure access, ensuring proper operation of the memory device by providing only a small number of mixed pads, rather than a very large number of high-speed pads, thus saving silicon area.

[0103] In this way, it is easy to manage potential customer returns when the memory device has been installed and then requires further testing before removal. In fact, for data along the high-speed path, hybrid pads can also be used. These are typically hybrid pads used for internal communication, where data along the low-speed path is "offset" and connected only to the high-speed pads. These hybrid pads are usually reserved for use in the manufacturing process, i.e., for factory-level testing of the device. In some cases, this also allows for the use of standard test machines designed for factory-level device testing to perform subsequent tests.

[0104] Appropriately, the sequence detection circuit using TPD circuitry should only allow permitted subsequent test modes. Specifically, after the first access to the memory at the factory level, a more secure access mechanism should be enabled to protect sensitive information written to the memory device, such as uCode, voltage values, or algorithms.

[0105] On each access, the test machine can change the bit sequence by using a new bit sequence on the next access (to avoid replay attacks).

[0106] In the foregoing detailed description, reference has been made to the accompanying drawings, which form part of the detailed description and illustrate specific examples by way of illustration. Throughout the drawings, similar reference numerals describe substantially similar components. Other examples may be utilized, and structural, logical, and / or electrical changes may be made without departing from the scope of this disclosure.

[0107] Similar elements or components between different figures can be identified by using similar numbers. It should be understood that elements shown in the various embodiments herein can be added, interchanged, and / or eliminated to provide multiple additional embodiments of this disclosure. Furthermore, it will be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate embodiments of this disclosure and should not be considered limiting.

[0108] As used herein, “a,” “an,” or “a number of” can refer to one or more such things. “A number of” means two or more. As used herein, the term “coupled” can include electrical coupling, direct coupling and / or direct connection (e.g., by direct physical contact) without intermediate elements, or indirect coupling and / or connection with intermediate elements. The term “coupled” can further include two or more elements that cooperate or interact with each other (e.g., as in a causal relationship).

[0109] While specific examples have been illustrated and described herein, those skilled in the art will understand that arrangements intended to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of this disclosure. It should be understood that the above description is illustrative rather than restrictive. The scope of one or more examples of this disclosure should be determined by reference to the appended claims together with the full scope of their equivalents.

Claims

1. A memory device comprising: an array of memory cells; a plurality of boundary cells configured to manage serial data and parallel data; a hybrid pad connected to the memory cells by a low speed path, the hybrid pad configured to be contacted by a probe of a tester machine; a high speed pad connected to the boundary cells by a high speed path; a tri-state multiplexer (MUX) block connected to the memory cells and the boundary cells and configured to receive at least a first input signal and a second input signal to the memory cells and the boundary cells, the tri-state MUX block further connected to the hybrid pad; an electrostatic discharge (ESD) network connected to the hybrid pad; an enable circuit connected to one of the hybrid pads configured to receive an external enable signal and provide an internal enable signal to the tri-state MUX; wherein the enable circuit comprises: a tester presence detector circuit connected to the hybrid pad, wherein the tester presence detector circuit comprises: a sequence detection circuit configured to: detect a bit sequence applied to the hybrid pad to verify that the tester machine is an authorized tester machine or that a test mode is a correct test mode and grant corresponding access to the memory cells from the hybrid pad; and be enabled by writing an internal non-volatile flag; and a timer configured to be triggered when the tester machine contacts the hybrid pad and configured to signal a possible timeout that requires restarting a test program; and a logic gate having respective input terminals connected to the tester presence detector circuit and configured to receive the external enable signal and an output terminal configured to provide the internal enable signal, the tester presence detector circuit configured to provide a presence signal to the logic gate when a tester machine is connected to the hybrid pad.

2. The memory device of claim 1, wherein: the enable circuit further comprises a pull-up circuit connected to the hybrid pad and the tester presence detector circuit; and the pull-up circuit comprises a pull-up gate transistor inserted between a power supply voltage reference and the hybrid pad and having a gate terminal connected to the tester presence detector circuit to receive a control signal from the tester presence detector circuit, the control signal configured to disconnect the pull-up gate transistor from the hybrid pad.

3. The memory device of claim 1, wherein the tester presence detector circuit is configured to: receive a test signal from the hybrid pad, the test signal indicating that the tester machine is connected to the hybrid pad; and identify the tester machine.

4. The memory device of claim 1, wherein the sequence detection circuit comprises: a finite state machine comprising a plurality of states connected according to a stored bit sequence such that only a correct bit sequence results in an unlock state, any other transition between states being indicated as an error; and a lookup table storing the bit sequence.

5. The memory device of claim 4, wherein: the bit sequence is stored in a dedicated cell of the array of memory cells; and the stored bit sequence is updated at the end of each test operation.

6. The memory device of claim 1, further comprising high voltage buffers connected to the hybrid pads and configured to receive the internal enable signal, wherein each high voltage buffer comprises a base buffer in an inverter configuration configured to be driven by the internal enable signal to enable I / O data transfer for a corresponding hybrid pad connected to the base buffer.

7. The memory device of claim 1, further comprising low capacitance buffers connected to the high speed pads.

8. The memory device of claim 1, wherein the tri-state MUX is configured to receive a select signal that controls which of the input signals of the tri-state MUX is provided to the hybrid pads.

9. The memory device of claim 1, wherein the array is configured to receive a specific enable signal to allow direct access to the memory cells.

10. The memory device of claim 1, further comprising a single tester presence detector circuit connected to all hybrid pads.

11. The memory device of claim 1, further comprising a plurality of tester presence detector circuits each connected to a different respective hybrid pad.

12. The memory device of claim 1, further comprising a single multi-pad tester presence detector circuit connected to all hybrid pads and configured to identify a plurality of different sequences in parallel.

13. A system on a chip (SoC) component comprising a memory device, the SoC component including: an array of memory cells; a plurality of boundary cells configured to manage serial data and parallel data; a hybrid pad connected to the memory cells through a low speed path, the hybrid pad configured to be contacted by a probe of a tester; a high speed pad connected to the boundary cells through a high speed path; a tri-state multiplexer (MUX) block connected to the memory cells and the boundary cells and configured to receive at least a first input signal and a second input signal to the memory cells and the boundary cells, the tri-state MUX block further connected to the hybrid pad; an electrostatic discharge (ESD) network connected to the hybrid pad; an enable circuit connected to one of the hybrid pads configured to receive an external enable signal and to provide an internal enable signal to the tri-state MUX; wherein the enable circuit comprises: a tester presence detector circuit connected to the hybrid pads, wherein the tester presence detector circuit comprises: a sequence detection circuit configured to: detect a bit sequence applied to the hybrid pads to verify that the test machine is an authorized test machine or that a test mode is a correct test mode and to grant corresponding access to the memory cells from the hybrid pads; and be enabled by writing an internal non-volatile flag; and a timer configured to be triggered when the test machine contacts the hybrid pads and configured to signal a possible timeout that requires restarting a test program; and a logic gate having respective input terminals connected to the tester presence detector circuit and configured to receive the external enable signal and an output terminal configured to provide the internal enable signal, the tester presence detector circuit is configured to provide a presence signal to the logic gate when the test machine is connected to the hybrid pads.

14. The SoC assembly of claim 13, wherein the tester presence detector circuit is configured to receive a power supply signal and a disable signal from a control circuit.

15. The SoC assembly of claim 13, wherein: the sequence detection circuit comprises a finite state machine comprising a plurality of states connected according to a stored bit sequence such that only a correct bit sequence leads to an unlocked state, any other transition between states being indicated as an error.

16. The SoC assembly of claim 13, wherein: latency of the SoC assembly is reduced by enabling direct memory access to the memory cells when reading data; and the array of memory cells is configured to receive a specific enable signal to allow the direct memory access to the memory cells by directly connecting the memory cells to the tri-state MUX and thus to the hybrid pads.

17. A method for memory operation, comprising: detecting connection of a test machine to a hybrid pad of a memory device comprising electrostatic discharge (ESD) protection of an array of memory cells, the hybrid pad being connected to an ESD network; by an enable circuit, enabling generation of an internal enable signal for a tri-state multiplexer (MUX) to provide an input signal from the memory cells to the hybrid pad, wherein the enable circuit comprises: a tester presence detector circuit connected to the hybrid pads, wherein the tester presence detector circuit comprises: a sequence detection circuit configured to: detect a bit sequence applied to the hybrid pads to verify that the test machine is an authorized test machine or that a test mode is a correct test mode and to grant corresponding access to the memory cells from the hybrid pads; and be enabled by writing an internal non-volatile flag; and a timer configured to be triggered when the test machine contacts the hybrid pads and configured to signal a possible timeout that requires restarting a test program; and a logic gate having respective input terminals connected to the tester presence detector circuit and configured to receive the external enable signal and an output terminal configured to provide the internal enable signal, the tester presence detector circuit is configured to provide a presence signal to the logic gate when the test machine is connected to the hybrid pads. detecting a bit sequence applied to the hybrid pad to verify that the test machine is an authorized test machine or that the test mode is a correct test mode, and granting corresponding access to the memory cells from the hybrid pad; and enabled by writing an internal non-volatile flag; and a timer configured to be triggered when the test machine contacts the hybrid pad, and configured to signal a possible timeout requiring restarting of the test program; and testing the hybrid pad.

18. The method of claim 17, further comprising using a selection signal received by the tri-state MUX to select the input signal from the memory cells.

19. The method of claim 17, further comprising using a high voltage buffer to connect the memory cells to the hybrid pad along a low speed path when an input signal is selected by the tri-state MUX.

20. The method of claim 17, further comprising using a buffer to connect a boundary cell to the hybrid pad along a high speed path when an input signal is selected by the tri-state MUX.

21. The method of claim 17, wherein detecting the connection comprises: driving a pull-up gated transistor to generate an internal enable signal, the pull-up gated transistor connected to the hybrid pad and the tester presence detector circuit.

22. The method of claim 17, further comprising: storing a bit sequence of the hybrid pad; and updating the stored bit sequence at the end of each test operation.

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