A semiconductor device and a method of fabricating the same

Abstract

The application discloses a semiconductor device and a preparation method thereof. The method comprises the following steps: providing a substrate comprising a first device area and a second device area; forming a first isolation structure in the substrate of the first device area, and forming a second isolation structure in the substrate of the second device area; performing ion implantation on the first isolation structure; and performing etching back on the first isolation structure and the second isolation structure, so as to form a first groove in the first isolation structure and a second groove in the second isolation structure.

Description

TECHNICAL FIELD

[0001] The present application relates to electronic devices, and more particularly, to a semiconductor device and a method of manufacturing the same. BACKGROUND

[0002] 3D NAND memory devices also include control chips, which are generally implemented using complementary metal oxide semiconductor (CMOS). In CMOS, both high voltage metal oxide semiconductor (HVMOS) and low voltage metal oxide semiconductor (LVMOS) transistors exist. There can also be a low low voltage metal oxide semiconductor (LLVMOS) transistor in CMOS, which has a lower voltage than the LVMOS.

[0003] In current 3D-NAND processes, the voltages of HVMOS, LVMOS and LLVMOS devices are different, so their structural characteristics are different. For example, the junction depth of HVMOS is deeper than that of LVMOS and LLVMOS. The deeper the junction depth, the deeper the groove needs to be formed in the isolation structure to meet the requirements of the device junction depth.

[0004] TECHNICAL PROBLEM

[0005] The present application aims to provide a semiconductor device and a method of manufacturing the same, which aims to achieve a first groove depth greater than a second groove depth when forming the first groove and the second groove at the same time to meet the requirements of the device.

[0006] TECHNICAL SOLUTION

[0007] In one aspect, the present application provides a method of manufacturing a semiconductor device, comprising:

[0008] providing a substrate, the substrate comprising a first device region and a second device region;

[0009] forming a first isolation structure in the substrate of the first device region, and forming a second isolation structure in the substrate of the second device region;

[0010] ion implanting the first isolation structure;

[0011] Then, the first isolation structure and the second isolation structure are etched back to form a first recess in the first isolation structure and a second recess in the second isolation structure, the depth of the first recess in a longitudinal direction perpendicular to the substrate being greater than the depth of the second recess in the longitudinal direction.

[0012] Further preferably, the depth of the first recess in the longitudinal direction is less than the depth of the first isolation structure in the longitudinal direction; and the depth of the second recess in the longitudinal direction is less than the depth of the second isolation structure in the longitudinal direction.

[0013] Further preferably, the step of forming the first isolation structure in the substrate of the first device region and the second isolation structure in the substrate of the second device region comprises:

[0014] Etching the substrate of the first device region to form a first trench;

[0015] Etching the substrates of the first device region and the second device region to form a first isolation groove in the position of the first trench and a second isolation groove in the second device region;

[0016] Filling the first isolation groove and the second isolation groove with a first insulating layer and a second insulating layer respectively to form the first isolation structure in the substrate of the first device region and the second isolation structure in the substrate of the second device region;

[0017] Wherein, the depth of the first isolation groove in the longitudinal direction is greater than the depth of the second isolation groove in the longitudinal direction, and the difference between the depths of the first isolation groove and the second isolation groove is equal to the depth of the first trench in the longitudinal direction.

[0018] Further preferably, the method further comprises:

[0019] Forming a first gate oxide layer on the sidewall of the first recess;

[0020] Forming a second gate oxide layer on the sidewall of the second recess;

[0021] Wherein, the area of the first gate oxide layer is greater than the area of the second gate oxide layer.

[0022] Further preferably, the method further comprises:

[0023] Forming the first gate oxide layer on the surface of the substrate of the first device region;

[0024] Forming the second gate oxide layer on the surface of the substrate of the second device region.

[0025] Further preferably, the method further comprises:

[0026] forming a first gate layer on a surface of the first gate oxide layer to form a first gate structure comprising the first gate oxide layer and the first gate layer;

[0027] forming a second gate layer on a surface of the second gate oxide layer to form a second gate structure comprising the second gate oxide layer and the second gate layer.

[0028] In another aspect, the present application provides a semiconductor device formed by a method of manufacturing a semiconductor device according to any one of the above, comprising:

[0029] a substrate comprising a first device region and a second device region;

[0030] a first isolation structure in the substrate in the first device region, the first isolation structure comprising a first insulating layer at a bottom;

[0031] a second isolation structure in the substrate in the second device region, the second isolation structure comprising a second insulating layer at a bottom;

[0032] a first gate structure between the first device region and the first isolation structure and on the first insulating layer;

[0033] a second gate structure between the second device region and the second isolation structure and on the second insulating layer;

[0034] wherein the first insulating layer has implanted ions therein and the second insulating layer has no implanted ions therein; and the first gate structure has a depth in a longitudinal direction perpendicular to the substrate that is greater than a depth of the second gate structure in the longitudinal direction.

[0035] Further preferably, the first isolation structure has a depth in the longitudinal direction that is greater than a depth of the second isolation structure in the longitudinal direction.

[0036] Further preferably, the method further comprises:

[0037] the first gate structure on a surface of the substrate in the first device region;

[0038] the second gate structure on a surface of the substrate in the second device region.

[0039] Further preferably, the first gate structure comprises a first gate oxide layer and a first gate layer on a surface of the first gate oxide layer; and the second gate structure comprises a second gate oxide layer and a second gate layer on a surface of the second gate oxide layer.

[0040] Further preferably, an area of the first gate oxide layer is greater than an area of the second gate oxide layer.

[0041] Advantages

[0042] The present application provides a semiconductor device and a preparation method thereof. The method comprises the following steps: providing a substrate comprising a first device region and a second device region; forming a first isolation structure in the substrate of the first device region and a second isolation structure in the substrate of the second device region; performing ion implantation on the first isolation structure; and performing etching back on the first isolation structure and the second isolation structure to form a first groove in the first isolation structure and a second groove in the second isolation structure. Since the ion implantation is performed on the first isolation structure before the etching back, the bombardment of the ion implantation process will make the crystal lattice of the first isolation structure be scattered, so that the etching rate of the first isolation structure is greater than that of the second isolation structure in the etching back process, and thus the depth of the first groove is greater than that of the second groove, to meet the device requirement. BRIEF DESCRIPTION OF DRAWINGS

[0043] The technical scheme and other advantages of the present application will be apparent from the following detailed description of the embodiments of the present application, taken in conjunction with the accompanying drawings.

[0044] Figure 1 is a flowchart of the preparation method of the semiconductor device provided by the embodiment of the present application;

[0045] Figures 2a-2k is a structural schematic diagram in the preparation process of the semiconductor device provided by the embodiment of the present application.

[0046] Embodiments of the present application

[0047] The technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work shall fall within the scope of protection of the present application.

[0048] It should be understood that although the terms first, second, etc. can be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component without departing from the scope of the present application.

[0049] It should be understood that when one component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there can be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0050] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer has a top side and a bottom side, where the bottom side of the layer is relatively close to a substrate and the top side is relatively far from the substrate. A layer can extend over an entire underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be between any set of horizontal planes that are between and at the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, where it can include one or more layers, and / or can have one or more layers on, above and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more electrically conductive layers and contact layers (where contacts, interconnect lines, and one or more dielectric layers are formed).

[0051] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends in a vertical direction relative to the substrate; "vertical" refers to a direction that is perpendicular to the substrate.

[0052] It should be noted that the drawings provided in the embodiments of the present application only schematically illustrate the basic concepts of the present application, and although only the components related to the present application are shown in the drawings, the actual implementation is not drawn according to the number, shape and size of the components, and the actual implementation of each component can be arbitrarily changed, and the component layout pattern can be more complex.

[0053] Please refer to Figure 1 , Figure 1 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application, please refer to Figures 2a-2k , Figures 2a-2k is a schematic diagram of a structure in a semiconductor device manufacturing process provided by an embodiment of the present application, the method for manufacturing a semiconductor device includes the following steps S1-S4.

[0054] Step S1: providing a substrate 10, the substrate 10 includes a first device region 101 and a second device region 102.

[0055] The substrate 10 can be a semiconductor substrate, for example, it can be a silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI), etc. In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, and can also be a laminated structure, such as Si / SiGe, etc.

[0056] The substrate 10 may include a first device region 101 and a second device region 102. The first device region 101 can be a high-voltage device, i.e., an HVMOS can be formed in the first device region 101; the second device region 102 can be a low-voltage device, i.e., an LVMOS and an LLVMOS can be formed in the second device region 102. The HVMOS has a high-voltage well region (or high-voltage active region), while the LVMOS and LLVMOS have low-voltage well regions (or low-voltage active regions), and the junction depth of the high-voltage well region is deeper than that of the low-voltage well region. In this embodiment, an isolation structure (such as shallow trench isolation (STI)) needs to be formed in each device region to isolate multiple active regions. Because the junction depth of the high-voltage active region is deeper, the depth of the isolation structure in the first device region is also deeper, and the depth of the recess formed in the isolation structure also needs to be deeper to meet the device performance requirements. This embodiment mainly describes the specific formation process related to the isolation structure.

[0057] Step S2: A first isolation structure 1012 is formed in the substrate 10 of the first device region 101, and a second isolation structure 1022 is formed in the substrate 10 of the second device region 102.

[0058] Before step S2, as Figure 2a As shown, a first gate oxide layer 121 located in the first device region 101 and a second gate oxide layer 122 located in the second device region 102 can be formed on the substrate 10 first, wherein the thickness of the first gate oxide layer 121 is greater than the thickness of the second gate oxide layer 122.

[0059] In one specific embodiment, step S2 may include:

[0060] 1) The substrate 10 of the first device region 101 is etched to form a first trench 1011 (e.g., Figures 2a-2b (As shown).

[0061] Specifically, a hard mask layer 13 and a photoresist layer 141 are first formed on the substrate 10 or the gate oxide layer (including the first gate oxide layer 121 and the second gate oxide layer 122). The photoresist layer 141 has a first opening 1410 at a position corresponding to the first device region 101. Then, the substrate 10 is etched based on the first opening 1410 to form a first trench 1011, the depth of which is H0. A dry etching process can be used to form the first trench 1011, and the depth H0 of the first trench 1011 can be... It should be noted that the term "depth" in this article refers to the distance extending downward from the upper surface of the substrate 10 along a longitudinal direction perpendicular to the substrate 10.

[0062] 2) etching the substrate 10 of the first device region 101 and the second device region 102 to form a first isolation groove 1010 at the position of the first trench 1011 and a second isolation groove 1020 at the second device region 102 (as shown in Figures 2c-2d

[0063] Specifically, a second opening 1411 is formed in the photoresist layer 141 at the position corresponding to the second device region 102, and then the substrate 10 is etched based on the first opening 1410 and the second opening 1411 to form the first isolation groove 1010 at the position of the first trench 1011 and the second isolation groove 1020 at the second device region 102, and finally the photoresist layer 141 is removed. The depth H1 of the first isolation groove 1010 in the longitudinal direction is greater than the depth H2 of the second isolation groove 1020 in the longitudinal direction, and the difference between the depths of the first isolation groove 1010 and the second isolation groove 1020 is equal to the depth H0 of the first trench 1011 in the longitudinal direction. For example, the depth H1 of the first isolation groove 1010 can be The depth H2 of the second isolation groove 1020 is The depth H0 of the first trench 1011 can be

[0064] 3) filling the first isolation groove 1010 and the second isolation groove 1020 with a first insulating layer 1013 and a second insulating layer 1021, respectively, to form a first isolation structure 1012 in the substrate 10 of the first device region 101 and a second isolation structure 1022 in the substrate 10 of the second device region 102 (as shown in Figure 2e

[0065] The materials of the first insulating layer 1013 and the second insulating layer 1021 can be the same, both of which can be silicon oxide.

[0066] Step S3: ion implantation is performed on the first isolation structure 1012.

[0067] As shown in Figure 2f the photoresist layer 141 is formed on the hard mask layer 13, and the photoresist layer 141 has a first opening 1410 at the position corresponding to the first isolation structure 1012. The first isolation structure 1012 can be bombarded by an ion implantation process, so that the lattice of the first isolation structure 1012 is scattered, thereby changing the compactness of the first isolation structure 1012 and increasing the etching rate when the first isolation structure 1012 is etched. Since the second isolation structure 1022 is shielded by the photoresist layer 141, the second isolation structure 1022 will not be subjected to the ion implantation process.

[0068] ​​Step S4: Then, the first isolation structure 1012 and the second isolation structure 1022 are etched back to form a first groove 1014 in the first isolation structure 1012 and a second groove 1023 in the second isolation structure 1022. The depth H3 of the first groove 1014 in the longitudinal direction perpendicular to the substrate 10 is greater than the depth H4 of the second groove 1023 in the longitudinal direction.

[0069] like Figure 2g As shown, the first isolation structure 1012 and the second isolation structure 1022 are etched again (etched back) to form a first groove 1014 and a second groove 1023 in the first isolation structure 1012 and the second isolation structure 1022, respectively. Since the etching rate of the first isolation structure 1012 is greater than the etching rate of the second isolation structure 1022, the depth H3 of the first groove 1014 formed by etching is greater than the depth H4 of the second groove 1023.

[0070] After step S4, please refer to Figures 2h-2k The method for fabricating a semiconductor device provided in this embodiment further includes: 1) forming the first gate oxide layer 121 on the sidewall of the first groove 1014, and forming the second gate oxide layer 122 on the sidewall of the second groove 1023 (e.g., Figure 2h As shown, a furnace tube oxidation process can be used to oxidize the exposed substrate 10 surfaces on the sidewalls of the first groove 1014 and the second groove 1023 to form a first gate oxide layer 121 and a second gate oxide layer 122 on the sidewalls of the first groove 1014 and the second groove 1023, respectively. Therefore, the first gate layer 121 is located on the sidewall of the first groove 1014 and the surface of the substrate 10, and the second gate oxide layer 122 is located on the sidewall of the second groove 1023 and the surface of the substrate 10. 2) A first gate layer 151 is formed on the surface of the first gate oxide layer 121, and the first gate oxide layer 121 and the first gate layer 151 form a first gate structure; a second gate layer 152 is formed on the surface of the second gate oxide layer 122, and the second gate oxide layer 122 and the second gate layer 152 form a second gate structure. Specifically, a first gate layer 151 is formed on the surface of the substrate 10 in the first recess 1014 and the first device region 101, and a second gate layer 152 is formed on the surface of the substrate 10 in the second recess 1023 and the second device region 102. The materials of the first gate layer 151 and the second gate layer 152 may include polysilicon, and the thickness of the first gate layer 151 may be greater than the thickness of the second gate layer 152 (e.g., ...). Figure 2iThe first gate layer 151 and the second gate layer 152 are etched to form a first isolation groove 1510 in the first gate layer 151 and a second isolation groove 1520 in the second gate layer 152, the first isolation groove 1510 separates the first gate layer 151 into two parts, and the second isolation groove 1520 separates the second gate layer 152 into two parts, thus forming the first gate layer 151 on the surface of the first gate oxide layer 121 and the second gate layer 152 on the surface of the second gate oxide layer 122 (as shown in FIG. 1C). Figure 2j The first gate layer 151 is isolated by the first isolation groove 1510 in the first isolation structure 1012, and the second gate layer 152 is isolated by the second isolation groove 1520 in the second isolation structure 1022; 4) filling an insulating material 154 (such as silicon dioxide) in the first isolation groove 1510 and the second isolation groove 1520. Figure 2k

[0071] Since the depth of the first recess 1014 is greater than the depth of the second recess 1023, the area of the first gate oxide layer 121 formed on the sidewall of the first recess 1014 is greater than the area of the second gate oxide layer 122 formed on the sidewall of the second recess 1023, which can improve the speed of the device in the first device region 101.

[0072] The preparation method further includes forming a high-voltage well region between the plurality of first isolation structures 1012 and forming a low-voltage well region between the plurality of second isolation structures 1022.

[0073] The preparation method of the semiconductor device provided by the embodiment of the present application first provides a substrate 10 including a first device region 101 and a second device region 102, then forms a first isolation structure 1012 in the substrate 10 of the first device region 101 and a second isolation structure 1022 in the substrate 10 of the second device region 102, then performs ion implantation on the first isolation structure 1012, and then performs etching on the first isolation structure 1012 and the second isolation structure 1022 to form a first recess 1014 in the first isolation structure 1012 and a second recess 1023 in the second isolation structure 1022. Since the etching rate of the first isolation structure 1012 subjected to ion bombardment is faster, the depth of the first recess 1014 is greater than the depth of the second recess 1023, which can meet the requirement of deep junction depth of the first device region 101, thus meeting the requirement of device performance.

[0074] The embodiment of the present application further provides a semiconductor device formed by the above preparation method. Figure 2k ​As shown, the semiconductor device 100 comprises: a substrate 10 comprising a first device region 101 and a second device region 102; a first isolation structure 1012 in the substrate 10 of the first device region 101, the first isolation structure 1012 comprising a first insulating layer 1013 at the bottom; a second isolation structure 1022 in the substrate 10 of the second device region 102, the second isolation structure 1022 comprising a second insulating layer 1021 at the bottom; a first gate structure between the first device region 101 and the first isolation structure 1012 and on the first insulating layer 1013, the first gate structure comprising a first gate oxide layer 121 and a first gate layer 151 on the surface of the first gate oxide layer 121; and a second gate structure between the second device region 102 and the second isolation structure 1022 and on the second insulating layer 1021, the second gate structure comprising a second gate oxide layer 122 and a second gate layer 152 on the surface of the second gate oxide layer 122. Wherein, a depth H3 of the first gate structure (or the first gate oxide layer 121) in a longitudinal direction perpendicular to the substrate 10 is greater than a depth H4 of the second gate structure (or the second gate oxide layer 122) in the longitudinal direction, the first insulating layer 1013 has implanted ions, and the second insulating layer 1021 does not have the implanted ions. Since the depth H3 of the first gate oxide layer 121 is greater than the depth H4 of the second gate oxide layer 122, the area of the first gate oxide layer 121 is greater than the area of the second gate oxide layer 122.

[0075] Preferably, a depth H1 of the first isolation structure 1012 in the longitudinal direction is greater than a depth H2 of the second isolation structure 1022 in the longitudinal direction.

[0076] The semiconductor device 100 further comprises: the first gate structure on the surface of the substrate 10 of the first device region 101; and the second gate structure on the surface of the substrate 10 of the second device region 102.

[0077] The semiconductor device 100 is formed by the preparation method of the semiconductor device provided by the above-mentioned embodiments, and thus has the same beneficial effects as the above-mentioned embodiments, which will not be described herein again.

[0078] The above-mentioned embodiments are only used to help understand the technical solutions and the core ideas of the present application; those skilled in the art should understand that: the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a substrate, the substrate comprising a first device region and a second device region, the first device region being a high-voltage device region, and the second device region being a low-voltage device region; forming a first gate oxide layer on a surface of the substrate in the first device region, and forming a second gate oxide layer on a surface of the substrate in the second device region, the first gate oxide layer having a thickness greater than that of the second gate oxide layer; after forming the first gate oxide layer and the second gate oxide layer, forming a first isolation structure in the substrate in the first device region, and forming a second isolation structure in the substrate in the second device region, the first isolation structure having a depth in a longitudinal direction greater than that of the second isolation structure; performing ion implantation on the first isolation structure; then performing etching-back on the first isolation structure and the second isolation structure to form a first recess in the first isolation structure, and to form a second recess in the second isolation structure, the first recess having a depth in a direction perpendicular to the longitudinal direction greater than that of the second recess; and oxidizing a surface of the substrate exposed by sidewalls of the first recess and the second recess to form a first gate oxide layer and a second gate oxide layer on the sidewalls of the first recess and the second recess, respectively. The depth of the first recess in the longitudinal direction is less than that of the first isolation structure in the longitudinal direction, and the depth of the second recess in the longitudinal direction is less than that of the second isolation structure in the longitudinal direction. The step of forming the first isolation structure in the substrate in the first device region, and forming the second isolation structure in the substrate in the second device region comprises: etching the substrate in the first device region to form a first trench; etching the substrate in the first device region and the second device region to form a first isolation groove in the first trench, and to form a second isolation groove in the second device region; filling a first insulating layer in the first isolation groove, and filling a second insulating layer in the second isolation groove to form the first isolation structure in the substrate in the first device region, and to form the second isolation structure in the substrate in the second device region; wherein the depth of the first isolation groove in the longitudinal direction is greater than that of the second isolation groove in the longitudinal direction, and the difference between the depths of the first isolation groove and the second isolation groove is equal to the depth of the first trench in the longitudinal direction. 4.The method according to claim 1, further comprising: forming a first gate layer on a surface of the first gate oxide layer to form a first gate structure comprising the first gate oxide layer and the first gate layer; and forming a second gate layer on a surface of the second gate oxide layer to form a second gate structure comprising the second gate oxide layer and the second gate layer. 5.A semiconductor device manufactured by the method according to claim 1, comprising: a substrate comprising a first device region and a second device region; a first isolation structure in the substrate in the first device region, the first isolation structure comprising a first insulating layer at a bottom; and a first gate structure in the substrate in the first device region, the first gate structure comprising a first gate oxide layer and a first gate layer. ​ ​ 2. The method of producing a semiconductor device according to claim 1, wherein ​ 3. The method of producing a semiconductor device according to claim 1, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ a second isolation structure in the substrate at the second device region, the second isolation structure including a second insulating layer at a bottom; a first gate structure between the first device region and the first isolation structure and on the first insulating layer; a second gate structure between the second device region and the second isolation structure and on the second insulating layer; wherein the first insulating layer has implanted ions therein and the second insulating layer does not have the implanted ions therein; the first gate structure has a depth in a longitudinal direction perpendicular to the substrate that is greater than a depth of the second gate structure in the longitudinal direction.

6. The semiconductor device of claim 5, wherein, the first isolation structure has a depth in the longitudinal direction that is greater than a depth of the second isolation structure in the longitudinal direction.

7. The semiconductor device of claim 5, further comprising: the first gate structure at a substrate surface at the first device region; the second gate structure at a substrate surface at the second device region.

8. The semiconductor device of claim 7, wherein, the first gate structure includes a first gate oxide layer and a first gate layer at a surface of the first gate oxide layer; the second gate structure includes a second gate oxide layer and a second gate layer at a surface of the second gate oxide layer.

9. The semiconductor device of claim 8, wherein, an area of the first gate oxide layer is greater than an area of the second gate oxide layer.

Images