Cache management in the memory subsystem

Abstract

The present application is directed to cache management in a memory subsystem. An interface controller may include a first buffer and a second buffer. The interface controller may use the first buffer and the second buffer to facilitate operating a volatile memory as a cache for a non-volatile memory. During an access operation, the interface controller may use the buffer to transfer data between the volatile memory, the non-volatile memory, and another device. In response to the access operation, the interface controller may use the second buffer to transfer second data from the volatile memory to the non-volatile memory.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 042,953, entitled “CACHE MANAGEMENT IN A MEMORY SUBSYSTEM,” filed by BALLAPURAM et al. on June 23, 2020, which is assigned to the assignee of the present invention, and the entire contents of the provisional patent application are expressly incorporated herein by reference.

[0003] The technical field relates to cache management in memory subsystems. Background Art

[0004] The following relates generally to one or more memory systems and, more particularly, to cache management in a memory subsystem.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells in the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, usually represented by a logical 1 or a logical 0. In some instances, a single memory cell can support more than two states, either of which can be stored. To access the stored information, a component can read or sense at least one storage state in the memory device. To store information, a component can write or program a state in the memory device.

[0006] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selection memory, chalcogenide memory technology, etc. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can retain its stored logic state for a long time even in the absence of external power. Volatile memory devices, such as DRAM, may lose their stored state when disconnected from the external power supply. Summary of the invention

[0007] An apparatus is described. The apparatus may include a nonvolatile memory; a volatile memory; and an interface controller coupled to the nonvolatile memory and the volatile memory. The interface controller may include a buffer and may be operable to: receive a command from a host device to write data to a memory address of the nonvolatile memory, the memory address being associated with a group of memory cells in a memory bank of the volatile memory; store the data in the buffer based at least in part on the command, the buffer having a storage capacity corresponding to a page size of the volatile memory; determine storage information of a group of memory cells in a memory bank of the volatile memory after storing the data in the buffer; and transfer the data from the buffer to a group of memory cells in a memory bank of the volatile memory based at least in part on the storage information of the group of memory cells.

[0008] An apparatus is described. The apparatus may include a nonvolatile memory; a volatile memory; and an interface controller coupled to the nonvolatile memory and the volatile memory. The interface controller may include a buffer and may be operable to: receive a command from a host device to read data from a memory address of the nonvolatile memory, the memory address being associated with a group of memory cells in a memory bank of the volatile memory; determine storage information of the group of memory cells in a memory bank of the volatile memory; and transfer data from the volatile memory or the nonvolatile memory, and based at least in part on the storage information of the group of memory cells, to the buffer in the interface controller, the buffer having a storage capacity corresponding to a page size of the volatile memory.

[0009] A device is described. The device may include a nonvolatile memory; a volatile memory including a memory bank; and an interface controller. The interface controller may include: a first buffer coupled to the memory bank of the volatile memory, the first buffer having a capacity corresponding to a page size of the volatile memory and configured to store data indicated by an access command; and a second buffer coupled to the memory bank of the volatile memory, the second buffer having a capacity corresponding to a page size of the volatile memory and configured to store data for transfer between the volatile memory and the nonvolatile memory.

[0010] A device is described. The device may include a ferroelectric random access memory (FeRAM); a dynamic random access memory (DRAM); and an interface controller coupled to the FeRAM and the DRAM. The interface controller may include a static random access memory (SRAM) buffer and is operable to: receive a command from a system on a chip (SoC) to access a memory address of the FeRAM, the memory address being associated with a group of memory cells in a bank of the DRAM; store data associated with the command in the SRAM buffer, the SRAM buffer having a storage capacity corresponding to a page size of the DRAM and coupled to the DRAM and the FeRAM; and transmit data from the SRAM buffer based at least in part on the command. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a system supporting cache management in a memory subsystem according to examples disclosed herein is shown.

[0012] Figure 2 An example of a memory subsystem supporting cache management according to examples disclosed herein is shown.

[0013] Figure 3 An example of a process flow to support cache management in a memory subsystem according to examples disclosed herein is shown.

[0014] Figure 4 An example of a process flow to support cache management in a memory subsystem according to examples disclosed herein is shown.

[0015] Figure 5 A block diagram of a memory subsystem supporting cache management according to aspects of the present disclosure is shown.

[0016] Figures 6 to 8 A flow chart is shown illustrating one or more methods of supporting cache management in a memory subsystem according to examples disclosed herein. DETAILED DESCRIPTION

[0017] A memory system may include one or more memory devices as main memory (e.g., primary memory for storing information and other operations) for a host device (e.g., a system on a chip (SoC) or a processor). For example, a memory system may include non-volatile memory (e.g., FeRAM) that stores data for the memory system. Non-volatile memory may provide benefits such as non-volatility, higher capacity, and lower power consumption compared to volatile memory. However, various incompatibilities or inefficiencies may exist between non-volatile memory and the host device. For example, the host device and the non-volatile memory may support features such as different latencies, page sizes, or communication protocols.

[0018] According to the technology described herein, incompatibility or inefficiency between a host device and a non-volatile memory can be solved by including a volatile memory in a memory system and using the volatile memory as a cache. A controller may be included in the memory system as an intermediary between the host device, the volatile memory and the non-volatile memory and other components. The controller may include one or more buffers that can facilitate the operation of the volatile memory as a cache. For example, the controller may include a first buffer and a second buffer for each memory bank of the volatile memory. In addition to other advantages, in order to simplify the transfer process, the buffer may have a storage capacity corresponding to (e.g., equal to) the page size of the volatile memory. The controller may use the first buffer of the memory bank of the volatile memory to store data for transmission between the host device, the volatile memory or the non-volatile memory (e.g., during an access process) or any combination thereof. The controller may use the second buffer of the memory bank of the volatile memory to store data for transmission from the volatile memory to the non-volatile memory (e.g., as part of an expulsion process to release space in the volatile memory for new data).

[0019] The features of this disclosure are initially described in reference Figure 1 and 2 The features of the present disclosure are described in the context of the memory systems and subsystems described herein. Figure 3 and 4 These and other features of the present disclosure are described in the context of the process flow described herein. Figure 5-8 The device diagrams and flow charts described herein related to cache management in a memory subsystem are further illustrated and described.

[0020] Figure 1An example of a memory system 100 supporting cache management in a memory subsystem according to an example disclosed herein is shown. The memory system 100 may be included in an electronic device such as a computer or a phone. The memory system 100 may include a host device 105 and a memory subsystem 110. The host device 105 may be a processor or a system on a chip (SoC) connected to an interface controller 115 and other components of the electronic device including the memory system 100. The memory subsystem 110 may store electronic information (e.g., digital information, data) for the host device 105 and provide access to the electronic information. The memory subsystem 110 may include an interface controller 115, a volatile memory 120, and a non-volatile memory 125. In some examples, the interface controller 115, the volatile memory 120, and the non-volatile memory 125 may be included in the same physical package, such as package 130. However, the interface controller 115, the volatile memory 120, and the non-volatile memory 125 may be disposed on different respective dies (e.g., silicon dies).

[0021] The devices in the memory system 100 may be coupled via various wires (e.g., traces, printed circuit board (PCB) wiring, redistribution layer (RDL) wiring), which may enable information (e.g., commands, addresses, data) communication between the devices. The wires may constitute a channel, a data bus, a command bus, an address bus, etc.

[0022] The memory subsystem 110 can be configured to provide the benefits of the non-volatile memory 125 while maintaining compatibility with a host device 105 that supports protocols of different types of memory (e.g., volatile memory 120, etc.). For example, the non-volatile memory 125 can provide benefits such as non-volatility, higher capacity, or lower power consumption (e.g., relative to the volatile memory 120). However, the host device 105 may be incompatible with or inefficiently configured for various aspects of the non-volatile memory 125. For example, the host device 105 may support voltages, access latencies, protocols, page sizes, etc. that are incompatible with the non-volatile memory 125. In order to compensate for the incompatibility between the host device 105 and the non-volatile memory 125, the memory subsystem 110 can be configured with a volatile memory 120 that is compatible with the host device 105 and used as a cache for the non-volatile memory 125. Therefore, the host device 105 can use the protocols supported by the volatile memory 120 while benefiting from the advantages of the non-volatile memory 125.

[0023] In some instances, the memory system 100 may be included in a computing device, an electronic device, a mobile computing device, or a wireless device, or coupled thereto. The device may be a portable electronic device. For example, the device may be a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet connection device, etc. In some instances, the device may be configured to perform two-way wireless communication through a base station or an access point. In some instances, the device associated with the memory system 100 may be capable of machine type communication (MTC), machine to machine (M2M) communication, or device to device (D2D) communication. In some instances, the device associated with the memory system 100 may be referred to as a user equipment (UE), a station (STA), a mobile terminal, etc.

[0024] The host device 105 may be configured to interface with the memory subsystem 110 using a first protocol (e.g., low power double data rate (LPDDR)) supported by the interface controller 115. Thus, in some instances, the host device 105 may interface directly with the interface controller 115 and indirectly with the non-volatile memory 125 and the volatile memory 120. In alternative instances, the host device 105 may interface directly with the non-volatile memory 125 and the volatile memory 120. The host device 105 may also interface with other components of the electronic device including the memory system 100. The host device 105 may be or include a SoC, a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In some instances, the host device 105 may be referred to as a host.

[0025] The interface controller 115 can be configured to interface with the volatile memory 120 and the non-volatile memory 125 on behalf of the host device 105 (e.g., based on one or more commands or requests issued by the host device 105). For example, the interface controller 115 can facilitate the retrieval and storage of data in the volatile memory 120 and the non-volatile memory 125 on behalf of the host device 105. Thus, the interface controller 115 can facilitate data transfer between various subcomponents, such as data transfer between at least some of the host device 105, the volatile memory 120, or the non-volatile memory 125. The interface controller 115 can interface with the host device 105 and the volatile memory 120 using a first protocol, and can interface with the non-volatile memory 125 using a second protocol supported by the non-volatile memory 125.

[0026] The non-volatile memory 125 may be configured to store digital information (e.g., data) of an electronic device including the memory system 100. Thus, the non-volatile memory 125 may include one or more memory cell arrays and a local memory controller configured to operate the memory cell arrays. In some instances, the memory cells may be or include FeRAM cells (e.g., the non-volatile memory 125 may be FeRAM). The non-volatile memory 125 may be configured to interface with the interface controller 115 using a second protocol that is different from the first protocol used between the interface controller 115 and the host device 105. In some instances, the non-volatile memory 125 may have a longer access operation latency than the volatile memory 120. For example, retrieving data from the non-volatile memory 125 may take longer than retrieving data from the volatile memory 120. Similarly, writing data to the non-volatile memory 125 may take longer than writing data to the volatile memory 120. In some examples, as described herein, non-volatile memory 125 can have a smaller page size than volatile memory 120 .

[0027] The volatile memory 120 may be configured to function as a cache for one or more components, such as the non-volatile memory 125. For example, the volatile memory 120 may store information (e.g., data) of an electronic device including the memory system 100. Thus, the volatile memory 120 may include one or more memory cell arrays and a local memory controller configured to operate the memory cell arrays. In some examples, the memory cells may be or include DRAM cells (e.g., the volatile memory may be a DRAM). The non-volatile memory 125 may be configured to interface with the interface controller 115 using a first protocol used between the interface controller 115 and the host device 105.

[0028] In some instances, the volatile memory 120 may have a shorter access operation latency than the nonvolatile memory 125. For example, it takes less time to retrieve data from the volatile memory 120 than to retrieve data from the nonvolatile memory 125. Similarly, it takes less time to write data to the volatile memory 120 than to write data to the nonvolatile memory 125. In some instances, the volatile memory 120 may have a larger page size than the nonvolatile memory 125. For example, the page size of the volatile memory 120 may be 2 kilobytes (2kB), and the page size of the nonvolatile memory 125 may be 64 bytes (64B) or 128 bytes (128B).

[0029] Although non-volatile memory 125 may be a higher density memory than volatile memory 120, accessing non-volatile memory 125 may take longer than accessing volatile memory 120 (e.g., due to different architectures and protocols, among other reasons). Therefore, operating volatile memory 120 as a cache may reduce latency in memory system 100. As an example, access requests for data from host device 105 may be satisfied relatively quickly by retrieving data from volatile memory 120 rather than from non-volatile memory 125. To facilitate operation of volatile memory 120 as a cache, interface controller 115 may include a plurality of buffers 135. Buffers 135 may be provided on the same die as interface controller 115 and may be configured to temporarily store data for transfer between volatile memory 120, non-volatile memory 125, or host device 105 (or any combination thereof) during one or more access operations (e.g., storage and retrieval operations).

[0030] An access operation may also be referred to as an access process or an access procedure, and may include one or more sub-operations performed by one or more components of the memory subsystem 110. Examples of access operations may include storage operations, in which data provided by the host device 105 is stored (e.g., written) in the volatile memory 120 or the non-volatile memory 125 (or both), and retrieval operations, in which data requested by the host device 105 is obtained (e.g., read) from the volatile memory 120 or the non-volatile memory 125 and returned to the host device 105.

[0031] To store data in the memory subsystem 110, the host device 105 may initiate a storage operation (or "storage process") by sending a storage command (also referred to as a storage request, a write command, or a write request) to the interface controller 115. The storage command may be directed to a group of nonvolatile memory cells in the nonvolatile memory 125. In some instances, a group of memory cells may also be referred to as a portion of a memory. The host device 105 may also provide the interface controller 115 with data to be written to a group of nonvolatile memory cells. The interface controller 115 may temporarily store the data in a buffer 135-a. After storing the data in the buffer 135-a, the interface controller 115 may transfer the data from the buffer 135-a to the volatile memory 120 or the nonvolatile memory 125, or both. In a write-through mode, the interface controller 115 may transfer the data to both the volatile memory 120 and the nonvolatile memory 125. In a write-back mode, the interface controller 115 may transfer the data only to the volatile memory 120.

[0032] In either mode, the interface controller 115 may identify an appropriate group of one or more volatile memory cells in the volatile memory 120 for storing data associated with the storage command. To this end, the interface controller 115 may implement a group-associative mapping, wherein each group (e.g., block) of one or more non-volatile memory cells in the non-volatile memory 125 may be mapped to multiple groups of volatile memory cells in the volatile memory 120. For example, the interface controller 115 may implement an n-way associative mapping, which allows data from a group of non-volatile memory cells to be stored in one of n groups of volatile memory cells in the volatile memory 120. Thus, the interface controller 115 may manage the volatile memory 120 as a cache of the non-volatile memory 125 by referencing the n groups of volatile memory cells associated with the target group of non-volatile memory cells. As used herein, a "group" of objects may refer to one or more objects unless otherwise described or illustrated. Although described with reference to set associative mapping, interface controller 115 may manage volatile memory 120 as a cache by implementing one or more other types of mapping, such as direct mapping or associative mapping.

[0033] After determining which n groups of volatile memory cells are associated with the target group of non-volatile memory cells, the interface controller 115 may store the data in one or more of the n groups of volatile memory cells. In this way, a subsequent retrieval command for data from the host device 105 may be efficiently satisfied by retrieving the data from the low latency volatile memory 120 rather than retrieving the data from the high latency non-volatile memory 125. The interface controller 115 may determine which group of the n groups of volatile memory 120 to store the data based on one or more parameters associated with the data stored in the n groups of volatile memory 120, such as the validity, age, or modification status of the data. Thus, a storage command of the host device 105 may be satisfied in full (e.g., in a write-back mode) or in part (e.g., in a write-through mode) by storing the data in the volatile memory 120. To track data stored in the volatile memory 120, the interface controller 115 may store a tag address for one or more groups of volatile memory cells (e.g., for each group of volatile memory cells) that indicates the non-volatile memory cells having data stored in a given group of volatile memory cells.

[0034] To retrieve data from the memory subsystem 110, the host device 105 may initiate a retrieval operation (also referred to as a retrieval process) by sending a retrieval command (also referred to as a retrieval request, a read command, or a read request) to the interface controller 115. The retrieval command may be directed to a group of one or more non-volatile memory cells in the non-volatile memory 125. Upon receiving the retrieval command, the interface controller 115 may check the volatile memory 120 for the requested data. For example, the interface controller 115 may check the n groups of volatile memory cells associated with the target group of non-volatile memory cells for the requested data. If one of the n groups of volatile memory cells stores the requested data (e.g., the data of the target group of non-volatile memory cells is stored), the interface controller 115 may transfer the data from the volatile memory 120 to the buffer 135-a (e.g., in response to determining that one of the n groups of volatile memory cells stores the requested data, such as Figure 4 and 5 ), so that it can be transferred to the host device 105. The term "hit" may be used to refer to a situation where the volatile memory 120 stores the data requested by the host device 105. If the n groups of one or more volatile memory cells do not store the requested data (e.g., the n groups of volatile memory cells store data of a group of non-volatile memory cells other than the target group of non-volatile memory cells), the interface controller 115 may transfer the requested data from the non-volatile memory 125 to the buffer 135-a (e.g., in response to determining that the n groups of volatile memory cells do not store the requested data, as described in reference to Figure 4 and 5 105) so that it can be transferred to the host device 105. The term "miss" may be used to refer to a situation where the volatile memory 120 does not store the data requested by the host device 105.

[0035] In the case of a miss, after transferring the requested data to buffer 135-a, interface controller 115 may transfer the requested data from buffer 135-a to volatile memory 120 so that subsequent read requests for the data may be satisfied by volatile memory 120 instead of non-volatile memory 125. For example, interface controller 115 may store data in one of n groups of volatile memory cells associated with a target group of non-volatile memory cells. However, n groups of volatile memory cells may already be storing data for other groups of non-volatile memory cells. Therefore, in order to save the other data, interface controller 115 may transfer the other data to buffer 135-b so that it can be transferred to non-volatile memory 125 for storage. Such a process may be referred to as "eviction", and the data transferred from volatile memory 120 to buffer 135-b may be referred to as "victim" data. In some cases, interface controller 115 may transfer a subset of the victim data from buffer 135-b to non-volatile memory 125. For example, the interface controller 115 may transmit one or more subsets of the victim data that have changed since the data was originally stored in the non-volatile memory 125. Data that is inconsistent between the volatile memory 120 and the non-volatile memory 125 (e.g., due to updates in one memory but not the other) may be referred to as "modified" or "dirty" data in some cases. In some instances (e.g., when the interface controller is operating in a mode such as a write-back mode), dirty data may be data that is present in the volatile memory 120 but not in the non-volatile memory 125.

[0036] Figure 2 An example of a memory subsystem 200 supporting cache management in a memory subsystem according to an example disclosed herein is shown. The memory subsystem 200 may be a reference Figure 1 Thus, as shown in FIG. Figure 1 As described, the memory subsystem 200 can interact with a host device. The memory subsystem 200 may include an interface controller 202, a volatile memory 204, and a non-volatile memory 206, as shown in FIG. Figure 1 As described, they may be instances of interface controller 115, volatile memory 120, and non-volatile memory 125, respectively. Figure 1As described, the interface controller 202 can interface with the volatile memory 204 and the non-volatile memory 206 on behalf of the host device. For example, the interface controller 202 can operate the volatile memory 204 as a cache for the non-volatile memory 206. Operating the volatile memory 204 as a cache can allow the subsystem to provide the benefits of the non-volatile memory 206 (e.g., non-volatility, high-density storage) while maintaining compatibility with host devices that support a different protocol than the non-volatile memory 206.

[0037] exist Figure 2 In the figure, the dashed lines between components represent data flow or data communication paths, and the solid lines between components represent command flow or command communication paths. In some cases, memory subsystem 200 is one of multiple similar or identical subsystems that can be included in an electronic device. In some instances, each subsystem can be referred to as a slice and can be associated with a corresponding channel of a host device.

[0038] The nonvolatile memory 206 may be configured to operate as a main memory of a host device (e.g., a memory for long-term data storage). In some cases, the nonvolatile memory 206 may include one or more FeRAM cell arrays. Each FeRAM cell may include a selection component and a ferroelectric capacitor, and may be accessed by applying an appropriate voltage to one or more access lines (e.g., a word line, a plate line, and a digital line). In some instances, a subset of FeRAM cells coupled to an activated word line may be sensed, for example, simultaneously or synchronously, without having to sense all FeRAM cells coupled to the activated word line. Therefore, the page size of the FeRAM array may be different from (e.g., smaller than) the page size of a DRAM. In the context of a memory device, a page may refer to a memory cell in a row (e.g., a group of memory cells having a common row address), and a page size may refer to the number of memory cells or column addresses in a row, or the number of column addresses accessed during an access operation. Alternatively, the page size may refer to the size of data handled by various interfaces. In some cases, different memory device types may have different page sizes. For example, the page size of DRAM (eg, 2 kB) may be a superset of the page size of non-volatile memory (eg, FeRAM) (eg, 64 B).

[0039] Since a single FeRAM cell may require more power to read or write than a single DRAM cell, a smaller page size of a FeRAM array may provide various efficiency advantages. For example, a smaller page size may promote efficient energy usage for a FeRAM array because a smaller number of FeRAM cells may be activated when the associated information changes are small. In some examples, the page size of a FeRAM cell array may be varied, for example dynamically (e.g., during operation of the FeRAM cell array), depending on the nature of the data and commands operating with the FeRAM.

[0040] Although a single FeRAM cell may require more power to read or write than a single DRAM cell, a FeRAM cell can retain its stored logic state for an extended period of time without external power because the ferroelectric material in the FeRAM cell can maintain a non-zero electric polarization in the absence of an electric field. Therefore, including a FeRAM array in non-volatile memory 206 can provide efficiency advantages over volatile memory cells (e.g., DRAM cells in volatile memory 204) because it can reduce or eliminate the need to perform refresh operations.

[0041] The volatile memory 204 may be configured to serve as a cache for the non-volatile memory 206. In some cases, the volatile memory 204 may include one or more DRAM cell arrays. Each DRAM cell may include a capacitor including a dielectric material to store a charge representing a programmable state. The memory cells of the volatile memory 204 may be logically grouped or arranged into one or more memory banks (referred to herein as "memory banks"). For example, the volatile memory 204 may include sixteen memory banks. The memory cells of the memory banks may be arranged in a grid or array of crossed columns and rows, and each memory cell may be accessed or refreshed by applying appropriate voltages to the digital lines (e.g., column lines) and word lines (e.g., row lines) of the memory cells. The rows of the memory banks may refer to pages, and the page size may refer to the number of columns or memory cells in a row. As described above, the page size of the volatile memory 204 may be different from (e.g., greater than) the page size of the non-volatile memory 206.

[0042] The interface controller 202 may include various circuits for interfacing (e.g., communicating) with other devices such as a host device, volatile memory 204, and non-volatile memory 206. For example, the interface controller 202 may include a data bus interface 208, a command and address (C / A) bus interface 210, a data bus interface 212, a C / A bus interface 214, a data bus interface 216, and a C / A bus interface 264. The data bus interfaces may support information communication using one or more communication protocols. For example, the data bus interface 208, the C / A bus interface 210, the data bus interface 216, and the C / A bus interface 264 may support information transmitted using a first protocol (e.g., LPDDR signaling), while the data bus interface 212 and the C / A bus interface 214 may support information transmitted using a second protocol. Therefore, the various bus interfaces coupled to the interface controller 202 may support different amounts of data or data rates.

[0043] The data bus interface 208 may be coupled to the data bus 260, the transaction bus 222, and the buffer circuit 224. The data bus interface 208 may be configured to send and receive data via the data bus 260, and to send and receive control information (e.g., confirmation / negative confirmation) or metadata via the transaction bus 222. The data bus interface 208 may also be configured to transfer data between the data bus 260 and the buffer circuit 224. The data bus 260 and the transaction bus 222 may be coupled to the interface controller 202 and the host device so that a conductive path is established between the interface controller 202 and the host device. In some examples, the pins of the transaction bus 222 may be referred to as data mask inversion (DMI) pins. Although one data bus 260 and one transaction bus 222 are shown, there may be any number of data buses 260 and any number of transaction buses 222 coupled to one or more data bus interfaces 208.

[0044] The C / A bus interface 210 may be coupled to the C / A bus 226 and the decoder 228. The C / A bus interface 210 may be configured to send and receive commands and addresses via the C / A bus 226. The commands and addresses received via the C / A bus 226 may be associated with data received or sent via the data bus 260. The C / A bus interface 210 may also be configured to send the commands and addresses to the decoder 228 so that the decoder 228 may decode the commands and relay the decoded commands and associated addresses to the command circuit 230.

[0045] The data bus interface 212 may be coupled to the data bus 232 and the memory interface circuit 234. The data bus interface 212 may be configured to send and receive data via the data bus 232, which may be coupled to the non-volatile memory 206. The data bus interface 212 may also be configured to transfer data between the data bus 232 and the memory interface circuit 234. The C / A bus interface 214 may be coupled to the C / A bus 236 and the memory interface circuit 234. The C / A bus interface 214 may be configured to receive commands and addresses from the memory interface circuit 234 and relay the commands and addresses to the non-volatile memory 206 (e.g., to a local controller of the non-volatile memory 206) via the C / A bus 236. The commands and addresses sent via the C / A bus 236 may be associated with the data received or sent via the data bus 232. The data bus 232 and the C / A bus 236 may be coupled to the interface controller 202 and the nonvolatile memory 206 such that a conductive path is established between the interface controller 202 and the nonvolatile memory 206 .

[0046] The data bus interface 216 may be coupled to the data bus 238 and the memory interface circuit 240. The data bus interface 216 may be configured to send and receive data via the data bus 238, which may be coupled to the volatile memory 204. The data bus interface 216 may also be configured to transfer data between the data bus 238 and the memory interface circuit 240. The C / A bus interface 264 may be coupled to the C / A bus 242 and the memory interface circuit 240. The C / A bus interface 264 may be configured to receive commands and addresses from the memory interface circuit 240 and relay the commands and addresses to the volatile memory 204 (e.g., to a local controller of the volatile memory 204) via the C / A bus 242. The commands and addresses sent via the C / A bus 242 may be associated with the data received or sent via the data bus 238. The data bus 238 and the C / A bus 242 may be coupled to the interface controller 202 and the volatile memory 204 such that a conductive path is established between the interface controller 202 and the volatile memory 204 .

[0047] In addition to the bus and bus interface for communicating with the coupled device, the interface controller 202 may include circuits for operating the non-volatile memory 206 as main memory and the volatile memory 204 as cache. For example, the interface controller 202 may include command circuit 230, buffer circuit 224, cache management circuit 244, one or more engines 246, and one or more schedulers 248.

[0048] Command circuitry 230 may be coupled to buffer circuitry 224, decoder 228, cache management circuitry 244, and scheduler 248, among other components. Command circuitry 230 may be configured to receive command and address information from decoder 228 and store the command and address information in queue 250. Command circuitry 230 may include logic 262 that processes command information (e.g., from a host device) and stored information from other components (e.g., cache management circuitry 244, buffer circuitry 224) and uses the information to generate one or more commands for scheduler 248. Command circuitry 230 may also be configured to transmit address information (e.g., address bits) to cache management circuitry 244. In some examples, the logic 262 ... 262 The circuit may be configured to operate as a finite state machine (FSM).

[0049] Buffer circuits 224 may be coupled to data bus interface 208, command circuits 230, memory interface circuits 234, and memory interface circuits 234. Buffer circuits 224 may include a set of one or more buffer circuits for at least some of the memory banks (if not each memory bank) of volatile memory 204. Buffer circuits 224 may also include components (e.g., a memory controller) for accessing the buffer circuits. In one example, volatile memory 204 may include sixteen memory banks, and buffer circuits 224 may include sixteen sets of buffer circuits. Each set of buffer circuits may be configured to store data from or for a corresponding memory bank of volatile memory 204 (or both). As an example, the buffer circuit group for storage body 0 (BK0) can be configured to store data from the first storage body of volatile memory 204 or store data for the first storage body of the volatile memory (or both), and the buffer circuit group for storage body 15 (BK15) can be configured to store data from the sixteenth storage body of volatile memory 204 or store data for the sixteenth storage body of the volatile memory (or both).

[0050] Each group of buffer circuits in the buffer circuit 224 may include a pair of buffers. The pair of buffers may include one buffer (e.g., an open page data (OPD) buffer) configured to store data targeted by an access command (e.g., a store command or a retrieve command) from a host device, and another buffer (e.g., a victim page data (VPD) buffer) configured to store data of an eviction process caused by the access command. For example, the buffer circuit group of BK0 may include buffer 218 and buffer 220, which may be instances of buffers 135-a and 135-b, respectively. Buffer 218 may be configured to store BK0 data targeted by an access command from a host device. And buffer 220 may be configured to store data transmitted from BK0 as part of an eviction process triggered by an access command. Each buffer in the buffer circuit group may be configured with a size (e.g., storage capacity) corresponding to the page size of the volatile memory 204. For example, if the page size of the volatile memory 204 is 2kB, the size of each buffer may be 2kB. Thus, in some instances, the size of the buffer may be equal to the page size of volatile memory 204 .

[0051] The cache management circuit 244 may be coupled to the command circuit 230, the engine 246, and the scheduler 248, among other components. The cache management circuit 244 may include a cache management circuit group for one or more memory banks (e.g., each memory bank) of the volatile memory. As an example, the cache management circuit 244 may include sixteen cache management circuit groups for BK0 to BK15. Each cache management circuit group may include two memory arrays, which may be configured to store storage information of the volatile memory 204. For example, the cache management circuit group of BK0 may include a memory array 252 (e.g., a CDRAM tag array (CDT-TA)) and a memory array 254 (e.g., a CDRAM valid (CDT-V) array), which may be configured to store storage information of BK0. In some instances, a memory array may also be referred to as an array or a buffer. In some cases, the memory array may be or include a volatile memory cell, such as an SRAM cell.

[0052] The storage information may include content information, validity information, or dirty information (or any combination thereof) associated with the volatile memory 204. The content information (which may also be referred to as tag information or address information) may indicate which data is stored in a group of volatile memory cells. For example, the content information (e.g., tag address) of a group of one or more volatile memory cells may indicate which group of one or more non-volatile memory cells currently has the data stored in the group of one or more volatile memory cells. The validity information may indicate whether the data stored in the group of volatile memory cells is actual data (e.g., data with an expected order or form) or placeholder data (e.g., random or virtual data with no expected or significant order). And the dirty information may indicate whether the data stored in the group of one or more volatile memory cells of the volatile memory 204 is different from the corresponding data in the group of one or more non-volatile memory cells of the non-volatile memory 206. For example, the dirty information may indicate whether the data stored in the group of volatile memory cells has been updated relative to the data stored in the non-volatile memory 206.

[0053] The memory array 252 may include memory cells that store storage information (e.g., content and validity information) of an associated memory bank (e.g., BK0) of the volatile memory 204. The storage information may be stored on a per-page basis (e.g., each page of an associated non-volatile memory bank may have corresponding storage information). The interface controller 202 may check the requested data in the volatile memory 204 by referencing the storage information in the memory array 252. For example, the interface controller 202 may receive a retrieval command for data in a group of non-volatile memory cells in the non-volatile memory 206 from a host device. The interface controller 202 may reference the storage information in the memory array 252 using a group of one or more address bits (e.g., a group of row address bits) to which the access request is directed. For example, using a group-associative mapping, the interface controller 202 may reference the content information in the memory array 252 to determine which group of volatile memory cells (if any) stores the requested data.

[0054] In addition to storing content information of volatile memory cells, the memory array 252 may also store validity information indicating whether the data in a group of volatile memory cells is actual data (also referred to as valid data) or random data (also referred to as invalid data). For example, the volatile memory cells in the volatile memory 204 may initially store random data and continue to do so until the volatile memory cells are written with data from the host device or the non-volatile memory 206. In order to keep track of which data is valid, the memory array 252 may be configured to set one bit for each group of volatile memory cells when actual data is stored in the group of volatile memory cells. This bit may be referred to as a valid bit or a valid flag. As with the content information, the validity information stored in the memory array 252 may be stored on a per-page basis. Thus, in some instances, each validity bit may indicate the validity of the data stored in the associated page.

[0055] The memory array 254 may be similar to the memory array 252 and may also include memory cells that store validity information of a bank (e.g., BK0) of the volatile memory 204 associated with the memory array 252. However, the validity information stored in the memory array 254 may be stored on a sub-block basis rather than on a per-page basis of the memory array 252. For example, the validity information stored in the memory cells of the memory array 254 may indicate the validity of data of a subset of volatile memory cells in a group (e.g., a page) of volatile memory cells. As an example, the validity information in the memory array 254 may indicate the validity of each subset of data (e.g., 64B) in a page of data stored in BK0 of the volatile memory 204. Storing content information and validity information on a per-page basis in the memory array 252 may allow the interface controller 202 to quickly and efficiently determine whether data in the volatile memory 204 is a hit or a miss. Storing validity information on a sub-block basis may allow the interface controller 202 to determine which subsets of data to retain in the non-volatile memory 206 during the eviction process.

[0056] Each cache management circuit group may also include a corresponding register pair coupled to the command circuit 230, the engine 246, the memory interface circuit 234, the memory interface circuit 240, and the memory array and other components for the cache management circuit group. For example, the cache management circuit group may include a first register (e.g., register 256, which may be an open page tag (OPT) register) configured to receive storage information (e.g., one or more bits of tag information, validity information, or dirty information) from the memory array 252 or the scheduler 248-b or both. The cache management circuit group may also include a second register (e.g., register 258, which may be a victim page tag (VPT) register) configured to receive storage information from the memory array 254 and the scheduler 248-a or both. The information in registers 256 and 258 may be transmitted to the command circuit 230 and the engine 246 to enable these components to make decisions. For example, the command circuit 230 may issue a command for reading the non-volatile memory 206 or the volatile memory 204 based on the content information from the register 256.

[0057] The engine 246-a may be coupled to the register 256, the register 258, and the scheduler 248. The engine 246-a may be configured to receive storage information from various components and issue commands to the scheduler 248 based on the storage information. For example, when the interface controller 202 is in a first mode such as a write-through mode, the engine 246-a may issue commands to the scheduler 248-b, and in response, the scheduler 248-b initiates or facilitates the transfer of data from the buffer 218 to both the volatile memory 204 and the non-volatile memory 206. Alternatively, when the interface controller 202 is in a second mode such as a write-back mode, the engine 246-a may issue commands to the scheduler 248-b, and in response, the scheduler 248-b may initiate or facilitate the transfer of data from the buffer 218 to the volatile memory 204. In the case of a write-back operation, the data stored in the volatile memory 204 may eventually be transferred to the non-volatile memory 206 in a subsequent eviction process.

[0058] The engine 246-b may be coupled to the register 258 and the scheduler 248-a. The engine 246-b may be configured to receive storage information from the register 258 and to issue commands to the scheduler 248-a based on the storage information. For example, the engine 246-b may issue a command to the scheduler 248-a to initiate or facilitate the transfer of dirty data from the buffer 220 to the non-volatile memory 206 (e.g., as part of an eviction process). If the buffer 220 holds a set of data (e.g., victim data) transferred from the volatile memory 204, the engine 246-b may indicate which subset or subsets (e.g., which 64B) of the set of data in the buffer 220 should be transferred to the non-volatile memory 206.

[0059] The scheduler 248-a can be coupled to various components of the interface controller 202 and can facilitate access to the non-volatile memory 206 by issuing commands to the memory interface circuit 234. The commands issued by the scheduler 248-a can be based on commands from the command circuit 230, the engine 246-a, the engine 246-b, or a combination of these components. Similarly, the scheduler 248-b can be coupled to various components of the interface controller 202 and can facilitate access to the volatile memory 204 by issuing commands to the memory interface circuit 240. The commands issued by the scheduler 248-b can be based on commands from the command circuit 230 or the engine 246-a, or both.

[0060] The memory interface circuit 234 may communicate with the non-volatile memory 206 through one or more of the data bus interface 212 and the C / A bus interface 214. For example, the memory interface circuit 234 may prompt the C / A bus interface 214 to relay commands issued by the memory interface circuit 234 through the C / A bus 236 to a local controller in the non-volatile memory 206. And the memory interface circuit 234 may send data to or receive data from the non-volatile memory 206 through the data bus 232. In some examples, the commands issued by the memory interface circuit 234 may be supported by the non-volatile memory 206, but not by the volatile memory 204 (e.g., the commands issued by the memory interface circuit 234 may be different from the commands issued by the memory interface circuit 240).

[0061] The memory interface circuit 240 may communicate with the volatile memory 204 through one or more of the data bus interface 216 and the C / A bus interface 264. For example, the memory interface circuit 240 may prompt the C / A bus interface 264 to relay commands issued by the memory interface circuit 240 through the C / A bus 242 to a local controller of the volatile memory 204. And the memory interface circuit 240 may send data to or receive data from the volatile memory 204 through the one or more data buses 238. In some examples, the commands issued by the memory interface circuit 240 may be supported by the volatile memory 204, but not supported by the non-volatile memory 206 (e.g., the commands issued by the memory interface circuit 240 may be different from the commands issued by the memory interface circuit 234).

[0062] Components of interface controller 202 may operate together non-volatile memory 206 as main memory and volatile memory 204 as cache. Such operations may be prompted by one or more access commands (e.g., read / retrieve commands / requests and write / store commands / requests) received from a host device.

[0063] In some examples, the interface controller 202 may receive a storage command from a host device. The storage command may be received via the C / A bus 226 and transmitted to the command circuit 230 via one or more C / A bus interfaces 210 and decoders 228. The storage command may include or be accompanied by address bits that target a memory address of the non-volatile memory 206. The data to be stored may be received via the data bus 260 and transmitted to the buffer 218 via the data bus interface 208. In a write-through mode, the interface controller 202 may transmit data to both the non-volatile memory 206 and the volatile memory 204. In a write-back mode, the interface controller 202 may transmit data only to the volatile memory 204. In either mode, the interface controller 202 may first check whether the volatile memory 204 has memory cells available for storing data. To do this, the command circuit 230 may reference the memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of the n groups (e.g., pages) of volatile memory cells associated with the memory address are empty (e.g., storing random or invalid data). In some cases, a group of volatile memory cells in volatile memory 204 may be referred to as a line or cache line.

[0064] If one of the n sets of associated volatile memory cells is available for storing information, the interface controller 202 may transfer the data from the buffer 218 to the volatile memory 204 for storage in one of the sets of volatile memory cells. However, if none of the sets of associated volatile memory cells are empty, the interface controller 202 may initiate an eviction process to make room for the data in the volatile memory 204. The eviction process may include transferring old data (e.g., existing data) in one of the n sets of associated volatile memory cells to the buffer 220. Dirty information of the old data may also be transferred to the memory array 254 or register 258 for identifying a dirty subset of the old data. After the old data is stored in the buffer 220, the new data may be transferred from the buffer 218 to the volatile memory 204, and the old data may be transferred from the buffer 220 to the non-volatile memory 206. In some cases, the dirty subset of the old data is transferred to the non-volatile memory 206, and the clean subset (e.g., the unmodified subset) is discarded. The engine 246 - b may identify the dirty subset based on dirty information transferred (eg, from the volatile memory 204 ) to the memory array 254 or registers 258 during the eviction process.

[0065] In another example, the interface controller 202 may receive a retrieval command from the host device. The retrieval command may be received via the C / A bus 226 and transmitted to the command circuit 230 via one or more C / A bus interfaces 210 and decoders 228. The retrieval command may include address bits that target a memory address of the non-volatile memory 206. Before attempting to access the target memory address of the non-volatile memory 206, the interface controller 202 may check whether the volatile memory 204 stores data. To do this, the command circuit 230 may reference the memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of the n groups of volatile memory cells associated with the memory address stores the requested data. If the requested data is stored in the volatile memory 204, the interface controller 202 may transmit the requested data to the buffer 218 for transmission to the host device via the data bus 260.

[0066] If the requested data is not stored in the volatile memory 204, the interface controller 202 may retrieve the data from the non-volatile memory 206 and transfer the data to the buffer 218 for transfer to the host device via the data bus 260. Additionally, the interface controller 202 may transfer the requested data from the buffer 218 to the volatile memory 204 so that the data may be accessed with lower latency during a subsequent retrieval operation. However, before transferring the requested data, the interface controller 202 may first determine whether one or more of the n sets of associated volatile memory cells are available to store the requested data. The interface controller 202 may determine the availability of the n sets of associated volatile memory cells by communicating with an associated cache management circuit group. If a set of associated volatile memory cells is available, the interface controller 202 may transfer the data in the buffer 218 to the volatile memory 204 without performing an eviction process. Otherwise, after performing an eviction process, the interface controller 202 may transfer the data from the buffer 218 to the volatile memory 204.

[0067] The memory subsystem 200 may be implemented in one or more configurations, including a single-chip version and a multi-chip version. The multi-chip version may include one or more components of the memory subsystem 200, including the interface controller 202, the volatile memory 204, and the non-volatile memory 206 (as well as other components or combinations of components), on a separate chip from a chip that includes one or more other components of the memory subsystem 200. For example, in a multi-chip version, a corresponding separate chip may include each of the interface controller 202, the volatile memory 204, and the non-volatile memory 206. In contrast, the single-chip version may include the interface controller 202, the volatile memory 204, and the non-volatile memory 206 on a single chip.

[0068] Figure 3 An example of a process flow 300 for supporting cache management in a memory subsystem according to an example disclosed herein is shown. The process flow 300 may be an example of a process flow for a storage operation. The process flow 300 may be referred to as Figure 1 The interface controller 115 described or referenced Figure 2120 and 125. The process flow 300 may be implemented by the interface controller 202 described above. For ease of reference, the process flow 300 is described with reference to the memory subsystem 200. For example, in addition to other components, various aspects of the process flow 300 may be implemented by the interface controller. Additionally or alternatively, various aspects of the process flow 300 may be implemented as instructions stored in a memory (e.g., firmware stored in the volatile memory 120 and / or the non-volatile memory 125). For example, when executed by a controller (e.g., the interface controller 115), the instructions may cause the controller to perform the operations of the process flow 300.

[0069] Alternative examples of process flow 300 may be implemented in which some operations are performed in a different order than described or not performed at all. In some cases, the operations may include functions not mentioned below, or additional operations may be added.

[0070] At 305, the interface controller 202 may receive a storage command from a host device, the storage command instructing the interface controller 202 to store data in the non-volatile memory 206. The storage command may include or be accompanied by a memory address indicating a group of non-volatile memory cells to which the storage command is directed (e.g., a group of non-volatile memory cells to which the data is to be written). The storage command and the memory address may be received by the command circuit 230 via one or more of the one or more C / A buses 226, the C / A bus interface 210, and the decoder 228. At 310, the interface controller 202 may transfer the data to a buffer 218 having a size (e.g., storage capacity) corresponding to or equal to a page size of the volatile memory 204. In some examples, the command circuit 230 may initiate and facilitate the transfer of data to the buffer 218 (e.g., based on or in response to the received storage command). Alternatively, the data may be automatically transferred via the data bus interface 208.

[0071] At 315, the interface controller 202 may determine n groups (e.g., sixteen groups) of volatile memory cells associated with the nonvolatile memory address. To this end, the command circuit 230 may select a group of nonvolatile memory address bits and transmit these bits to the cache management circuit group so that the register 256 can return storage information associated with the nonvolatile memory address. For example, the register 256 may return storage information stored by the memory array 252, which storage information may be referenced based on a group of address bits. The storage information returned by the register 256 may include content information (e.g., tag addresses) indicating which group (if any) of the n groups of associated volatile memory cells is available to store the provided data. If a group of volatile memory cells stores invalid data (e.g., random data), then the group of volatile memory cells is considered available to store data. Therefore, determining whether a group of associated volatile memory cells is available may include referencing valid information of a group of volatile memory cells stored in the memory array 252. In some cases, a group of associated available memory cells may be referred to as a "write hit".

[0072] At 320, the interface controller 202 can determine whether one or more of the n sets of associated volatile memory cells are available to store data. As discussed, the interface controller 202 can determine the availability of the n sets of associated volatile memory cells based on the storage information of the n sets of associated volatile memory cells. If one of the n sets of associated memory cells is available, then at 325, the interface controller can transfer the provided data from the buffer 218 to the volatile memory 204 for storage in the available set of volatile memory cells.

[0073] At 330, the interface controller 202 may update storage information of a group of volatile memory cells for storing the provided data. For example, the interface controller 202 may update content information and validity information of a group of volatile memory cells in the memory array 252. In some examples (e.g., when the interface controller operates in a write-through mode), at 330, the interface controller 202 may transfer the provided data to a target group of non-volatile memory cells for storage in the non-volatile memory 206.

[0074] At 320, if the interface controller determines that none of the n sets of associated memory cells are available (a condition known as a "write miss"), the interface controller 202 may initiate (e.g., via the engine 246-a and scheduler 248-b) an eviction process 340. For example, at 345, the interface controller 202 may select one of the n sets of associated volatile memory cells to evict. At 350, the interface controller 202 may transfer victim data from the set of volatile memory cells selected for eviction to the buffer 220. The engine 246-a and scheduler 248-b may facilitate the transfer of the victim data from the volatile memory 204 to the buffer 220. In some instances, the interface controller 202 may also transfer storage information (e.g., dirty information) of the set of volatile memory cells to the register 258. After transferring the victim data to the buffer 220, the interface controller 202 may continue to operate in parallel. For example, the interface controller 202 may perform operations between 325 and 335 while performing the remaining operations of the eviction process 340.

[0075] At 355, the interface controller 202 may determine which subsets of the victim data (e.g., which 32B or 64B) are dirty (e.g., include dirty data). To do this, the interface controller 202 (e.g., using the engine 246-b) may reference dirty information (e.g., stored in the register 258) for the subset of the victim data. As described above, dirty data may refer to data that is inconsistent with data in the non-volatile memory 206. For example, dirty data may be data that has been modified in the volatile memory 204 since it was stored in the non-volatile memory 206. Or dirty data may be data that has only been written to the volatile memory 204 (and not the non-volatile memory 206).

[0076] At 360, the interface controller 202 may transfer a subset of the dirty victim data from the buffer 220 to the non-volatile memory 206. For example, the subset of dirty victim data may be transferred to a set of non-volatile memory cells associated with the victim data. The interface controller 202 may determine a correct set of non-volatile memory cells by referencing content information of a set of volatile memory cells (e.g., tag information stored in the memory array 252). Clean victim data (e.g., data that is consistent with corresponding data in the non-volatile memory 206) may be discarded. In some examples, the engine 246-a and the scheduler 248-a may facilitate the transfer of the dirty victim data from the buffer 220 to the non-volatile memory 206. Thus, the interface controller 202 may satisfy a storage request from a host device.

[0077] Figure 4An example of a process flow 400 for supporting cache management in a memory subsystem according to an example disclosed herein is shown. The process flow 400 may be an example of a process flow for a retrieval operation. The process flow 400 may be referred to as Figure 1 The interface controller 115 described or referenced Figure 2 4. The process flow 400 may be implemented by the interface controller 202 described above. For ease of reference, the process flow 400 is described with reference to the memory subsystem 200. For example, in addition to other components, various aspects of the process flow 400 may be implemented by the interface controller. Additionally or alternatively, various aspects of the process flow 400 may be implemented as instructions stored in a memory (e.g., firmware stored in the volatile memory 120 and / or the non-volatile memory 125). For example, when executed by a controller (e.g., the interface controller 115), the instructions may cause the controller to perform the operations of the process flow 400.

[0078] Alternative examples of process flow 400 may be implemented in which some operations are performed in a different order than described or not performed at all. In some cases, the operations may include functions not mentioned below, or additional operations may be added.

[0079] At 405, the interface controller 202 may receive a retrieval command from the host device instructing the interface controller 202 to retrieve data from the non-volatile memory 206. The retrieval command may include or be accompanied by a memory address that indicates a group of non-volatile memory cells to which the retrieval command is directed (e.g., a group of non-volatile memory cells from which data is to be read). The retrieval command and the memory address may be received by the command circuit 230 via one or more C / A buses 226, the C / A bus interface 210, and the decoder 228.

[0080] At 410, the interface controller 202 may determine n groups (e.g., sixteen groups) of volatile memory cells associated with the nonvolatile memory address. To this end, the command circuit 230 may select a group of nonvolatile memory address bits and transmit these bits to the cache management circuit group so that the register 256 can return storage information associated with the nonvolatile memory address. For example, the register 256 can return storage information stored by the memory array 252, which can be referenced based on the group of address bits. The storage information returned by the register 256 may include content information (e.g., tag address) indicating which group (if any) of the n groups of associated volatile memory cells stores the requested data.

[0081] At 415, the interface controller 202 may determine whether one or more of the n sets of associated volatile memory cells store the requested data. As discussed, the interface controller 202 may determine whether the n sets of associated volatile memory cells store the requested data based on the storage information of the n sets of associated volatile memory cells. If one of the n sets of associated volatile memory cells stores the requested data, then at 420, the interface controller 202 may transfer the requested data from the volatile memory 204 to the buffer 218 (e.g., by reading a set of memory cells and transferring the requested data through the data bus 238, the data bus interface 216, and the memory interface circuit 240). Then, at 425, the interface controller 202 may transfer the requested data from the buffer 218 to the host device (e.g., using the data bus interface 208 and the data bus 260).

[0082] At 415, if the interface controller 202 determines that none of the n sets of associated volatile memory cells stores the requested data, then at 430, the interface controller 202 may transfer the requested data from the non-volatile memory 206 to the buffer 218. For example, the interface controller 202 may prompt the requested data to be read from the target set of non-volatile memory cells and transferred to the buffer 218 via one or more of the data bus 232, the data bus interface 212, and the memory interface circuit 234. The interface controller 202 may continue with the operations of 425 and 435. For example, at 435, the interface controller 202 may determine whether one or more of the n sets of associated volatile memory cells are available to store the requested data (e.g., for future low-latency retrieval).

[0083] If one of the n associated sets of volatile memory cells is available, then at 440, the interface controller may transfer the requested data from the buffer 218 to the volatile memory 204 for storage in the available set of volatile memory cells. Then, at 445, the interface controller 202 may update the storage information of the set of volatile memory cells, and the data is written to the set of volatile memory cells.

[0084] For example, the interface controller 202 may update content information and validity information of a group of volatile memory cells in the memory array 252. At 435, if the interface controller determines that none of the n groups of associated memory cells are available, then at 450, the interface controller 202 may initiate an eviction process, such as the eviction process 340. After the eviction process 340 moves the victim data from the group of associated volatile memory cells to the buffer 220, the interface controller 202 may transfer the requested data from the buffer 218 to a group of volatile memory cells in the volatile memory 204. Then, at 445, the memory controller may update the storage information of the group of volatile memory cells into which the requested data is written. Thus, the interface controller 202 may satisfy the retrieval request from the host device.

[0085] Figure 5 A block diagram 500 of a memory subsystem 502 supporting cache management in a memory subsystem according to examples disclosed herein is shown. The memory subsystem 502 may be referred to as Figure 1 and 2 1 or 2. The memory subsystem 502 may be an example of various aspects of the memory subsystem 110 or memory subsystem 200 described herein. Thus, the memory subsystem may be coupled to a host device, a volatile memory, and a non-volatile memory. The memory subsystem 502 may include a communication module 505, a buffer manager 510, a volatile memory manager 515, a non-volatile memory manager 520, a data manager 525, and a storage information manager 530. Each of these modules may include circuits configured to perform the functions described herein. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses or other conductive connections).

[0086] The memory subsystem 502 may be configured to perform access operations in response to access commands from a host device. In a first example, the memory subsystem 502 may be configured to service storage commands from a host device. For example, the communication module 505 may be configured to receive a command from a host device to write data to a memory address of a non-volatile memory. The memory address may be associated with a group of memory cells in a volatile memory group. A group of memory cells may be one of n groups of volatile memory cells associated with the memory address (e.g., in a group-associative mapping scheme). In some examples, the communication module 505 includes a reference Figure 2 For example, communication module 505 may include aspects of data bus 260, transaction bus 222, data bus interface 208, C / A bus 226, C / A bus interface 210, decoder 228 or command circuit 230, among other components.

[0087] The buffer manager 510 can be configured to store data in a buffer based at least in part on (e.g., in response to) a command. In some instances, the buffer is an instance of the buffer 218. Thus, the buffer can have a storage capacity corresponding to (e.g., equal to) a page size of the volatile memory. The buffer manager 510 can also be configured to determine storage information (e.g., content information, validity information) of a set of memory cells in a bank of the volatile memory after storing the data in the buffer. In some instances, the buffer manager 510 includes a reference Figure 2 Components of interface controller 202 are described. For example, buffer manager 510 may include aspects of command circuitry 230, cache management circuitry 244, and buffer circuitry 224, among other components.

[0088] The volatile memory manager 515 can be configured to transfer data from the buffer to a group of memory cells in a bank of volatile memory based at least in part on the storage information of the group of memory cells. In some examples, the volatile memory manager 515 includes a reference Figure 2 Components of interface controller 202 are described. For example, volatile memory manager 515 may include aspects of command circuit 230, engine 246-a, scheduler 248-b, buffer circuit 224, and memory interface circuit 240, among other components.

[0089] In some examples, buffer manager 510 may be configured to determine, based at least in part on the storage information, whether a group of memory cells stores the second data. If non-volatile memory manager 520 determines that a group of memory cells stores the second data, then non-volatile memory manager 520 may be configured to transfer a subset (e.g., a 32B or 64B block) of the second data to non-volatile memory based at least in part on (e.g., in response to) non-volatile memory manager 520 determining that a group of memory cells stores the second data. In some examples, non-volatile memory manager 520 includes reference Figure 2 Components of interface controller 202 are described. For example, non-volatile memory manager 520 may include aspects of command circuit 230, engine 246-b, scheduler 248-a, buffer circuit 224, and memory interface circuit 234, among other components.

[0090] In some instances, the interface controller of the memory subsystem 502 includes a second buffer. In some instances, the second buffer is an instance of buffer 220. Thus, the second buffer can have a storage capacity corresponding to (e.g., equal to) a page size of the volatile memory. The volatile memory manager 515 can be configured to transfer the second data from a group of memory cells to the second buffer and transfer the data from the buffer to a group of memory cells. The data manager 525 can be configured to determine whether a subset of the second data is different from corresponding data stored in the non-volatile memory (e.g., the data manager 525 can be configured to determine whether the subset of the second data is dirty). In some instances, the data manager 525 includes a reference Figure 2 Components of the interface controller 202 described herein. For example, the data manager 525 may include aspects of the cache management circuit 244, the engine 246-b and the scheduler 248-a, the buffer circuit 224, and other components. In some instances, (e.g., if the data manager 525 determines that the subset of the data is different from the corresponding data), the non-volatile memory manager 520 may be configured to initiate a write operation to store the subset of the second data from the second buffer in the non-volatile memory based at least in part on (e.g., in response to) determining that the subset of the second data is different from the corresponding data. Thus, in some instances, the non-volatile memory manager 520 may include aspects of the engine 246-b, the scheduler 248-a, and the memory interface circuit 234, and other components.

[0091] In some instances, the interface controller of the memory subsystem 502 includes an array storing storage information of a subset of memory cells in a memory bank of volatile memory. In some instances, the array is an instance of the memory array 254. The buffer manager 510 can be configured to select a set of address bits included in the command. In some instances, the set of address bits is a portion of a memory address. The storage information manager 530 can be configured to reference the array storing storage information of a subset of memory cells in a memory bank of volatile memory based at least in part on the set of address bits. In such an instance, transferring the subset of second data to the non-volatile memory can be based at least in part on the storage information of the subset of memory cells storing the subset of second data. In some instances, the storage information manager 530 includes referencing Figure 2 Components included in interface controller 202 are described. For example, storage information manager 530 may include aspects of command circuit 230 and cache management circuit 244, as well as other components.

[0092] In some examples, the buffer manager 510 is configured to determine, based at least in part on the storage information (e.g., based on the content and / or validity information), that a group of memory cells are available for storing data. The buffer manager 510 may also be configured to read data from the buffer. The volatile memory manager 515 may be configured to initiate a write operation to store data in a group of memory cells of the volatile memory.

[0093] In some instances, the interface controller of the memory subsystem 502 includes an array storing storage information of a storage bank of volatile memory. In some instances, the array is an instance of the memory array 252. In some instances, the buffer manager 510 is configured to select a set of address bits included in the command. In some instances, the set of address bits is a portion of a memory address. The storage information manager 530 can be configured to reference the array storing storage information of the storage bank of volatile memory based at least in part on the set of address bits. In this case, the buffer manager 510 can be configured to determine the storage information based at least in part on the reference array.

[0094] In some instances (e.g., in write-through mode), the nonvolatile memory manager 520 can be configured to transfer data from the buffer to the nonvolatile memory based at least in part on a command from the host device. The nonvolatile memory manager 520 can also be configured to initiate a write operation to store data at a memory address.

[0095] As described above, the memory subsystem 502 can be configured to perform access operations in response to an access command from a host device. In a second example, the memory subsystem 502 can be configured to service a retrieval command from a host device. For example, the communication module 505 can be configured to receive a command from the host device to read data from a memory address of a non-volatile memory. The memory address can be associated with a group of memory cells in a volatile memory group. A group of memory cells can be a group of n groups of volatile memory cells associated with the memory address (e.g., according to a group association mapping scheme). The buffer manager 510 can be configured to determine the storage information of a group of memory cells in a storage body of the volatile memory (e.g., in response to the command). The buffer manager 510 can also be configured to transfer data from the volatile memory or the non-volatile memory and at least partially based on the storage information of a group of memory cells to a buffer in the interface controller (e.g., buffer 218). The storage capacity of the buffer can correspond to the page size of the volatile memory.

[0096] In some examples, buffer manager 510 can be configured to determine whether a group of memory cells in volatile memory stores data based at least in part on the storage information. In such examples, volatile memory manager 515 can be configured to transfer data from the volatile memory to the buffer based at least in part on the determination that a group of memory cells stores data. Communication module 505 can be configured to transfer data from the buffer to a host device.

[0097] In some examples, buffer manager 510 can be configured to determine whether a group of memory cells in volatile memory stores data based at least in part on the storage information. In such examples, non-volatile memory manager 520 can be configured to transfer data from non-volatile memory to the buffer based at least in part on the determination that a group of memory cells do not store data. Communication module 505 can be configured to transfer data from the buffer to a host device.

[0098] In some instances, the interface controller of the memory subsystem 502 includes a second buffer. In some instances, the second buffer is an instance of the buffer 220. Thus, the buffer may have a storage capacity corresponding to a page size of the volatile memory. The buffer manager 510 may be configured to determine whether a group of memory cells in the volatile memory stores the second data based at least in part on the storage information. The non-volatile memory manager 520 may be configured to transfer data from the non-volatile memory to the buffer based at least in part on determining that a group of memory cells stores the second data. The buffer manager 510 may be configured to transfer the second data from a group of memory cells in the volatile memory to the second buffer in the interface controller. In some instances, the non-volatile memory manager 520 may be configured to transfer a subset of the second data from the second buffer to the non-volatile memory based at least in part on the subset of the second data being different from the corresponding data stored in the non-volatile memory. The volatile memory manager 515 may be configured to transfer the data from the buffer to a group of memory cells in the volatile memory.

[0099] In some examples, the buffer manager 510 can be configured to select a set of address bits included in the command. The storage information manager 530 can be configured to reference an array storing storage information of a bank of volatile memory based at least in part on the set of address bits, wherein the storage information is determined based at least in part on referencing the array.

[0100] As described above, the memory subsystem 502 can be configured to perform an access operation in response to an access command from a host device. In a third example, the memory subsystem may include a FeRAM coupled to an interface controller and a DRAM coupled to the interface controller. The interface controller may include an SRAM buffer coupled to the DRAM and the FeRAM and having a storage capacity corresponding to the page size of the DRAM. The communication module 505 can be configured to receive a command from a host device (e.g., an SoC or a processor) to access a memory address of the FeRAM. The memory address can be associated with a group of memory cells in a memory bank of the DRAM. The buffer manager 510 can be configured to store data associated with a command (e.g., requested data or provided data) in an SRAM buffer. The buffer manager 510 can also be configured to transfer data from the SRAM buffer based at least in part on the command.

[0101] In some instances, the interface controller includes a second SRAM buffer having a capacity corresponding to a page size of the DRAM. The volatile memory manager 515 may be configured to transfer the second data from a group of memory cells in the DRAM to the second SRAM buffer. The non-volatile memory manager 520 may be configured to transfer the second data from the second SRAM buffer to the FeRAM. If the command is a read command, the buffer manager 510 may be configured to determine whether a group of memory cells in the DRAM stores the second data. The non-volatile memory manager 520 may be configured to transfer the data from the FeRAM to the SRAM buffer based at least in part on determining that a group of memory cells in the DRAM stores the second data. And the volatile memory manager 515 may be configured to transfer the data from the SRAM buffer to a group of memory cells in the DRAM after the second data is transferred from a group of memory cells in the DRAM to the second SRAM buffer.

[0102] If the command is a write command for data, the non-volatile memory manager 520 may be configured to transfer the data to the FeRAM at the memory address for storage. The buffer manager 510 may be configured to determine whether a group of memory cells in the DRAM stores the second data. And the volatile memory manager 515 may be configured to transfer the data from the SRAM buffer to a group of memory cells in the DRAM after the second data is transferred from the group of memory cells in the DRAM to the second SRAM buffer, wherein the data is transferred from the SRAM buffer to the group of memory cells in the DRAM based at least in part on determining that the group of memory cells in the DRAM stores the second data.

[0103] Figure 61 shows a flow chart illustrating one or more methods 600 for supporting cache management in a memory subsystem according to aspects of the present disclosure. The operations of the method 600 may be implemented by a memory subsystem or components thereof as described herein. For example, the operations of the method 600 may be implemented by reference to Figures 1 to 5 The memory subsystem described herein may be used to perform the functions described herein. In some examples, the memory subsystem may execute a set of instructions to control the functional elements of the memory subsystem to perform the functions described herein. Additionally or alternatively, the memory subsystem may use dedicated hardware to perform various aspects of the functions described herein.

[0104] In some examples, the operations of method 600 may be implemented by a device including an interface controller, a non-volatile memory coupled to the interface controller, and a volatile memory coupled to the interface controller. The interface controller may include a buffer.

[0105] At 605, the method may include receiving a command from a host device to write data to a memory address of a non-volatile memory. The memory address may be associated with a group of memory cells in a volatile memory group. The operations of 605 may be performed according to the methods described herein. In some examples, aspects of the operations of 605 may be described by reference to Figure 5 The communication module described is executed.

[0106] At 610, the method may include storing data in a buffer based at least in part on the command, the buffer having a storage capacity corresponding to a page size of the volatile memory. The operations of 610 may be performed according to the methods described herein. In some examples, aspects of the operations of 610 may be performed as described in reference to Figure 5 The buffer manager described is implemented.

[0107] At 615, the method may include determining storage information of a group of memory cells in a bank of volatile memory after storing the data in the buffer. The operations of 615 may be performed according to the methods described herein. In some examples, aspects of the operations of 615 may be performed as described in reference to Figure 5 The buffer manager described is implemented.

[0108] At 620, the method may include transferring data from the buffer to a group of memory cells in a bank of volatile memory based at least in part on the stored information of the group of memory cells. The operations of 620 may be performed according to the methods described herein. In some examples, aspects of the operations of 620 may be performed as described in reference to Figure 5 The described volatile memory manager is implemented.

[0109] In some examples, an apparatus described herein may perform one or more methods, such as method 600. The apparatus may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following steps: receiving a command from a host device to write data to a memory address of a non-volatile memory, the memory address being associated with a group of memory cells in a memory bank of a volatile memory; storing the data in a buffer based at least in part on the command, the buffer having a storage capacity corresponding to a page size of the volatile memory; after storing the data in the buffer, determining storage information of a group of memory cells in a memory bank of the volatile memory; and transferring the data from the buffer to a group of memory cells in a memory bank of the volatile memory based at least in part on the storage information of the group of memory cells.

[0110] Some instances of the method 600 and apparatus described herein may also include operations, features, components, or instructions for performing the following steps: determining whether a group of memory cells stores second data based at least in part on the storage information; and transferring a subset of the second data to a non-volatile memory based at least in part on determining that a group of memory cells stores the second data.

[0111] Some instances of the method 600 and devices described herein may also include operations, features, components, or instructions for performing the following steps: transferring second data from a group of memory cells to a second buffer included in an interface controller before transferring the data from the buffer to a group of memory cells; determining whether a subset of the second data is different from corresponding data stored in a non-volatile memory; and initiating a write operation to store the subset of the second data from the second buffer in a non-volatile memory based at least in part on determining that the subset of the second data is different from the corresponding data.

[0112] Some instances of the method 600 and apparatus described herein may also include operations, features, components, or instructions for performing the following steps: selecting a set of address bits included in a command; and referencing an array (included in an interface controller) storing storage information of a subset of memory cells in a storage body of a volatile memory based at least in part on the set of address bits, wherein transferring the subset of second data to the non-volatile memory is based at least in part on the storage information of the subset of memory cells storing the subset of second data.

[0113] Some instances of the method 600 and apparatus described herein may also include operations, features, components, or instructions for performing the following steps: determining, based at least in part on the storage information, that a set of memory cells are available for storing data; reading data from a buffer; and initiating a write operation to store data in a set of memory cells of a volatile memory.

[0114] Some instances of the method 600 and apparatus described herein may also include operations, features, components, or instructions for performing the following steps: selecting a set of address bits included in a command; and referencing an array (included in an interface controller) of storage information of a storage body storing volatile memory based at least in part on the set of address bits, wherein the storage information is determined at least in part based on the referenced array.

[0115] Some examples of the method 600 and apparatus described herein may also include operations, features, components, or instructions for performing the following steps: transferring data from the buffer to the non-volatile memory based at least in part on a command from a host device; and initiating a write operation to store data at a memory address. In some examples, the host device is a SoC or a processor.

[0116] Figure 7 1 shows a flow chart illustrating one or more methods 700 for supporting cache management in a memory subsystem according to aspects of the present disclosure. The operations of the method 700 may be implemented by a memory subsystem or components thereof as described herein. For example, the operations of the method 700 may be implemented by reference to Figures 1 to 5 The memory subsystem described herein may be used to perform the functions described herein. In some examples, the memory subsystem may execute a set of instructions to control the functional elements of the memory subsystem to perform the functions described herein. Additionally or alternatively, the memory subsystem may use dedicated hardware to perform various aspects of the functions described herein.

[0117] In some examples, the operations of method 700 may be implemented by a device including an interface controller, a non-volatile memory coupled to the interface controller, and a volatile memory coupled to the interface controller. The interface controller may include a buffer.

[0118] At 705, the method may include receiving a command from a host device to read data from a memory address of a non-volatile memory. The memory address may be associated with a group of memory cells in a volatile memory group. The operations of 705 may be performed according to the methods described herein. In some examples, aspects of the operations of 705 may be described by reference to Figure 5 The communication module described is executed.

[0119] At 710, the method may include determining storage information of a group of memory cells in a memory bank of a volatile memory. The operations of 710 may be performed according to the methods described herein. In some examples, aspects of the operations of 710 may be performed as described in reference to Figure 5 The buffer manager described is implemented.

[0120] At 715, the method may include transferring data from the volatile memory or the non-volatile memory to a buffer in the interface controller based at least in part on the stored information of a group of memory cells, the buffer having a storage capacity corresponding to a page size of the volatile memory. The operations of 715 may be performed according to the methods described herein. In some examples, aspects of the operations of 715 may be performed as described in reference to Figure 5 The buffer manager described is implemented.

[0121] In some examples, an apparatus described herein may perform one or more methods, such as method 700. The apparatus may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following steps: receiving a command from a host device to read data from a memory address of a non-volatile memory, the memory address being associated with a group of memory cells in a memory bank of the volatile memory; determining storage information of a group of memory cells in a memory bank of the volatile memory; and transferring data from the volatile memory or the non-volatile memory, and based at least in part on the storage information of the group of memory cells, to a buffer in an interface controller, the buffer having a storage capacity corresponding to a page size of the volatile memory.

[0122] In some examples of the method 700 and apparatus described herein, determining storage information may include operations, features, components, or instructions for performing the following steps: determining whether a group of memory cells in a volatile memory stores data based at least in part on the storage information, wherein based at least in part on determining that a group of memory cells stores data, transferring the data from the volatile memory to a buffer; and transferring the data from the buffer to a host device.

[0123] In some examples of the method 700 and apparatus described herein, determining storage information may include operations, features, components, or instructions for performing the following steps: determining whether a group of memory cells in a volatile memory stores data based at least in part on the storage information, wherein, based at least in part on determining that a group of memory cells do not store data, transferring data from a non-volatile memory to a buffer; and transferring data from the buffer to a host device.

[0124] In some examples of the methods 700 and devices described herein, determining the storage information may include operations, features, components, or instructions for performing the following steps: determining whether a group of memory cells in the volatile memory stores second data based at least in part on the storage information, wherein based at least in part on determining that the group of memory cells stores the second data, transferring the data from the non-volatile memory to a buffer; and transferring the second data from the group of memory cells in the volatile memory to a second buffer in the interface controller, the second buffer having a storage capacity corresponding to a page size of the volatile memory. In some examples of the methods 700 and devices described herein, determining the storage information may include operations, features, components, or instructions for performing the following steps: transferring a subset of the second data from the second buffer to the non-volatile memory based at least in part on that the subset of the second data is different from the corresponding data stored in the non-volatile memory; and transferring the data from the buffer to the group of memory cells in the volatile memory.

[0125] In some instances of the method 700 and apparatus described herein, determining storage information may include operations, features, components, or instructions for performing the following steps: selecting a set of address bits included in a command; and referencing an array of storage information of a storage body storing a volatile memory based at least in part on the set of address bits, wherein the storage information is determined at least in part based on the referenced array.

[0126] Figure 8 800. The operations of method 800 may be implemented by a memory subsystem or components thereof as described herein. For example, the operations of method 800 may be implemented by reference to Figures 1 to 5 The memory subsystem described herein may be used to perform the functions described herein. In some examples, the memory subsystem may execute a set of instructions to control the functional elements of the memory subsystem to perform the functions described herein. Additionally or alternatively, the memory subsystem may use dedicated hardware to perform various aspects of the functions described herein.

[0127] In some examples, the operations of method 800 may be implemented by a device including an interface controller, a FeRAM coupled to the interface controller, and a DRAM coupled to the interface controller. The interface controller may include an SRAM buffer.

[0128] At 805, the method may include receiving a command from the SoC to access a memory address of the FeRAM, the memory address being associated with a group of memory cells in the DRAM group. The operations of 805 may be performed according to the methods described herein. In some examples, aspects of the operations of 805 may be described with reference to Figure 5 The communication module described is executed.

[0129] At 810, the method may include storing data associated with the command in an SRAM buffer having a storage capacity corresponding to a page size of the DRAM and coupled to the DRAM and the FeRAM. The operations of 810 may be performed according to the methods described herein. In some examples, aspects of the operations of 810 may be performed as described in reference to Figure 5 The buffer manager described is implemented.

[0130] At 815, the method may include transferring data from the SRAM buffer based at least in part on the command. The operations of 815 may be performed according to the methods described herein. In some examples, aspects of the operations of 815 may be performed as described in reference to Figure 5 The buffer manager described is implemented.

[0131] In some examples, the apparatus described herein may perform one or more methods, such as method 800. The apparatus may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following steps: receiving a command from the SoC to access a memory address of the FeRAM, the memory address being associated with a group of memory cells in a bank of the DRAM; storing data associated with the command in an SRAM buffer, the SRAM buffer having a storage capacity corresponding to a page size of the DRAM and coupled to the DRAM and the FeRAM; and transmitting data from the SRAM buffer based at least in part on the command.

[0132] Some instances of the method 800 and apparatus described herein may also include operations, features, components, or instructions for performing the following steps: transferring second data from a group of memory cells in the DRAM to a second SRAM buffer included in the interface controller, the second SRAM buffer having a capacity corresponding to a page size of the DRAM; and transferring the second data from the second SRAM buffer to the FeRAM.

[0133] Some instances of the method 800 and apparatus described herein may also include operations, features, components, or instructions for performing the following steps: when the command is a read command, determining whether a group of memory cells in the DRAM stores second data; transferring data from the FeRAM to the SRAM buffer based at least in part on determining that a group of memory cells in the DRAM stores the second data; and after transferring the second data from the group of memory cells in the DRAM to the second SRAM buffer, transferring data from the SRAM buffer to a group of memory cells in the DRAM.

[0134] Some instances of the method 800 and apparatus described herein may also include operations, features, components, or instructions for performing the following steps: when the command is a write command, transferring data to the FeRAM at the memory address for storage; determining whether a group of memory cells in the DRAM stores second data; and after transferring the second data from the group of memory cells in the DRAM to a second SRAM buffer, transferring the data from the SRAM buffer to a group of memory cells in the DRAM, wherein the data is transferred from the SRAM buffer to the group of memory cells in the DRAM based at least in part on determining that a group of memory cells in the DRAM stores the second data.

[0135] In some examples, the device described herein may perform aspects of methods 600, 700, and 800. The device may include a nonvolatile memory (e.g., nonvolatile memory 125 or nonvolatile memory 206), a volatile memory (e.g., volatile memory 120 or volatile memory 204), and an interface controller (e.g., interface controller 115 or interface controller 202). The interface controller may include: a first buffer (e.g., buffer 135-a or buffer 218), the first buffer is coupled to a storage bank of the volatile memory, the first buffer has a capacity corresponding to a page size of the volatile memory and is configured to store data indicated by an access command; and a second buffer (e.g., buffer 135-b or buffer 220), the second buffer is coupled to a storage bank of the volatile memory, the second buffer has a capacity corresponding to a page size of the volatile memory, and is configured to store data for transfer between the volatile memory and the nonvolatile memory.

[0136] In some instances, the volatile memory includes a plurality of memory banks, and the interface controller includes: a first plurality of buffers, the first plurality of buffers including a first buffer, wherein each buffer of the first plurality of buffers is coupled to a corresponding memory bank of the plurality of memory banks and is configured to store data indicated by an access command of the corresponding memory bank; and a second plurality of buffers, the second plurality of buffers including a second buffer, wherein each buffer of the second plurality of buffers is coupled to a corresponding memory bank of the plurality of memory banks and is configured to store data for transmission between the corresponding memory bank and the non-volatile memory.

[0137] In some examples, the apparatus includes circuitry (e.g., command circuitry 230) coupled to a bus (e.g., C / A bus 226) between an interface controller and a host device. The circuitry can be configured to receive commands and addresses from the host device over the bus and to issue commands to one or more circuits (e.g., scheduler 248-a, scheduler 248-b) that control access to volatile memory and non-volatile memory.

[0138] In some examples, the device includes a first array (e.g., memory array 252) configured to store storage information of a group of memory cells in a memory bank of a volatile memory, and a second array (e.g., memory array 254) coupled to the first array and configured to store update information of a subset of memory cells of the group of memory cells.

[0139] In some examples, the interface controller includes a first circuit (e.g., memory interface circuit 234) coupled to a non-volatile memory. The first circuit can be configured to issue commands to the non-volatile memory and transfer data between the non-volatile memory and the first buffer and the second buffer; and a second circuit (e.g., memory interface circuit 240) coupled to the volatile memory, the second circuit configured to issue commands to the volatile memory and transfer data between the volatile memory and the first buffer and the second buffer.

[0140] In some examples, the interface controller, the first buffer, and the second buffer are on a first die, the volatile memory is on a second die, and the non-volatile memory is on a third die. In some examples, the non-volatile memory, the volatile memory, and the interface controller are in the same package.

[0141] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, parts of two or more methods may be combined.

[0142] The information and signals described herein may be represented using a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some of the figures may represent a signal as a single signal; however, one of ordinary skill in the art will appreciate that the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0143] A protocol may define one or more communication processes and one or more communication parameters used by a device or component. For example, a protocol may define various operations, the timing and frequency of these operations, the meaning of various commands or signals or both, one or more addressing schemes for one or more memories, the type of communication for which pins are reserved, the size of data processed at various components such as interfaces, the data rate supported by various components such as interfaces, or the bandwidth supported by various components such as interfaces, and other parameters and metrics, or any combination thereof. The use of a shared protocol may enable interaction between devices, because each device may operate in a manner that is expected, recognized, and understood by another device. For example, two devices supporting the same protocol may interact according to the policies, processes, and parameters defined by the protocol, while two devices supporting different protocols may be incompatible.

[0144] For example, two devices supporting different protocols may not be compatible because the protocols define different addressing schemes (e.g., different numbers of address bits). As another illustration, two devices supporting different protocols may not be compatible because the protocols define different transmission procedures in response to a single command (e.g., the burst length or number of bytes allowed in response to a command may be different). Simply translating a command into an action should not be understood as using two different protocols. In contrast, two protocols may be considered different if the corresponding procedures or parameters defined by the protocols are different. For example, if a device supports different addressing schemes or different transmission procedures in response to a command, then the device may be said to support two different protocols.

[0145] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (or conductive contact or connected or coupled) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device including the connected components, the conductive path between the components that are in electronic communication (or conductive contact or connected or coupled) with each other may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some instances, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0146] The term "coupling" refers to the transition from an open circuit relationship between components (where signals cannot currently be transmitted between components via conductive paths) to a closed circuit relationship between components (where signals can be transmitted between components via conductive paths). When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not allow signals to flow.

[0147] The term "isolated" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from each other if an open circuit exists between them. For example, two components isolated by a switch located between the components are isolated from each other when a switch is open. When a controller isolates two components, the controller uses the conductive path that previously allowed a signal to flow to effect a change that prevents the signal from flowing between the components.

[0148] The devices including memory arrays discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled by doping with various chemical substances, including but not limited to phosphorus, boron or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0149] The switch component or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device, including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped, such as degenerate semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type field effect transistor or a p-type field effect transistor, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the transistor threshold voltage is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0150] The description set forth herein, in conjunction with the accompanying drawings, describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "used as an example, instance, or illustration," rather than "preferred" or "superior to other examples." The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be implemented without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid the concept of the described examples.

[0151] In the drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. If only the first reference label is used in the specification, the description applies to any one of the similar components having the same first reference label, regardless of the second reference label.

[0152] The information and signals described herein may be represented using a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips cited throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0153] The various illustrative blocks and modules described in conjunction with the disclosure herein may be implemented or executed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration).

[0154] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented by software executed by a processor, these functions can be stored in a computer-readable medium as one or more instructions or codes or transmitted by it. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software, hardware, firmware, hard wiring, or any combination of these executed by a processor. The features of implementing the functions can also be physically located in different locations, including being distributed so that some functions are implemented in different physical locations. In addition, as used herein, including in the claims, the "or" used in the list of items (for example, a list of items beginning with phrases such as "at least one" or "one or more") represents an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (that is, A and B and C). In addition, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, the exemplary steps described as "based on condition A" can be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0155] Computer readable media include non-transitory computer storage media and communication media, and communication media include any medium that is convenient for transmitting a computer program from one place to another.Non-transitory storage media can be any available medium that a general or special-purpose computer can access.As an example and not limitation, non-transitory computer readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or can be used for carrying or storing desired program code components in the form of instructions or data structures and any other non-transitory medium that can be accessed by a general or special-purpose computer or a general or special-purpose processor.In addition, any connection is properly referred to as computer readable media.For example, if coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) are used to transmit software from a website, server or other remote source, coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) are included in the definition of medium. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0156] The description provided herein enables those skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but conforms to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, comprising: Non-volatile memory; A volatile memory, wherein the volatile memory comprises a plurality of memory banks; as well as an interface controller coupled to the non-volatile memory and the volatile memory, the interface controller including, for each memory bank of the plurality of memory banks of the volatile memory, a corresponding first buffer of the plurality of first buffers of the interface controller and a corresponding second buffer of the plurality of second buffers of the interface controller, the corresponding first buffer and the corresponding second buffer both being allocated to the each memory bank of the volatile memory, both being configured for data transfer involving the each memory bank of the volatile memory, and both having a storage capacity equal to a page size of the volatile memory, the interface controller being operable to: receiving a command from a host device to write first data to a memory address of the non-volatile memory, the memory address of the non-volatile memory being associated with a group of memory cells in a memory bank of the plurality of memory banks of the volatile memory; storing the first data in the corresponding first buffer assigned to the memory bank of the volatile memory based at least in part on the command; determining storage information of the group of memory cells in the memory bank of the volatile memory after storing the first data in the corresponding first buffer assigned to the memory bank of the volatile memory; based at least in part on determining that the set of memory cells in the memory bank of the volatile memory stores second data, transferring the second data from the set of memory cells in the memory bank of the volatile memory to the corresponding second buffer of the interface controller assigned to the memory bank of the volatile memory; as well as After transferring the second data from the group of memory cells in the storage bank of the volatile memory to the corresponding second buffer allocated to the storage bank of the volatile memory, the first data is transferred from the corresponding first buffer allocated to the storage bank of the volatile memory to the group of memory cells in the storage bank of the volatile memory based at least in part on the storage information of the group of memory cells.

2. The memory device according to claim 1, in, The interface controller is further operable to: determining, based at least in part on the storage information, whether the group of memory cells stores second data; as well as Based at least in part on determining that the group of memory cells stores the second data and transferring the second data to the corresponding second buffer, transferring a subset of the second data from the corresponding second buffer to the non-volatile memory.

3. The memory device according to claim 2, in, The interface controller is further operable to: determining whether the subset of the second data is different from corresponding data stored in the non-volatile memory; as well as Based at least in part on determining that the subset of the second data is different from the corresponding data, a write operation is initiated to store the subset of the second data in the non-volatile memory from the corresponding second buffer assigned to the memory bank of the volatile memory.

4. The memory device according to claim 2, in, The interface controller comprises an array storing storage information of a subset of memory cells in the memory bank of the volatile memory, and wherein the interface controller is further operable to: selecting a set of address bits to be included in the command; and The array storing storage information of a subset of memory cells in the memory bank of the volatile memory is referenced based at least in part on the set of address bits, wherein transferring the subset of the second data to the non-volatile memory is based at least in part on the storage information of the subset of memory cells storing the subset of the second data.

5. The memory device according to claim 1, in, The interface controller is further operable to: determining that the set of memory cells are available for storing the first data based at least in part on transferring the second data from the set of memory cells to the respective second buffers: reading the first data from the corresponding first buffer; and A write operation is initiated to store the first data in the group of memory cells of the volatile memory.

6. The memory device according to claim 1, in, The interface controller comprises an array storing storage information of the memory bank of the volatile memory, and wherein the interface controller is further operable to: selecting a set of address bits to be included in the command; and The array storing the storage information of the memory bank of the volatile memory is referenced based at least in part on the set of address bits, wherein the storage information is determined based at least in part on referencing the array.

7. The memory device according to claim 1, in, The interface controller is further operable to: transferring the first data from the corresponding first buffer to the non-volatile memory based at least in part on the command from the host device; and A write operation is initiated to store the first data at the memory address.

8. The memory device according to claim 1, in, The host device includes a system on a chip or a processor.

9. A memory device comprising: Non-volatile memory; A volatile memory, wherein the volatile memory comprises a plurality of memory banks; as well as an interface controller coupled to the non-volatile memory and the volatile memory, the interface controller including, for each memory bank of the plurality of memory banks of the volatile memory, a corresponding first buffer of the plurality of first buffers of the interface controller and a corresponding second buffer of the plurality of second buffers of the interface controller, the corresponding first buffer and the corresponding second buffer both being allocated to the each memory bank of the volatile memory, both being configured for data transfer involving the each memory bank of the volatile memory, and both having a storage capacity equal to a page size of the volatile memory, the interface controller being operable to: receiving a command from a host device to read first data from a memory address of the non-volatile memory, the memory address of the non-volatile memory being associated with a group of memory cells in a memory bank of the plurality of memory banks of the volatile memory; determining storage information of the set of memory cells in the memory bank of the volatile memory; transferring the first data from the non-volatile memory to the corresponding first buffer of the interface controller assigned to the memory bank of the volatile memory based at least in part on the storage information of the group of memory cells; as well as Based at least in part on the storage information and determining that the group of memory cells of the volatile memory stores second data, the second data is transferred from the group of memory cells in the memory bank of the volatile memory to the corresponding second buffer in the interface controller assigned to the memory bank of the volatile memory.

10. The memory device according to claim 9, in, The interface controller is further operable to: transferring the first data from the corresponding first buffer to the host device; and The first data is transferred from the corresponding first buffer to the set of memory cells based at least in part on transferring the second data from the set of memory cells to the corresponding second buffer.

11. The memory device according to claim 9, in, The interface controller is further operable to: determining, based at least in part on the storage information, whether the set of memory cells in the volatile memory stores the first data, wherein based at least in part on determining that the set of memory cells does not store the first data, transferring the first data from the non-volatile memory to the corresponding first buffer; and The first data is transferred from the corresponding first buffer to the host device.

12. The memory device according to claim 9, in, The interface controller is further operable to: Based at least in part on the storage information, it is determined whether the set of memory cells in the volatile memory stores the second data, wherein the first data is transferred from the non-volatile memory to the corresponding first buffer based at least in part on determining that the set of memory cells stores the second data.

13. The memory device according to claim 12, in, The interface controller is further operable to: transferring the subset of the second data from the corresponding second buffer assigned to the memory bank of the volatile memory to the non-volatile memory based at least in part on the subset of the second data being different from corresponding data stored in the non-volatile memory; as well as The first data is transferred from the corresponding first buffer assigned to the memory bank of the volatile memory to the group of memory cells in the volatile memory.

14. The memory device according to claim 9, in, The interface controller is further operable to: selecting a set of address bits to be included in the command; and An array storing the storage information of the memory bank of the volatile memory is referenced based at least in part on the set of address bits, wherein the storage information is determined based at least in part on referencing the array.

15. A memory device comprising: Non-volatile memory; A volatile memory, the volatile memory comprising a plurality of memory banks; and An interface controller, the interface controller comprising: a plurality of first buffers, each of the plurality of first buffers having a storage capacity equal to a page size of the volatile memory, wherein each first buffer of the plurality of first buffers is coupled to a corresponding memory bank of the plurality of memory banks of the volatile memory, is assigned to the corresponding memory bank, is configured for data transfer involving the corresponding memory bank, and is configured to store data indicated by an access command of the corresponding memory bank; and a plurality of second buffers, each of the plurality of second buffers having a storage capacity equal to the page size of the volatile memory, wherein each of the plurality of second buffers is coupled to a corresponding memory bank of the plurality of memory banks of the volatile memory, is assigned to the corresponding memory bank, is configured for data transfer involving the corresponding memory bank, and is configured to store data for transfer between the corresponding memory bank of the volatile memory and the non-volatile memory.

16. The memory device of claim 15, further comprising: A circuit is coupled to a bus between the interface controller and a host device, the circuit being configured to receive commands and addresses from the host device via the bus and to issue commands to one or more circuits that control access to the volatile memory and the non-volatile memory.

17. The memory device of claim 15, further comprising: a first array configured to store storage information of a group of memory cells in the plurality of memory banks of the volatile memory; and A second array is coupled to the first array and configured to store update information for a subset of memory cells of the group of memory cells.

18. The memory device according to claim 15, in, The interface controller also includes: a first circuit coupled to the nonvolatile memory, the first circuit configured to issue a command to the nonvolatile memory and to transfer data between the nonvolatile memory and the plurality of first buffers and the plurality of second buffers; as well as A second circuit is coupled to the volatile memory, the second circuit being configured to issue a command to the volatile memory and to transfer data between the volatile memory and the plurality of first buffers and the plurality of second buffers.

19. The memory device according to claim 15, in, The interface controller, the plurality of first buffers, and the plurality of second buffers are on a first die, the volatile memory is on a second die, and the non-volatile memory is on a third die.

20. The memory device according to claim 15, in, The non-volatile memory, the volatile memory, and the interface controller are in the same package.

21. A memory device comprising: Ferroelectric random access memory FeRAM; A dynamic random access memory DRAM, wherein the DRAM comprises a plurality of memory banks; and an interface controller coupled to the FeRAM and the DRAM, the interface controller including, for each of the plurality of memory banks of the DRAM, a corresponding first SRAM buffer of a plurality of first static random access memory SRAM buffers of the interface controller and a corresponding second SRAM buffer of a plurality of second SRAM buffers of the interface controller, the corresponding first SRAM buffer and the corresponding second SRAM buffer both being allocated to the each memory bank of the DRAM, both being configured for data transfer involving the each memory bank of the DRAM, and both having a storage capacity equal to a page size of the DRAM, the interface controller being operable to: receiving, from a system on chip SoC, a command to access a memory address of the FeRAM, the memory address of the FeRAM being associated with a group of memory cells in a memory bank of the plurality of memory banks of the DRAM; based at least in part on the command, storing first data associated with the command in the corresponding first SRAM buffer assigned to the memory bank of the DRAM; based at least in part on determining that the set of memory cells in the memory bank of the DRAM stores second data, transferring the second data from the set of memory cells in the memory bank of the DRAM to the corresponding second SRAM buffer of the interface controller assigned to the memory bank of the DRAM; as well as The first data is transferred from the corresponding first SRAM buffer based at least in part on the command and after the second data is transferred from the memory bank of the DRAM to the corresponding second SRAM buffer.

22. The memory device according to claim 21, in, The interface controller is further operable to: The second data is transferred from the corresponding second SRAM buffer to the FeRAM.

23. The memory device according to claim 22, in, The command includes a read command for the first data, and the interface controller is further operable to: determining whether the group of memory cells in the DRAM stores the second data; Based at least in part on determining that the set of memory cells in the DRAM stores the second data, the first data is transferred from the FeRAM to the corresponding first SRAM buffer, wherein the first data is transferred from the corresponding first SRAM buffer to the set of memory cells in the DRAM.

24. The memory device according to claim 22, in, The command includes a write command for the first data, and the interface controller is further operable to: transferring the first data to the FeRAM for storage at the memory address; and Determine whether the group of memory cells in the DRAM stores the second data, wherein the first data from the corresponding first SRAM buffer is transferred to the group of memory cells in the DRAM at least partially based on determining that the group of memory cells in the DRAM stores the second data.

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