Layout Method, Device and Related Equipment of Node Unit in Programmable Logic Device

Abstract

The present invention discloses a layout method for node units in a programmable logic device, which is applied to the field of FPGA chip design and is used to improve the efficiency of global layout in the FPGA chip design process. The method provided by the present invention includes: obtaining all timing paths from input units to output units, and a preset maximum delay threshold for each timing path; setting the path between adjacent node units in each timing path as a sub-timing path, and calculating the preset maximum delay of the sub-timing path; adjusting the positions of at least one of the node units, and the actual sub-timing path delay of the sub-timing path of the adjusted node unit is less than the preset maximum delay of the sub-timing path; calculating a timing loss value and determining whether the timing loss value is less than a preset timing loss value. If not, loop the steps between adjusting the positions of at least one of the node units and determining whether the timing loss value is less than the preset timing loss value. If so, complete the global layout of the FPGA chip.

Description

Technical Field

[0001] The present invention relates to the technical field of programmable logic devices (Programmable Logic Device), and particularly relates to a layout method, device, computer device and storage medium for node units in a programmable logic device. Background Art

[0002] The FPGA chip in a programmable logic device has programmable functions, but often the designed chip needs to meet relatively high timing requirements. How to ensure that the timing meets the design requirements during the chip layout design is very important; global layout is a very important link in the chip design layout process, which basically determines the approximate positions of the chip design units and has a great impact on the actual timing of the chip design. Therefore, it is more important to ensure the timing requirements of the chip design during the global layout process.

[0003] In the traditional global layout process of an FPGA chip, the positions of the design units are continuously adjusted. After each adjustment is completed, it is necessary to recalculate whether the total delay of each timing-required path where the adjusted design unit is located is within the specified range, resulting in a very long time-consuming global layout process and reducing the efficiency of FPGA chip design and development. Summary of the Invention

[0004] Embodiments of the present invention provide a layout method, device, computer device and storage medium for node units in a programmable logic device to solve the problem of long time consumption in the global layout process in traditional FPGA chip design.

[0005] A layout method for node units in a programmable logic device includes:

[0006] Obtain all timing paths from the input unit to the output unit, and the preset maximum delay threshold for each timing path;

[0007] Set the path between adjacent node units in each timing path as a sub-timing path, and calculate the preset maximum sub-timing path delay according to the preset maximum delay threshold and the number of the sub-timing paths, where the node units include the input unit and the output unit;

[0008] Adjust the position of at least one of the node units so that the actual sub-timing path delay of the sub-timing path of the adjusted node unit is less than the preset maximum sub-timing path delay;

[0009] Calculate a timing loss value according to the preset maximum sub-timing path delay, the actual sub-timing path delay and a preset loss function;

[0010] Determine whether the timing loss value is less than a preset timing loss value. If not, loop through the steps between adjusting the positions of at least one of the node units and determining whether the timing loss value is less than the preset timing loss value until the layout is completed when the timing loss value is less than the preset timing loss value.

[0011] A layout device for node units in a programmable logic device, comprising:

[0012] An acquisition module, configured to acquire all timing paths from an input unit to an output unit, and a preset maximum delay threshold for each timing path;

[0013] A first calculation module, configured to set the path between adjacent node units in each timing path as a sub-timing path, and calculate a preset maximum sub-timing path delay according to the preset maximum delay threshold and the number of the sub-timing paths, where the node units include the input unit and the output unit;

[0014] An adjustment module, configured to adjust the positions of at least one of the node units such that the actual sub-timing path delay of the sub-timing path of the adjusted node unit is less than the preset maximum sub-timing path delay;

[0015] A second calculation module, configured to calculate a timing loss value according to the preset maximum sub-timing path delay, the actual sub-timing path delay, and a preset loss function;

[0016] A judgment module, configured to judge whether the timing loss value is less than a preset timing loss value. If not, loop through the steps between adjusting the positions of at least one of the node units and judging whether the timing loss value is less than the preset timing loss value until the layout is completed when the timing loss value is less than the preset timing loss value.

[0017] A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, where when the processor executes the computer program, the steps of the layout method for node units in the above programmable logic device are implemented.

[0018] A computer-readable storage medium storing a computer program, where when the computer program is executed by a processor, the steps of the layout method for node units in the above programmable logic device are implemented.

[0019] The layout method, device, computer device and storage medium of node units in a programmable logic device proposed in this application are applied to the field of FPGA chip design. By calculating the preset maximum delay of each sub-timing path according to the preset maximum delay threshold set for each timing path, and then during the global placement process of the FPGA chip, when adjusting the position of a single node unit, ensuring that the actual delay of the sub-timing path where the node unit is located does not exceed the preset maximum delay of the sub-timing path. After adjusting the node unit during the global placement process, there is no need to perform timing calculation and analysis tasks, which greatly reduces the time consumption of the global placement process and also meets the timing requirements of the FPGA chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0021] Figure 1 is a flowchart of a layout method of node units in a programmable logic device according to an embodiment of the present invention;

[0022] Figure 2 is a schematic structural diagram of a timing path and a sub-timing path according to an embodiment of the present invention;

[0023] Figure 3 is an example diagram of a simple timing path according to an embodiment of the present invention;

[0024] Figure 4 is an example diagram of a complex timing path according to an embodiment of the present invention;

[0025] Figure 5 is a schematic structural diagram of a layout device of node units in a programmable logic device according to an embodiment of the present invention;

[0026] Figure 6 is a schematic diagram of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0028] In one embodiment, asFigure 1 As shown in the figure, a layout method for node units in a programmable logic device is provided, including the following steps S101 to S105:

[0029] S101. Obtain all timing paths from input units to output units, and the preset maximum delay threshold for each timing path.

[0030] Among them, in this embodiment, an FPGA chip, which is one of the programmable logic devices, is taken as an example for illustration.

[0031] Among them, as Figure 2 shown, FF1 and FF2 are common register units in the FPGA chip design, LUT1, LUT2, and LUT3 are common look-up tables (LUTs) in the FPGA chip design, and CLK is a system clock related to timing; the data DATA to be transmitted needs to be input from the FF1 unit, then pass through the LUT1 unit, the LUT2 unit, and the LUT3 unit, and finally output from the FF2 unit. Then, the data transmission path with timing requirements from the FF1 unit to the FF2 unit is called a timing path; when performing global layout, the maximum delay threshold of the timing path from the FF1 unit to the FF2 unit will be set.

[0032] In some embodiments, setting a preset maximum delay threshold for each of the timing paths can ensure that the timing paths meet the design requirements in the global layout process of the FPGA chip design.

[0033] Among them, the determination of the timing path can be the timing path from the FF1 unit to the FF2 unit or the timing path from the FF2 unit to the FF1 unit. That is, the timing path from the FF1 unit to the FF2 unit and the timing path from the FF2 unit to the FF1 unit are defined as the same timing path; before searching for the timing path, the determination rule of the timing path will be formulated first, that is, the path from the input unit to the output unit is unified as the only timing path or the path from the output unit to the input unit is unified as the only timing path.

[0034] S102. Set the path between adjacent node units in each timing path as a sub-timing path, and calculate the preset maximum delay of the sub-timing path according to the preset maximum delay threshold and the number of the sub-timing paths. The node units include the input unit and the output unit.

[0035] Among them, as Figure 2As shown, on the timing path from the FF1 unit to the FF2 unit, there are sub-paths from the FF1 unit to the LUT1 unit, from the LUT1 unit to the LUT2 unit, from the LUT2 unit to the LUT3 unit, and from the LUT3 unit to the FF2 unit.

[0036] After a preset maximum delay threshold exists in the timing path, the preset maximum delay of the sub-timing path can be calculated; the steps of calculating the preset maximum delay of the sub-timing path according to the preset maximum delay threshold and the number of sub-timing paths include:

[0037] Calculate the preset maximum delay of the sub-timing path through the following formula:

[0038] z_time = T max / N node

[0039] Where, T max represents the preset maximum delay threshold, N node represents the number of sub-timing paths, and z_time represents the preset maximum delay of the sub-timing path.

[0040] As Figure 3 shown, FF3 represents the input unit, FF4 represents the output unit, there is a timing path from the FF3 unit to the FF4 unit, the LUT3 unit, the LUT4 unit, and the LUT5 unit are the node units in the timing path, the preset maximum delay threshold of the timing path is total_delay, there are 4 sub-timing paths in the timing path, namely the first sub-timing path from the FF3 unit to the LUT3 unit, the second sub-timing path from the LUT3 unit to the LUT4 unit, the third sub-timing path from the LUT4 unit to the LUT5 unit, and the fourth sub-timing path from the LUT5 unit to the FF4 unit. Finally, the preset maximum delay delay of the first sub-timing path, the second sub-timing path, the third sub-timing path, and the fourth sub-timing path can be calculated according to the preset maximum delay calculation formula of the sub-timing path.

[0041] In the FPGA chip design diagram, there are timing paths more complex than the Figure 2 timing path shown. In this embodiment, the timing paths in the FPGA chip design diagram include simple timing paths and complex timing paths.

[0042] Among them, the simple timing path has no same node units as other timing paths, and the complex timing path has at least one same node unit as other timing paths; Figure 2 What is shown in Figure 4As described above, an example of a complex path is given in the figure. In the figure, there is not only the first timing path from the FF5 cell to the FF6 cell and the preset maximum delay threshold total_delay0 of the first timing path, but also the second timing path from the FF5 cell to the FF7 cell and the preset maximum delay threshold total_delay1 of the second timing path; the first timing path includes the sub-timing paths from the FF5 cell to the LUT6 cell, from the LUT6 cell to the LUT7 cell, from the LUT7 cell to the LUT8 cell, and from the LUT8 cell to the FF6 cell, and the second timing path includes the sub-timing paths from the FF5 cell to the LUT6 cell, from the LUT6 cell to the LUT7 cell, and from the LUT7 cell to the FF7 cell; the first timing path and the second timing path have the same node cells: the FF5 cell, the LUT6 cell, and the LUT7 cell; according to the preset maximum delay threshold total_delay0 of the first timing path, the number 4 of the sub-timing paths of the first timing path, and the preset maximum delay calculation formula for the sub-timing paths, the preset maximum delay delay0 of the sub-timing paths of the first timing path is calculated; for the second timing path, the first preset maximum delay of the sub-timing path from the FF5 cell to the LUT6 cell and the second preset maximum delay of the sub-timing path from the LUT6 cell to the LUT7 cell have been calculated, and by subtracting the first preset maximum delay of the sub-timing path and the second preset maximum delay of the sub-timing path from the preset maximum delay threshold total_delay1 of the second timing path, the preset maximum delay delay1 of the sub-timing path from the LUT7 cell to the FF7 cell is obtained.

[0043] Among them, there can also be a second calculation method for the preset maximum delay delay1 of the sub-timing path from the LUT7 cell to the FF7 cell; the preset maximum delay delay1 of the sub-timing path can also be calculated according to the preset maximum delay calculation formula for the sub-timing paths to obtain the preset maximum delay of the sub-timing path from the LUT7 cell to the FF7 cell; the preset maximum delay delay1 of the sub-timing path can also be assigned to the sub-timing paths from the FF5 cell to the LUT6 cell and from the LUT6 cell to the LUT7 cell; specifically, the calculation method of the preset maximum delay of the sub-timing path can be flexibly selected and changed according to the timing requirements of the FPGA chip design, or only a part of the timing paths can be selected to use the second calculation method.

[0044] S103. Adjust the position of at least one of the node units such that the actual sub-timing path delay of the sub-timing path of the adjusted node unit is less than the preset maximum sub-timing path delay.

[0045] Among them, during the global layout process, the position of one or more node units will be adjusted according to design requirements or other situations. Since the maximum sub-timing path delay is preset, during the process of adjusting the position of the node unit, the actual path delay of the sub-timing path where the node unit is located will be continuously calculated and compared with the preset maximum sub-timing path delay. If the actual path delay of the sub-timing path is greater than the preset maximum sub-timing path delay, it is determined that the current adjusted position of the node unit does not meet the requirements and needs to be readjusted. If the actual path delay of the sub-timing path is less than or equal to the preset maximum sub-timing path delay, it is determined that the current adjusted position of the node unit meets the requirements.

[0046] S104. Calculate the timing loss value according to the preset maximum sub-timing path delay, the actual sub-timing path delay, and a preset loss function.

[0047] In some embodiments, the step of calculating the timing loss value includes:

[0048] Calculate the timing loss value through the following preset loss function:

[0049]

[0050] Among them, d represents the actual sub-timing path delay, c represents the preset maximum sub-timing path delay, k represents a preset constant value, i represents the serial number of the sub-timing path, and c_time represents the calculated timing loss value.

[0051] In some embodiments, the calculating the preset maximum sub-timing path delay according to the preset maximum delay threshold and the number of sub-timing paths includes the following steps:

[0052] Calculate the preset maximum sub-timing path delay of the simple timing path;

[0053] Calculate the preset maximum sub-timing path delay of the complex timing path.

[0054] Among them, by default, the preset maximum sub-timing path delay of the simple timing path can be calculated first and then the preset maximum sub-timing path delay of the complex timing path, or the preset maximum sub-timing path delay of the complex timing path can be calculated first and then the preset maximum sub-timing path delay of the simple timing path. At the same time, it is also allowed to change the default calculation order.

[0055] In some embodiments, the step of calculating the maximum delay of the preset sub-timing path of the complex timing path includes:

[0056] Obtain a single timing path included in the complex timing path;

[0057] Arrange the single timing paths in ascending or descending order according to the number of sub-timing paths they contain;

[0058] Calculate the maximum delay of the preset sub-timing path of each single timing path in sequence according to the arranged result.

[0059] In some embodiments, the number of sub-timing paths owned by a single timing path represents the complexity of calculating the maximum delay of the preset sub-timing path; in this embodiment, multiple threads are started to calculate the maximum delay of the preset sub-timing path of the complex path; because after arranging the single timing paths in ascending or descending order according to the number of sub-timing paths they contain, that is, sorting the calculation complexity of all single timing paths, the number of threads to be established for calculation can be determined according to the number of single timing paths, and then the single timing paths are evenly distributed to each thread for calculation according to the sorting of the calculation complexity.

[0060] In some embodiments, since each single timing path starts from the input unit and ends at the output unit, the single timing paths included in the complex timing path are obtained by using a directed graph algorithm to count the set of single timing paths existing in the complex timing path; among them, there are two different traversal methods for the directed graph algorithm, breadth-first and depth-first. The breadth-first method and / or the depth-first method can be reasonably selected according to the layout characteristics of the node units designed by the FPGA chip; the breadth-first method and the depth-first method are common traversal methods in the algorithm field, and the specific implementation principles of the breadth-first method and the depth-first method are not described in detail in this embodiment.

[0061] S105. Determine whether the timing loss value is less than a preset timing loss value. If not, loop through the steps between adjusting the position of at least one of the node units and determining whether the timing loss value is less than the preset timing loss value until the timing loss value is less than the preset timing loss value, and then complete the layout.

[0062] Among them, when the timing loss value calculated by the preset loss function is greater than or equal to the preset timing loss value, at least one node unit in the FPGA chip design diagram will be adjusted, and then a new timing loss value will be calculated again according to the preset loss function and judged until the timing loss value is less than the preset loss value, then stop adjusting the node unit and terminate the global layout process of the FPGA.

[0063] In the layout method of the node unit in the programmable logic device proposed in this embodiment, by calculating the preset maximum delay of each sub-timing path according to the preset maximum delay threshold set for each timing path; then during the global layout process of the FPGA chip, when adjusting the position of a single node unit, it is ensured that the actual delay of the sub-timing path where the node unit is located does not exceed the preset maximum delay of the sub-timing path. After adjusting the node unit during the global layout process, the timing calculation and analysis tasks are reduced, ensuring that each adjustment of the node unit meets the timing requirements, reducing the number of trial-and-error times and the time consumed for adjusting the node unit, greatly reducing the time consumed in the global layout process, and also meeting the timing requirements of the FPGA chip design.

[0064] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0065] In one embodiment, a layout device for node units in a programmable logic device is provided. The layout device for node units in the programmable logic device corresponds one-to-one with the layout method of the node units in the programmable logic device in the above embodiment. As Figure 5 shown, the layout device 20 for node units in the programmable logic device includes an acquisition module 201, a first calculation module 202, an adjustment module 203, a second calculation module 204, and a judgment module 205. The detailed description of each functional module is as follows:

[0066] The acquisition module is used to acquire all the timing paths from the input unit to the output unit, and the preset maximum delay threshold of each timing path;

[0067] The first calculation module is used to set the path between adjacent node units in each timing path as a sub-timing path, and calculate the preset maximum delay of the sub-timing path according to the preset maximum delay threshold and the number of the sub-timing paths. The node units include the input unit and the output unit;

[0068] Among them, the first calculation module calculates the preset maximum delay of the sub-timing path through the following formula:

[0069] z_time = T max / N node

[0070] Among them, T max represents the preset maximum delay threshold, N node represents the number of the sub-timing paths, and z_time represents the calculated preset maximum delay of the sub-timing path.

[0071] An adjustment module for at least adjusting the position of one of the node units such that the actual sub-timing path delay of the sub-timing path of the adjusted node unit is less than the preset maximum sub-timing path delay;

[0072] A second calculation module for calculating a timing loss value according to the preset maximum sub-timing path delay, the actual sub-timing path delay, and a preset loss function;

[0073] Wherein, the second calculation module calculates the timing loss value through the following preset loss function:

[0074]

[0075] Wherein, d represents the actual sub-timing path delay, c represents the preset maximum sub-timing path delay, k represents a preset constant value, i represents the serial number of the sub-timing path, and c_time represents the calculated timing loss value.

[0076] A judgment module for judging whether the timing loss value is less than a preset timing loss value. If not, the steps of looping the position adjustment of at least one of the node units until judging whether the timing loss value is less than the preset timing loss value are repeated until the layout is completed when the timing loss value is less than the preset timing loss value.

[0077] In some embodiments, the timing path includes a simple timing path and a complex timing path. Among them, the simple timing path has no same node units as other timing paths, and the complex timing path has at least one same node unit as other timing paths; the first calculation module includes:

[0078] A simple timing path calculation unit for calculating a preset maximum sub-timing path delay threshold of the simple timing path;

[0079] A complex timing path calculation unit for calculating a preset maximum sub-timing path delay threshold of the complex timing path.

[0080] In some embodiments, the complex timing path calculation unit further includes:

[0081] A single timing path acquisition sub-unit for acquiring a single timing path included in the complex timing path;

[0082] A single timing path sorting sub-unit for sorting the single timing paths in ascending or descending order according to the number of sub-timing paths included;

[0083] A third calculation sub-unit for sequentially calculating the preset maximum sub-timing path delay of the single timing paths according to the arranged result.

[0084] The meanings of "first" and "second" in the above-mentioned module / unit are only used to distinguish different modules / units, and are not used to limit which module / unit has a higher priority or other limiting meanings. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules does not necessarily have to be limited to those steps or modules clearly listed, but may include other steps or modules that are not clearly listed or are inherent to these processes, methods, products, or devices. The division of modules in this application is only a logical division, and there may be other division methods in actual implementation.

[0085] For the specific limitations on the layout device of the node unit in the programmable logic device, reference can be made to the limitations on the layout method of the node unit in the programmable logic device in the above text, which will not be elaborated here. Each module in the layout device of the node unit in the above programmable logic device can be implemented in whole or in part by software, hardware, and their combination. The above-mentioned modules can be embedded in the processor in the computer device in hardware form or be independent of it, or can be stored in the memory in the computer device in software form, so as to facilitate the processor to call and execute the operations corresponding to the above-mentioned modules.

[0086] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the layout method of the node unit in the programmable logic device in the above embodiment are implemented, such as Figure 1 the steps 101 to 105 shown and the extension of other extended and related steps of the method. Alternatively, when the computer program is executed by a processor, the functions of each module / unit of the layout device of the node unit in the programmable logic device in the above embodiment are implemented, such as Figure 5 the functions of the modules 201 to 205 shown. To avoid repetition, it will not be elaborated here.

[0087] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in this application can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0088] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the layout method of the node unit in the programmable logic device in the above embodiment, such as Figure 1 Steps 101 to 105 shown and the extensions and related steps of the method. Or, when the processor executes the computer program, it implements the functions of each module / unit of the layout device of the node unit in the programmable logic device in the above embodiment, such as Figure 5 The functions of modules 201 to 205 shown. To avoid repetition, it will not be elaborated here.

[0089] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc. The processor is the control center of the computer device, connecting various parts of the entire computer device through various interfaces and lines.

[0090] The memory can be used to store the computer program and / or modules. By running or executing the computer program and / or modules stored in the memory, and by calling the data stored in the memory, the processor realizes various functions of the computer device. The memory mainly includes a program storage area and a data storage area. Among them, the program storage area can store the operating system, application programs required for at least one function (such as text editing function, image drawing function, etc.); the data storage area can store the data created according to the use of the computer device (such as text data, image data, etc.).

[0091] The memory can be integrated in the processor or can be separately provided from the processor.

[0092] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above.

[0093] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A layout method for node units in a programmable logic device, characterized in that, Including: Obtain all timing paths from the input unit to the output unit, and the preset maximum delay threshold for each timing path; Set the path between adjacent node units in each timing path as a sub-timing path, and calculate the preset maximum sub-timing path delay according to the preset maximum delay threshold and the number of the sub-timing paths, where the node units include the input unit and the output unit; Adjust the position of at least one of the node units so that the actual sub-timing path delay of the sub-timing path of the adjusted node unit is less than the preset maximum sub-timing path delay; Calculate the timing loss value according to the preset maximum sub-timing path delay, the actual sub-timing path delay, and a preset loss function; Judge whether the timing loss value is less than a preset timing loss value. If not, loop the steps between adjusting the position of at least one of the node units and judging whether the timing loss value is less than the preset timing loss value until the timing loss value is less than the preset timing loss value to complete the layout; Among them, the step of calculating the maximum delay of the preset sub-timing path according to the preset maximum delay threshold and the number of the sub-timing paths includes: calculating the maximum delay of the preset sub-timing path through the following formula: ; where represents the preset maximum delay threshold, represents the number of the sub-timing paths, represents the calculated maximum delay of the preset sub-timing path; Among them, the step of calculating the timing loss value includes: calculating the timing loss value through the following preset loss function: ; among them, represents the actual sub-timing path delay, represents the maximum preset sub-timing path delay, represents a preset constant value, i represents the serial number of the sub-timing path, represents the calculated timing loss value.

2. The layout method of the node unit in the programmable logic device according to claim 1, wherein The timing paths include simple timing paths and complex timing paths; Among them, a simple timing path has no same node units as other timing paths, and a complex timing path has at least one same node unit as other timing paths.

3. The layout method of the node unit in the programmable logic device according to claim 2, wherein, The calculating the preset maximum sub-timing path delay according to the preset maximum delay threshold and the number of the sub-timing paths includes the following steps: Calculate the preset maximum sub-timing path delay of the simple timing path; Calculate the preset maximum sub-timing path delay of the complex timing path.

4. The layout method of the node unit in the programmable logic device according to claim 3, characterized in that, The step of calculating the preset maximum sub-timing path delay of the complex timing path includes: Obtain a single timing path included in the complex timing path; Arrange the single timing path in ascending or descending order according to the number of the sub-timing paths included; Calculate the preset maximum sub-timing path delay of the single timing path in sequence according to the arranged result.

5. A layout device for a node unit in a programmable logic device, characterized in that, Including: An obtaining module, configured to obtain all timing paths from the input unit to the output unit, and the preset maximum delay threshold for each timing path; A first calculating module, configured to set the path between adjacent node units in each timing path as a sub-timing path, and calculate the preset maximum sub-timing path delay according to the preset maximum delay threshold and the number of the sub-timing paths, where the node units include the input unit and the output unit; An adjusting module, configured to adjust the position of at least one of the node units so that the actual sub-timing path delay of the sub-timing path of the adjusted node unit is less than the preset maximum sub-timing path delay; A second calculating module, configured to calculate the timing loss value according to the preset maximum sub-timing path delay, the actual sub-timing path delay, and a preset loss function; A judging module, configured to judge whether the timing loss value is less than a preset timing loss value. If not, loop the steps between adjusting the position of at least one of the node units and judging whether the timing loss value is less than the preset timing loss value until the timing loss value is less than the preset timing loss value to complete the layout; Among them, the first calculation module calculates the maximum delay of the preset sub-timing path through the following formula: ; where represents the preset maximum delay threshold, represents the number of the sub-timing paths, represents the calculated maximum delay of the preset sub-timing path; Among them, the second calculation module calculates the timing loss value through the following preset loss function: ; among them, represents the actual sub-timing path delay, represents the maximum preset sub-timing path delay, represents a preset constant value, i represents the serial number of the sub-timing path, represents the calculated timing loss value.

6. The layout device of the node unit in the programmable logic device according to claim 5, characterized in that, The first calculating module includes: A simple timing path calculation unit for calculating the maximum delay threshold of a preset sub-timing path of a simple timing path; A complex timing path calculation unit for calculating the maximum delay threshold of a preset sub-timing path of a complex timing path.

7. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, the steps of the layout method of the node unit in the programmable logic device according to any one of claims 1 to 4 are implemented.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, the steps of the layout method of the node unit in the programmable logic device according to any one of claims 1 to 4 are implemented.

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