Storage System

Abstract

An embodiment of the present invention provides a storage system capable of stable and cost-effective operation at extremely low temperatures. The storage system comprises: a memory; a first substrate on which the memory is mounted and set to a temperature below -40°C; a controller for controlling the memory; and a second substrate on which the controller is mounted, set to a temperature above -40°C, and for transmitting and receiving signals with the first substrate via a signal transmission cable.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2020-117214 (filing date: July 7, 2020), and the present application incorporates all the contents of the basic application by reference. Technical Field

[0003] One embodiment of the present invention relates to a storage system. Background Art

[0004] Memory and storage used in electronic devices used in environments with large temperature fluctuations and extremely low temperature environments are required to operate stably. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a storage system that can operate stably and at low cost at extremely low temperatures.

[0006] An embodiment provides a storage system comprising: a memory; a first substrate on which the memory is mounted and which is set to a temperature below -40°C; a controller for controlling the memory; and a second substrate on which the controller is mounted, which is set to a temperature above -40°C and which transmits and receives signals to and from the first substrate via a signal transmission cable. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a diagram showing a schematic configuration of a storage system 1 according to one embodiment.

[0008] Figure 2 This is a diagram showing a schematic configuration of a storage system 1 according to a first modification.

[0009] Figure 3 It is a diagram showing a schematic configuration of a storage system 1 according to a second modification.

[0010] Figure 4 It is a diagram showing a schematic configuration of a storage system 1 according to a third modification.

[0011] Figure 5A It is a diagram showing a first example of the temperature detector 12 .

[0012] Figure 5B It is a diagram showing a second example of the temperature detector 12 .

[0013] Figure 6 It is a block diagram showing the structure of the NAND flash memory 100.

[0014] Figure 7This is a circuit diagram showing an example of a three-dimensional NAND flash memory cell array.

[0015] Figure 8 FIG. 1 is a cross-sectional view of a portion of a NAND flash memory cell array of a three-dimensional NAND flash memory.

[0016] Figure 9 This is a diagram showing an example of threshold distribution of memory cell transistors in the SSD according to this embodiment.

[0017] Figure 10 This is a cross-sectional view showing an example of performing air bonding when connecting a pad of a memory chip and a lead of a package using a bonding wire.

[0018] Figure 11A This is a perspective view showing a state where a plurality of memory chips are stacked.

[0019] Figure 11B Observed from the normal direction of the chip surface Figure 11A Top view of the stacked chip.

[0020] Figure 11C It is from Figure 11B Side view viewed in the direction of the arrow.

[0021] Figure 12 It is a schematic representation of the manufacturing Figure 1 A step-by-step diagram of the steps of the storage system is shown.

[0022] Figure 13 This is a diagram showing the IV characteristics of the NAND flash memory used in the storage system of this embodiment.

[0023] Figure 14 This is a diagram showing the steps of countermeasures to the failure of overlapping threshold voltage distributions.

[0024] Figure 15 This is a diagram showing an example of the internal structure of a memory cell array having a plurality of storage areas corresponding to a plurality of temperature conditions.

[0025] Figure 16 This is a graph showing the threshold voltage variation characteristics of a NAND flash memory before and after heat treatment at 250° C. for 2 hours. DETAILED DESCRIPTION

[0026] The following describes an embodiment of a storage system with reference to the accompanying drawings. The following description focuses on the main components of the storage system. However, the storage system may contain components or functions not shown or described. The following description does not exclude components or functions not shown or described.

[0027] Generally speaking, it's known that the lower the temperature of a substance, the higher its electrical conductivity. In particular, at extremely low temperatures, below 77 degrees Kelvin (the boiling point of liquid nitrogen), the conductivity of an electrical conductor increases dramatically, allowing the transmission of electronic states (information generated by electrical signals) without loss or noise. In this context, for example, in quantum computers, research is underway to operate processing circuits at extremely low temperatures. Furthermore, the memory or storage connected to these circuits also needs to operate at extremely low temperatures to prevent heat transfer to the processing circuits.

[0028] Furthermore, as space continues to be developed, there is a significant temperature difference between areas in space exposed to sunlight and areas not exposed to sunlight. Consequently, the memory or storage used in electronic devices used in space must be able to withstand large temperature fluctuations and operate stably even at extremely low temperatures.

[0029] The price per bit of storage is decreasing year by year, and the price per bit of SSDs (Solid State Drives) with built-in NAND flash memory is becoming increasingly affordable. Therefore, for storage used in extremely low temperatures, SSDs are ideal.

[0030] In such a situation, for example, regarding storage devices such as SSDs, there is a demand for a technology that enables the storage devices to operate stably and at low cost at extremely low temperatures.

[0031] The storage system described below, in one embodiment, can 1) be used as storage for quantum computing; 2) utilize storage with the lowest bit cost; and 3) also be used as storage for the space industry. Before explaining the structure and operation of the storage system of this embodiment, a brief description of the storage in 1) through 3) will be provided.

[0032] 1) Storage for quantum computing

[0033] Quantum computers have processing capabilities far superior to those of existing computers, but their CPUs (Central Processing Units) are designed to operate at extremely low temperatures, less than 1K (mK). However, in reality, conventional CPUs are difficult to operate at these extremely low temperatures. As an alternative, processing circuits, such as Josephson junction elements, are being developed that operate at temperatures around 4K. Connecting wiring to processing circuits operating at extremely low temperatures will cause heat conduction, raising the surrounding temperature of the processing circuit. However, at temperatures around 4K, it is expected that heat conduction can be suppressed, maintaining an extremely low temperature.

[0034] A memory or storage needs to be connected to a CPU or other computing processing circuit. From the perspective of suppressing signal transmission loss and heat conduction, it is ideal to set the memory or storage to the same temperature as the CPU (for example, 4K). However, it is difficult to make the memory or storage operate at a temperature of 4K. Since the CMOS (Complementary Metal-Oxide-Semiconductor) circuit or memory element used in the memory or storage does not operate at a temperature of 4K, or the characteristics are greatly different, it is impossible to make the memory or storage operate in the same way as before. However, as described below, the memory or storage can operate at a temperature of 77K. When the CPU of a quantum computer is operated at a temperature of, for example, 4K, if the memory is installed on a substrate different from the CPU and set to a temperature of, for example, 77K, then the CPU and the memory can be configured so that the heat from the memory is not transferred to the CPU. Therefore, one of the characteristics of the storage system of this embodiment is that the memory can still operate normally and stably even at an extremely low temperature of about 77K.

[0035] 2) Storage with the lowest bit price

[0036] Quantum computers are undergoing various technological developments for practical application, and it is expected that the demand for memories that can be stably read and written at extremely low temperatures will gradually increase. There are various types of memories or storage devices with different operating principles. Since the amount of data to be processed continues to increase year by year, it is required that the memory with the lowest bit price can operate stably at extremely low temperatures. Nowadays, it is believed that the NAND flash memory used in SSDs has a cheaper bit price than other memories or various recording devices. Therefore, one of the characteristics of the storage system of this embodiment is that the NAND flash memory is made to operate stably at extremely low temperatures (for example, 77K). In addition, as described below, the memory used in the storage system of this embodiment is not necessarily limited to NAND flash memory, but when NAND flash memory is used, it can be used stably at extremely low temperatures.

[0037] 3) Storage for the space industry

[0038] In space, temperatures fluctuate significantly between areas shielded from sunlight and those exposed to it, ranging from approximately -200°C to over 100°C. Electronic devices used in space are designed to withstand these large temperature fluctuations and incorporate internal heaters and cooling systems to allow electronic components to operate at temperatures close to room temperature. However, this increases the complexity and cost of the entire device, including temperature control. As space development is expected to continue to advance, a memory that is as easy to control as possible, minimizes costs, and operates stably is highly sought after.

[0039] Hereinafter, a storage system that can be used as the storage in the above 1) to 3) will be described in detail. Figure 1 FIG. 1 is a diagram showing a schematic configuration of a storage system 1 according to an embodiment of the present invention. Figure 1 As shown, a storage system 1 of one embodiment includes a first substrate 3 and a second substrate 4 connected to each other by a signal transmission cable 2. There is no special requirement for the type of the first substrate 3 and the second substrate 4, and they may be, for example, a printed wiring board or a glass substrate. There is no special requirement for the type and length of the signal transmission cable 2, and the signal transmission cable 2 may have a length of, for example, more than tens of centimeters. The signal transmission cable 2 may be, for example, an FPC (Flexible Printed Circuit), or other signal transmission cables 2, such as a USB (Universal Serial Bus) signal transmission cable 2. The signal cable is made to be more than tens of centimeters in length in order to prevent heat transfer between the first substrate 3 and the second substrate 4.

[0040] Memory 5 is mounted on the first substrate 3 and is set to a temperature below -40°C. Since thermometers and temperature sensors may have measurement errors due to environmental conditions, "below -40°C" in this specification means that the target temperature is set to "below -40°C." Measurement errors in temperature sensors, etc., may result in the target temperature being set slightly above -40°C. There are no particular requirements for the type of memory 5; typically, non-volatile memories such as NAND flash memory or NOR flash memory are used. Various other non-volatile memories, such as MRAM (Magnetoresistive Random Access Memory), PRAM (Phase Change Random Access Memory), and ReRAM (Resistive Random Access Memory), may also be used as memory 5. Alternatively, memory 5 may be a volatile memory such as DRAM (Dynamic Random Access Memory). The following description focuses on an example using NAND flash memory 100 as memory 5.

[0041] In this specification, the first substrate 3 on which the NAND flash memory is mounted is sometimes referred to as an SSD module. The memory 5 is mounted on the first substrate 3 in a packaged state. Multiple memory chips 11 may be stacked in a single package. In this specification, packages mounted on the first substrate 3 and containing built-in memory chips are collectively referred to as memories 5. Alternatively, the first substrate 3 on which the memory 5 is mounted may be modularized by being covered with a housing or resin. In this case, the internal temperature of the module is assumed to be below -40°C. The reason for setting the first substrate 3 on which the memory 5 is mounted to below -40°C is that this embodiment assumes that the memory 5 operates at extremely low temperatures. While the minimum guaranteed operating temperature of conventional memories 5 is often -40°C, the memory 5 of this embodiment is different from conventional memories and is assumed to be used at temperatures below -40°C, which is the temperature at which conventional memories are guaranteed to operate. The characteristics of the memory 5 when operated below -40°C will be described below. The memory 5 internally includes a memory array and a memory controller as a peripheral circuit that controls the operation of the memory array. The present inventors have experimentally confirmed that the memory controller operates at a temperature of 77K.

[0042] A controller 6 is mounted on the second substrate 4 and is set to a temperature of -40°C or higher. The controller 6 controls the writing, reading, and erasing of data from the memory 5 in accordance with instructions from the host device. Since the controller 6 includes CMOS circuitry and has a guaranteed operating range of generally -40°C to 125°C, it can be manufactured using the same technology used in conventional SSD products.

[0043] The inventors conducted an operational test by immersing a substrate on which an existing NAND flash memory was mounted in liquid nitrogen (77K, approximately -196°C). The results confirmed that normal read operation was possible.

[0044] Based on the above experimental results, in the memory system 1 of this embodiment, the first substrate 3 on which the memory 5 is mounted is operated at a temperature of -40°C or lower, which is the lowest temperature for ensuring normal operation of the memory 5.

[0045] Figure 1 In the example, it is assumed that the first substrate 3 on which the memory 5 is mounted is immersed in, for example, liquid nitrogen. Liquid nitrogen can be manufactured industrially at low cost, so immersing the first substrate 3 in liquid nitrogen can be achieved without incurring excessive costs. Furthermore, since the first substrate 3 only needs to be kept at a temperature of -40°C or below, a refrigerant other than liquid nitrogen can also be used and the first substrate 3 can be placed in the refrigerant.

[0046] The inventors also conducted experiments to determine whether the second substrate 4, on which the controller 6 is mounted, operates at temperatures below -40°C. Specifically, they prepared multiple second substrates 4 with controllers 6 mounted on them and immersed them in liquid nitrogen for operational testing. The results revealed that none of the controllers 6 on any of the second substrates 4 operated. This is believed to be due to the fact that the controllers 6 contain built-in logic circuits, which are guaranteed to operate only at temperatures above -40°C. This leads to timing variations in various signals within the logic circuits, which can cause malfunctions. Furthermore, even if the controller 6 operates at temperatures below -40°C, since it controls all of the memories 5 mounted on the first substrate 3, there is still the problem of heat generation. For example, immersing the second substrate 4 in liquid nitrogen increases the consumption of liquid nitrogen and the cooling costs.

[0047] Therefore, in this embodiment, the temperature of the second substrate 4 on which the controller 6 is mounted is set to -40°C or higher.

[0048] As a specific example of setting the temperature of the first substrate 3 on which the memory 5 is mounted to be -40°C or lower, Figure 2 As shown in the storage system 1a of the first variation, the first substrate 3 is placed in a housing 8 containing a refrigerant 7 at a temperature below -40°C. The refrigerant 7 can be, for example, a liquid having a boiling point below -40°C, such as liquid nitrogen or liquid carbon dioxide. In addition, the refrigerant 7 needs to be a substance that is harmless to humans and, ideally, can be obtained at a low price. As for the housing 8, in order to prevent the refrigerant 7 from coming into contact with the atmosphere and causing the temperature of the refrigerant 7 to rise, and to prevent the refrigerant 7 from diffusing into the atmosphere and reducing the amount of the refrigerant 7, an insulated container with an opening as small as possible can be considered.

[0049] On the other hand, since the second substrate 4 on which the controller 6 is mounted only needs to be kept at a temperature of -40°C or above, it is also possible to set it to room temperature, for example, without using a refrigerant 7 or a cooling member. However, if there is a concern that the controller 6 is generating heat, appropriate heat dissipation measures should be implemented, such as placing a cooling member such as a heat sink in contact with the controller 6.

[0050] Figure 3 Yes Figure 1 FIG. 2 is a diagram showing a schematic configuration of a storage system 1b according to a second variation of the present invention. Figure 3 The memory system 1b includes a first substrate 3 on which the memory 5 is mounted and a second substrate 4 on which the controller 6 is mounted, and further includes a temperature control unit 9. The temperature control unit 9 controls the temperature of the first substrate 3 on which the memory 5 is mounted to be -40°C or lower.

[0051] Figure 4 Yes Figure 3 A block diagram of a storage system 1c according to a third variation in which the structure is further specified. Figure 4In the storage system 1c, a first substrate 3 is placed in a housing 8 containing a refrigerant 7, and a refrigerant control unit 10 is provided. The refrigerant control unit 10 controls at least one of the temperature and amount of the refrigerant 7. As described below, a temperature control unit 9 controls the refrigerant control unit 10 based on temperature information from a temperature detector (described below) that detects the temperature of the first substrate 3 or the memory 5. The refrigerant control unit 10 controls at least one of the temperature and amount of the refrigerant 7 in the housing 8 so that the temperature of the first substrate 3 is kept below -40°C.

[0052] Figure 5A 1 is a diagram showing a first example of the temperature detector 12. Figure 5B It is a diagram showing a second example of the temperature detector 12 . Figure 5A and Figure 5B Each of them includes a memory 5 , which is formed by covering a plurality of memory chips 11 stacked on a first substrate 3 with a package 13 .

[0053] Figure 5A The temperature detector 12 is built into the memory 5 mounted on the first substrate 3 . Figure 5A This example shows a plurality of memory chips 11 stacked on a first substrate 3. However, it is not necessary to provide a temperature detector 12 on each memory chip 11. At extremely low temperatures, thermal conductivity improves, minimizing temperature differences among the stacked memory chips 11. Therefore, by providing temperature detectors 12 on some of the stacked memory chips 11, the temperatures of memory chips 11 without built-in temperature detectors 12 can be estimated with high accuracy.

[0054] Figure 5A The temperature detector 12 detects the temperature based on, for example, a change in the resistance value of a conductor (e.g., a wiring pattern) within the memory chip 11. Thus, the temperature can be detected with high precision using a smaller circuit area. The temperature information detected by the temperature detector 12 is transmitted to the controller 6 via the signal transmission cable 2. The controller 6 sends the temperature information to the temperature control unit 9. Furthermore, the temperature control unit 9 may also be built into, for example, a host device. The temperature or amount of the refrigerant 7 for cooling the first substrate 3 may also be controlled based on instructions from the host device.

[0055] Figure 5B In the second example, a temperature detector 12 is provided inside a portion of the stacked memory chips 11 , and a temperature detector 12 is also provided on the upper surface of the uppermost memory chip 11 and the first substrate 3 . Figure 5BAlthough not shown in the figure, the temperature detector 12 may be provided on the surface of the package 13. In this way, by providing the temperature detector 12 not only inside the memory chip 11 but also inside or on the surface of the package and on the first substrate 3, the temperature of the plurality of stacked memory chips 11 can be detected with high accuracy.

[0056] As described above, the first substrate 3 is set to a temperature of -40°C or lower. However, for example, the thermal conductivity at a temperature close to -40°C is lower than that at a temperature close to -100°C. Therefore, when the first substrate 3 is set to a temperature close to -40°C, the Figure 5B As shown, a temperature detector 12 is also provided in a portion other than the interior of the memory chip 11, so as to estimate the temperature of each memory chip 11. When the first substrate 3 is set to an extremely low temperature with a sufficiently high thermal conductivity, as shown in FIG. Figure 5A As shown, the temperature detector 12 is provided only inside a portion of the memory chips 11 .

[0057] Figure 5B The temperature detector 12 disposed on the upper surface of the memory chip 11 or on the first substrate 3 may be, for example, a thermocouple formed by connecting two different metals. By using a thermocouple for temperature measurement, the temperature can be detected with high accuracy using a small circuit area.

[0058] [NAND flash memory]

[0059] As the memory 5 of this embodiment, a NAND flash memory 100 with a relatively low bit price can be used. Figure 1 The controller 6 corresponds to the controller 200. Figure 6 This is a block diagram showing the schematic structure of an SSD. Figure 1 As shown, the NAND flash memory 100 is mounted on a first substrate 3 , and the controller 200 is mounted on a second substrate 4 .

[0060] The NAND flash memory 100 has a plurality of storage cells and stores data in a non-volatile manner. Figure 1The controller 200 is connected to the NAND flash memory 100 via the NAND bus in the signal transmission cable 2 shown, and is connected to the host device 300 via the host bus. Furthermore, the controller 200 controls the NAND flash memory 100 and accesses the NAND flash memory 100 in response to commands received from the host device 300. The host device 300 is, for example, an electronic device such as a personal computer, and the host bus is, for example, a bus based on an interface such as PCIexpress (PCIe, Peripheral Component Interconnect express), UFS (Universal Flash Storage), or Ethernet. The NAND bus sends and receives signals based on a NAND interface such as a Toggle IF (Toggle Interface).

[0061] The controller 200 includes a host interface circuit 210 , a built-in memory (RAM) 220 , a processor (CPU) 230 , a buffer memory 240 , a NAND interface circuit 250 , and an ECC (Error Checking and Correcting) circuit 260 .

[0062] The host interface circuit 210 is connected to the host device 300 via a host bus, and transfers commands and data received from the host device 300 to the CPU 230 and the buffer memory 240. In addition, the host interface circuit 210 transfers data in the buffer memory 240 to the host device 300 in response to commands from the CPU 230.

[0063] The CPU 230 controls the overall operation of the controller 200. For example, upon receiving a write command from the host device 300, the CPU 230 responds by issuing a write command to the NAND interface circuit 250. The same applies to reading and erasing. Furthermore, the CPU 230 performs various processes for managing the NAND flash memory 100, such as wear leveling. The operations of the controller 200 described below can be implemented by the CPU executing firmware or by hardware.

[0064] The NAND interface circuit 250 is connected to the NAND flash memory 100 via the NAND bus within the signal transmission cable 2 and is responsible for communication with the NAND flash memory 100. Furthermore, the NAND interface circuit 250 transmits various signals to the NAND flash memory 100 and receives signals from the NAND flash memory 100 based on commands received from the CPU 230. The buffer memory 240 temporarily stores write data or read data.

[0065] RAM 220 is a semiconductor memory 5 such as DRAM or SRAM (Static Random Access Memory), and is used as a work area for CPU 230. RAM 220 also stores firmware for managing NAND flash memory 100 and various management tables.

[0066] The ECC circuit 260 performs error detection and error correction on the data stored in the NAND flash memory 100. Specifically, the ECC circuit 260 generates an error correction code when writing data, adds the error correction code to the write data, and decodes the error correction code when reading data.

[0067] Next, the configuration of the NAND flash memory 100 will be described. Figure 6 FIG. 1 is a block diagram of a storage system 1, 1a, 1b, 1c including a NAND flash memory 100. Figure 6 As shown, the NAND flash memory 100 includes a memory cell array 110 , a row decoder 120 , a driver circuit 130 , a column control circuit 140 , a register group 150 , and a sequencer 160 .

[0068] The memory cell array 110 includes a plurality of blocks BLK. These blocks BLK include a plurality of nonvolatile memory cells corresponding to rows and columns. Figure 6 , four blocks BLK0 to BLK3 are shown as an example. Memory cell array 110 stores data provided from controller 200 .

[0069] The row decoder 120 selects any one of the blocks BLK0 to BLK3 and further selects the row direction of the selected block BLK. The driver circuit 130 supplies a voltage to the selected block BLK via the row decoder 120.

[0070] When reading data, the column control circuit 140 senses the data read from the memory cell array 110, performs necessary calculations, and outputs the data DAT to the controller 200. When writing data, the column control circuit 140 transmits the write data DAT received from the controller 200 to the memory cell array 110.

[0071] The register group 150 includes an address register, a command register, etc. The address register stores an address received from the controller 200 , and the command register stores a command received from the controller 200 .

[0072] The sequencer 160 controls the overall operation of the NAND flash memory 100 based on various information stored in the register group 150 .

[0073] Figure 71 is a circuit diagram showing an example of a three-dimensional NAND flash memory cell array 110 . Figure 7 FIG. 1 shows a circuit configuration of one block BLK among a plurality of blocks in a three-dimensional NAND flash memory cell array 110. The other blocks of the NAND flash memory cell array 110 also have the same Figure 7 The circuit configuration is the same. In addition, this embodiment can also be applied to a memory cell having a two-dimensional structure.

[0074] like Figure 7 As shown, block BLK, for example, has four fingers FNG (FNG0-FNG3). Furthermore, each finger FNG includes multiple NAND strings NS. Each NAND string NS, for example, includes eight memory cell transistors MT (MT0-MT7) connected in series, and select transistors ST1 and ST2. In this specification, each finger FNG is sometimes referred to as a string St.

[0075] Furthermore, the number of memory cell transistors MT in the NAND string NS is not limited to 8. The memory cell transistors MT are arranged between the select transistors ST1 and ST2 with their current paths connected in series. The current path of the memory cell transistor MT7 at one end of the series connection is connected to one end of the current path of the select transistor ST1, and the current path of the memory cell transistor MT0 at the other end is connected to one end of the current path of the select transistor ST2.

[0076] The gates of the select transistors ST1 in each of the fingers FNG0-FNG3 are connected in common to select gate lines SGD0-SGD3. Meanwhile, the gates of the select transistors ST2 are connected in common to the same select gate line SGS across the multiple fingers FNG. Furthermore, the control gates of the memory cell transistors MT0-MT7 within the same block BLK are connected in common to word lines WL0-WL7. In other words, while word lines WL0-WL7 and select gate line SGS are connected in common across the multiple fingers FNG0-FNG3 within the same block BLK, select gate line SGD remains independent for each finger FNG0-FNG3 even within the same block BLK.

[0077] The control gate electrodes of the memory cell transistors MT0-MT7 that make up the NAND string NS are connected to word lines WL0-WL7, respectively. Furthermore, the i-th memory cell transistors MTi (i=0-n) in each NAND string NS within the same finger FNG are connected in common via the same word line WLi (i=0-n). In other words, the control gate electrodes of the memory cell transistors MTi in the same row within the block BLK are connected to the same word line WLi.

[0078] Each NAND string NS is connected to a word line WLi and also to a bit line. Each memory cell within each NAND string NS can be identified by identifying the address of the word line WLi and select gate lines SGD0-SGD3, as well as the address of the bit line. As described above, the data of the memory cells (memory cell transistors MT) located in the same block BLK is erased at once. On the other hand, data is read and written in units of physical sectors MS. One physical sector MS is connected to one word line WLi and includes multiple memory cells belonging to one finger FNG.

[0079] The controller 200 writes (programs) data in units of all NAND strings NS connected to one word line in one finger. Therefore, the unit of the amount of data programmed by the controller 200 is 4 bits x the number of bit lines.

[0080] When performing a read operation and a program operation, one word line WLi and one select gate line SGD are selected according to a physical address, and a physical sector MS is selected. In this specification, writing data to a memory cell as needed is referred to as programming.

[0081] Figure 8 FIG. 1 is a cross-sectional view of a portion of the NAND flash memory cell array 110 of the three-dimensional NAND flash memory 100. Figure 8 As shown, multiple NAND strings NS are formed in the vertical direction on a p-type well region (P-well) 41 of a semiconductor substrate. Specifically, multiple wiring layers 42 functioning as select gate lines SGS, multiple wiring layers 43 functioning as word lines WLi, and multiple wiring layers 44 functioning as select gate lines SGD are formed in the vertical direction on the p-type well region 41.

[0082] Furthermore, a memory hole 45 is formed, penetrating these wiring layers 42, 43, and 44 to reach the p-type well region 41. A blocking insulating film 46, a charge accumulation layer 47, and a gate insulating film 48 are sequentially formed on the sides of the memory hole 45. Furthermore, a conductive film 49 is embedded within the memory hole 45. The conductive film 49 functions as a current path for the NAND string NS and forms a channel when the memory cell transistor MT and the select transistors ST1 and ST2 operate. The charge accumulation layer 47 can be formed of a charge trapping film or a floating gate.

[0083] In each NAND string NS, a selection transistor ST2, a plurality of memory cell transistors MT, and a selection transistor ST1 are sequentially stacked on the p-type well region 41. A wiring layer functioning as a bit line BL is formed on the upper end of the conductive film 49.

[0084] Furthermore, an n+-type impurity diffusion layer and a p+-type impurity diffusion layer are formed within the surface of the p-type well region 41. A contact plug 50 is formed on the n+-type impurity diffusion layer, and a wiring layer functioning as a source line SL is formed on contact plug 50. Furthermore, a contact plug 51 is formed on the p+-type impurity diffusion layer, and a wiring layer functioning as a well wiring CPWELL is formed on contact plug 51. Well wiring CPWELL is used to apply an erase voltage.

[0085] Figure 8 The NAND flash memory cell array 110 is shown in FIG. Figure 8 There are multiple finger FNGs arranged in the depth direction of the paper, and a set of multiple NAND strings NS arranged in a row in the depth direction forms one finger FNG. Other finger FNGs are formed, for example, Figure 8 in the left and right directions. Figure 7 The middle figure shows 4 finger FNG0~3, Figure 8 , an example is shown in which three fingers are arranged between the contact plugs 50 and 51 .

[0086] Figure 9 1 is a diagram showing an example of threshold distribution of memory cell transistors MT in the SSD according to the present embodiment. Figure 9 Figure 2 shows an example of the threshold region distribution of a 4-bit / cell (QLC (Quadruple Level Cell)) nonvolatile memory 5. In the nonvolatile memory 5, information is stored based on the amount of charge of electrons accumulated in the charge accumulation layer 47 of the memory cell. Each memory cell has a threshold voltage corresponding to the amount of charge. Furthermore, the multiple data values ​​stored in the memory cell are associated with multiple regions (threshold regions) with different threshold voltages.

[0087] Figure 9 Regions S0 to S15 represent the threshold distribution within the 16 threshold regions. Figure 9 The horizontal axis represents the threshold voltage, and the vertical axis represents the number of memory cells (cell count). The so-called threshold distribution refers to the range of threshold fluctuation. In this way, each memory cell has 16 threshold regions separated by 15 boundaries, and each threshold region has a unique threshold distribution. Vr1 to Vr15 are the threshold voltages that serve as the boundaries of each threshold region.

[0088] In nonvolatile memory 5, such as NAND flash memory 100, multiple data values ​​correspond to multiple threshold regions of a memory cell. This correspondence is called a data code. This data code is predefined, and when data is written (programmed), charge is injected into the charge accumulation layer 47 within the memory cell so that the threshold value falls within the threshold region corresponding to the data value stored according to the data code. Furthermore, when reading data, a read voltage is applied to the memory cell, and the data logic is determined based on whether the threshold value of the memory cell is above or below the read voltage.

[0089] When reading data, the logic of the data is determined by whether the threshold of the memory cell being read is below or above the boundary read level. When the threshold is at its lowest, the memory cell is in the "erased" state, with all bits defined as "1." When the threshold is above the "erased" state, the memory cell is in the "programmed" state, with data defined as "1" or "0" according to the encoding.

[0090] [Wire bonding]

[0091] As described above, the first substrate 3 is set to a temperature below -40°C. When multiple memory chips 11 are stacked on the first substrate 3, bonding wires are required to connect the pads of the memory chips 11 in each layer to the external connection pins of the package. When the temperature is set below -40°C, the bonding wires shrink, exerting compressive stress, weakening the bonding strength between the bonding wires and the pads (pins). Depending on the situation, there is a risk of the bonding wires detaching from the pads (pins) or breaking. Especially when the bonding wires are covered with resin, the difference in thermal shrinkage between the resin and metal at low temperatures can easily lead to bond wire breakage or poor connection.

[0092] Therefore, in this embodiment, hollow bonding can be adopted. Figure 10 This is a cross-sectional view showing an example of air bonding when connecting the pads of the memory chip 11 and the leads of the package 13 using the bonding wires 15 . Figure 10 In the example, the memory chip 11 is not covered by the resin component and is in a hollow state. The memory chip 11 is arranged in the concave portion of the package 13, and a cover component 14 for sealing the package 13 is arranged above the memory chip 11 in the concave portion. Bonding wires 15 are arranged in the hollow portion surrounded by the cover component 14, the package 13 and the memory chip 11. The hollow portion can be set to a vacuum, and a specific gas (such as nitrogen) can be removed (blown away). Figure 10 As shown, by performing hollow bonding so that the periphery of the bonding wire 15 is not covered with resin, it is possible to prevent breakage or connection failure of the bonding wire 15 caused by the difference in thermal shrinkage between the resin member and the metal member.

[0093] Figure 10 1 shows an example of configuring a single-layer memory chip 11 in the concave portion of the package 13, but a plurality of stacked memory chips 11 may also be configured. In the case of stacking a plurality of memory chips 11, as shown in FIG. Figure 11A As shown in the perspective view of FIG, it is ideal to extend the bonding wires 15 evenly from the four sides of the rectangular memory chip 11. This allows the memory chip 11 to be supported by substantially the same force from all four sides, eliminating stress variations and preventing excessive stress from being applied to some bonding wires 15. This prevents failures such as breakage of the bonding wires 15.

[0094] Figure 11B Observed from the normal direction of the chip surface Figure 11A Top view of the stacked chip. Figure 11C It is from Figure 11B The side view is obtained by observing the direction of the arrow. In addition, Figure 11A and Figure 11B In the figure, for simplicity, a state in which two memory chips 11 are stacked is shown. In contrast, Figure 11C The figure shows a stacked state with four memory chips 11. As shown, by stacking the memory chips 11 with steps, the bonding wires 15 of the memory chips 11 stacked in an even-numbered order are routed in the same direction, while the bonding wires 15 of the memory chips 11 stacked in an odd-numbered order are routed in opposite directions. In each layer, the bonding wires 15 are routed from two adjacent sides of the four edges. When two memory chips 11 are stacked, the bonding wires 15 are routed evenly along all four edges, applying uniform stress to the bonding wires 15. Furthermore, each bonding wire 15 can be hollow-bonded, preventing breakage.

[0095] [Storage system manufacturing steps]

[0096] Figure 12 It is a schematic representation of the manufacturing Figure 1 The step diagram of the memory system 1, 1a, 1b, and 1c shown in FIG. In the process of manufacturing the semiconductor device, the electrical characteristics and the like are inspected using a semiconductor tester 22 in the state of the wafer 21. Generally speaking, the semiconductor tester 22 uses a temperature range of 0°C to 85°C as an operation guarantee temperature, and only the semiconductor tester 22 that inspects special semiconductor devices that operate at a temperature above -40°C is guaranteed to operate at a temperature above -40°C. In this embodiment, since the first substrate 3 on which the memory 5 is mounted is set to a temperature below -40°C, the existing semiconductor tester 22 cannot be used for inspection under this temperature condition. If a semiconductor tester 22 capable of inspection at a temperature below -40°C is developed, there is a concern that a lot of time and money will be spent. Therefore, in this embodiment, as Figure 12As shown in the step diagram, for the memory 5 mounted on the first substrate 3, the wafer 21 is in a state before being cut, and an existing semiconductor tester 22 is used to inspect it at the operation guarantee temperature of the semiconductor tester 22 (for example, a temperature range of 0°C to 85°C) (step S1). The wafer 21 that has passed the inspection is cut and singulated into individual memory chips 11 (step S2), and packaged (step S3). Thereafter, the packaged memory 5 is mounted on the first substrate 3, and the controller 6 is mounted on the second substrate 4 (step S4). Thereafter, the first substrate 3 on which the memory chip 11 is mounted is set to a temperature below -40°C for inspection.

[0097] Figure 12 In step S1, when the semiconductor tester 22 is performing an inspection, information required for the operation of the NAND flash memory 100 may be written to a portion of the storage area (hereinafter referred to as the ROM block) used as the ROM (Read-Only Memory) within the NAND flash memory 100. The data in the ROM block must be read normally even at extremely low temperatures. To this end, it is necessary to consider in advance that in actual use, the temperature of the semiconductor inspection step where data is written to the ROM block (e.g., room temperature) will drop to a temperature below -40°C (e.g., 77K) to write data to the ROM block.

[0098] [Writing ROM Block]

[0099] Figure 13 1 is a diagram showing IV characteristics (volt-ampere characteristics) of memory cell transistors of the NAND flash memory 100 used in the memory systems 1 , 1 a , 1 b , and 1 c according to the present embodiment. Figure 13 The horizontal axis is the gate voltage and the vertical axis is the source current. Figure 13 2 shows IV characteristic curves when the temperature of the NAND flash memory 100 is changed. Waveform w1 is 85°C, waveform w2 is room temperature (RT), waveform w3 is 77K (-196°C), and waveform w4 is -100°C.

[0100] Figure 13The waveform w5 represents the reference source current (e.g., 1 nanoampere). The gate voltage at each intersection of waveforms w1 to w4 and waveform w5 is the threshold voltage (Vth) of the memory cell transistor, and the difference between them is about 1V at room temperature and 77K. Specifically, the threshold voltage at 77K moves to a point about 1V higher than the threshold voltage at room temperature. This means that the lower the temperature, the higher the threshold voltage of the NAND flash memory 100. Therefore, in the semiconductor inspection step, when writing setting information to the ROM block in each NAND flash memory 100 in the state of the wafer 21, it is considered to read the data in the ROM block at a temperature below -40°C (e.g., 77K), and write the data in a manner that becomes, for example, a threshold voltage that is about 1V lower than the threshold voltage at room temperature. Therefore, when the temperature is set to below -40°C, the threshold voltage rises, so errors are reduced and data can be read normally.

[0101] Alternatively, while the first substrate 3 on which the memory 5 is mounted is set to a temperature of -40°C or lower (e.g., 77K), data in the NAND flash memory 100 can be read, error corrected, and the corrected data stored back in the NAND flash memory 100. Consequently, if the data, which has been error-corrected at an extremely low temperature, is stored in the NAND flash memory 100 at that temperature, the threshold voltage does not fluctuate within the range set to the same temperature conditions, thereby reducing the frequency of errors when the data is subsequently read.

[0102] In addition, when writing data into the NAND flash memory 100, the temperature information at the time of writing can also be written. Figure 13 As shown, the threshold voltage of the NAND flash memory 100 varies depending on the temperature. Therefore, when the first substrate 3 is set to a specific temperature of -40°C or lower, the threshold voltage of the NAND flash memory 100 at the specific temperature can be determined based on the temperature when writing data to the NAND flash memory 100 and the specific temperature of -40°C or lower.

[0103] Furthermore, the data written to the NAND flash memory 100 loses its retention characteristics over time, increasing the likelihood of retention errors. Therefore, when the temperature of the first substrate 3 on which the memory 5 is mounted is set to -40°C or lower, it is ideal to write data to the ROM block, etc., before the temperature is set to -40°C or lower.

[0104] When used under multiple temperature conditions Figure 1When the first substrate 3 on which the memory 5 is mounted is shown, multiple storage areas corresponding to multiple temperature conditions may be provided within the memory 5. As a more specific example, blocks that perform writing and reading at temperatures above -40°C and blocks that perform writing and reading at 77K (approximately -196°C) may be provided within the NAND flash memory 100. When writing data to each block, the write voltage may be adjusted in consideration of the read temperature.

[0105] Figure 15 1 is a diagram showing an example of the internal structure of a memory cell array 110 having a plurality of storage areas corresponding to a plurality of temperature conditions. Figure 15 The memory cell array 110 has a storage region 110a for use at temperatures above 85°C, a storage region 110b for use at temperatures between -40°C and 85°C, a storage region 110c for use at temperatures between -100°C and -40°C, and a storage region 110d for use at temperatures below -100°C.

[0106] Figure 15 NAND flash memory is provided in each of the memory areas 110a-110d. However, access conditions can be modified for each memory area 110a-110d. Here, access conditions refer to, for example, write voltages and write pulse widths. Because each memory area 110a-110d is used at different temperatures, it is ideal to optimize access conditions to ensure normal and stable reading and writing at the operating temperature.

[0107] [Improvement of properties through heat treatment]

[0108] When the NAND flash memory 100 is repeatedly read and written, a failure occurs in which adjacent threshold voltage distributions overlap. Figure 14 This is a diagram showing the steps to deal with the threshold voltage distribution overlap fault. Figure 14 As shown in step S11, when adjacent threshold voltage distributions overlap, the overlap of the threshold voltage distributions can be eliminated (step S13) by performing a heat treatment at a high temperature for a predetermined time while the NAND flash memory 100 is covered by the package 13 (step S12).

[0109] Figure 16 Graphs showing threshold voltage variation characteristics of the NAND flash memory 100 before and after heat treatment at 250° C. for 2 hours. Figure 16The middle figure shows the threshold variations ΔVth1 to ΔVth3 before and after heat treatment for three write conditions (1) to (3). ΔVth1 in (1) shows the threshold variation when only one read / write cycle is performed in the initial state. ΔVth2 in (2) shows the threshold variation after 1200 read / write cycles from the initial state. ΔVth3 in (3) shows the threshold variation after heat treatment at 250°C for 2 hours.

[0110] The threshold voltage changes greatly due to repeated reading and writing, but if Figure 16 As shown, by performing a heat treatment, the fluctuation of the threshold voltage of the NAND flash memory 100 can be suppressed and restored to its initial state. As shown in this embodiment, when the NAND flash memory 100 is used at a temperature below -40°C and the overlap of the threshold voltage distributions of the memory cell transistors increases due to repeated reading and writing to a certain number of times, it is temporarily placed outside the environment below -40°C and then heat treated at a high temperature to restore the initial characteristics, allowing it to be used again in an environment below -40°C.

[0111] Thus, in this embodiment, since the NAND flash memory 100 can still read and write normally at a temperature below -40°C, and the controller 6 can operate normally as long as the temperature is above -40°C, Figure 1 As shown, the first substrate 3 on which the memory 5 is mounted is set to a temperature below -40°C, and the second substrate 4, which is connected to the first substrate 3 by a signal transmission cable 2 and on which the controller 6 is mounted, is set to a temperature above -40°C. Since the controller 6 operates at a temperature above -40°C, an existing controller 6 can be used as is, thereby reducing development costs. Since the controller 6 controls all the memories 5 mounted on the first substrate 3, the operation time is long, the power consumption is high, and the heat generation is high. However, in this embodiment, since the controller 6 operates at a temperature above -40°C, it is not affected by the amount of refrigerant 7 (e.g., liquid nitrogen) used to cool the first substrate 3, and the cooling cost of the entire storage system can be kept low.

[0112] Furthermore, since the first substrate 3 and the second substrate 4 are connected by the signal transmission cable 2 , heat from the controller 6 on the second substrate 4 can be prevented from being transferred to the first substrate 3 , thereby reducing cooling costs and maintaining the first substrate 3 at a low temperature.

[0113] As a specific example of this embodiment, the first substrate 3 on which the memory 5 is mounted can be immersed in inexpensive liquid nitrogen serving as the refrigerant 7, and the second substrate 4 connected to the other end of the signal transmission cable 2 connected to the first substrate 3 can be set to a temperature of -40°C or higher to operate the controller 6. Since the storage systems 1, 1a, 1b, and 1c can be constructed using existing components without using particularly expensive components, development costs and cooling costs can be reduced.

[0114] Since the storage systems 1, 1a, 1b, and 1c of this embodiment assume that the memory 5 can be read and written at extremely low temperatures of -40°C or below, they can be applied to the memory 5 used in quantum computers, for example. This allows for the installation of large-capacity storage and memory near the quantum bits of the quantum computer or the CPU that controls the quantum bits. In the storage systems 1, 1a, 1b, and 1c of this embodiment, although the controller 6 mounted on the second substrate 4 operates at temperatures above -40°C, heat transfer is blocked between the first substrate 3 and the second substrate 4 by the signal transmission cable 2. This prevents the quantum computer or the control CPU from being affected by heat diffusion.

[0115] Furthermore, the memory systems 1, 1a, 1b, and 1c of this embodiment can also be used in locations with significant temperature differences, such as outer space. As described above, since multiple storage areas corresponding to various temperature conditions can be provided within the memory 5 mounted on the first substrate 3, and the threshold voltage optimally set for each storage area corresponding to the corresponding temperature condition, the memory 5 can be used under a wide range of temperature conditions.

[0116] Furthermore, as the memory 5 mounted on the first substrate 3, a NAND flash memory 5 with the cheapest bit price can be used. In addition, the controller 6 can use an existing controller, so the component cost of the storage system 1, 1a, 1b, 1c of this embodiment can be suppressed to a low level.

[0117] The present invention is not limited to the above-described embodiments and encompasses various modifications that could be conceived by those skilled in the art. Furthermore, the effects of the present invention are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible without departing from the conceptual ideas and gist of the present invention as defined by the claims and their equivalents.

[0118] [Explanation of Symbols]

[0119] 1,1a,1b,1c Storage System

[0120] 2 Signal transmission cables

[0121] 3. First substrate

[0122] 4 Second substrate

[0123] 5 Memory

[0124] 6 Controller

[0125] 7 refrigerant

[0126] 8 Housing

[0127] 9. Temperature Control Unit

[0128] 10 Refrigerant control unit

[0129] 11 memory chips

[0130] 12 Temperature detector

[0131] 13 Package

[0132] 100 NAND flash memory

[0133] 200 controller

[0134] 14 Cover parts

[0135] 15 bonding wires.

Claims

1. A storage system comprising: Memory; The first substrate is used to mount the memory and is set to be below -40°C; A controller for controlling the memory; The second substrate is used to mount the controller, is set to a temperature of -40°C or higher, and transmits and receives signals with the first substrate via a signal transmission cable; a package having a plurality of pins for external connection and covering the memory; and A plurality of hollow bonding wires connect the plurality of pads of the memory and the plurality of pins.

2. The storage system according to claim 1, wherein the memory is a laminated body formed by laminating a plurality of rectangular chips. The plurality of hollow bonding wires are evenly arranged in four directions from the chips of each layer of the laminate.

3. A storage system comprising: Memory; The first substrate is used to mount the memory and is set to be below -40°C; a controller to control the memory; and The second substrate is for mounting the controller, is set to a temperature of -40°C or higher, and transmits and receives signals with the first substrate via a signal transmission cable; and The memory includes a nonvolatile storage unit for storing an operating condition of the memory. The nonvolatile storage unit stores the operating condition at a temperature of -40° C. or higher based on a result of testing the wafer of the memory before dicing at a temperature of -40° C. or higher. 4 . The storage system according to claim 3 , wherein the nonvolatile storage unit assumes that reading of the nonvolatile storage unit is performed at a temperature below −40° C. based on a test result of the wafer, and stores the operating condition at a temperature above −40° C.

5. The storage system according to claim 4, wherein the nonvolatile storage unit sets the operating condition by assuming that a threshold voltage when the nonvolatile storage unit is read at a temperature below -40°C is higher than a threshold voltage when the nonvolatile storage unit is read at a temperature above -40°C.

6. The storage system according to claim 3, wherein the controller reads the operating condition written to the nonvolatile storage unit at a temperature of -40°C or higher at a temperature of -40°C or lower, corrects errors, and rewrites the read condition to the nonvolatile storage unit.

7. The storage system according to claim 3, wherein the controller writes temperature information when writing the data into the nonvolatile storage unit based on a threshold voltage when data written to the memory at a temperature above -40°C is read at a specific temperature below -40°C.

8. A storage system comprising: Memory; The first substrate is used to mount the memory and is set to be below -40°C; a controller to control the memory; and The second substrate is for mounting the controller, is set to a temperature of -40°C or higher, and transmits and receives signals with the first substrate via a signal transmission cable; and When the memory is continuously used at a temperature below -40°C, causing the characteristics of the memory to deteriorate, an annealing treatment is continuously performed at a specified temperature higher than room temperature for a specified time. After the characteristics are restored by the annealing treatment, the memory is used again at a temperature below -40°C. 9 . The memory system according to claim 1 , further comprising a temperature control unit configured to control the temperature of the first substrate on which the memory is mounted to be -40° C. or lower.

10. The storage system according to claim 9, wherein at least one of the memory and the first substrate has a temperature detector. The controller transmits the temperature detected by the temperature detector to the temperature control section, and the temperature control section controls the temperature of the first substrate based on the temperature detected by the temperature detector.

11. The storage system according to claim 8, wherein the memory has a built-in temperature detector. The temperature detector detects the temperature of the memory using the resistance value of a conductor in the memory.

12. The memory system according to claim 8, comprising a temperature detector, the temperature detector being arranged at least one of an interior of a package covering the memory, a surface of the package, and the first substrate. The temperature detector detects temperature using a voltage generated by a thermocouple.

13. The memory system according to any one of claims 1 to 8, wherein the memory is a nonvolatile memory that stores charges in a floating gate or a charge trapping film. 14 . The storage system according to claim 13 , wherein the nonvolatile memory comprises at least one of a NAND flash memory and a NOR flash memory. 15 . The storage system according to claim 14 , wherein the nonvolatile memory is an SSD (Solid State Drive) having at least one of a NAND flash memory and a NOR flash memory built in.

16. The memory system according to any one of claims 1 to 8, wherein the temperature of the first substrate on which the memory is mounted is set to 77K or lower. 17 . The memory system according to claim 16 , wherein the memory has a built-in memory controller that operates at a temperature of 77K or lower.

18. The storage system according to claim 16, wherein the first substrate is disposed in liquid nitrogen.

19. The storage system according to any one of claims 1, 3, and 8, wherein the controller divides the memory into a plurality of storage areas, and stores the data in the storage area corresponding to a temperature when writing data to the memory.

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