Reducing power of memory subsystems and power delivery networks with latency

Abstract

This application relates to reducing power of a memory subsystem and delaying power delivery networks. A package containing a memory subsystem can include a controller, volatile memory, and non-volatile memory. The package can include one or more pins for receiving a supply voltage that can be distributed to the controller, the volatile memory, and the non-volatile memory using one or more power supply rails. The memory subsystem can include one or more switching components along the one or more power supply rails for selectively decoupling the non-volatile memory from the one or more power supply rails, thereby enabling the non-volatile memory to be powered down separately from the controller and volatile memory. The controller can determine whether to couple or decouple the non-volatile memory from a power supply rail based on various criteria associated with accessing the non-volatile memory.

Description

[0001] CROSS REFERENCE

[0002] This patent application claims priority to U.S. Patent Application No. 63 / 050,677, entitled “REDUCING POWER FOR MEMORY SUBSYSTEM AND HAVING LATENCY FOR POWER DELIVERY NETWORK,” filed July 10, 2020, in the name of Mohamed Roumi et al., assigned to the assignee hereof and expressly incorporated herein in its entirety by reference thereto. TECHNICAL FIELD

[0003] The technical field relates to reducing power for a memory subsystem and having latency for a power delivery network. BACKGROUND

[0004] The following relates generally to one or more systems for memory, and more specifically, to power control for non-volatile memory.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, binary memory cells can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, individual memory cells can support more than two states, any of which can be stored. To access stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write or program a state in the memory device.

[0006] There are a variety of types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selective memory, sulfide memory technology, and the like. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain their stored logic state for a long period of time even in the absence of an external power source. Volatile memory devices, such as DRAM, can lose their stored state when disconnected from an external power source. SUMMARY

[0007] An apparatus is described. The apparatus can include volatile memory; non-volatile memory; and an interface controller coupled with the volatile memory and the non-volatile memory. The interface controller can be configured such that the apparatus: determines whether criteria associated with accessing the non-volatile memory are satisfied; and deactivates a switching component to decouple the non-volatile memory from a first power rail based at least in part on determining that the criteria are satisfied, where the first power rail is coupled with the volatile memory and with the interface controller.

[0008] An apparatus is described. The apparatus can include non-volatile memory; volatile memory; an interface controller coupled with the non-volatile memory and the volatile memory; a first power rail coupled with the volatile memory and the interface controller and configured to supply a first voltage to the volatile memory and the interface controller; and a switching component coupled with the interface controller, the first power rail, and the non-volatile memory and configured to selectively couple the first power rail with the non-volatile memory based at least in part on a signal received from the interface controller.

[0009] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium can store code that includes instructions executable by a processor of an electronic device to cause the electronic device to: determine whether criteria associated with accessing non-volatile memory of the electronic device are satisfied; and deactivate a switching component to decouple the non-volatile memory from a first power rail based at least in part on determining that the criteria are satisfied, where the first power rail is coupled with the volatile memory of the electronic device and with the interface controller of the electronic device. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 An example of a system that supports power control for non-volatile memory in accordance with examples disclosed herein is shown.

[0011] Figure 2 An example of a memory sub-system that supports power control for non-volatile memory in accordance with examples disclosed herein is shown.

[0012] Figure 3 An example of a memory sub-system that supports power control for non-volatile memory in accordance with examples disclosed herein is shown.

[0013] Figure 4 A block diagram of a memory device that supports power control for non-volatile memory in accordance with examples disclosed herein is shown.

[0014] Figure 5The illustrated flow diagrams illustrate one or more methods of supporting power control of non-volatile memory in accordance with examples disclosed herein. DETAILED DESCRIPTION

[0015] In some examples, a memory die can be included in a package that is configured to receive various signals or voltages related to operating the memory die via particular electrical contacts (e.g., balls, pins) of the package. For example, the package can include particular electrical contacts associated with receiving various power voltages, which can include DC (e.g., constant) voltages such as a VDD voltage. The power voltages received via the electrical contacts of the package can be distributed throughout the memory die using power rails (e.g., wires).

[0016] Some memory sub-systems can include a control component (e.g., a controller), volatile memory, and non-volatile memory within a single package. To maintain electrical compatibility with other memory packages, the memory sub-system package can receive power voltages using the same electrical contacts, and can distribute the received power voltages to the controller, volatile memory, and non-volatile memory. That is, in some examples, the controller, volatile memory, and non-volatile memory can be coupled with the same power rails (e.g., the same set of power rails).

[0017] However, when the memory sub-system is powered down (e.g., when power voltages are reduced or eliminated), the controller and volatile memory can lose their state (e.g., user data, configuration information, or other types of information), while the non-volatile memory can retain its state. Thus, in some cases, state information from the volatile memory can be stored in the non-volatile memory prior to the memory sub-system being powered down to ensure that the information is not lost.

[0018] In some examples, the memory sub-system can perform various operations, or can operate in various modes in which the memory sub-system does not need to access the non-volatile memory. During such periods, it can be desirable to disconnect power (e.g., power down) to the non-volatile memory to reduce power consumption of the memory sub-system. Reducing power consumption can be particularly valuable in the context of using the memory sub-system in a device with a limited battery life, such as a mobile device. However, because the non-volatile memory can be coupled to the same power rails as the controller and volatile memory, it can be difficult or impossible to power down the non-volatile memory without also powering down the controller and volatile memory.

[0019] To address this challenge and reduce power consumption of the memory sub-system, in some examples described in the disclosure, the memory sub-system can include a switching component along the power rail that enables the memory sub-system to selectively decouple the non-volatile memory from the power rail, thereby powering down the non-volatile memory separately from the controller and the volatile memory, even though the non-volatile memory can receive power via the same power rail. For example, the controller in the memory sub-system can enable or disable the switching component to couple or decouple the non-volatile memory from one or more power rails based on one or more criteria. For example, the switching component can be located on the same die as the non-volatile memory, or elsewhere on the memory sub-system package. In some examples, the switching component can be a physical switching component (e.g., a transistor) rather than software or firmware implemented in the non-volatile memory to enable the switching component to be enabled when the non-volatile memory is powered down.

[0020] In some examples, the controller can determine whether to couple or decouple the non-volatile memory from the power rail based on one or more criteria associated with determining whether the controller can receive a command or whether there is otherwise a reason (e.g., a desire) to access the non-volatile memory. For example, the controller can determine whether the memory sub-system is operating in a given mode, such as an intermediate result scratchpad mode, in which the memory sub-system is using the volatile memory as a given type of memory, such as an intermediate result scratchpad memory, without accessing the non-volatile memory. In response to determining that the memory sub-system is operating in a mode such as an intermediate result scratchpad mode, the controller can decouple the non-volatile memory from the power rail (or, if the non-volatile memory is already decoupled from the power rail, the controller can refrain from coupling the non-volatile memory from the power rail).

[0021] As another example, the memory sub-system can determine whether data required for an operation (e.g., data requested by a host device based on a command) is resident (e.g., stored) in the volatile memory or the non-volatile memory. If the data is resident in the volatile memory, the controller can decouple the non-volatile memory from the power rail (or, if the non-volatile memory is already decoupled from the power rail, the controller can refrain from coupling the non-volatile memory from the power rail).

[0022] As yet another example, a memory sub-system can sometimes enter a power saving mode, such as a sleep mode, in which portions or all of the components of the memory sub-system can be powered down or operate at a reduced power. For example, the memory sub-system can receive a command to enter a sleep mode or can enter another mode of operation such that components in the memory sub-system are powered down. For example, the memory sub-system can periodically "wake up" (e.g., power up) to send messages or check for incoming signals. When the memory sub-system wakes up to perform these functions, the memory sub-system can not need to use the non-volatile memory. Thus, in some examples, the controller can determine that the memory sub-system is entering a sleep mode and can disable the switching component to decouple the non-volatile memory from the power rail prior to entering the sleep mode. When the memory sub-system "wakes up," the controller can refrain from coupling the non-volatile memory to the power rail, thereby powering down the non-volatile memory to conserve battery life.

[0023] Features of the disclosure are described initially in the context of a system and die described with reference to Figures 1-2 Features of the disclosure are described initially in the context of a system and die described with reference to Figure 3 Features of the disclosure are described initially in the context of a system and die described with reference to Figures 4-5 These and other features of the disclosure are further illustrated by and described in terms of apparatus diagrams and flowcharts related to power control to non-volatile memory, as described with reference to

[0024] Figure 1 An example of a system 100 that supports power control to non-volatile memory in accordance with examples disclosed herein is shown. The system 100 can be included in an electronic device, such as a computer or a phone. The system 100 can include a host device 105 and a memory sub-system 110. The host device 105 can be a processor or system on a chip (SoC) that interfaces with an interface controller 115 and other components of an electronic device that includes the system 100. The memory sub-system 110 can store and provide access to electronic information (e.g., digital information, data) for the host device 105. The memory sub-system 110 can include the interface controller 115, volatile memory 120, and non-volatile memory 125. In some examples, the interface controller 115, volatile memory 120, and non-volatile memory 125 can be included in the same physical package, such as a package 130. However, the interface controller 115, volatile memory 120, and non-volatile memory 125 can be disposed on different, respective dies (e.g., silicon dies).

[0025] Devices in system 100 can be coupled through various conductive lines (e.g., traces, printed circuit board (PCB) wiring, redistribution layer (RDL) wiring), which can enable communication of information (e.g., commands, addresses, data) between devices. The conductive lines can constitute channels, data buses, command buses, address buses, etc.

[0026] Memory sub-system 110 can be configured to provide the advantages of non-volatile memory 125 while maintaining compatibility with host device 105, which supports protocols for different types of memory (e.g., volatile memory 120, among other examples). For example, non-volatile memory 125 can provide advantages (e.g., relative to volatile memory 120), such as non-volatility, higher capacity, or lower power consumption. However, host device 105 can be configured incompatibly or inefficiently with various aspects of non-volatile memory 125. For example, host device 105 can support voltages, access latencies, protocols, page sizes, etc. that are incompatible with non-volatile memory 125. To compensate for the incompatibilities between host device 105 and non-volatile memory 125, memory sub-system 110 can be configured with volatile memory 120, which can be compatible with host device 105 and act as a cache for non-volatile memory 125. Thus, host device 105 can use protocols supported by volatile memory 120 while benefiting from the advantages of non-volatile memory 125.

[0027] In some examples, system 100 can be included in or coupled to a computing device, an electronic device, a mobile computing device, or a wireless device. The device can be a portable electronic device. For example, the device can be a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, etc. In some examples, the device associated with system 100 can be configured for two-way wireless communication via a base station or an access point. In some examples, the device associated with system 100 can be capable of machine type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication. In some examples, the device associated with system 100 can be referred to as user equipment (UE), a station (STA), a mobile terminal, etc.

[0028] The host device 105 can be configured to interface with the memory sub-system 110 using a first protocol supported by the interface controller 115 (e.g., low power double data rate (LPDDR)). Thus, in some examples, the host device 105 can interface directly with the interface controller 115 and indirectly with the non-volatile memory 125 and the volatile memory 120. In alternative examples, the host device 105 can interface directly with the non-volatile memory 125 and the volatile memory 120. The host device 105 can also interface with other components of an electronic device that includes the system 100. The host device 105 can be or include a SoC, a general purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it can be a combination of these types of components. In some examples, the host device 105 can be referred to as a host.

[0029] The interface controller 115 can be configured to interface with the volatile memory 120 and the non-volatile memory 125 on behalf of the host device 105 (e.g., based on one or more commands or requests issued by the host device 105). For example, the interface controller 115 can facilitate retrieval and storage of data in the volatile memory 120 and the non-volatile memory 125 on behalf of the host device 105. Thus, the interface controller 115 can facilitate transfer of data between various subcomponents, such as between the host device 105, at least some of the volatile memory 120, or the non-volatile memory 125. The interface controller 115 can interface with the host device 105 and the volatile memory 120 using a first protocol and can interface with the non-volatile memory 125 using a second protocol supported by the non-volatile memory 125. In some examples, the interface controller 115 can be referred to as a control component.

[0030] The non-volatile memory 125 can be configured to store digital information (e.g., data) for an electronic device that includes the system 100. Accordingly, the non-volatile memory 125 can include one or more arrays of memory cells and a local memory controller configured to operate the arrays of memory cells. In some examples, the memory cells can be or include FeRAM cells (e.g., the non-volatile memory 125 can be FeRAM). The non-volatile memory 125 can be configured to interface with the interface controller 115 using a second protocol that is different from a first protocol used between the interface controller 115 and the host device 105. In some examples, the non-volatile memory 125 can have a longer access operation latency than the volatile memory 120. For example, retrieving data from the non-volatile memory 125 can take longer than retrieving data from the volatile memory 120. Similarly, writing data to the non-volatile memory 125 can take longer than writing data to the volatile memory 120. In some examples, as described herein, the non-volatile memory 125 can have a smaller page size than the volatile memory 120.

[0031] The volatile memory 120 can be configured to be used as a cache for one or more components (e.g., the non-volatile memory 125). For example, the volatile memory 120 can store information (e.g., data) for an electronic device that includes the system 100. Accordingly, the volatile memory 120 can include one or more arrays of memory cells and a local memory controller configured to operate the arrays of memory cells. In some examples, the memory cells can be or include DRAM cells (e.g., the volatile memory can be DRAM). The non-volatile memory 125 can be configured to interface with the interface controller 115 using a first protocol used between the interface controller 115 and the host device 105.

[0032] In some examples, the volatile memory 120 can have a shorter access operation latency than the non-volatile memory 125. For example, retrieving data from the volatile memory 120 can take less time than retrieving data from the non-volatile memory 125. Similarly, writing data to the volatile memory 120 can take less time than writing data to the non-volatile memory 125. In some examples, the volatile memory 120 can have a larger page size than the non-volatile memory 125. For example, the page size of the volatile memory 120 can be 2 kilobytes (2 kB) and the page size of the non-volatile memory 125 can be 64 bytes (64 B) or 128 bytes (128 B).

[0033] While the non-volatile memory 125 can be a higher density memory compared to the volatile memory 120, accessing the non-volatile memory 125 can take more time than accessing the volatile memory 120 (e.g., due to different architectures and protocols, among other reasons). Thus, using the volatile memory 120 as a cache can reduce latency in the system 100. As an example, by retrieving data from the volatile memory 120 rather than from the non-volatile memory 125, an access request for data from the host device 105 can be satisfied relatively quickly. To facilitate using the volatile memory 120 as a cache, the interface controller 115 can include a plurality of buffers 135. The buffers 135 can be disposed on the same die as the interface controller 115 and can be configured to temporarily store data for transfer between the volatile memory 120, the non-volatile memory 125, or the host device 105 (or any combination thereof) during one or more access operations (e.g., storage and retrieval operations).

[0034] An access operation can also be referred to as an access process or an access procedure and can involve one or more sub-operations performed by one or more of the components of the memory sub-system 110. Examples of access operations can include: a storage operation, in which data provided by the host device 105 is stored (e.g., written) in the volatile memory 120 or the non-volatile memory 125 (or both); and a retrieval operation, in which data requested by the host device 105 is obtained (e.g., read) from the volatile memory 120 or the non-volatile memory 125 and returned to the host device 105.

[0035] To store data in the memory sub-system 110, the host device 105 can initiate a storage operation (or“storage process”) by transmitting a storage command (also referred to as a storage request, a write command, or a write request) to the interface controller 115. The storage command can be for a set of non-volatile memory cells in the non-volatile memory 125. In some examples, the set of memory cells can also be referred to as a portion of memory. The host device 105 can also provide data to be written to the set of non-volatile memory cells to the interface controller 115. The interface controller 115 can temporarily store the data in the buffer 135-a. After storing the data in the buffer 135-a, the interface controller 115 can transfer the data from the buffer 135-a to the volatile memory 120 or the non-volatile memory 125, or both. In a write-through mode, the interface controller 115 can transfer the data to both the volatile memory 120 and the non-volatile memory 125. In a write-back mode, the interface controller 115 can transfer the data to only the volatile memory 120.

[0036] In either mode, the interface controller 115 can identify an appropriate set of one or more volatile memory units in the volatile memory 120 for storing data associated with a store command. To do so, the interface controller 115 can implement a set-associative mapping in which each set (e.g., block) of one or more non-volatile memory units in the non-volatile memory 125 can be mapped to a plurality of sets of volatile memory units in the volatile memory 120. For example, the interface controller 115 can implement an n-way associative mapping that allows data from a set of non-volatile memory units to be stored in one of n sets of volatile memory units in the volatile memory 120. Accordingly, the interface controller 115 can manage the volatile memory 120 as a cache for the non-volatile memory 125 by referencing the n sets of volatile memory units associated with a target set of non-volatile memory units. As used herein, a "set" of objects can refer to one or more of the objects, unless otherwise described or referred to. While described with reference to a set-associative mapping, the interface controller 115 can manage the volatile memory 120 as a cache by implementing one or more other types of mappings, such as direct mappings or associative mappings, among other examples.

[0037] After determining which n sets of volatile memory units are associated with a target set of non-volatile memory units, the interface controller 115 can store data in one or more of the n sets of volatile memory units. Accordingly, by retrieving data from the low-latency volatile memory 120 instead of the high-latency non-volatile memory 125, subsequent retrieval commands for the data from the host device 105 can be efficiently satisfied. The interface controller 115 can determine which of the n sets of volatile memory 120 to store data based on one or more parameters associated with the data stored in the n sets of volatile memory 120, such as a validity, age, or modification status of the data. Accordingly, by storing data in the volatile memory 120, a store command of the host device 105 can be satisfied completely (e.g., in write-back mode) or partially (e.g., in write-through mode). To track data stored in the volatile memory 120, the interface controller 115 can store a tag address for one or more sets of volatile memory units (e.g., for each set of volatile memory units) that indicates non-volatile memory units with data stored in a given set of volatile memory units.

[0038] To retrieve data from the memory sub-system 110, the host device 105 can initiate a retrieval operation (also referred to as a retrieval process) by transmitting a retrieval command (also referred to as a retrieval request, a read command, or a read request) to the interface controller 115. The retrieval command can be for a set of one or more non-volatile memory cells in the non-volatile memory 125. After receiving the retrieval command, the interface controller 115 can check the requested data in the volatile memory 120. For example, the interface controller 115 can check the requested data in the n-sets of volatile memory cells that are associated with the target set of non-volatile memory cells. If one of the n-sets of volatile memory cells stores the requested data (e.g., stores data for the target set of non-volatile memory cells), the interface controller 115 can transfer the data from the volatile memory 120 to the buffer 135-a so that it can be transmitted to the host device 105. The term “hit” can be used to refer to the context in which the volatile memory 120 stores the data requested by the host device 105. If the n-sets of one or more volatile memory cells do not store the requested data (e.g., the n-sets of volatile memory cells store data for a set of non-volatile memory cells other than the target set of non-volatile memory cells), the interface controller 115 can transfer the requested data from the non-volatile memory 125 to the buffer 135-a so that it can be transmitted to the host device 105. The term “miss” can be used to refer to the context in which the volatile memory 120 does not store the data requested by the host device 105.

[0039] In a miss context, after transferring the requested data to buffer 135-a, interface controller 115 can transfer the requested data from buffer 135-a to volatile memory 120, so that subsequent read requests for the data can be satisfied by volatile memory 120 instead of non-volatile memory 125. For example, interface controller 115 can store the data in one of the n sets of volatile memory cells associated with the target set of non-volatile memory cells. But the n sets of volatile memory cells can already store data for other sets of non-volatile memory cells. Thus, to preserve this other data, interface controller 115 can transfer the other data to buffer 135-b so that it can be transferred to non-volatile memory 125 for storage. Such a process can be referred to as “eviction,” and the data transferred from volatile memory 120 to buffer 135-b can be referred to as “victim” data. In some cases, interface controller 115 can transfer a subset of the victim data from buffer 135-b to non-volatile memory 125. For example, interface controller 115 can transfer one or more subsets of the victim data that have changed since the data was originally stored in non-volatile memory 125. Data that is not consistent between volatile memory 120 and non-volatile memory 125 (e.g., due to updates in one memory but not the other) can in some cases be referred to as “modified” or “dirty” data. In some examples (e.g., when the interface controller operates in a mode such as write-back mode), dirty data can be data that exists in volatile memory 120 but not in non-volatile memory 125.

[0040] In some examples, memory sub-system 110 can be configured to receive one or more supply voltages via one or more pins of memory sub-system 110 and distribute the one or more supply voltages to interface controller 115, volatile memory 120, and non-volatile memory 125 using one or more supply rails (e.g., electrically conductive paths within memory sub-system 110). In some examples, memory sub-system 110 can include one or more switching components coupled between the supply rails and non-volatile memory 125 to enable interface controller 115 to power down non-volatile memory 125 independently of interface controller 115 and volatile memory 120. Interface controller 115 can determine whether to power down non-volatile memory 125 based on various criteria associated with accessing non-volatile memory 125, as described with reference to Figure 3 More details are described.

[0041] Figure 2 An example of a memory sub-system 200 that supports power control for non-volatile memory in accordance with examples disclosed herein is shown. Memory sub-system 200 can be a memory sub-system as described with reference to Figure 1An example of the memory sub-system 110 is described. Thus, the memory sub-system 200 can interact with a host device as described with reference to Figure 1 The memory sub-system 200 can include an interface controller 202, volatile memory 204, and non-volatile memory 206, which can be examples of the interface controller 115, volatile memory 120, and non-volatile memory 125, respectively, described with reference to Figure 1 Thus, the interface controller 202 can represent a host device as described with reference to Figure 1 The interface controller 202 can use the volatile memory 204 as a cache for the non-volatile memory 206. Using the volatile memory 204 as a cache can allow the sub-system to provide the advantages of the non-volatile memory 206 (e.g., non-volatile, high-density storage) while maintaining compatibility with host devices that support different protocols as compared to the non-volatile memory 206.

[0042] In Figure 2 The dashed lines between components represent a data flow or a path of communication of data, and the solid lines between components represent a command flow or a path of communication of commands. In some cases, the memory sub-system 200 is one of a plurality of similar or identical sub-systems that can be included in an electronic device. Each sub-system can be referred to as a slice and can be associated with a respective channel of a host device in some examples.

[0043] The non-volatile memory 206 can be configured to be used as main memory for a host device (e.g., memory for long-term data storage). In some cases, the non-volatile memory 206 can include one or more arrays of FeRAM cells. Each FeRAM cell can include a selection component and a ferroelectric capacitor, and can be accessed by applying an appropriate voltage to one or more access lines, such as word lines, plate lines, and digit lines. In some examples, a subset of FeRAM cells coupled with an enabled word line can be sensed, e.g., in parallel or simultaneously, without having to sense all FeRAM cells coupled with the enabled word line. Thus, a page size for a FeRAM array can be different from (e.g., smaller than) a DRAM page size. In the context of a memory device, a page can refer to a row of memory cells (e.g., a group of memory cells having a common row address), and a page size can refer to a number of row addresses or column addresses that are accessed during an access operation, or a size of data handled by various interfaces. In some cases, different memory device types can have different page sizes. For example, a DRAM page size (e.g., 2kB) can be a superset of a non-volatile memory (e.g., FeRAM) page size (e.g., 64B).

[0044] Smaller page sizes for FeRAM arrays can provide various efficiency advantages because individual FeRAM cells can require more power to read or write as compared to individual DRAM cells. For example, smaller page sizes for FeRAM arrays can facilitate efficient energy usage because a smaller number of FeRAM cells can be enabled when associated changes in information are minor. In some examples, depending on the nature of data and commands that utilize FeRAM operations, page sizes for arrays of FeRAM cells can change, e.g., dynamically (e.g., during operation of arrays of FeRAM cells).

[0045] While individual FeRAM cells can require more power to read or write as compared to individual DRAM cells, FeRAM cells can maintain their stored logic state for extended periods of time in the absence of an external power source because ferroelectric material in FeRAM cells can maintain a non-zero electric polarization in the absence of an electric field. Thus, inclusion of FeRAM arrays in non-volatile memory 206 can provide efficiency advantages over volatile memory cells (e.g., DRAM cells in volatile memory 204) because it can reduce or eliminate the need to perform refresh operations.

[0046] Volatile memory 204 can be configured to function as a cache for non-volatile memory 206. In some cases, volatile memory 204 can include one or more arrays of DRAM cells. Each DRAM cell can include a capacitor that includes a dielectric material to store an electric charge representing a programmable state. Memory cells of volatile memory 204 can be logically grouped or arranged into one or more memory banks (as referred to herein as “banks”). For example, volatile memory 204 can include sixteen banks. Memory cells of a bank can be arranged in a grid or intersecting column and row array, and each memory cell can be accessed or refreshed by applying appropriate voltages to digit lines (e.g., column lines) and word lines (e.g., row lines) for the memory cell. Rows of a bank can be referred to as pages, and a page size can refer to the number of columns or memory cells in a row. As noted, page sizes of volatile memory 204 can be different (e.g., greater) than page sizes of non-volatile memory 206.

[0047] The interface controller 202 can include various circuitry for interfacing (e.g., communicating) with, for example, a host device, volatile memory 204, and non-volatile memory 206, among other devices. For example, the interface controller 202 can include a data (DA) bus interface 208, a command and address (C / A) bus interface 210, a data bus interface 212, a C / A bus interface 214, a data bus interface 216, and a C / A bus interface 264. The data bus interfaces can support the communication of information using one or more communication protocols. For example, the data bus interface 208, the C / A bus interface 210, the data bus interface 216, and the C / A bus interface 264 can support information communicated using a first protocol (e.g., LPDDR signaling), while the data bus interface 212 and the C / A bus interface 214 can support information communicated using a second protocol. Thus, the various bus interfaces coupled with the interface controller 202 can support different amounts of data or data rates.

[0048] The data bus interface 208 can be coupled with a data bus 260, a transaction bus 222, and buffer circuitry 224. The data bus interface 208 can be configured to transmit and receive data on the data bus 260 and to transmit and receive control information (e.g., acknowledgement / negative acknowledgement) or metadata on the transaction bus 222. The data bus interface 208 can also be configured to transfer data between the data bus 260 and the buffer circuitry 224. The data bus 260 and the transaction bus 222 can be coupled with the interface controller 202 and a host device such that a conductive path is established between the interface controller 202 and the host device. In some examples, the pins of the transaction bus 222 can be referred to as data mask inversion (DMI) pins. While shown with one data bus 260 and one transaction bus 222, there can be any number of data buses 260 and any number of transaction buses 222 coupled with the one or more data bus interfaces 208.

[0049] The C / A bus interface 210 can be coupled with a C / A bus 226 and a decoder 228. The C / A bus interface 210 can be configured to transmit and receive commands and addresses on the C / A bus 226. The commands and addresses received on the C / A bus 226 can be associated with data received or transmitted on the data bus 260. The C / A bus interface 210 can also be configured to transmit the commands and addresses to the decoder 228 such that the decoder 228 can decode the commands and forward the decoded commands and associated addresses to command circuitry 230.

[0050] The data bus interface 212 can be coupled with a data bus 232 and memory interface circuitry 234. The data bus interface 212 can be configured to transmit and receive data on the data bus 232, which can be coupled with the non-volatile memory 206. The data bus interface 212 can also be configured to transfer data between the data bus 232 and the memory interface circuitry 234. The C / A bus interface 214 can be coupled with a C / A bus 236 and the memory interface circuitry 234. The C / A bus interface 214 can be configured to receive commands and addresses from the memory interface circuitry 234 and forward the commands and addresses on the C / A bus 236 to the non-volatile memory 206 (e.g., to a local controller of the non-volatile memory 206). The commands and addresses transmitted on the C / A bus 236 can be associated with data received or transmitted on the data bus 232. The data bus 232 and the C / A bus 236 can be coupled with the interface controller 202 and the non-volatile memory 206 such that a conductive path is established between the interface controller 202 and the non-volatile memory 206.

[0051] The data bus interface 216 can be coupled with a data bus 238 and memory interface circuitry 240. The data bus interface 216 can be configured to transmit and receive data on the data bus 238, which can be coupled with the volatile memory 204. The data bus interface 216 can also be configured to transfer data between the data bus 238 and the memory interface circuitry 240. The C / A bus interface 264 can be coupled with a C / A bus 242 and the memory interface circuitry 240. The C / A bus interface 264 can be configured to receive commands and addresses from the memory interface circuitry 240 and forward the commands and addresses on the C / A bus 242 to the volatile memory 204 (e.g., to a local controller of the volatile memory 204). The commands and addresses transmitted on the C / A bus 242 can be associated with data received or transmitted on the data bus 238. The data bus 238 and the C / A bus 242 can be coupled with the interface controller 202 and the volatile memory 204 such that a conductive path is established between the interface controller 202 and the volatile memory 204.

[0052] In addition to the buses and bus interfaces for communicating with coupled devices, the interface controller 202 can include circuitry for using the non-volatile memory 206 as main memory and the volatile memory 204 as cache. For example, the interface controller 202 can include command circuitry 230, buffer circuitry 224, cache management circuitry 244, one or more engines 246, and one or more schedulers 248.

[0053] Command circuitry 230 can be coupled with buffer circuitry 224, decoder 228, cache management circuitry 244, and scheduler 248, among other components. Command circuitry 230 can be configured to receive command and address information from decoder 228 and store the command and address information in queue 250. Command circuitry 230 can include logic 262 that processes command information (e.g., from a host device) and stores information from other components (e.g., cache management circuitry 244, buffer circuitry 224) and uses the information to generate one or more commands for scheduler 248. Command circuitry 230 can also be configured to transfer address information (e.g., address bits) to cache management circuitry 244. In some examples, logic 262 can be circuitry configured to function as a finite state machine (FSM).

[0054] Buffer circuitry 224 can be coupled with data bus interface 208, command circuitry 230, memory interface circuitry 234, and memory interface circuitry 240. Buffer circuitry 224 can include a set of one or more buffer circuits for at least some groups (if not every group) of volatile memory 204. Buffer circuitry 224 can also include components (e.g., a memory controller) for accessing the buffer circuits. In one example, volatile memory 204 can include sixteen groups and buffer circuitry 224 can include sixteen sets of buffer circuits. Each set of buffer circuits can be configured to store data from (or for, or both) a respective group of volatile memory 204. As an example, the set of buffer circuits for group 0 (BK0) can be configured to store data from (or for, or both) a first group of volatile memory 204, and the buffer circuits for group 15 (BK15) can be configured to store data from (or for, or both) a sixteenth group of volatile memory 204.

[0055] Each set of buffer circuits in buffer circuitry 224 can include a pair of buffers. The pair of buffers can include one buffer (e.g., an open page data (OPD) buffer) configured to store data targeted by an access command (e.g., a store command or a retrieve command) from a host device and another buffer (e.g., a victim page data (VPD) buffer) configured to store data for an eviction process caused by the access command. For example, the set of buffer circuits for BK0 can include buffer 218 and buffer 220, which can be instances of buffers 135-a and 135-b, respectively. Buffer 218 can be configured to store BK0 data targeted by an access command from a host device. In addition, buffer 220 can be configured to store data transferred from BK0 as part of an eviction process triggered by the access command. Each buffer in a set of buffer circuits can be configured with a size (e.g., a storage capacity) that corresponds to a page size of volatile memory 204. For example, if the page size of volatile memory 204 is 2 kB, then the size of each buffer can be 2 kB. Thus, in some examples the size of a buffer can be equivalent to the page size of volatile memory 204.

[0056] Cache management circuitry 244 can be coupled with command circuitry 230, engine 246, and scheduler 248, among other components. Cache management circuitry 244 can include a set of cache management circuits for one or more (e.g., each) bank of volatile memory. As an example, cache management circuitry 244 can include sixteen sets of cache management circuits for BK0 through BK15. Each set of cache management circuits can include two memory arrays that can be configured to store storage information for volatile memory 204. As an example, the set of cache management circuits for BK0 can include memory array 252 (e.g., a CDRAM tag array (CDT-TA)) and memory array 254 (e.g., a CDRAM valid (CDT-V) array) that can be configured to store storage information for BK0. In some examples, a memory array can also be referred to as an array or a buffer. In some cases, a memory array can be or include volatile memory cells, such as SRAM cells.

[0057] The stored information can include content information, validity information, or dirtiness information (or any combination thereof) associated with the volatile memory 204. The content information (which can also be referred to as tag information or address information) can indicate which data is stored in a set of volatile memory cells. For example, the content information (e.g., tag address) for a set of one or more volatile memory cells can indicate which set of one or more non-volatile memory cells currently has the data stored in the set of one or more volatile memory cells. The validity information can indicate whether the data stored in the set of volatile memory cells is actual data (e.g., data having an expected order or form) or placeholder data (e.g., random or dummy data, not having an expected or significant order). Additionally, the dirtiness information can indicate whether the data stored in the set of one or more volatile memory cells of the volatile memory 204 is different from the corresponding data stored in the set of one or more non-volatile memory cells of the non-volatile memory 206. For example, the dirtiness information can indicate whether the data stored in the set of volatile memory cells has been updated with respect to the data stored in the non-volatile memory 206.

[0058] The memory array 252 can include memory cells that store stored information (e.g., content and validity information) for an associated group (e.g., BK0) of volatile memory 204. The stored information can be stored on a per-page basis (e.g., there can be respective stored information for each page of an associated group of non-volatile memory). The interface controller 202 can check for requested data in the volatile memory 204 by referencing the stored information in the memory array 252. For example, the interface controller 202 can receive a retrieval command from a host device for data in a set of non-volatile memory cells in the non-volatile memory 206. The interface controller 202 can use a set of one or more address bits (e.g., a set of row address bits) targeted by the access request to reference the stored information in the memory array 252. For example, using a set-associative mapping, the interface controller 202 can reference the content information in the memory array 252 to determine which set of volatile memory cells (if any) stores the requested data.

[0059] In addition to storing content information for volatile memory cells, memory array 252 can also store validity information indicating whether data in a set of volatile memory cells is actual data (also referred to as valid data) or random data (also referred to as invalid data). For example, volatile memory cells in volatile memory 204 can initially store random data and continue to do so until the volatile memory cells are written with data from a host device or non-volatile memory 206. To track which data is valid, memory array 252 can be configured to set a bit for each set of volatile memory cells when actual data is stored in the set of volatile memory cells. This bit can be referred to as a validity bit or validity flag. Like content information, validity information stored in memory array 252 can be stored on a per-page basis. Thus, in some examples each validity bit can indicate the validity of data stored in an associated page.

[0060] Memory array 254 can be similar to memory array 252 and can also include memory cells that store validity information for a group of volatile memory 204 (e.g., BK0) associated with memory array 252. However, in contrast to a per-page basis for memory array 252, validity information stored in memory array 254 can be stored on a sub-block basis. For example, validity information stored in memory cells of memory array 254 can indicate the validity of data for a subset of volatile memory cells in a set (e.g., a page) of volatile memory cells. As an example, validity information in memory array 254 can indicate the validity of each subset (e.g., 64B) of data in a page of data stored in BK0 of volatile memory 204. Storing content information and validity information on a per-page basis in memory array 252 can allow interface controller 202 to quickly and efficiently determine whether there is a hit or miss of data in volatile memory 204. Storing validity information on a sub-block basis can allow interface controller 202 to determine which subsets of data to retain in non-volatile memory 206 during an eviction process.

[0061] Each set of cache management circuitry can also include a respective pair of registers coupled with command circuitry 230, engine 246, memory interface circuitry 234, memory interface circuitry 240, and a memory array for the set of cache management circuitry, among other components. For example, a set of cache management circuitry can include a first register (e.g., register 256, which can be an open page tag (OPT) register) configured to receive storage information (e.g., one or more bits of tag information, validity information, or dirtiness information) from memory array 252 or scheduler 248-b, or both. The set of cache management circuitry can also include a second register (e.g., register 258, which can be a victim page tag (VPT) register) configured to receive storage information from memory array 254 and scheduler 248-a, or both. The information in register 256 and register 258 can be communicated to command circuitry 230 and engine 246 to enable decision making by these components. For example, command circuitry 230 can issue commands for reading non-volatile memory 206 or volatile memory 204 based on content information from register 256.

[0062] Engine 246-a can be coupled with register 256, register 258, and scheduler 248. Engine 246-a can be configured to receive storage information from various components and issue commands to scheduler 248 based on the storage information. For example, when interface controller 202 is in a first mode, such as a write-through mode, engine 246-a can issue a command to scheduler 248-b, and in response scheduler 248-b initiates or facilitates data transfer from buffer 218 to both volatile memory 204 and non-volatile memory 206. Alternatively, when interface controller 202 is in a second mode, such as a write-back mode, engine 246-a can issue a command to scheduler 248-b, and in response scheduler 248-b can initiate or facilitate data transfer from buffer 218 to volatile memory 204. In the case of a write-back operation, data stored in volatile memory 204 during a subsequent eviction process can eventually be transferred to non-volatile memory 206.

[0063] The engine 246-b can be coupled with the register 258 and the scheduler 248-a. The engine 246-b can be configured to receive the storage information from the register 258 and issue commands to the scheduler 248-a based on the storage information. For example, the engine 246-b can issue a command to the scheduler 248-a to initiate or facilitate a transfer of dirty data from the buffer 220 to the non-volatile memory 206 (e.g., as part of an eviction process). If the buffer 220 retains a set of data transferred from the volatile memory 204 (e.g., victim data), the engine 246-b can indicate which subset(s) of the set of data in the buffer 220 (e.g., which 64Bs) should be transferred to the non-volatile memory 206.

[0064] The scheduler 248-a can be coupled with various components of the interface controller 202 and can facilitate accessing the non-volatile memory 206 by issuing commands to the memory interface circuitry 234. The commands issued by the scheduler 248-a can be based on commands from the command circuitry 230, the engine 246-a, the engine 246-b, or a combination of these components. Similarly, the scheduler 248-b can be coupled with various components of the interface controller 202 and can facilitate accessing the volatile memory 204 by issuing commands to the memory interface circuitry 240. The commands issued by the scheduler 248-b can be based on commands from the command circuitry 230 or the engine 246-a, or both.

[0065] The memory interface circuitry 234 can communicate with the non-volatile memory 206 via one or more of the data bus interface 212 and the C / A bus interface 214. For example, the memory interface circuitry 234 can prompt the C / A bus interface 214 to forward a command issued by the memory interface circuitry 234 to a local controller in the non-volatile memory 206 over the C / A bus 236. Additionally, the memory interface circuitry 234 can transmit data to or receive data from the non-volatile memory 206 over the data bus 232. In some examples, the commands issued by the memory interface circuitry 234 can be supported by the non-volatile memory 206 but not the non-volatile memory 204 (e.g., the commands issued by the memory interface circuitry 234 can be different from the commands issued by the memory interface circuitry 240).

[0066] Memory interface circuitry 240 can communicate with volatile memory 204 via one or more of data bus interface 216 and C / A bus interface 264. For example, memory interface circuitry 240 can prompt C / A bus interface 264 to forward a command issued by memory interface circuitry 240 to a local controller of volatile memory 204 over C / A bus 242. Additionally, memory interface circuitry 240 can transmit data to or receive data from volatile memory 204 over one or more data buses 238. In some examples, the commands issued by memory interface circuitry 240 can be supported by volatile memory 204 rather than non-volatile memory 206 (e.g., the commands issued by memory interface circuitry 240 can be different than the commands issued by memory interface circuitry 234).

[0067] In summary, the components of interface controller 202 can use non-volatile memory 206 as main memory and volatile memory 204 as cache. Such operations can be prompted by one or more access commands (e.g., read / retrieve commands / requests and write / store commands / requests) received from a host device.

[0068] In some examples, interface controller 202 can receive a store command from a host device. The store command can be received on C / A bus 226 and transferred to command circuitry 230 via one or more of C / A bus interface 210 and decoder 228. The store command can include or be accompanied by address bits for a memory address of non-volatile memory 206. Data to be stored can be received on data bus 260 and transferred to buffer 218 via data bus interface 208. In a write-through mode, interface controller 202 can transfer the data to both non-volatile memory 206 and volatile memory 204. In a write-back mode, interface controller 202 can transfer the data only to volatile memory 204. In either mode, interface controller 202 can first check to find whether volatile memory 204 has memory cells available for storing the data. To do so, command circuitry 230 can reference memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of the n sets of volatile memory cells (e.g., pages) associated with the memory address are empty (e.g., storing random or invalid data). In some cases, a set of volatile memory cells in volatile memory 204 can be referred to as a row or cache line.

[0069] If one of the n associated sets of volatile memory cells is available for storing information, the interface controller 202 can transfer data from the buffer 218 to the volatile memory 204 for storage in the set of volatile memory cells. However, if the associated set of volatile memory cells is not empty, the interface controller 202 can initiate an eviction process to make room for the data in the volatile memory 204. The eviction process can involve transferring old data (e.g., existing data) in one of the n associated sets of volatile memory cells to the buffer 220. Dirty information for the old data can also be transferred to the memory array 254 or the registers 258 for identification of a dirty subset of the old data. After storing the old data in the buffer 220, the new data can be transferred from the buffer 218 to the volatile memory 204 and the old data can be transferred from the buffer 220 to the non-volatile memory 206. In some cases, the dirty subset of the old data is transferred to the non-volatile memory 206 and the clean subset (e.g., unmodified subset) is discarded. The dirty subset can be identified by the engine 246-b based on the dirty information transferred to the memory array 254 or the registers 258 during the eviction process (e.g., from the volatile memory 204).

[0070] In another example, the interface controller 202 can receive a retrieve command from the host device. The retrieve command can be received on the C / A bus 226 and transferred to the command circuitry 230 via one or more of the C / A bus interface 210 and the decoder 228. The retrieve command can include address bits for a memory address of the non-volatile memory 206. Before attempting to access the target memory address of the non-volatile memory 206, the interface controller 202 can check to see if the volatile memory 204 stores data. To do so, the command circuitry 230 can reference the memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of the n sets of volatile memory cells associated with the memory address store the requested data. If the requested data is stored in the volatile memory 204, the interface controller 202 can transfer the requested data to the buffer 218 for transmission to the host device on the data bus 260.

[0071] If the requested data is not stored in volatile memory 204, interface controller 202 can retrieve the data from non-volatile memory 206 and transfer the data to buffer 218 for transmission to the host device on data bus 260. Additionally, interface controller 202 can transfer the requested data from buffer 218 to volatile memory 204 so that the data can be accessed with less latency during subsequent retrieval operations. However, before transferring the requested data, interface controller 202 can first determine whether one or more of the n associated sets of volatile memory cells are available for storing the requested data. Interface controller 202 can determine the availability of the n associated sets of volatile memory cells by communicating with the associated set of cache management circuitry. If the associated set of volatile memory cells is available, interface controller 202 can transfer the data in buffer 218 to volatile memory 204 without performing an eviction process. Otherwise, interface controller 202 can transfer the data from buffer 218 to volatile memory 204 after performing an eviction process.

[0072] Memory sub-system 200 can be implemented in one or more configurations, including single-chip versions and multi-chip versions. Multi-chip versions can include one or more components of memory sub-system 200 on a chip separate from a chip that includes one or more other components of memory sub-system 200, including interface controller 202, volatile memory 204, and non-volatile memory 206 (as well as other components or combinations of components). For example, in one multi-chip version, respective separate chips can include each of interface controller 202, volatile memory 204, and non-volatile memory 206. In contrast, single-chip versions can include interface controller 202, volatile memory 204, and non-volatile memory 206 on a single chip.

[0073] In some examples, interface controller 202 can determine whether a criterion associated with accessing non-volatile memory 206 is satisfied and can disable a switch component to decouple non-volatile memory 206 from a power rail (e.g., a conductive path that provides a power supply voltage to non-volatile memory 206) based on determining that the criterion is satisfied, as described herein, for example, with reference to Figure 3 More detailed descriptions are described.

[0074] Figure 3 An example of a memory sub-system 300 that supports power control to non-volatile memory in accordance with examples disclosed herein is shown. Memory sub-system 300 can be a memory sub-system 200, respectively, as described with reference to Figure 1or 2 described memory sub-system 110 or memory sub-system 200, and can be included in or referred to as a memory device. Memory sub-system 300 can include interface controller 305, volatile memory 310, and non-volatile memory 315, which can be as described with reference to Figure 1 described interface controller 115, volatile memory 120, and non-volatile memory 125.

[0075] Memory sub-system 300 can include one or more power rails 320, such as power rail 320-a, 320-b, 320-c. In some examples, each power rail 320 can be coupled with one or more of interface controller 305, volatile memory 310, and non-volatile memory 315 to provide a power supply voltage to one or more of interface controller 305, volatile memory 310, and non-volatile memory 315. In some examples, each power rail 320 can provide a different power supply voltage to one or more of these components.

[0076] For example, power rail 320-a can provide a VDDQ voltage, power rail 320-b can provide a VDD1 voltage, and power rail 320-c can provide a VDD2H voltage. Such voltages can be the same or different, and can provide power to various elements within interface controller 305, volatile memory 310, and non-volatile memory 315. For example, the VDDQ voltage can provide power to a physical layer of components of memory sub-system 300, such as to I / O blocks of one or more of interface controller 305, volatile memory 310, and non-volatile memory 315. VDD1 can be used to provide power to analog components, such as for memory core operations, as a high power supply voltage for a phase-locked loop (PLL) of memory sub-system 300, or for other purposes. For example, VDD2H can provide a main power supply voltage for memory data path operations.

[0077] Other memory sub-systems can provide different numbers of power rails, which can provide the same or different power supply voltages, without departing from the scope of the application.

[0078] Each power rail 320 can be coupled with a voltage supply component (e.g., voltage regulator, power supply) that drives the respective power supply voltage onto the power rail 320. For example, memory sub-system 300 can receive power supply voltages via one or more pins of memory sub-system 300, such as can be coupled with electrical contacts (e.g., balls) of a package containing memory sub-system 300.

[0079] The memory sub-system 300 can include a switch component 325 for selectively coupling (e.g., electrically connecting) and decoupling (e.g., electrically isolating) the non-volatile memory 315 with one or more power rails 320. In some examples, the switch component 325 can include separate switch components 325-a, 325-b, 325-c for corresponding power rails 320-a, 320-b, 320-c, such that each power rail 320 can be selectively coupled or decoupled with the non-volatile memory 315 by enabling or disabling the corresponding switch component 325. In some examples, the switch component 325 or one or more separate switch components 325-a, 325-b, or 325-c can be on the same die as one or more other components (e.g., the non-volatile memory 315). In some examples, the switch component 325 or one or more separate switch components 325-a, 325-b, or 325-c can be within the same package as the interface controller 305, the volatile memory 310, and the non-volatile memory 315.

[0080] In some examples, the interface controller 305 can couple or decouple the non-volatile memory 315 with one or more power rails 320 by enabling or disabling (respectively) one or more switch components 325 (e.g., by transmitting a control signal to one or more switch components 325).

[0081] In some examples, the switch component 325 can represent or can include one or more physical switch components, such as one or more transistors or other types of switching circuitry. In some examples, one or more of the switch components 325-a, 325-b, 325-c can represent or can include a physical switch. For example, using a physical switch component instead of a software-implemented switching function can reduce leakage current when the switch component 325 is disabled, and can enable the switch component 325 to be enabled (e.g., by the interface controller 305) when the non-volatile memory 315 is powered off.

[0082] The interface controller 305 can be configured to determine whether criteria associated with accessing the non-volatile memory 315 are satisfied, and in response to determining that the criteria are satisfied, disable one or more switch components 325 (e.g., one or more of the switch components 325-a, 325-b, 325-c) to decouple the non-volatile memory 315 from one or more power rails 320. In response to determining that the criteria are not satisfied, the interface controller 305 can enable one or more switch components 325 to couple the non-volatile memory 315 with one or more power rails 320 (e.g., if the switch component 325 is currently disabled), or the interface controller 305 can refrain from disabling one or more switch components 325 (e.g., if the switch component 325 is already enabled).

[0083] Various examples of criteria that interface controller 305 can use to determine whether to power down non-volatile memory 315 are described below (e.g., by determining whether one or more criteria are satisfied). These examples are not intended to be exhaustive, but rather to illustrate the broader principles and elements described herein.

[0084] For example, interface controller 305 can determine whether memory sub-system 300 is operating in a particular (first) mode, such as an intermediate result scratchpad mode. In some examples, the intermediate result scratchpad mode can be a mode in which memory sub-system 300 can access volatile memory 310 but not non-volatile memory 315, or a mode in which interface controller 305 can transfer information from volatile memory 310 to non-volatile memory 315 in the background. Memory sub-system 300 can operate in the intermediate result scratchpad mode in order to provide lower latency access for certain latency sensitive applications, such as streaming audio. In some examples, a criterion can be satisfied when interface controller 305 determines that memory sub-system 300 is operating in the first mode. In response to determining that the criterion is satisfied (e.g., in response to determining that memory sub-system 300 is operating in the first mode), interface controller 305 can deactivate one or more switch components 325 to decouple non-volatile memory 315 from one or more power supply rails 320, thereby powering down non-volatile memory 315 to conserve power.

[0085] In some examples, prior to deactivating non-volatile memory 315, interface controller 305 can transfer data stored in non-volatile memory 315 to volatile memory 310 in order for this data to be available in volatile memory 310 after non-volatile memory 315 is powered down. For example, such a transfer can incur some overhead associated with powering down non-volatile memory 315. Accordingly, in some examples, interface controller 305 can determine whether to power down non-volatile memory 315 based on an expected duration (e.g., a period of time) for which memory sub-system 300 is expected to operate in the first mode, in order to avoid incurring the overhead associated with powering down non-volatile memory 315 in cases where memory sub-system 300 is expected to operate in the first mode for a relatively short duration.

[0086] For example, if interface controller 305 determines that memory sub-system 300 is to operate in the first mode (e.g., the intermediate result scratchpad mode) for a relatively long duration, interface controller 305 can determine that a criterion is satisfied, and can power down non-volatile memory 315 (by deactivating one or more switch components 325).

[0087] In contrast, if the interface controller 305 determines that the memory sub-system 300 is to operate in the first mode for a relatively short duration, the interface controller 305 can determine that the criterion is not satisfied and can refrain from powering down the non-volatile memory 315 (e.g., by refraining from deactivating the one or more switching components 325). Thus, in some examples, the interface controller 305 can determine whether the criterion is satisfied by determining, prior to or after determining that the memory sub-system 300 is to operate in the first mode, an estimated duration for which the memory sub-system 300 is to operate in the first mode. In some examples, the criterion is satisfied when the estimated duration satisfies a threshold (e.g., a minimum duration). In some examples, in response to determining that the estimated duration satisfies the threshold, the interface controller 305 can deactivate the one or more switching components 325 to decouple the non-volatile memory 315 from the one or more power supply rails 320, thereby powering down the non-volatile memory 315.

[0088] In some examples, the interface controller 305 can determine whether the criterion is satisfied based on determining whether information to be retrieved by the interface controller 305 resides in the volatile memory 310 such that the interface controller 305 can not access the non-volatile memory 315. For example, if the non-volatile memory 315 is powered down (e.g., the one or more switching components 325 are deactivated such that the non-volatile memory 315 is decoupled from the one or more power supply rails 320) and the memory sub-system 300 receives a request for data (e.g., from a host device), the interface controller 305 can determine whether the requested data resides in (e.g., is located in, is available in) the volatile memory 310. In response to determining that the requested data does not reside in the volatile memory 310, the interface controller 305 can activate the one or more switching components 325 to couple the non-volatile memory 315 to the one or more power supply rails 320 to power up the non-volatile memory 315, and can then read the data from the non-volatile memory 315 and transmit the data to the host device.

[0089] In contrast, in response to determining that the requested data resides in the volatile memory 310, the interface controller 305 can refrain from activating the one or more switching components 325 to couple the non-volatile memory 315 to the one or more power supply rails 320 such that the non-volatile memory 315 remains powered down. The interface controller 305 can instead read the requested data from the volatile memory 310 and transmit the data to the host device.

[0090] In some examples, memory sub-system 300 can be included in a device that can enter a power saving mode of operation, such as a sleep mode, from time to time, in which power (e.g., voltage, current) supplied to some components of the device can be reduced. For example, some cellular devices can periodically enter a sleep mode to conserve power, and can periodically exit the sleep mode (e.g., wake up) to check for incoming messages or to transmit a signal (e.g., a status signal) to another device before returning to the sleep mode. In some examples, memory sub-system 300 within such a cellular device can enter a sleep mode during such periods in which portions or all of the circuitry of memory sub-system 300 are disabled or powered down.

[0091] In some examples, memory sub-system 300 can receive an indication associated with causing memory sub-system 300 to enter a power saving mode of operation. For example, memory sub-system 300 can receive a command from a host device to cause memory sub-system 300 to enter a power saving mode, or memory sub-system 300 can periodically enter a power saving mode based on an output of a timer (e.g., in cases in which the memory sub-system periodically enters and exits a power saving mode of operation based on predetermined active and inactive time durations).

[0092] In some examples, memory sub-system 300 can transfer data from non-volatile memory 315 to volatile memory 310 in response to receiving an indication associated with causing memory sub-system 300 to enter a power saving mode of operation (e.g., in preparation for entering a power saving mode of operation). In some examples, memory sub-system 300 can enter a power saving mode after transferring data from non-volatile memory 315 to volatile memory 310.

[0093] Such data can include, for example, data that memory sub-system 300 can use when memory sub-system 300 exits a power saving mode of operation (e.g., when memory sub-system 300 periodically “wakes up” to check for incoming messages or to transmit a status signal to another device). By transferring such data to volatile memory 310 prior to entering a power saving mode of operation, memory sub-system 300 is able to power down non-volatile memory 315 during some periods in which memory sub-system 300 is awake. That is, in some examples, memory sub-system 300 can refrain from enabling one or more switching components 325 (e.g., to couple non-volatile memory 315 with one or more power supply rails 320) when memory sub-system is awake based on determining that such data has already been transferred from non-volatile memory 315 to volatile memory 310.

[0094] In some examples, the memory sub-system 300 can disable one or more switching components 325 to decouple the non-volatile memory 315 from one or more power rails 320 in response to receiving a command from the host device. That is, the memory sub-system 300 can determine whether a command has been received from the host device and can disable one or more switching components 325 based on receiving the command.

[0095] Figure 4 A block diagram 400 of a memory device 405 that supports power control of non-volatile memory in accordance with examples disclosed herein is shown. The memory device 405 can be an example of a memory sub-system as described with reference to Figures 1 to 3 FIG. 1, or can include aspects of the memory sub-system described. The memory device 405 can include a criteria determination component 410, a switch control component 415, a command component 420, a data locator component 425, a data retrieval component 430, a data transfer component 435, a data delivery component 440, and a power control component 445. Each of these modules can communicate, directly or indirectly, with one another (e.g., via one or more buses).

[0096] The criteria determination component 410 can determine, by a control component of the memory device, whether a criteria associated with accessing non-volatile memory of the memory device is satisfied.

[0097] In some examples, the criteria determination component 410 can determine whether the memory device is operating in a first mode, where the criteria is satisfied when the memory device is operating in the first mode, the first mode including an intermediate results scratchpad mode.

[0098] In some examples, prior to or after determining whether the memory device is operating in the first mode, a projected duration of time that the memory device will operate in the first mode is determined, where determining whether the criteria associated with accessing the non-volatile memory is satisfied includes determining whether the projected duration of time satisfies a threshold, and the criteria is satisfied when the projected duration of time satisfies the threshold.

[0099] In some cases, the first power rail includes a VDD power rail associated with supplying a VDD voltage to the non-volatile memory, the control component, and the volatile memory.

[0100] The switch control component 415 can disable a switching component to decouple the non-volatile memory from the first power rail based on determining that the criteria is satisfied, where the first power rail is coupled with a volatile memory of the memory device and with the control component.

[0101] In some examples, the switch control component 415 can cause the switching component to be enabled to couple the non-volatile memory with the first power rail based on determining that the data does not reside in the volatile memory.

[0102] In some examples, the switch control component 415 can enable the switch component to couple the non-volatile memory with the first power rail prior to determining whether the criterion is satisfied.

[0103] In some examples, the switch control component 415 can refrain from disabling the switch component based on determining that the criterion is not satisfied.

[0104] In some examples, the switch control component 415 can enable the switch component to couple the non-volatile memory with the first power rail based on determining that the criterion is not satisfied. In some cases, the switch component is a physical switch component coupled between the first power component and the non-volatile memory.

[0105] The command component 420 can receive a request for data from the host device after disabling the switch component.

[0106] In some examples, the command component 420 can receive an indication associated with causing the memory device to enter a power save operational mode.

[0107] In some examples, a command associated with disabling the non-volatile memory is received from the host device prior to determining whether the criterion is satisfied, where determining whether the criterion is satisfied includes determining whether the command has been received, where the criterion is satisfied when the command has been received.

[0108] The data locator component 425 can determine whether the data resides in the volatile memory.

[0109] The data retrieval component 430 can read the data from the non-volatile memory based on enabling the switch component.

[0110] The data transfer component 435 can transfer the data to the host device.

[0111] The data transfer component 440 can transfer second data from the non-volatile memory to the volatile memory based on receiving the indication, where determining whether the criterion is satisfied includes determining whether the second data has been transferred from the non-volatile memory to the volatile memory.

[0112] The power control component 445 can enter a power save operational mode based on receiving the indication and transferring the second data from the non-volatile memory to the volatile memory.

[0113] Figure 5 The illustrated flow diagram illustrates one or more methods 500 that support power control of non-volatile memory in accordance with aspects of the present disclosure. The operations of method 500 can be implemented by a memory device or its components as described herein. For example, the operations of method 500 can be implemented by the memory device 100 as described with reference to Figure 4The described memory device performs. In some examples, the memory device can execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device can use special-purpose hardware to perform aspects of the described functions.

[0114] At 505, the memory device can determine, by a control component of the memory device, whether a criterion associated with accessing a non-volatile memory of the memory device is satisfied. The operations of 505 can be performed according to the methods described herein. In some examples, the operations of 505 can be performed by a reference Figure 4 The described criterion-determining component performs aspects of the operations of 505.

[0115] At 510, the memory device can disable, based on determining that the criterion is satisfied, a switching component to decouple the non-volatile memory from a first power rail, where the first power rail is coupled with a volatile memory of the memory device and with the control component. The operations of 510 can be performed according to the methods described herein. In some examples, the operations of 510 can be performed by a reference Figure 4 The described switching control component performs aspects of the operations of 510.

[0116] In some examples, an apparatus as described herein can perform one or more methods, such as method 500. The apparatus can include features, means, or instructions for determining, by a control component of the memory device, whether a criterion associated with accessing a non-volatile memory of the memory device is satisfied, and disabling, based on determining that the criterion is satisfied, a switching component to decouple the non-volatile memory from a first power rail, where the first power rail is coupled with a volatile memory of the memory device and with the control component.

[0117] In some examples of method 500 and apparatuses described herein, determining whether the criterion associated with accessing the non-volatile memory is satisfied can include operations, features, means, or instructions for determining whether the memory device is operable in a first mode, where the criterion can be satisfied when the memory device is operable in the first mode, the first mode including an intermediate result register mode.

[0118] Some examples of method 500 and apparatuses described herein can further include operations, features, means, or instructions for determining, before or after determining whether the memory device is operable in the first mode, an estimated duration of time for which the memory device will operate in the first mode, where determining whether the criterion associated with accessing the non-volatile memory is satisfied includes determining whether the estimated duration of time satisfies a threshold, and the criterion can be satisfied when the estimated duration of time satisfies the threshold.

[0119] Some examples of the method 500 and the apparatus described herein can further include operations, features, means, or instructions for receiving a request for data from the host device after the switch component is disabled, determining whether the data resides in the volatile memory, causing, by the control component, the switch component to be enabled to couple the non-volatile memory with the first power rail based on determining that the data does not reside in the volatile memory, reading the data from the non-volatile memory based on enabling the switch component, and transmitting the data to the host device.

[0120] Some examples of the method 500 and the apparatus described herein can further include operations, features, means, or instructions for receiving an indication associated with causing the memory device to enter a power save operational mode, transferring second data from the non-volatile memory to the volatile memory based on receiving the indication, where determining whether the criteria can be satisfied includes determining whether the second data has been transferred from the non-volatile memory to the volatile memory, and entering the power save operational mode based on receiving the indication and transferring the second data from the non-volatile memory to the volatile memory.

[0121] In some examples of the method 500 and the apparatus described herein, the first power rail includes a VDD power rail associated with supplying a VDD voltage to the non-volatile memory, the control component, and the volatile memory.

[0122] In some examples of the method 500 and the apparatus described herein, the switch component can be a physical switch component coupled between the first power component and the non-volatile memory.

[0123] Some examples of the method 500 and the apparatus described herein can further include operations, features, means, or instructions for receiving a command associated with disabling the non-volatile memory from the host device prior to determining whether the criteria can be satisfied, where determining whether the criteria can be satisfied includes determining whether the command can have been received, where the criteria can be satisfied when the command can have been received.

[0124] Some examples of the method 500 and the apparatus described herein can further include operations, features, means, or instructions for enabling the switch component to couple the non-volatile memory with the first power rail prior to determining whether the criteria can be satisfied.

[0125] Some examples of the method 500 and the apparatus described herein can further include operations, features, means, or instructions for avoiding disabling the switch component based on determining that the criteria can not be satisfied.

[0126] Some examples of the method 500 and the apparatus described herein can further include operations, features, means, or instructions for enabling the switch component to couple the non-volatile memory with the first power rail based on determining that the criteria can not be satisfied.

[0127] It should be noted that the methods described herein are possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0128] An apparatus is described. The apparatus can include a non-volatile memory; a volatile memory; a control component coupled with the non-volatile memory and the volatile memory; a first power rail coupled with the volatile memory and the control component and configured to supply a first voltage to the volatile memory and the control component; and a switch component coupled with the first power rail and with the non-volatile memory, where the control component is configured to cause the apparatus to determine whether a criterion associated with accessing the non-volatile memory is satisfied and to disable the switch component to decouple the non-volatile memory from the first power rail based on a determination that the criterion is satisfied.

[0129] Some examples of the apparatus can include a second power rail coupled with the volatile memory and the control component and configured to supply a second voltage to the volatile memory and the control component; and a second switch component coupled with the second power rail and with the non-volatile memory, and where the control component can be configured to cause the apparatus to disable the second switch component to decouple the non-volatile memory from the second power rail based on a determination that the criterion can be satisfied.

[0130] Some examples can further include enabling the switch component to couple the non-volatile memory with the first power rail based on a determination that the criterion can not be satisfied.

[0131] In some examples, the switch component can be on the same die as the non-volatile memory. In some examples, the switch component can be within the same package as the control component, the volatile memory, and the non-volatile memory.

[0132] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it will be understood by a person of ordinary skill in the art that the signals can be represented by buses, where buses can have any number of bits.

[0133] The terms "in electronic communication," "in conductive contact," "connected," and "coupled" can refer to a relationship between components in which electrons are supported to flow between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. The conductive path between components that are in electronic communication with each other (or in conductive contact or connected or coupled to each other) can be open or closed at any given time, based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intervening components such as switches, transistors, or other components. In some examples, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intervening components such as switches or transistors.

[0134] The term "coupled" refers to the condition of moving from an open relationship between components in which signals cannot currently be conveyed between the components through a conductive path, to a closed relationship between the components in which signals can be conveyed between the components through a conductive path. When a component such as a controller couples other components together, the component initiates a change that allows signals to flow between the other components via a conductive path through which signals were not previously permitted to flow.

[0135] The term "isolated" refers to a relationship between components in which signals cannot currently flow between the components. Components are isolated from each other if there is an open circuit between the components. Components that are isolated from each other by a switch that is positioned between the two components are isolated from each other when the switch is open. When a controller isolates two components from each other, the controller implements a change that prevents signals from flowing between the components using a conductive path through which signals were previously permitted to flow.

[0136] A protocol can define one or more communication protocols and one or more communication parameters that are supported by a device or component. For example, a protocol can define various operations, timing and frequencies for those operations, devices or both for various commands or signals, one or more addressing schemes for one or more memories, types of communications in which pins are reserved, sizes of data handled at various components such as interfaces, data rates supported by various components such as interfaces, or bandwidths supported by various components such as interfaces, among other parameters and measures, or any combination thereof. The use of a shared protocol can enable interaction between devices because each device can operate in a manner that is expected, recognized, and understood by another device. For example, two devices that support the same protocol can interact according to the policies, procedures, and parameters defined by the protocol, whereas two devices that support different protocols can be incompatible.

[0137] For illustration, two devices supporting different protocols can be incompatible because the protocols define different addressing schemes (e.g., different number of address bits). As another illustration, two devices supporting different protocols can be incompatible because the protocols define different transfer procedures for responding to a single command (e.g., the burst length or number of bytes permitted in response to a command can be different). Merely converting a command to an action should not be understood as use of two different protocols. Indeed, protocols can be considered different if the corresponding procedures or parameters defined by the two protocols change. For example, a device can be said to support two different protocols if it supports different addressing schemes or different transfer procedures for responding to a command.

[0138] The devices discussed herein, including the memory array, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or sub-regions of the substrate, can be controlled by doping using various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0139] The switch components or transistors discussed herein can represent field effect transistors (FETs) and include three-terminal devices that include a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive material, such as metal. The source and drain can be conductive and can include heavily doped, e.g., degenerate, semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become conductive. A transistor can be“turned on” or“enabled” when a voltage greater than or equal to the threshold voltage of the transistor is applied to the gate of the transistor. A transistor can be“turned off” or“disabled” when a voltage less than the threshold voltage of the transistor is applied to the gate of the transistor.

[0140] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that can be implemented or that are within the scope of the claims. The term “exemplary” used herein means “serving as an example, instance, or illustration,” and not “preferred” or “superior.” The detailed description includes specific details to provide an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0141] In the appended figures, similar components or features can have the same reference label. Further, various components of the same type can be distinguished by following the convention, in which the first digit or digits of the reference label identifies the component type. Where component types are identical among the figures, only the last two digits or characters of the reference label can be employed. Specific descriptions of shown examples can not pertain to or describe every implementation, but can pertain only to or describe one possible implementation.

[0142] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0143] The various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0144] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein, including in the claims, "or" as used in a list of items (for example, a list of items prefaced by a phrase such as "at least one of" or "one or more of") indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" shall not be construed as a referral to a closed set of conditions. For example, an exemplary step that is described as "based on condition A" can be based on both conditions A and B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" shall be construed in the same manner as the phrase "based at least in part on."

[0145] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0146] The description herein is presented to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Volatile memory; Non-volatile memory; as well as An interface controller, coupled to the volatile memory and the non-volatile memory, is configured such that the device: Determine whether the criteria associated with accessing the non-volatile memory are met; The switching assembly is deactivated to disconnect the non-volatile memory from the first power rail, which is coupled to the volatile memory and the interface controller, at least in part based on the determination that the criteria are met. as well as The switching assembly is enabled to couple the non-volatile memory to the first power rail, based at least in part on the determination that the data requested by the host device does not exist in the volatile memory.

2. The device of claim 1, wherein the interface controller is configured such that the device determines whether the criteria associated with accessing the non-volatile memory are met by: Determine whether the device is operating in a first mode, wherein the criteria are met when the device is operating in the first mode, the first mode including an intermediate result register mode.

3. The device of claim 1, wherein the first power rail includes a VDD power rail associated with supplying VDD voltage to the non-volatile memory, the interface controller, and the volatile memory.

4. The device of claim 1, wherein the switching component is a physical switching component coupled between the first power supply component and the non-volatile memory.

5. The device of claim 1, wherein the interface controller is configured such that the device: Before determining whether the criterion is met, a command associated with disabling the non-volatile memory is received from the host device, wherein the interface controller is configured to determine whether the criterion is met by determining whether the command has been received, wherein the criterion is met when the command has been received.

6. The device of claim 1, wherein the interface controller is configured such that the device: Before determining whether the criteria are met, the switching assembly is enabled to couple the non-volatile memory to the first power rail.

7. The device of claim 6, wherein the interface controller is configured such that the device: The switching assembly is avoided, at least in part, based on the determination that the criteria are not met.

8. The device of claim 1, wherein the interface controller is configured such that the device: The switching assembly is enabled to couple the non-volatile memory to the first power rail, at least in part, based on the determination that the criteria are not met.

9. An apparatus comprising: Volatile memory; Non-volatile memory; as well as An interface controller coupled to the volatile memory and the non-volatile memory, wherein the interface controller is configured such that the device: Whether the criteria associated with accessing the nonvolatile memory are met is determined by determining whether the device operates in a first mode, wherein the criteria are met when the device operates in the first mode, the first mode including an intermediate result register mode; The switching assembly is deactivated to disconnect the non-volatile memory from the first power rail, which is coupled to the volatile memory and the interface controller, at least in part based on the determination that the criteria are met. as well as Before or after determining whether the device is operating in the first mode, an estimated duration for which the device will operate in the first mode is determined, wherein the interface controller is configured such that the device determines whether the criteria associated with accessing the non-volatile memory are met by determining whether the estimated duration meets a threshold, and wherein the criteria are met when the estimated duration meets the threshold.

10. An apparatus comprising: Volatile memory; Non-volatile memory; as well as An interface controller coupled to the volatile memory and the non-volatile memory, wherein the interface controller is configured such that the device: Determine whether the criteria associated with accessing the non-volatile memory are met; The switching assembly is deactivated to disconnect the non-volatile memory from the first power rail, which is coupled to the volatile memory and the interface controller, at least in part based on the determination that the criteria are met. After the switch assembly is deactivated, a request for data is received from the host device; Determine whether the data resides in the volatile memory; The switching assembly is enabled to couple the non-volatile memory to the first power rail, at least in part based on the determination that the data does not reside in the volatile memory. The data is read from the non-volatile memory, at least in part, based on enabling the switching component; as well as The data is transmitted to the host device.

11. An apparatus comprising: Volatile memory; Non-volatile memory; as well as An interface controller coupled to the volatile memory and the non-volatile memory, wherein the interface controller is configured such that the device: Receive an instruction associated with putting the device into a power-saving operation mode; Based at least in part on receiving the instruction, the second data is transferred from the non-volatile memory to the volatile memory; Determine whether a criterion associated with accessing the non-volatile memory is met, wherein the interface controller is configured such that the device determines whether the criterion is met by determining whether the second data has been transferred from the non-volatile memory to the volatile memory. The switching assembly is deactivated to disconnect the non-volatile memory from the first power rail, which is coupled to the volatile memory and the interface controller, at least in part based on the determination that the criteria are met. as well as The power-saving operation mode is entered at least in part based on receiving the instruction and transferring the second data from the non-volatile memory to the volatile memory.

12. An apparatus comprising: Non-volatile memory, Volatile memory, An interface controller, coupled to both the non-volatile memory and the volatile memory, A first power rail, coupled to the volatile memory and the interface controller and configured to supply a first voltage to the volatile memory and the interface controller, and A switching assembly, coupled to the interface controller, the first power rail, and the non-volatile memory, and configured to selectively couple the first power rail to the non-volatile memory, at least in part, based on signals received from the interface controller, wherein the interface controller is configured such that the device: The switching assembly is deactivated to isolate the non-volatile memory from the first power rail; as well as The switching assembly is enabled to couple the non-volatile memory to the first power rail, at least in part based on the fact that the data requested by the host device does not exist in the volatile memory.

13. The device according to claim 12, further comprising: A second power rail, coupled to the interface controller and the volatile memory and configured to supply a second voltage to the volatile memory and the interface controller; as well as A second switching assembly, coupled to the interface controller, the second power rail, and the non-volatile memory, is configured to selectively couple the second power rail to the non-volatile memory, at least in part, based on a second signal received from the interface controller.

14. The device of claim 12, wherein the interface controller is configured such that the device: The switching assembly is activated to couple the non-volatile memory to the first power rail, at least in part based on the determination that the criteria are not met.

15. The device of claim 12, wherein the switching assembly and the non-volatile memory are located on the same die.

16. The device of claim 12, wherein the switching assembly is located in the same package as the interface controller, the volatile memory, and the non-volatile memory.

17. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: Determine whether the criteria associated with accessing the non-volatile memory of the electronic device are met; The switching assembly is deactivated to disconnect the non-volatile memory from the first power rail, which is coupled to the volatile memory of the electronic device and to the interface controller of the electronic device, at least in part based on the determination that the criteria are met. as well as The switching assembly is enabled to couple the non-volatile memory to the first power rail, based at least in part on the determination that the data requested by the host device does not exist in the volatile memory.

18. The non-transitory computer-readable medium of claim 17, wherein determining whether the criterion associated with accessing the non-volatile memory is met includes determining whether the electronic device operates in a first mode, wherein the criterion is met when the electronic device operates in the first mode, the first mode including an intermediate result register mode.

19. The non-transitory computer-readable medium of claim 18, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Before or after determining whether the electronic device is operating in the first mode, determine the expected duration for which the electronic device will operate in the first mode. Determining whether the criteria associated with accessing the non-volatile memory are met includes determining whether the expected duration meets a threshold, and wherein the criteria are met when the expected duration meets the threshold.

20. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: After the switch assembly is deactivated, a request for data is received from the host device; Determine whether the data resides in the volatile memory; The data is read from the non-volatile memory, at least in part, based on enabling the switching component; as well as The data is transmitted to the host device.

21. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Receive an instruction associated with putting the electronic device into a power-saving operation mode; Based at least in part on receiving the instruction, the second data is transferred from the non-volatile memory to the volatile memory, wherein determining whether the criterion is met includes determining whether the second data has been transferred from the non-volatile memory to the volatile memory; as well as The power-saving operation mode is entered at least in part based on receiving the instruction and transferring the second data from the non-volatile memory to the volatile memory.

22. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Before determining whether the criterion is met, a command associated with disabling the non-volatile memory is received from the host device, wherein determining whether the criterion is met includes determining whether the command has been received, wherein the criterion is met when the command has been received.

23. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Before determining whether the criteria are met, the switching assembly is enabled to couple the non-volatile memory to the first power rail.

24. The non-transitory computer-readable medium of claim 23, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The switching assembly is avoided, at least in part, based on the determination that the criteria are not met.

25. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The switching assembly is enabled to couple the non-volatile memory to the first power rail, at least in part, based on the determination that the criteria are not met.

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