An 8T SRAM circuit structure for implementing iterative exclusive-OR calculation in memory

Abstract

The present invention discloses an 8T SRAM circuit structure for implementing iterative exclusive-OR calculation in memory. The circuit sets memory cells in an n-row and n-column arrangement with 8T SRAM cells as the basic unit. Each 8T SRAM cell includes two cross-coupled inverters, a pair of data transfer transistors, and a pair of control transistors. The data transfer transistors are arranged on the left and right sides of the cross-coupled inverters, with one on each side. The control transistors are arranged between the cross-coupled inverters, one on the upper side and one on the lower side. One end of the upper control transistor is connected to the output terminal of the left inverter, and the other end is connected to the right storage node in the inverter. One end of the lower control transistor is connected to the output terminal of the right inverter, and the other end is connected to the left storage node in the inverter. This circuit can not only implement exclusive-OR calculation of multiple rows of data but also implement exclusive-OR calculation of multiple columns of data, breaking the spatial limitation on calculation, and thus having a wider range of application scenarios.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and particularly to an 8T SRAM (8-Transistor Static Random Access Memory) circuit structure for implementing iterative exclusive-OR calculation in memory. Background Art

[0002] With the rapid development of artificial intelligence, some application fields such as machine learning and edge computing have developed rapidly, and there is a higher requirement for computing speed. However, in the traditional von Neumann architecture, the processor computing unit and the memory are separated. When the processor performs operations, it reads data from the memory, and then writes the data back to the memory after the processor finishes processing the data. Due to the rapid development of Moore's Law, the memory operation speed is out of sync with the processor speed, and the memory access speed lags far behind the processor computing speed. Memory performance has become an important bottleneck in the overall computer performance, and this bottleneck is particularly obvious in fields with large amounts of computing such as machine learning and image recognition.

[0003] To overcome the drawbacks brought by these traditional von Neumann architectures, computing in memory (abbreviated as CIM) has become a hot topic to solve this problem. Computing in memory does not need to transfer data to the processor and directly performs operations in the memory. Therefore, it greatly reduces the energy consumption of data access during the computing process, and at the same time improves the computing speed and energy efficiency. Among them, the calculation of iterative exclusive-OR has important applications in the Advanced Encryption Standard (abbreviated as AES), but there is a lack of a circuit structure for iterative exclusive-OR calculation in memory in the prior art. Summary of the Invention

[0004] The purpose of the present invention is to provide an 8T SRAM circuit structure for implementing iterative exclusive-OR calculation in memory. This circuit can not only implement the exclusive-OR calculation of multiple rows of data, but also implement the exclusive-OR calculation of multiple columns of data, breaking the spatial limitation on calculation, so the application scenario is more extensive.

[0005] The purpose of the present invention is achieved by the following technical solutions:

[0006] An 8T SRAM circuit structure for implementing iterative exclusive-OR calculation in memory, the circuit sets memory cells of n rows and n columns with 8T SRAM cells as basic units. Each 8T SRAM cell includes two cross-coupled inverters, a pair of data transfer tubes, and a pair of control transistors, wherein:

[0007] A pair of data transmission tubes are arranged on the left and right sides of the cross-coupled inverters, one on each side, where:

[0008] One end of the left data transmission tube is connected to the gate in the left inverter, and the other end is connected to the row bit line R_BL;

[0009] One end of the right data transmission tube is connected to the gate in the right inverter, and the other end is connected to the column bit line C_BL;

[0010] A pair of control transistors are arranged between the cross-coupled inverters, one on the upper side and one on the lower side, where:

[0011] One end of the upper control transistor is connected to the source / drain of the left inverter, and the other end is connected to the gate in the right inverter;

[0012] One end of the lower control transistor is connected to the source / drain of the right inverter, and the other end is connected to the gate in the left inverter;

[0013] In the memory cells of n rows and n columns, the data transmission tubes on the left side of the 8T SRAM cells in the same row are all connected to the same row word line R_WL, and the upper control transistors are all connected to the same control line Control_L, and the lower control transistors are all connected to the same control line Control_R;

[0014] The data transmission tubes on the right side of the 8T SRAM cells in the same column are all connected to the same column word line C_WL, and the upper control transistors are all connected to the same control line Control_L, and the lower control transistors are all connected to the same control line Control_R.

[0015] It can be seen from the technical solutions provided by the present invention described above that the above circuit can not only perform exclusive OR calculations on multiple rows of data, but also perform exclusive OR calculations on multiple columns of data. Therefore, the application scenarios are more extensive; moreover, the circuit structure is simple, which can effectively improve the operation efficiency and speed, and reduce the energy consumed during the transmission process. Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 It is a schematic structural diagram of each 8T SRAM cell in the 8T SRAM circuit for implementing iterative exclusive OR calculation in the memory provided by the embodiment of the present invention;

[0018] Figure 2 Schematic diagram of an iterative XOR computing structure implemented by an n-bit SRAM cell in a row in the circuit according to an embodiment of the present invention;

[0019] Figure 3 Schematic diagram of an iterative XOR computing structure implemented by an n-bit SRAM cell in a column in the circuit according to an embodiment of the present invention;

[0020] Figure 4 Waveform diagram of an iterative XOR computing implemented by the first 8T SRAM cell in a row in the circuit according to an embodiment of the present invention;

[0021] Figure 5 Waveform diagram of an iterative XOR computing implemented by the first 8T SRAM cell in a column in the circuit according to an embodiment of the present invention. Detailed implementation manners

[0022] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments, which do not constitute a limitation to the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0023] The circuit in the embodiment of the present invention sets memory cells of n rows and n columns with 8T SRAM cells as basic units. As Figure 1 shown in the schematic diagram of the structure of each 8T SRAM cell in the 8T SRAM circuit, each 8T SRAM cell includes two cross-coupled inverters, a pair of data transfer tubes, and a pair of control transistors, where:

[0024] A pair of data transfer tubes are arranged on the left and right sides of the cross-coupled inverters, with one on each side, where:

[0025] One end of the left data transfer tube is connected to the gate in the left inverter, and the other end is connected to the row bit line R_BL;

[0026] One end of the right data transfer tube is connected to the gate in the right inverter, and the other end is connected to the column bit line C_BL;

[0027] A pair of control transistors are arranged between the cross-coupled inverters, one on the top and one on the bottom, where:

[0028] One end of the upper control transistor is connected to the source / drain of the left inverter, and the other end is connected to the gate in the right inverter;

[0029] One end of the lower control transistor is connected to the source / drain of the right inverter, and the other end is connected to the gate in the left inverter;

[0030] In the memory cells of n rows and n columns, the data transfer tubes on the left side of the 8T SRAM cells in the same row are all connected to the same row word line R_WL, and the upper control transistors are all connected to the same control line Control_L, and the lower control transistors are all connected to the same control line Control_R;

[0031] The data transfer tubes on the right side of the 8T SRAM cells in the same column are all connected to the same column word line C_WL, and the upper control transistors are all connected to the same control line Control_L, and the lower control transistors are all connected to the same control line Control_R.

[0032] As Figure 1 shown, the two cross-coupled inverters include two PMOS transistors and two NMOS transistors. The two PMOS transistors are denoted as M1 and M3, and the two NMOS transistors are denoted as M2 and M4; a pair of data transfer tubes are two NMOS transistors, denoted as M7 and M8; a pair of control transistors are two NMOS transistors, denoted as M5 and M6; where:

[0033] The gate of PMOS transistor M1 is electrically connected to the gates of NMOS transistors M2, the source of NMOS transistor M7, and the drain of NMOS transistor M6; the source of PMOS transistor M1 is electrically connected to the sources of NMOS transistors M5 and the drain of NMOS transistor M2;

[0034] The gate of PMOS transistor M3 is electrically connected to the gates of NMOS transistors M4, the source of NMOS transistor M8, and the drain of NMOS transistor M5; the source of PMOS transistor M2 is electrically connected to the sources of NMOS transistors M6 and the drain of NMOS transistor M4;

[0035] The row input signal R_IN1 is electrically connected to the source of PMOS transistor M1, and the row input signal R_IN2 is electrically connected to the source of NMOS transistor M2;

[0036] The column input signal C_IN1 is electrically connected to the source of PMOS transistor M3, and the column input signal C_IN2 is electrically connected to the source of NMOS transistor M4;

[0037] The row word line signal R_WL is electrically connected to the gate of NMOS transistor M7, and the column word line signal C_WL is electrically connected to the gate of NMOS transistor M8;

[0038] The row bit line signal R_BL is electrically connected to the drain of NMOS transistor M7, and the column bit line signal C_BL is electrically connected to the drain of NMOS transistor M8.

[0039] Based on the above circuit structure, as Figure 2The figure shows a schematic diagram of an iterative XOR calculation structure implemented by an n-bit SRAM cell in a row of the circuit according to an embodiment of the present invention. When the circuit is in the row read operation stage:

[0040] The control signals Control_L and Control_R are at high level, the row input signal R_IN1 and the column input signal C_IN1 are at high level, the row input signal R_IN2 and the column input signal C_IN2 are at low level, the row word line R_WL is at high level, and the row bit line is pre-charged to high level;

[0041] If the voltage of the left storage node Q is "0" and the voltage of the right storage node QB is "1", the row bit line R_BL discharges through the NMOS transistor M4 to complete the read "0" operation;

[0042] If the voltage of the left storage node Q is "1" and the voltage of the right storage node QB is "0", the row bit line R_BL remains at high level unchanged to complete the read "1" operation;

[0043] The sense amplifier in the circuit realizes the reading of the stored data in each SRAM cell by detecting the level change of the row bit line R_BL to complete the row read operation.

[0044] As Figure 2 shown, when the circuit is in the row write operation stage, a single-ended write method is adopted, specifically:

[0045] The control signal Control_R is at low level, Control_L is at high level, the row input signal R_IN1 and the column input signal C_IN1 are at high level, and the row input signal R_IN2 and the column input signal C_IN2 are at low level;

[0046] If writing data "1", the row bit line R_BL is set to high level, the row word line R_WL is enabled, the voltage of the left storage node Q becomes "1", and then Control_R is set to high level, and two cross-coupled inverter structures appear. The left storage node Q forces the right storage node QB to be cleared to complete the write "1" operation;

[0047] If writing data "0", the row bit line R_BL is set to low level, the row word line R_WL is enabled, the voltage of the left storage node Q becomes "0", and then Control_R is set to high level, and two cross-coupled inverter structures appear. The left storage node Q forces the right storage node QB to be set to "1" to complete the write "0" operation.

[0048] As Figure 2 shown, when the circuit is in the row XOR operation stage:

[0049] The control signal Control_R is at a low level, the column input signal C_IN1 is at a high level, and the column input signal C_IN2 is at a low level;

[0050] If the voltage of the left storage node Q is "1" and the voltage of the right storage node QB is "0", when the voltage of the row input signal R_IN1 is "1" and the voltage of the row input signal R_IN2 is "0", then first set the control signal Control_L to a low level, then set the control signal Control_R to a high level, and then set the control signal Control_L to a high level, thereby realizing the exclusive OR operation of the right storage node QB being "1" and the row input signal R_IN1 being "1", and the result is "1";

[0051] When the voltage of the row input signal R_IN1 is "0" and the voltage of the row input signal R_IN2 is "1", then first set the control signal Control_L to a low level, then set the control signal Control_R to a high level, and then set the control signal Control_L to a high level, thereby realizing the exclusive OR operation of the left storage node Q being "1" and the row input signal R_IN1 being "0", and the result is "0".

[0052] As Figure 3 shown is a schematic structural diagram of realizing iterative exclusive OR calculation by a column of n-bit SRAM cells in the circuit according to an embodiment of the present invention. When the circuit is in the column read operation stage:

[0053] The control signals Control_L and Control_R are at a high level, the row input signal R_IN1 and the column input signal C_IN1 are at a high level, the row input signal R_IN2 and the column input signal C_IN2 are at a low level, the row word line C_WL is at a high level, and the column bit line is precharged to a high level;

[0054] If the voltage of the left storage node Q is "1" and the voltage of the right storage node QB is "0", then the column bit line C_BL discharges through the NMOS transistor M2 to complete the read "1" operation;

[0055] If the voltage of the left storage node Q is "0" and the voltage of the right storage node QB is "1", then the column bit line C_BL remains at a high level unchanged to complete the read "0" operation;

[0056] The sense amplifier in the circuit realizes the reading of the stored data in each column of SRAM cells by detecting the level change of the column bit line C_BL to complete the column read operation.

[0057] As Figure 3 shown, the circuit adopts a single-ended write method in the column write operation stage, specifically:

[0058] The control signal Control_L is at a low level, Control_R is at a high level, the row input signal R_IN1 and the column input signal C_IN1 are at high levels, and the row input signal R_IN2 and the column input signal C_IN2 are at low levels;

[0059] If writing the data "0", the column bit line C_BL is set to a high level, the row word line C_WL is enabled, the voltage of the right storage node QB becomes "1", then Control_L is set to a high level, and two cross-coupled inverter structures appear, completing the write "0" operation;

[0060] If writing the data "1", the column bit line C_BL is set to a low level, the column word line C_WL is enabled, the voltage of the right storage node QB becomes "0", then Control_L is set to a high level, and two cross-coupled inverter structures appear, completing the write "1" operation.

[0061] As Figure 3 shown, when the circuit is in the column exclusive-OR operation stage:

[0062] The control signal Control_L is at a low level, the row input signal R_IN1 is at a high level, and the row input signal R_IN2 is at a low level;

[0063] If the voltage of the left storage node Q is "0" and the voltage of the right storage node QB is "1", when the voltage of the column input signal C_IN1 is "1" and the voltage of the column input signal C_IN2 is "0", first set the control signal Control_R to a low level, then set the control signal Control_L to a high level, and then set the control signal Control_R to a high level, thereby realizing the exclusive-OR operation of the left storage node Q being "0" and the column input signal C_IN1 being "1", and the result is "0";

[0064] When the voltage of the column input signal C_IN1 is "0" and the voltage of the column input signal C_IN2 is "1", first set the control signal Control_R to a low level, then set the control signal Control_L to a high level, and then set the control signal Control_R to a high level, thereby realizing the exclusive-OR operation of the left storage node Q being "0" and the column input signal C_IN1 being "0", and the result is "1".

[0065] To more clearly show the technical solution provided by the present invention and the technical effects produced, take the first 8T SRAM cell in a row and the first 8T SRAM cell in a column for simulation verification of row exclusive-OR and column exclusive-OR calculations:

[0066] As Figure 4The waveform diagram of the first 8T SRAM cell in a row of the circuit according to the embodiment of the present invention for implementing iterative exclusive-OR calculation is shown. For completing the iterative exclusive-OR calculation of the input data and the storage nodes, the initial state is: the storage nodes Q and QB are "0" and "1" respectively, C_IN1 is at a high level, C_IN2 is at a low level, and the control signals Control_L and Control_R are both at a high level.

[0067] Calculation stage of the first cycle: First, the control signal Control_R changes to a low level. Then, the input data R_IN1 is at a low level, R_IN2 is at a high level, and the storage node QB discharges through M1 to below the threshold voltage. After 0.5 unit time, the control signal Control_L is turned off. After another 0.5 unit time, the control signal Control_R is turned on. The output terminal of the right inverter charges the storage node Q through M6. After 0.5 unit time, the control signal Control_L is turned on, making the structure an interconnected inverter, and the value of the storage node QB drops from the threshold voltage to a low level. The final result of the exclusive-OR of the input "1" and the storage node Q being "0" is "1", and it is stored in the storage node Q.

[0068] Calculation stage of the second cycle: R_IN1 is at a high level, R_IN2 is at a high level. The process is the same as that of the first cycle, and the final result remains unchanged, implementing the iterative exclusive-OR calculation in the row dimension.

[0069] As Figure 5 The waveform diagram of the first 8T SRAM cell in a column of the circuit according to the embodiment of the present invention for implementing iterative exclusive-OR calculation is shown. For completing the iterative exclusive-OR calculation of the input data and the storage nodes, the initial state is: the storage nodes Q and QB are "0" and "1" respectively, R_IN1 is at a high level, R_IN2 is at a low level, and the control signals Control_L and Control_R are both at a high level.

[0070] Calculation stage of the first cycle: First, the control signal Control_L changes to a low level. Then, the input data C_IN1 is at a low level, C_IN2 is at a high level, and the storage node Q charges through M4 to above the threshold voltage. After 0.5 unit time, the control signal Control_R is turned off. After another 0.5 unit time, the control signal Control_L is turned on. The storage node QB discharges through M2 to a low level. After 0.5 unit time, the control signal Control_R is turned on, making the structure an interconnected inverter, and the value of the storage node Q rises from the threshold voltage to a high level. The final result of the exclusive-OR of the input "1" and the storage node Q being "0" is "1", and it is stored in the storage node Q.

[0071] Calculation stage of the second cycle: C_IN1 is at high level and C_IN2 is at high level. The process is the same as the calculation process of the first cycle, and the final result remains unchanged, realizing iterative exclusive-OR calculation in the column dimension.

[0072] It should be noted that the content not described in detail in the embodiments of the present invention belongs to the prior art well-known to those skilled in the art.

[0073] In summary, the circuit structure provided by the embodiments of the present invention is simple. Using the 8T SRAM cell as the basic unit, it can calculate the single exclusive-OR result in the row dimension or the single exclusive-OR result in the column dimension within one cycle, and can calculate the N exclusive-OR results in the row dimension or the N exclusive-OR results in the column dimension in N cycles; compared with the traditional von Neumann architecture that stores in memory and calculates in the processor, this circuit can reduce the consumption of power during data transmission and improve the operation speed and efficiency at the same time; compared with the traditional 6T SRAM structure, this circuit can not only perform multi-row reading or writing, but also perform multi-column reading or writing. Therefore, this circuit structure can realize two-way iterative exclusive-OR calculation.

[0074] The above are only the preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. The information disclosed in the background art section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or any form of suggestion that this information constitutes the prior art already known to those skilled in the art.

Claims

1. An 8T SRAM circuit structure for implementing iterative exclusive-OR calculation in memory, characterized in that, The 8TSRAM circuit structure sets up memory cells in an n - row and n - column arrangement with 8T SRAM cells as the basic unit. Each 8T SRAM cell includes two cross - coupled inverters, a pair of data transfer transistors, and a pair of control transistors, where: A pair of data transfer transistors are arranged on the left and right sides of the cross - coupled inverters, with one on each side, where: One end of the left - hand data transfer transistor is connected to the gate of the left - hand inverter, and the other end is connected to the row bit - line R_BL; One end of the right - hand data transfer transistor is connected to the gate of the right - hand inverter, and the other end is connected to the column bit - line C_BL; A pair of control transistors are arranged between the cross - coupled inverters, one on the top and one on the bottom, where: One end of the upper control transistor is connected to the source / drain of the left - hand inverter, and the other end is connected to the gate of the right - hand inverter; One end of the lower control transistor is connected to the source / drain of the right - hand inverter, and the other end is connected to the gate of the left - hand inverter; In the n - row and n - column memory cells, the left - hand data transfer transistors of the 8T SRAM cells in the same row are all connected to the same row word - line R_WL, and the upper control transistors are all connected to the same control line Control_L, and the lower control transistors are all connected to the same control line Control_R; The right - hand data transfer transistors of the 8T SRAM cells in the same column are all connected to the same column word - line C_WL, and the upper control transistors are all connected to the same control line Control_L, and the lower control transistors are all connected to the same control line Control_R.

2. The 8T SRAM circuit structure for implementing iterative exclusive-OR calculation in memory according to claim 1, wherein The two cross - coupled inverters include two PMOS transistors and two NMOS transistors. The two PMOS transistors are denoted as M1 and M3, and the two NMOS transistors are denoted as M2 and M4; The pair of data transfer transistors are two NMOS transistors, denoted as M7 and M8; The pair of control transistors are two NMOS transistors, denoted as M5 and M6; Among them, the gate of PMOS transistor M1 is electrically connected to the gate of NMOS transistor M2, the source of NMOS transistor M7, and the drain of NMOS transistor M6; the source of PMOS transistor M1 is electrically connected to the source of NMOS transistor M5 and the drain of NMOS transistor M2; The gate of PMOS transistor M3 is electrically connected to the gate of NMOS transistor M4, the source of NMOS transistor M8, and the drain of NMOS transistor M5; the source of PMOS transistor M2 is electrically connected to the source of NMOS transistor M6 and the drain of NMOS transistor M4; The row input signal R_IN1 is electrically connected to the source of PMOS transistor M1, and the row input signal R_IN2 is electrically connected to the source of NMOS transistor M2; The column input signal C_IN1 is electrically connected to the source of PMOS transistor M3, and the column input signal C_IN2 is electrically connected to the source of NMOS transistor M4; The row word - line signal R_WL is electrically connected to the gate of NMOS transistor M7, and the column word - line signal C_WL is electrically connected to the gate of NMOS transistor M8; The row bit - line signal R_BL is electrically connected to the drain of NMOS transistor M7, and the column bit - line signal C_BL is electrically connected to the drain of NMOS transistor M8.

3. The 8T SRAM circuit structure for implementing iterative exclusive - OR calculation in memory according to claim 1, characterized in that, Based on the above circuit structure, during the row read operation stage of the 8T SRAM circuit structure: The control signals Control_L and Control_R are at high level, the row input signal R_IN1 and the column input signal C_IN1 are at high level, the row input signal R_IN2 and the column input signal C_IN2 are at low level, the row word line R_WL is at high level, and the row bit line is pre-charged to high level; If the voltage of the left storage node Q is "0" and the voltage of the right storage node QB is "1", the row bit line R_BL discharges through the NMOS transistor M4 to complete the read "0" operation; If the voltage of the left storage node Q is "1" and the voltage of the right storage node QB is "0", the row bit line R_BL remains at high level unchanged to complete the read "1" operation; The sense amplifier in the 8T SRAM circuit structure realizes the reading of the stored data in each SRAM cell by detecting the level change of the row bit line R_BL to complete the row read operation.

4. The 8T SRAM circuit structure for implementing iterative exclusive-OR calculation in memory according to claim 1, wherein Based on the circuit structure, the 8T SRAM circuit structure adopts a single-ended write method during the row write operation stage, specifically: The control signal Control_R is at low level, Control_L is at high level, the row input signal R_IN1 and the column input signal C_IN1 are at high level, and the row input signal R_IN2 and the column input signal C_IN2 are at low level; If writing data "1", the row bit line R_BL is set to high level, the row word line R_WL is enabled, the voltage of the left storage node Q becomes "1", and then Control_R is set to high level. Two cross-coupled inverter structures appear, and the left storage node Q forces the right storage node QB to be cleared to complete the write "1" operation; If writing data "0", the row bit line R_BL is set to low level, the row word line R_WL is enabled, the voltage of the left storage node Q becomes "0", and then Control_R is set to high level. Two cross-coupled inverter structures appear, and the left storage node Q forces the right storage node QB to be set to "1" to complete the write "0" operation.

5. The 8T SRAM circuit structure for implementing iterative exclusive - OR calculation in memory according to claim 1, characterized in that, Based on the circuit structure, during the row exclusive-OR operation stage of the 8T SRAM circuit structure: The control signal Control_R is at low level, the column input signal C_IN1 is at high level, and the column input signal C_IN2 is at low level; If the voltage of the left storage node Q is "1" and the voltage of the right storage node QB is "0", when the voltage of the row input signal R_IN1 is "1" and the voltage of the row input signal R_IN2 is "0", first the control signal Control_L is set to low level, then the control signal Control_R is set to high level, and then the control signal Control_L is set to high level, thus realizing the exclusive-OR operation of the right storage node QB being "1" and the row input signal R_IN1 being "1", and the result is "1"; When the voltage of the row input signal R_IN1 is "0", the voltage of the row input signal R_IN2 is "1", then first set the control signal Control_L to low level, then set the control signal Control_R to high level, and then set the control signal Control_L to high level, thus realizing the exclusive OR operation of the left storage node Q being "1" and the row input signal R_IN1 being "0", and the result is "0".

6. The 8T SRAM circuit structure for implementing iterative exclusive - OR calculation in memory according to claim 1, wherein Based on the above circuit structure, during the column read operation stage of the 8T SRAM circuit structure: The control signals Control_L and Control_R are at high level, the row input signal R_IN1 and the column input signal C_IN1 are at high level, the row input signal R_IN2 and the column input signal C_IN2 are at low level, the row word line C_WL is at high level, and the column bit line is pre-charged to high level; If the voltage of the left storage node Q is "1" and the voltage of the right storage node QB is "0", then the column bit line C_BL discharges through the NMOS transistor M2 to complete the read "1" operation; If the voltage of the left storage node Q is "0" and the voltage of the right storage node QB is "1", then the column bit line C_BL remains at high level unchanged to complete the read "0" operation; The sense amplifier in the 8T SRAM circuit structure realizes the reading of the stored data in each column of SRAM cells by detecting the level change of the column bit line C_BL to complete the column read operation.

7. The 8T SRAM circuit structure for implementing iterative exclusive-OR calculation in memory according to claim 1, characterized in that Based on the above circuit structure, the 8T SRAM circuit structure adopts a single-ended write method during the column write operation stage, specifically: The control signal Control_L is at low level, Control_R is at high level, the row input signal R_IN1 and the column input signal C_IN1 are at high level, and the row input signal R_IN2 and the column input signal C_IN2 are at low level; If writing data "0", set the column bit line C_BL to high level, turn on the row word line C_WL, the voltage of the right storage node QB becomes "1", and then set Control_L to high level, and two cross-coupled inverter structures appear to complete the write "0" operation; If writing data "1", set the column bit line C_BL to low level, turn on the column word line C_WL, the voltage of the right storage node QB becomes "0", and then set Control_L to high level, and two cross-coupled inverter structures appear to complete the write "1" operation.

8. The 8T SRAM circuit structure for implementing iterative exclusive-OR calculation in memory according to claim 1, characterized in that Based on the above circuit structure, during the column exclusive OR operation stage of the 8T SRAM circuit structure: The control signal Control_L is at low level, the row input signal R_IN1 is at high level, and the row input signal R_IN2 is at low level; If the voltage of the left storage node Q is "0" and the voltage of the right storage node QB is "1", when the voltage of the column input signal C_IN1 is "1" and the voltage of the column input signal C_IN2 is "0", first set the control signal Control_R to a low level, then set the control signal Control_L to a high level, and then set the control signal Control_R to a high level, thereby realizing the exclusive OR operation of the left storage node Q being "0" and the column input signal C_IN1 being "1", and the result is "0". When the voltage of the column input signal C_IN1 is "0" and the voltage of the column input signal C_IN2 is "1", first set the control signal Control_R to a low level, then set the control signal Control_L to a high level, and then set the control signal Control_R to a high level, thereby realizing the exclusive OR operation of the left storage node Q being "0" and the column input signal C_IN1 being "0", and the result is "1".

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