Memory devices

Abstract

The present application discloses a memory device, which includes a first pad, a second pad, and a double data rate (DDR) test controller. The first pad can receive a write enable signal. The second pad can receive a data strobe signal. The DDR test controller is connected to the first pad and the second pad and outputs an internal write enable signal and an internal data strobe signal. In at least a portion of a DDR test operation of the memory device, the DDR test controller generates an internal data strobe signal based on the write enable signal received via the first pad.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly, to memory devices. Background Art

[0002] The memory device can be formed in a two-dimensional structure in which strings are arranged horizontally on a semiconductor substrate, or in a three-dimensional structure in which strings are vertically stacked on a semiconductor substrate. A three-dimensional memory device is a memory device designed to address the integration limitations of a two-dimensional memory device and can include multiple memory cells stacked vertically on a semiconductor substrate.

[0003] The memory device can be tested by the test device in a wafer step. During the test operation of the memory device, as the number of pads of the memory device connected to the test device is reduced, the manufacturing cost of the test device can be reduced. Summary of the Invention

[0004] A memory device according to an embodiment of the present disclosure may include a first pad, a second pad, and a double data rate (DDR) test controller. The first pad may receive a write enable signal. The second pad may receive a data strobe signal. The DDR test controller may be connected to the first pad and the second pad and may output an internal write enable signal and an internal data strobe signal. The DDR test controller generates an internal data strobe signal based on the write enable signal received by the first pad in at least a portion of a DDR test operation of the memory device.

[0005] A memory device according to another embodiment of the present disclosure may include a memory cell array, a peripheral circuit, control logic, and a double data rate (DDR) test controller. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a programming operation, an erase operation, or a read operation on the memory cell array. The control logic may control the operation of the peripheral circuit. The DDR test controller may generate an internal write enable signal and an internal data select signal for transmission to the control logic based on signals received from a first pad and a second pad. During normal operation of the memory device, the DDR test controller generates an internal write enable signal based on a first signal received through the first pad and may generate an internal data select signal based on a second signal received through the second pad. The DDR test controller may generate an internal data select signal based on the first signal received through the first pad in at least a portion of a DDR test operation of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram illustrating a memory device.

[0007] Figure 2 This is an example Figure 1 FIG. 1 is a diagram of an embodiment of a memory cell array.

[0008] Figure 3 This is an example Figure 2 A circuit diagram of any one memory block BLKa among the memory blocks BLK1 to BLKz.

[0009] Figure 4 This is an example Figure 2 FIG. 1 is a circuit diagram of another embodiment of any one memory block BLKb among the memory blocks BLK1 to BLKz.

[0010] Figure 5 This is an example Figure 1 1 is a circuit diagram of an embodiment of any one memory block BLKc among the memory blocks BLK1 to BLKz included in the memory cell array 110.

[0011] Figure 6 A diagram describing the pin configuration of a memory device.

[0012] Figure 7 is a diagram for describing a single data rate (SDR) test of a memory device.

[0013] Figure 8 is a timing diagram used to describe SDR testing of a memory device.

[0014] Figure 9 is a diagram for describing a double data rate (DDR) test of a memory device.

[0015] Figure 10 is a timing diagram used to describe DDR testing of memory devices.

[0016] Figure 11 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0017] Figure 12 is used to describe Figure 11 The timing diagram of the DDR test of the memory device is shown.

[0018] Figure 13 This is an example Figure 11 A block diagram of an example of an implementation of a DDR test controller is shown in FIG.

[0019] Figure 14 is an example used to generate Figure 13 Figure 2 shows a diagram of the flip-flop for the DDR write enable signal.

[0020] Figure 15 is used to describe Figure 11 The timing diagram of the DDR test of the memory device is shown.

[0021] Figure 16 It is used to describe Figure 1 FIG. 1 is a diagram of an embodiment of a system of memory devices shown.

[0022] Figure 17 It is used to describe Figure 1 A diagram of another embodiment of a system of memory devices is shown.

[0023] Figure 18 It is used to describe Figure 1 A diagram of another embodiment of a system of memory devices is shown.

[0024] Figure 19 It is used to describe Figure 1 A diagram of another embodiment of a system of memory devices is shown. DETAILED DESCRIPTION

[0025] The specific structural descriptions or functional descriptions of the embodiments disclosed in this specification or application are merely illustrative for describing the embodiments of the concepts of the present disclosure. The embodiments of the concepts of the present disclosure can be implemented in various forms, and the description is not limited to the embodiments described in this specification or application.

[0026] Embodiments of the present disclosure provide a memory device capable of reducing testing costs.

[0027] In an embodiment, during normal operation of the memory device, the DDR test controller may output a write enable signal received through the first pad as an internal write enable signal and output a data strobe signal received through the second pad as an internal data strobe signal.

[0028] In an embodiment, during a DDR test operation, the DDR test controller may output a write enable signal received through the first pad as an internal write enable signal in a period in which a command or an address is input.

[0029] In an embodiment, during a DDR test operation, the DDR test controller may output a write enable signal received through the first pad as an internal data strobe signal in a period of inputting data.

[0030] In an embodiment, the DDR test controller may include: a multiplexer connected to the first pad and the second pad through an input terminal and configured to output an internal data selection signal according to the control of a DDR write enable signal; an inverter configured to invert the signal input to the first pad; and a NAND (NAND) gate configured to perform a NAND (NAND) operation on the output of the inverter and the inverted DDR write enable signal to generate an internal write enable signal.

[0031] In an embodiment, the DDR test controller may further include a trigger, the DDR test enable signal may be input to a data input terminal of the trigger, the data input control signal may be input to a clock input terminal of the trigger, the column count end signal may be input to a reset input terminal of the trigger, and the DDR write enable signal may be output to an output terminal of the trigger.

[0032] In an embodiment, when the memory device receives a command for a DDR test operation, the DDR test enable signal may be activated to a high state in response to the reception of the command.

[0033] In an embodiment, when the memory device completes reception of the address signal, the data input control signal may be activated to a high state in response to completion of reception of the address signal.

[0034] In an embodiment, when the memory device completes receiving the data, the column count end signal may be activated to a high state in response to the completion of receiving the data.

[0035] In an embodiment, when the data input control signal transitions high, the DDR write enable signal output to the output terminal of the flip-flop may follow the DDR test enable signal.

[0036] In an embodiment, the memory device may further include a data path logic circuit configured to receive the internal write enable signal and the internal data strobe signal and transmit the internal write enable signal and the internal data strobe signal to the control logic.

[0037] In an embodiment, during a DDR test operation, the DDR test controller may generate an internal write enable signal based on a first signal received through the first pad in a period in which a command or an address is input.

[0038] In an embodiment, during a DDR test operation, the DDR test controller may generate an internal data strobe signal based on a first signal received through the first pad in a period of inputting data.

[0039] In an embodiment, the DDR test controller may include: a multiplexer connected to the first pad and the second pad through an input terminal and configured to output an internal data selection signal under the control of a third signal; an inverter configured to invert the signal input to the first pad; and a NAND gate configured to perform a NAND operation on the output of the inverter and the inverted third signal to generate an internal write enable signal.

[0040] In an embodiment, the DDR test controller may further include a trigger, the fourth signal may be input to a data input terminal of the trigger, the fifth signal may be input to a clock input terminal of the trigger, the sixth signal may be input to a reset input terminal of the trigger, and the third signal may be output to an output terminal of the trigger.

[0041] In an embodiment, when the memory device receives a command for a DDR test operation, the fourth signal may be changed to an active state in response to the reception of the command.

[0042] In an embodiment, when the memory device completes reception of the address signal, the fifth signal may change to an active state in response to completion of reception of the address signal.

[0043] In an embodiment, when the memory device completes reception of data, the sixth signal may change to an active state in response to completion of reception of the data.

[0044] In an embodiment, the third signal output to the output terminal of the flip-flop may follow an edge of the fourth signal.

[0045] The present technology can provide a memory device capable of reducing testing costs.

[0046] It will be understood by those skilled in the art that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help improve understanding of the embodiments of the present teachings. In addition, the description and drawings do not necessarily require the order in which they are presented. It will be further appreciated that some actions and / or steps may be described or depicted in a particular order of occurrence, and those skilled in the art will understand that such specificity regarding the order is not actually required.

[0047] As used herein, signals having a low level are distinguished from signals having a high level. For example, a high level may correspond to a signal having a first voltage, while a low level may correspond to a signal having a second voltage. For some embodiments, the first voltage is greater than the second voltage. In other embodiments, different characteristics of the signal (such as frequency or amplitude) determine whether the signal has a high level or a low level. In some cases, the high and low levels of a signal represent logical binary states.

[0048] For reference, embodiments including additional components may be provided. Furthermore, depending on the embodiment, the active-high or active-low configurations indicating the activation state of a signal or circuit may be varied. Furthermore, the configuration of one or more logic gates required to implement the same function or operation may be modified. That is, depending on the specific circumstances, a logic gate configuration for one type of operation may be substituted for another logic gate configuration for the same type of operation. A variety of logic gates may be employed to implement the configuration, if desired.

[0049] It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components and / or signals, these elements, components and / or signals should not be limited by these terms. These terms are only used to distinguish one element, component or signal from another element, component or signal. Therefore, without departing from the teachings of the present disclosure, the first element, component or signal discussed below may be referred to as the second element, component or signal.

[0050] Figure 1 is a block diagram illustrating a memory device.

[0051] Reference Figure 1 , the memory device 100 includes a memory cell array 110, an address decoder 120, a read / write circuit 130, a control logic 140, and a voltage generator 150. The control logic 140 can be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 140 can be a control logic circuit that operates according to an algorithm and / or a processor that executes control logic code.

[0052] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 120 via word lines WL. The plurality of memory blocks BLK1 to BLKz are connected to the read / write circuit 130 via bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. As an embodiment, the plurality of memory cells are non-volatile memory cells and may be composed of non-volatile memory cells having a vertical channel structure. The memory cell array 110 may be configured as a memory cell array with a two-dimensional structure. According to an embodiment, the memory cell array 110 may be configured as a memory cell array with a three-dimensional structure. In addition, each of the plurality of memory cells included in the memory cell array may store at least one bit of data. In an embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a single-level cell (SLC) storing one bit of data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a multi-level cell (MLC) storing two bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a triple-level cell (TLC) storing three bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a quad-level cell (QLC) storing four bits of data. Depending on the embodiment, the memory cell array 110 may include a plurality of memory cells each storing five or more bits of data.

[0053] The address decoder 120, the read / write circuit 130, the control logic 140, and the voltage generator 150 operate as peripheral circuits for driving the memory cell array 110. The address decoder 120 is connected to the memory cell array 110 through word lines WL. The address decoder 120 is configured to operate in response to the control of the control logic 140. The address decoder 120 receives an address through an input / output buffer (not shown) inside the memory device 100.

[0054] The address decoder 120 is configured to decode a block address from among the received addresses. The address decoder 120 selects at least one memory block based on the decoded block address. Furthermore, during a read operation, the address decoder 120 applies a read voltage Vread generated by the voltage generator 150 to the selected word line of the selected memory block at the time of a read voltage application operation, and applies a pass voltage Vpass to the remaining unselected word lines. Furthermore, during a program verification operation, the address decoder 120 applies a verification voltage generated by the voltage generator 150 to the selected word line of the selected memory block, and applies a pass voltage Vpass to the remaining unselected word lines.

[0055] The address decoder 120 is configured to decode the column address in the received address and send the decoded column address to the read / write circuit 130 .

[0056] Memory device 100 performs read and program operations in page units. The address received when requesting a read or program operation includes a block address, a row address, and a column address. Address decoder 120 selects a memory block and a word line based on the block and row addresses. The column address is decoded by address decoder 120 and provided to read / write circuit 130.

[0057] The address decoder 120 may include a block decoder, a row decoder, a column decoder, an address buffer, and the like.

[0058] The read / write circuit 130 includes a plurality of page buffers PB1 to PBm. The read / write circuit 130 can operate as a "read circuit" during a read operation of the memory cell array 110, and can operate as a "write circuit" during a write operation of the memory cell array 110. The plurality of page buffers PB1 are connected to the memory cell array 110 through bit lines BL1 to BLm. During a read operation and a program verification operation, in order to sense the threshold voltage of a memory cell, the plurality of page buffers PB1 to PBm sense changes in the amount of current flowing according to the programming state of the corresponding memory cell through a sense node while continuously supplying a sense current to the bit line connected to the memory cell, and latch the sensed change as sense data. The read / write circuit 130 operates in response to a page buffer control signal output from the control logic 140.

[0059] During a read operation, the read / write circuit 130 senses data of a memory cell, temporarily stores the read data, and outputs the data DATA to an input / output buffer (not shown) of the memory device 100. As an example of an embodiment, the read / write circuit 130 may further include a column selection circuit, etc., in addition to a page buffer (or page register).

[0060] The control logic 140 is connected to the address decoder 120, the read / write circuit 130, and the voltage generator 150. The control logic 140 receives a command CMD and a control signal CTRL via an input / output buffer (not shown) of the memory device 100. The control logic 140 is configured to control the overall operation of the memory device 100 in response to the control signal CTRL. In addition, the control logic 140 outputs a control signal for adjusting the precharge potential level of the sense nodes of the plurality of page buffers PB1 to PBm. The control logic 140 can control the read / write circuit 130 to perform a read operation on the memory cell array 110.

[0061] The voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during a read operation in response to a control signal output from the control logic 140. To generate a plurality of voltages having various voltage levels, the voltage generator 150 may include a plurality of pumping capacitors that receive an internal power supply voltage and generate the plurality of voltages by selectively activating the plurality of pumping capacitors in response to control of the control logic 140.

[0062] The address decoder 120, the read / write circuit 130, and the voltage generator 150 may serve as a "peripheral circuit" for performing read operations, write operations, and erase operations on the memory cell array 110. The peripheral circuit performs read operations, write operations, and erase operations on the memory cell array 110 based on the control of the control logic 140.

[0063] Figure 2 This is an example Figure 1 FIG. 1 is a diagram of an embodiment of a memory cell array.

[0064] Reference Figure 2 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. Such a plurality of memory cells are arranged along the +X direction, the +Y direction, and the +Z direction. Figure 4 and Figure 5 Describes the structure of each storage block.

[0065] Figure 3 This is an example Figure 2 A circuit diagram of any one memory block BLKa among the memory blocks BLK1 to BLKz.

[0066] Reference Figure 3 , the memory block BLKa includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. As an embodiment, each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings are arranged in a row direction (ie, +X direction). Figure 4 , two cell strings are arranged in the column direction (ie, +Y direction). However, this is for convenience of description, and it can be understood that three or more cell strings may be arranged in the column direction.

[0067] Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.

[0068] Each of the select transistors SST and DST and the memory cells MC1 to MCn may have a similar structure. As an embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating film, a charge storage film, and a blocking insulating film. As an embodiment, a pillar for providing a channel layer may be provided in each cell string. As an embodiment, a pillar for providing at least one of the channel layer, the tunneling insulating film, the charge storage film, and the blocking insulating film may be provided in each cell string.

[0069] The source selection transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCp.

[0070] As an embodiment, source selection transistors of cell strings arranged in the same row are connected to a source selection line extending in the row direction, and source selection transistors of cell strings arranged in different rows are connected to different source selection lines. Figure 4 , the source selection transistors of the cell strings CS11 to CS1m of the first row are connected to the first source selection line SSL1, and the source selection transistors of the cell strings CS21 to CS2m of the second row are connected to the second source selection line SSL2.

[0071] As another embodiment, the source selection transistors of the cell strings CS11 to CS1m and CS21 to CS2m may be commonly connected to one source selection line.

[0072] The first to nth memory cells MC1 to MCn of each cell string are connected between a source select transistor SST and a drain select transistor DST.

[0073] The first to nth memory cells MC1 to MCn can be divided into first to pth memory cells MC1 and (p+1)th memory cells MCp+1 to nth memory cells MCn. The first to pth memory cells MC1 to MCp are arranged sequentially in a direction opposite to the +Z direction and are connected in series between a source select transistor SST and a tube transistor PT. The (p+1)th memory cells MCp+1 to nth memory cells MCn are arranged sequentially in the +Z direction and are connected in series between a tube transistor PT and a drain select transistor DST. The first to pth memory cells MC1 and (p+1)th memory cells MCp+1 to nth memory cells MCn are connected to each other via the tube transistor PT. The gates of the first to nth memory cells MC1 to MCn of each cell string are connected to the first to nth word lines WL1 to WLn, respectively.

[0074] The gate of the tube transistor PT of each cell string is connected to the pipe line PL.

[0075] The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MCp+1 to MCn. The cell strings arranged in the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0076] The cell strings arranged in the column direction are connected to the bit lines extending in the column direction. Figure 4 , the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1, and the cell strings CS1m and CS2m of the mth column are connected to the mth bit line BLm.

[0077] Memory cells connected to the same word line in the cell strings arranged in the row direction constitute a page. For example, the memory cells connected to the first word line WL1 in the cell strings CS11 to CS1m in the first row constitute one page. The memory cells connected to the first word line WL1 in the cell strings CS21 to CS2m in the second row constitute another page. The cell strings arranged in a row can be selected by selecting any one of the drain select lines DSL1 and DSL2. A page in the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0078] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to m-th bit lines BL1 to BLm. In addition, even cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be connected to even bit lines, respectively, and odd cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be connected to odd bit lines, respectively.

[0079] As an embodiment, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. As more dummy memory cells are provided, the operational reliability of the memory block BLKa improves, however, the size of the memory block BLKa increases. As fewer memory cells are provided, the size of the memory block BLKa can be reduced, however, the operational reliability of the memory block BLKa decreases.

[0080] In order to efficiently control at least one dummy memory cell, each dummy memory cell can have a desired threshold voltage. Before or after an erase operation on the memory block BLKa, a programming operation can be performed on all or part of the dummy memory cells. When an erase operation is performed after the programming operation, the dummy memory cells can have the desired threshold voltage by controlling the voltage applied to the dummy word lines connected to the respective dummy memory cells.

[0081] Figure 4 This is an example Figure 2 FIG. 1 is a circuit diagram of another embodiment of any one memory block BLKb among the memory blocks BLK1 to BLKz.

[0082] Reference Figure 4 , the memory block BLKb includes a plurality of cell strings CS11′ to CS1m′ and CS21′ to CS2m′. Each of the plurality of cell strings CS11′ to CS1m′ and CS21′ to CS2m′ extends along the +Z direction. Each of the plurality of cell strings CS11′ to CS1m′ and CS21′ to CS2m′ includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST stacked on a substrate (not shown) below the memory block BLKb.

[0083] The source select transistor SST of each cell string is connected between a common source line CSL and memory cells MC1 to MCn. The source select transistors of the cell strings arranged in the same row are connected to the same source select line. The source select transistors of the cell strings CS11′ to CS1m′ arranged in the first row are connected to a first source select line SSL1. The source select transistors of the cell strings CS21′ to CS2m′ arranged in the second row are connected to a second source select line SSL2. As another embodiment, the source select transistors of the cell strings CS11′ to CS1m′ and CS21′ to CS2m′ may be connected in common to one source select line.

[0084] The first to nth memory cells MC1 to MCn of each cell string are connected in series between a source select transistor SST and a drain select transistor DST. Gates of the first to nth memory cells MC1 to MCn are connected to first to nth word lines WL1 to WLn, respectively.

[0085] The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the cell strings arranged in the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the cell strings CS11′ to CS1m′ in the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21′ to CS2m′ in the second row are connected to the second drain select line DSL2.

[0086] As a result, in addition to excluding the tube transistor PT from each cell string, Figure 4 The storage block BLKb and Figure 3 The storage block BLKa has a similar equivalent circuit.

[0087] As another embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. In addition, even cell strings among the cell strings CS11′ to CS1m′ or CS21′ to CS2m′ arranged in the row direction may be connected to even bit lines, and odd cell strings among the cell strings CS11′ to CS1m′ or CS21′ to CS2m′ arranged in the row direction may be connected to odd bit lines, respectively.

[0088] As an embodiment, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain select transistor DST and the memory cells MC1 to MCn. As more dummy memory cells are provided, the operational reliability of the memory block BLKb improves; however, the size of the memory block BLKb increases. As fewer memory cells are provided, the size of the memory block BLKb can be reduced; however, the operational reliability of the memory block BLKb decreases.

[0089] To efficiently control at least one dummy memory cell, each dummy memory cell can have a desired threshold voltage. Before or after an erase operation on memory block BLKb, a programming operation can be performed on all or some of the dummy memory cells. When an erase operation is performed after the programming operation, the dummy memory cells can have the desired threshold voltage by controlling the voltage applied to the dummy word lines connected to the respective dummy memory cells.

[0090] Figure 5 is included in the example Figure 1 1 is a circuit diagram of an embodiment of any one memory block BLKc among the memory blocks BLK1 to BLKz in the memory cell array 110.

[0091] Reference Figure 5 The memory block BKLc includes a plurality of cell strings CS1 to CSm. The plurality of cell strings CS1 to CSm can be connected to a plurality of bit lines BL1 to BLm, respectively. Each of the cell strings CS1 to CSm includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST.

[0092] Each of the select transistors SST and DST and the memory cells MC1 to MCn may have a similar structure. As an embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating film, a charge storage film, and a blocking insulating film. As an embodiment, a pillar for providing a channel layer may be provided in each cell string. As an embodiment, a pillar for providing at least one of the channel layer, the tunneling insulating film, the charge storage film, and the blocking insulating film may be provided in each cell string.

[0093] The source selection transistor SST of each cell string is connected between a common source line CSL and the memory cells MC1 to MCn.

[0094] The first to nth memory cells MC1 to MCn of each cell string are connected between a source select transistor SST and a drain select transistor DST.

[0095] The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn.

[0096] Memory cells connected to the same word line constitute one page. Cell strings CS1 to CSm can be selected by selecting a drain select line DSL. One page in the selected cell string can be selected by selecting any one of word lines WL1 to WLn.

[0097] As another embodiment, even and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. Even cell strings among the cell strings CS1 to CSm may be connected to even bit lines, and odd cell strings may be connected to odd bit lines, respectively.

[0098] like Figures 2 to 4 As shown, the memory cell array 110 of the memory device 100 may be configured as a three-dimensional memory cell array. Figure 5 As shown, the memory cell array 110 of the memory device 100 may be configured as a two-dimensional memory cell array.

[0099] Figure 6 This is a diagram used to describe the pin configuration of a memory device. Figure 6 , the memory device 100 communicates with an external memory controller through multiple lines.

[0100] The memory device 100 communicates with the memory controller through a chip enable (CE) line, a command latch enable (CLE) line, an address latch enable (ALE) line, a write enable (WE_N) line, a read enable (RE_N) line, a ready busy (RB) line, a data input / output (DQ<7:0>) line, and a data strobe (DQS) line.

[0101] The chip enable (CE) line transmits a chip enable (CE) signal, which is a signal indicating that the corresponding memory device 100 (i.e., memory chip) is operational. The chip enable (CE) signal can be selectively applied to memory chips connected to the same channel. When the chip enable (CE) signal drops to low, the chip enable (CE) signal indicates that all operations in the corresponding memory chip are feasible. When the chip enable (CE) signal is high, the chip enable (CE) signal indicates that the corresponding memory chip is in a standby state.

[0102] When an operation is being performed within the memory chip, the ready busy (RB) signal transmitted to the ready busy (RB) line is in a low state. When the ready busy (RB) signal is in a low state, the memory chip does not exchange other signals with the outside world. When the ready busy (RB) signal is high, this indicates that the memory chip is in a ready state. When the memory chip is in the ready state, the memory chip can exchange signals with the outside world.

[0103] When a command CMD is input to the memory device 100, a command latch enable (CLE) signal goes high. When an address is input to the memory device, an address latch enable (ALE) signal goes high.

[0104] When the write enable (WE_N) signal transitions from low to high, i.e., at the rising edge of the write enable (WE_N) signal, the command CMD and the address are input to the selected memory chip. In another embodiment, when the write enable (WE_N) signal transitions from high to low, i.e., at the falling edge of the write enable (WE_N) signal, the command CMD and the address ADD may be input to the selected memory chip.

[0105] When commands and addresses are loaded onto the memory chip, a write enable (WE_N) signal is toggled, and when data is loaded onto the memory controller, a read enable (RE_N) signal is toggled.

[0106] Data input / output (DQ<7:0>, i.e., DQ <0> To DQ <7> ) lines input commands, addresses, and data to memory device 100, or output data from memory device 100 to a memory controller. Since data consists of 8 bits, there are also 8 data input / output (DQ<7:0>) lines. However, the number of data input / output lines is not limited to eight and can be expanded to 16 or 32 in various embodiments.

[0107] The data strobe (DQS) signal is a signal used for synchronization when inputting / outputting data through the data input / output (DQ<7:0>) line. For example, in double data rate (DDR) mode, the data signal can be input to or output from the memory device 100 through the data input / output (DQ<7:0>) line at the rising edge and falling edge of the data strobe (DQS) signal. In an embodiment, the data strobe (DQS) signal can be input to and output from the memory device 100 through the data strobe (DQS) line.

[0108] Figure 7 is a diagram used to describe a single data rate (SDR) test of a memory device. Figure 7 , a command latch enable (CLE) signal, an address latch enable (ALE) signal, a write enable (WE_N) signal, a data strobe (DQS) signal, and a read enable (RE_N) signal can be input through pads 161, 162, 163, 164, and 165, respectively. In addition, data can be input / output through pads 166, 167, ..., and 168. Figure 7 In the figure, the pads for inputting the chip enable (CE) signal and the ready busy (RB) signal are omitted.

[0109] When performing the SDR test of the memory device 100, the probe card of the test device 500a may be connected to the pads 161 to 163 and 165 to 168 included in the memory device 100. Specifically, the data strobe (DQS) signal may not be used in the SDR test of the memory device 100. Figure 7 As shown, when performing the SDR test of the memory device 100 , the probe card of the test device 500 a may not be connected to the pad 164 .

[0110] Figure 8 This is a timing diagram used to describe the SDR test of memory devices. Figure 8 , shows signals of a data input / output (DQ<7:0>) line, a command latch enable (CLE) signal, an address latch enable (ALE) signal, and a write enable (WE_N) signal during an SDR test of the memory device 100 .

[0111] In step 1 (P1), in a state where the command latch enable (CLE) signal is activated to high, an "80h" signal may be input through the data input / output (DQ<7:0>) line. The "80h" signal is part of the programming command and may be a signal indicating the start of the programming operation. After the "80h" signal is input, the command latch enable (CLE) signal may be deactivated to low, and the address latch enable (ALE) signal may be activated to high. In a state where the address latch enable (ALE) signal is activated, address signals A0 to A4 may be input through the data input / output (DQ<7:0>) line. After the address signals A0 to A4 are input, the address latch enable (ALE) signal may be deactivated to low. In step 1 (P1), the "80h" signal and the address signals A0 to A4 as part of the programming command may be input synchronously with the write enable (WE_N) signal. Figure 7 In an example of FIG. 5 , an “80h” signal and address signals A0 to A4 as part of a program command may be input to the memory device at a rising edge of a write enable (WE_N) signal.

[0112] In step 2 (P2), data signals D0 to D1 may be input to the memory device via the data input / output (DQ<7:0>) lines. n In the case of SDR testing, similar to commands and addresses, data signals D0 to D1 may be input to the memory device at the rising edge of the write enable signal WE_N. n .

[0113] In step 3 (P3) after the data input is completed, a "10h" signal may be input through the data input / output (DQ<7:0>) line in a state where the command latch enable (CLE) signal is activated high. The "10h" signal may be a signal indicating that a data signal to be programmed is input to the memory device. Although Figure 8 Not shown, but the data input after step 3 (P3) may be programmed in the memory cells of the selected page in the memory device.

[0114] like Figure 8 As shown, in the SDR mode of the memory device, the command, address, and data signals may be input synchronously with the write enable (WE_N) signal. Therefore, in this case, the data strobe (DQS) pad of the memory device is not used.

[0115] Figure 9 is a diagram used to describe a double data rate (DDR) test of a memory device. Figure 9A command latch enable (CLE) signal, an address latch enable (ALE) signal, a write enable (WE_N) signal, a data strobe (DQS) signal, and a read enable (RE_N) signal can be input through pads 161, 162, 163, 164, and 165, respectively. In addition, data can be input and output through pads 166, 167, ..., and 168.

[0116] When performing a DDR test of the memory device 100, the probe card of the test device 500b may be connected to the pads 161 to 168 included in the memory device 100. Specifically, in the DDR test of the memory device 100, unlike the SDR test, a data strobe (DQS) signal may be used. Figure 7 As shown, when performing a DDR test on the memory device 100 , a probe card of the test device 500 b needs to be connected to the pad 164 .

[0117] Figure 10 This is a timing diagram used to describe the DDR test of memory devices. Figure 10 , shows signals of a data input / output (DQ<7:0>) line, a command latch enable (CLE) signal, an address latch enable (ALE) signal, a write enable (WE_N) signal, and a data strobe (DQS) signal during a DDR test of the memory device 100.

[0118] In step 4 (P4), in a state where the command latch enable (CLE) signal is activated to high, an "80h" signal may be input through the data input / output (DQ<7:0>) line. The "80h" signal is part of the programming command and may be a signal indicating the start of the programming operation. After the "80h" signal is input, the command latch enable (CLE) signal may be deactivated to low, and the address latch enable (ALE) signal may be activated to high. In a state where the address latch enable (ALE) signal is activated, address signals A0 to A4 may be input through the data input / output (DQ<7:0>) line. After the address signals A0 to A4 are input, the address latch enable (ALE) signal may be deactivated to low. During step 4 (P4), the data strobe (DQS) signal may remain in a high state. Figure 10 Step 4 (P4) shown can be combined with Figure 8 Step 1 (P1) shown is essentially the same.

[0119] In step 5 (P5), data signals D0 to D1 may be input to the memory device via the data input / output (DQ<7:0>) lines. m In addition to the SDR test, in the DDR test, data signals D0 to D1 may be input to the memory device at the rising and falling edges of the data strobe (DQS) signal.m Additionally, during step 5 (P5), the write enable (WE_N) signal may be maintained in a high state.

[0120] In step 6 (P6) after the data input is completed, a "10h" signal may be input through the data input / output (DQ<7:0>) line in a state where the command latch enable (CLE) signal is activated high. The "10h" signal may be a signal indicating that a data signal to be programmed is input to the memory device. Although Figure 10 Not shown, but the data input after step 6 (P6) may be programmed in the memory cells of the selected page in the memory device. Figure 10 Step 6 (P6) shown can be combined with Figure 8 Step 3 (P3) shown is essentially the same.

[0121] like Figure 10 As shown, in the DDR mode of the memory device, command and address signals can be input synchronously with the write enable (WE_N) signal. In addition, in the DDR mode of the memory device, data signals can be input synchronously with the data strobe (DQS) signal. Therefore, in this case, the data strobe (DQS) pad of the memory device needs to be used.

[0122] Reference Figure 7 and Figure 8 , the probe card of the test device 500a performing the SDR test of the memory device 100 does not need to be connected to the data strobe (DQS) pad. Therefore, the probe card of the test device 500a can omit the component for connecting to the data strobe (DQS) pad. In this case, the manufacturing cost of the test device 500a can be reduced.

[0123] However, referring to Figure 9 and Figure 10 , the probe card of the test device 500b that performs the DDR test of the memory device 100 needs to be connected to the data strobe (DQS) pad. Figure 7 Compared to the test device 500a shown, Figure 9 The probe card of the test apparatus 500b shown in FIG. 5 needs to include a component for connecting with a data strobe (DQS) pad. Therefore, the manufacturing cost of the test apparatus 500b capable of performing a DDR test increases.

[0124] A memory device according to an embodiment of the present disclosure includes a DDR test controller that generates an internal write enable (WE_N_INT) signal and an internal data strobe (DQS_INT). The DDR test controller outputs a data strobe (DQS) signal input via a pad during normal operation as the internal data strobe (DQS_INT). Furthermore, the DDR test controller outputs a write enable (WE_N) signal input via a pad during normal operation as the internal write enable signal (WE_N_INT).

[0125] Furthermore, during a DDR test operation, the DDR test controller outputs a write enable (WE_N) signal input through the pad as an internal data strobe DQS_INT during at least a portion of the test operation. Therefore, a DDR test of the memory device 100 can be performed without using a pad for inputting a data strobe (DQS) signal.

[0126] Refer again Figure 10 During the DDR test operation of the memory device 100, during period 4 (P4) when the "80h" command and address are input, and during period 6 (P6) when the "10h" command is input, the data strobe (DQS) signal remains high while the write enable (WE_N) signal switches. Furthermore, during period 5 (P5) when data is input, the write enable (WE_N) signal remains high while the data strobe (DQS) signal switches. That is, during the DDR test operation of the memory device 100, there is no period during which the data strobe (DQS) signal and the write enable (WE_N) signal switch simultaneously.

[0127] Taking advantage of this, a signal used as a write enable (WE_N) signal can be input through the pad 163 from the test device 500a in period 4 (P4) when the "80h" command and address are input, and in period 6 (P6) when the "10h" command indicating the end of programming is input. In addition, a signal used as a data strobe (DQS) signal is input through the pad 163 from the test device 500a in period 5 (P5) when data is input. The memory device 100 according to the present disclosure can use the signal input through the pad 163 during periods 4 (P4) and 6 (P6) as a write enable (WE_N) signal, and use the signal input through the pad 163 during period 5 (P5) as a data strobe (DQS) signal. Therefore, DDR testing can be performed in a state where the probe card of the test device 500a is not connected to the pad 164.

[0128] That is, you can use Figure 7The test apparatus 500a shown in FIG. 1 is used to perform a DDR test on the memory device 100. Therefore, the manufacturing cost of a test apparatus capable of performing both a DDR test and an SDR test on the memory device 100 can be reduced. Consequently, the test cost of the memory device 100 can be reduced.

[0129] Figure 11 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0130] Reference Figure 11 The memory device according to the embodiment of the present disclosure includes a DDR test controller 170 and a data path logic circuit (DP LOGIC) 180. The DDR test controller 170 may be connected to the pads 163 and 164. In addition, the DDR test controller 170 may be connected to the data path logic circuit 180.

[0131] The data path logic circuit 180 may be a core area (eg, Figure 1 The control logic 140 shown in FIG. 1 is a circuit for transmitting the received internal data strobe (DQS_INT) signal and the internal write enable (WE_N_INT) signal. Figure 11 , but the data path logic circuit 180 may be connected directly or indirectly to Figure 7 and Figure 9 The data path logic circuit 180 can provide a plurality of data signals to the pads 161, 162, 165, 166, 167, ... and 168 shown, and receive a command latch enable (CLE) signal, an address latch enable (ALE) signal, a read enable (RE_N) signal and a data signal. Figure 1 The control logic 140 shown transmits a command latch enable (CLE) signal, an address latch enable (ALE) signal, and a read enable (RE_N) signal. In addition, the data path logic circuit 180 can send Figure 1 The read / write circuit 130 is shown transmitting data signals received via the data input / output (DQ<7:0>) lines.

[0132] During normal operation of the memory device 100, the DDR test controller 170 transmits a signal received via pad 164 as an internal data strobe (DQS_INT) signal to the data path logic circuit 180. Furthermore, during normal operation of the memory device 100, the DDR test controller 170 transmits a signal received via pad 163 as an internal write enable (WE_N_INT) signal to the data path logic circuit 180. The internal write enable (WE_N_INT) signal may be transmitted to the control logic 140.

[0133] During the SDR test operation of the memory device 100, the DDR test controller 170 transmits the signal received via the pad 163 as the internal write enable (WE_N_INT) signal to the data path logic circuit 180. In this case, there is no need to generate the internal data strobe (DQS_INT) signal. In addition, during the SDR test operation of the memory device 100, the pad 164 is not used.

[0134] During the DDR test operation of the memory device 100, the pad 164 is not used. During the DDR test operation of the memory device 100, during the period when a program command and address are input, the DDR test controller 170 transmits the signal input to the pad 163 as the internal write enable (WE_N_INT) signal to the data path logic circuit 180. In addition, during the period when a program command and address are input during the DDR test operation, the DDR test controller 170 generates a high internal data strobe (DQS_INT) signal and transmits the internal data strobe (DQS_INT) signal to the data path logic circuit 180.

[0135] Furthermore, during the DDR test operation, in the period of inputting data, the DDR test controller 170 transmits the signal input to the pad 163 as the internal data strobe (DQS_INT) signal to the data path logic circuit 180. Furthermore, during the DDR test operation, in the period of inputting data, the DDR test controller 170 generates a high state internal write enable (WE_N_INT) signal and transmits the internal write enable (WE_N_INT) signal to the data path logic circuit 180. Hereinafter, referring to Figure 12 Give more description.

[0136] Figure 12 is used to describe Figure 11 The timing diagram of the DDR test of the memory device is shown.

[0137] Reference Figure 12 , shows the signals of the data input / output (DQ<7:0>) line, the command latch enable (CLE) signal, the address latch enable (ALE) signal, the internal write enable (WE_N_INT) signal, the write enable (WE_N) signal, and the internal data strobe (DQS_INT) signal during the DDR test operation of the memory device 100. Since the memory device 100 does not receive the data strobe (DQS) signal from the outside during the DDR test operation, Figure 12 The timing diagram of the data strobe (DQS) signal is omitted.

[0138] In period 7 (P7), while the command latch enable (CLE) signal is activated high, an "80h" signal may be input through the data input / output (DQ<7:0>) line. After the "80h" signal is input, the command latch enable (CLE) signal is deactivated low, and the address latch enable (ALE) signal may be activated high. While the address latch enable (ALE) signal is activated, address signals A0 to A4 may be input through the data input / output (DQ<7:0>) line.

[0139] In period 7 (P7), the DDR test controller 170 may transmit the write enable (WE_N) signal transmitted through the pad 163 to the data path logic circuit 180 as the internal write enable (WE_N_INT) signal. Therefore, in period 7 (P7), the internal write enable signal WE_N_INT may be switched in the same manner as the write enable (WE_N) signal. In period 7 (P7), the "80h" signal and the address signals A0 to A4 as part of the program command may be input in synchronization with the internal write enable signal WE_N_INT. Figure 12 In the example of FIG, an “80h” signal and address signals A0 to A4 as part of a program command may be input to the memory device at a rising edge of the internal write enable signal WE_N_INT. Furthermore, in period 7 (P7), the DDR test controller 170 may generate an internal data strobe (DQS_INT) signal in a high state and transmit the internal data strobe (DQS_INT) signal to the data path logic circuit 180.

[0140] In period 8 (P8), data signals D0 to D1 may be input to the memory device through the data input / output (DQ<7:0>) lines. m In period 8 (P8), the DDR test controller 170 may transmit the write enable (WE_INT) signal transmitted through the pad 163 to the data path logic circuit 180 as the internal data strobe (DQS_INT) signal. Therefore, in period 8 (P8), the internal data strobe (DQS_INT) signal may switch in the same manner as the write enable (WE_N) signal. The data signals D0 to D1 may be input to the memory device at the rising and falling edges of the internal data strobe (DQS_INT) signal. m .

[0141] Furthermore, in period 8 ( P8 ), the DDR test controller 170 may generate an internal write enable (WE_N_INT) signal of a high state and transmit the internal write enable (WE_N_INT) signal to the data path logic circuit 180 .

[0142] In period 9 (P9) after data input is completed, a "10h" signal can be input through the data input / output (DQ<7:0>) line in a state where the command latch enable (CLE) signal is activated high. Basically the same as period 7 (P7), in period 9 (P9), the DDR test controller 170 can transmit the write enable (WE_N) signal transmitted through pad 163 to the data path logic circuit 180 as the internal write enable (WE_N_INT) signal. Therefore, in period 9 (P9), the internal write enable (WE_N_INT) signal can be switched in the same manner as the write enable (WE_N) signal. In period 9 (P9), the "10h" signal can be input synchronously with the internal write enable signal WE_N_INT.

[0143] Substantially the same as period 7 ( P7 ), in period 9 ( P9 ), the DDR test controller 170 may generate an internal data strobe (DQS_INT) signal of a high state and transmit the internal data strobe (DQS_INT) signal to the data path logic circuit 180 .

[0144] According to an embodiment of the present disclosure, commands and addresses can be input to the memory device 100 in synchronization with an internal write enable (WE_N_INT) signal. During a DDR test, the DDR test controller 170 of the memory device 100 can transmit the write enable (WE_N) signal received through the pad 163 as the internal write enable (WE_N_INT) signal to the data path logic circuit 180 during the period of inputting commands and addresses. In this case, the DDR test controller 170 can generate an internal data strobe (DQS_INT) signal in a high state and transmit the internal data strobe (DQS_INT) signal to the data path logic circuit 180.

[0145] Furthermore, according to an embodiment of the present disclosure, data can be input to the memory device 100 in synchronization with an internal data strobe (DQS_INT) signal. During a DDR test, the DDR test controller 170 of the memory device 100 can transmit a write enable (WE_N) signal received via the pad 163 as the internal data strobe (DQS_INT) signal to the data path logic circuit 180 during a period of inputting data. In this case, the DDR test controller 170 can generate a high internal write enable (WE_N_INT) signal and transmit the internal write enable (WE_N_INT) signal to the data path logic circuit 180.

[0146] Therefore, according to an embodiment of the present disclosure, a DDR test of the memory device 100 can be performed without using the pad 164 for inputting a data strobe (DQS) signal. Therefore, the manufacturing cost of a test device capable of performing both a DDR test and an SDR test of the memory device 100 can be reduced. Consequently, the test cost of the memory device 100 can be reduced.

[0147] Figure 13 This is an example Figure 11 A block diagram of an example of an implementation of a DDR test controller is shown.

[0148] Reference Figure 13 DDR test controller 170 includes a multiplexer 171, an inverter 173, and a NAND gate 175. A first input terminal of multiplexer 171 is connected to pad 164. A second input terminal of multiplexer 171 is connected to pad 163. Multiplexer 171 is controlled by a DDR write enable (DDR_WE_EN) signal. When the DDR write enable (DDR_WE_EN) signal is high, multiplexer 171 may transmit a write enable (WE_N) signal received from pad 163 to data path logic circuit 180 as an internal data strobe DQS_INT. When the DDR write enable (DDR_WE_EN) signal is low, multiplexer 171 may transmit a data strobe (DQS) signal received from pad 164 to data path logic circuit 180 as an internal data strobe DQS_INT.

[0149] Inverter 173 inverts the write enable (WE_N) signal and transmits the inverted write enable signal to the first input terminal of NAND gate 175. Furthermore, the inverted DDR write enable (DDR_WE_EN_N) signal is input to the second input terminal of the NAND gate. NAND gate 175 generates an internal write enable (WE_N_INT) signal by performing a NAND operation on the signals at the first and second input terminals.

[0150] When the DDR write enable (DDR_WE_EN) signal is high, the inverted DDR write enable (DDR_WE_EN_N) signal may be low. In this case, regardless of the write enable (WE_N) signal, the NAND gate 175 may generate a high internal write enable (WE_N_INT) signal and transmit the internal write enable (WE_N_INT) signal to the data path logic circuit 180.

[0151] When the DDR write enable (DDR_WE_EN) is low, the inverted DDR write enable (DDR_WE_EN_N) signal may be high. In this case, the NAND gate 175 may invert the signal received by the first input terminal to generate an internal write enable (WE_N_INT) signal and transmit the internal write enable (WE_N_INT) signal to the data path logic circuit 180. In other words, the write enable (WE_N) signal may be transmitted to the data path logic circuit 180 as the internal write enable (WE_N_INT) signal.

[0152] According to an embodiment of the present disclosure, commands and addresses can be input to the memory device 100 in synchronization with an internal write enable (WE_N_INT) signal. During a DDR test, the DDR test controller 170 of the memory device 100 can transmit the write enable (WE_N) signal received through the pad 163 as the internal write enable (WE_N_INT) signal to the data path logic circuit 180 during a period in which commands and addresses are input. Therefore, during a DDR test, the DDR write enable (DDR_WE_EN) signal is in a high state during a period in which commands and addresses are input.

[0153] Furthermore, according to an embodiment of the present disclosure, data can be input to the memory device 100 in synchronization with the internal data strobe (DQS_INT) signal. During a DDR test, the DDR test controller 170 of the memory device 100 can transmit a write enable (WE_N) signal received through the pad 163 as the internal data strobe (DQS_INT) signal to the data path logic circuit 180 during a period of inputting data. Therefore, during a DDR test, the DDR write enable (DDR_WE_EN) signal has a low state during a period of inputting data.

[0154] Therefore, according to an embodiment of the present disclosure, a DDR test of the memory device 100 can be performed without using the pad 164 for inputting a data strobe (DQS) signal. Therefore, the manufacturing cost of a test device capable of performing both a DDR test and an SDR test of the memory device 100 can be reduced. Consequently, the test cost of the memory device 100 can be reduced.

[0155] Figure 14 is an example used to generate Figure 13 FIG. 1 is a diagram of a trigger for a DDR write enable signal. In an embodiment, Figure 14 The trigger 177 may be included in the DDR test controller 170 .

[0156] Reference Figure 14, a DDR test enable (DDR_TEST_EN) signal is input to the data input terminal D of the flip-flop 177. The DDR test enable (DDR_TEST_EN) signal is a signal that controls the memory device 100 to enter a DDR test operation. As an embodiment, when the memory device 100 receives a command for a DDR test operation from the outside, the DDR test enable (DDR_TEST_EN) signal may be activated high in response to the command.

[0157] The data input control (DATAIN) signal is input to the clock input terminal CLK of the flip-flop 177. The data input control (DATAIN) signal may be a signal generated within the memory device 100. For example, the input of the "80h" signal and the address signal may be completed, and the address latch enable (ALE) signal may be deactivated to low. In response to the address latch enable (ALE) signal being deactivated to low, the data input control (DATAIN) signal may be activated from low to high. In other words, the data input control (DATAIN) signal may be a signal that is activated after the address is input and before the data is input.

[0158] The column count end (CC_END) signal is input to the reset input terminal R of the flip-flop 177. The column count end (CC_END) signal is a signal generated inside the memory device 100 and may be a signal for counting columns for receiving data. Figure 10 As shown, when the program data is input in units of m+1, the column count end (CC_END) signal may transition to high after counting (m+1) / 2 clocks. In other words, the column count end (CC_END) signal may be activated when the input of the program data is completed. In addition, the DDR write enable (DDR_WE_EN) signal is output via the output terminal Q of the flip-flop 177. In some embodiments, m may be a natural number.

[0159] Regarding the operation of the flip-flop 177, the signal at the output terminal Q of the flip-flop 177 follows the signal at the data input terminal D at the edge of the signal input to the clock input terminal CLK. When the signal input to the clock input terminal CLK does not change, the signal at the output terminal Q does not change even if the signal at the data input terminal D changes.

[0160] Therefore, the DDR write enable (DDR_WE_EN) signal output to the output terminal Q of the flip-flop 177 follows the DDR test enable (DDR_TEST_EN) signal at the edge of the data input control (DATAIN) signal.

[0161] In addition, when the column count end (CC_END) signal input to the reset input terminal R changes from low to high, the signal of the output terminal Q of the flip-flop 177 (ie, the DDR write enable (DDR_WE_EN) signal) is reset to zero. Figure 15 Describes DDR testing of memory devices.

[0162] Figure 15 is used to describe Figure 11 The timing diagram of the DDR test of the memory device is shown.

[0163] In period 10 (P10), a DDR test command CMDT may be input from outside the memory device 100. As an example, the DDR test command CMDT may be input by a test device connected to the memory device 100. The DDR test command CMDT may be input by a command latch enable (CLE) signal, and the address ADDR may be input by an address latch enable (ALE) signal. However, this is an example, and the address ADDR may not be input in period 10 (P10). In period 10 (P10), the DDR test command CMDT and the address ADDR may be input synchronously with an internal write enable (WE_N_INT) signal. That is, the DDR test controller 170 may receive a write enable (WE_N) signal and transmit the write enable (WE_N) signal to the data path logic circuit 180 as an internal write enable (WE_N_INT) signal. More specifically, during period P10, the DDR write enable (DDR_WE_EN) signal is in a low state, and the inverted DDR write enable (DDR_WE_EN_N) signal is in a high state. Therefore, NAND gate 175 can transmit the write enable (WE_N) signal received through pad 163 to data path logic circuit 180 as an internal write enable (WE_N_INT) signal.

[0164] During period 10 (P10), since the DDR write enable (DDR_WE_EN) signal is in a low state, multiplexer 171 can transmit the signal received from pad 164 to data path logic circuit 180 as the internal data strobe (DQS_INT) signal. However, during the DDR test operation, no signal can be input to pad 164. Therefore, pad 164 can be in a high impedance (high z) state. Therefore, the internal data strobe (DQS_INT) signal can be in a high state.

[0165] Furthermore, in response to the DDR test command CMDT received in period 10 (10), the DDR test enable (DDR_TEST_EN) signal may transition from a low state to a high state. Furthermore, the inverted DDR test enable (DDR_TEST_EN_N) signal may transition from a high state to a low state.

[0166] In period 11 (P11), in a state where the command latch enable (CLE) signal is activated high, an "80h" signal may be input through the data input / output (DQ<7:0>) line. After the "80h" signal is input, the command latch enable (CLE) signal may be deactivated low, and the address latch enable (ALE) signal may be activated high. In a state where the address latch enable (ALE) signal is activated, address signals A0 to A4 may be input through the data input / output (DQ<7:0>) line. After the address signals A0 to A4 are input, the address latch enable (ALE) signal may be deactivated low.

[0167] At time t1, the data input control (DATAIN) signal may be activated to a high state. As described above, in response to the address latch enable (ALE) signal being deactivated to low, the data input control (DATAIN) signal may be activated from low to high. Figure 14 , the DDR write enable (DDR_WE_EN) signal follows the DDR test enable (DDR_TEST_EN) signal at the edge of the data input control (DATAIN) signal input to the clock input terminal CLK of the flip-flop 177. Therefore, at time t1, the DDR write enable (DDR_WE_EN) signal follows the DDR test enable (DDR_TEST_EN) signal and transitions to a high state.

[0168] As the DDR write enable (DDR_WE_EN) signal changes to a high state, the multiplexer 171 of the DDR test controller 170 transmits the write enable (WE_N) signal received from the pad 163 as the internal data strobe DQS_INT to the data path logic circuit 180. That is, starting from time t1, the internal data strobe DQS_INT switches according to the write enable (WE_N) signal.

[0169] In addition, as the DDR write enable (DDR_WE_EN) signal changes to a high state, the inverted DDR write enable (DDR_WE_EN_N) signal changes to a low state. As the inverted DDR write enable (DDR_WE_EN_N) signal changes to a low state, regardless of the write enable (WE_N) signal, starting from time t1, NAND gate 175 generates a high internal write enable (WE_N_INT) signal and transmits the internal write enable (WE_N_INT) signal to data path logic circuit 180.

[0170] In period 12 (P12), data D0 to D1 are input through the data input / output (DQ<7:0>) lines. m In period 12 (P12), data D0 to D1 can be received synchronously with the internal data strobe DQS_INT. m When input data D0 to D m When the last data signal Dm is received, the column count end (CC_END) signal may be turned high at time t2. As the column count end (CC_END) signal turns high, Figure 14 The flip-flop 177 is reset. Therefore, the DDR write enable (DDR_WE_EN) signal, which is a signal output to the output terminal Q of the flip-flop 177 from time t2, changes from a high state to a low state.

[0171] As the DDR write enable (DDR_WE_EN) signal changes to a low state, multiplexer 171 transmits the signal received from pad 164 to data path logic circuit 180 as the internal data strobe (DQS_INT) signal. However, during DDR test operations, no signal can be input to pad 164. Therefore, pad 164 can be in a high impedance (high z) state. Therefore, the internal data strobe (DQS_INT) signal can change to a high state at time t2.

[0172] In addition, as the DDR write enable (DDR_WE_EN) signal goes low, the inverted DDR write enable (DDR_WE_EN_N) signal goes high. Therefore, starting from time t2, NAND gate 175 can transmit the write enable (WE_N) signal received through pad 163 to data path logic circuit 180 as the internal write enable (WE_N_INT) signal.

[0173] In period 13 (P13) after data input is completed, a "10h" signal may be input through the data input / output (DQ<7:0>) line while the command latch enable (CLE) signal is activated high. Substantially the same as period 10 (P10), in period 13 (P13), the DDR test controller 170 may transmit the write enable (WE_N) signal transmitted through pad 163 to the data path logic circuit 180 as the internal write enable (WE_N_INT) signal. Therefore, in period 13 (P13), the internal write enable (WE_N_INT) signal may switch in the same manner as the write enable (WE_N) signal. In period 13 (P13), the "10h" signal may be input synchronously with the internal write enable signal WE_N_INT.

[0174] As described above, according to an embodiment of the present disclosure, commands and addresses can be input to the memory device 100 in synchronization with the internal write enable (WE_N_INT) signal. During a DDR test, the DDR test controller 170 of the memory device 100 can transmit the write enable (WE_N) signal received through the pad 163 as the internal write enable (WE_N_INT) signal to the data path logic circuit 180 during a period in which commands and addresses are input. Therefore, during a DDR test, the DDR write enable (DDR_WE_EN) signal is in a high state during a period in which commands and addresses are input.

[0175] Furthermore, according to an embodiment of the present disclosure, data can be input to the memory device 100 in synchronization with the internal data strobe (DQS_INT) signal. During a DDR test, the DDR test controller 170 of the memory device 100 can transmit a write enable (WE_N) signal received through the pad 163 as the internal data strobe (DQS_INT) signal to the data path logic circuit 180 during a period of inputting data. Therefore, during a DDR test, the DDR write enable (DDR_WE_EN) signal has a low state during a period of inputting data.

[0176] Therefore, according to an embodiment of the present disclosure, a DDR test of the memory device 100 can be performed without using the pad 164 for inputting a data strobe (DQS) signal. Therefore, the manufacturing cost of a test device capable of performing both a DDR test and an SDR test of the memory device 100 can be reduced. Consequently, the test cost of the memory device 100 can be reduced.

[0177] Figure 16 It is used to describe Figure 1 FIG. 1 is a diagram of an embodiment of a system of memory devices shown.

[0178] Reference Figure 16, system 30000 can be implemented as a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), or a wireless communication device.

[0179] The system 30000 may include a memory device 100 and a memory controller 1100 capable of controlling operations of the memory device 100. The memory controller 1100 may control data access operations of the memory device 100, such as program operations, erase operations, or read operations, under the control of the host 2000.

[0180] Data programmed in the memory device 100 may be output through the display 3200 under the control of the memory controller 1100 .

[0181] The radio transceiver 3300 can transmit and receive radio signals via the antenna ANT. For example, the radio transceiver 3300 can convert radio signals received via the antenna ANT into signals that can be processed by the host 2000. Thus, the host 2000 can process the signals output from the radio transceiver 3300 and transmit the processed signals to the memory controller 1100 or the display 3200. The memory controller 1100 can transmit the processed signals from the host 2000 to the memory device 100. Furthermore, the radio transceiver 3300 can convert signals output from the host 2000 into radio signals and output the converted radio signals to an external device via the antenna ANT. The input device 3400 can be a device capable of inputting control signals for controlling the operation of the host 2000 or data to be processed by the host 2000. The input device 3400 can be implemented as a pointing device such as a touchpad or a computer mouse, a keypad, or a keyboard. The host 2000 may control the operation of the display 3200 so that data output from the memory controller 1100 , data output from the radio transceiver 3300 , or data output from the input device 3400 is output through the display 3200 .

[0182] Figure 17 It is used to describe Figure 1 A diagram of another embodiment of a system of memory devices is shown.

[0183] Reference Figure 17 , the system 40000 can be implemented as a personal computer (PC), a tablet PC, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

[0184] The system 40000 may include a memory device 100 and a memory controller 1100 capable of controlling data processing operations of the memory device 4500 .

[0185] The host 2000 may output data stored in the memory device 100 through the display 4300 according to data input through the input device 4200. For example, the input device 4200 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

[0186] The host 2000 may control the overall operation of the system 40000 and control the operation of the memory controller 1100 .

[0187] Figure 18 It is used to describe Figure 1 A diagram of another embodiment of a system of memory devices is shown.

[0188] Reference Figure 18 The system 50000 may be implemented as an image processing apparatus, for example, a digital camera, a portable phone equipped with a digital camera, a smart phone equipped with a digital camera, or a tablet PC equipped with a digital camera.

[0189] The system 50000 may include a memory device 100 and a memory controller 1100 capable of controlling a data processing operation of the memory device 100 , for example, a program operation, an erase operation, or a read operation.

[0190] The image sensor 5200 of the system 50000 can convert an optical image into a digital signal. The converted digital signal can be transmitted to the host 2000. Under the control of the host 2000, the converted digital signal can be output through the display 5300 or stored in the memory device 100 through the memory controller 1100. In addition, the data stored in the memory device 100 can be output through the display 5300 under the control of the host 2000.

[0191] Figure 19 It is used to describe Figure 1 A diagram of another embodiment of a system of memory devices is shown.

[0192] Reference Figure 19 , the system may include a host 2000 and a memory card 70000 .

[0193] The memory card 70000 may be implemented as a smart card. The memory card 70000 may include a memory device 100 , a memory controller 1100 , and a card interface 7100 .

[0194] The memory controller 1100 can control the data exchange between the memory device 100 and the card interface 7100. According to an embodiment, the card interface 7100 can be a secure digital (SD) card interface or a multimedia card (MMC) interface, but is not limited thereto. In addition, the card interface 7100 can interface the data exchange between the host 2000 and the memory controller 1100 according to the protocol of the host 2000. According to an embodiment, the card interface 7100 can support the universal serial bus (USB) protocol and the inter-chip (IC)-USB protocol. Here, the card interface 7100 can refer to hardware that can support the protocol used by the host 2000, software installed in the hardware, or a signal transmission method.

[0195] Although the detailed description of the present disclosure describes specific embodiments, various changes and modifications may be made without departing from the scope and technical spirit of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the above-mentioned embodiments, but should be determined by the equivalents of the claims of the present disclosure and the appended claims.

[0196] CROSS-REFERENCE TO RELATED APPLICATIONS

[0197] This application claims the benefit of Korean Patent Application No. 10-2020-0084980 filed on July 9, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device, comprising: a first pad capable of receiving a write enable signal; a second pad capable of receiving a data strobe signal; as well as a double data rate (DDR) test controller connected to the first pad and the second pad and configured to output an internal write enable signal and an internal data strobe signal, In the period of input data during a DDR test operation of the memory device, the DDR test controller generates the internal data strobe signal based on the write enable signal received through the first pad without using the data strobe signal received through the second pad.

2. The memory device according to claim 1, wherein During normal operation of the memory device, the DDR test controller outputs the write enable signal received through the first pad as the internal write enable signal, and outputs the data strobe signal received through the second pad as the internal data strobe signal.

3. The memory device according to claim 1, wherein During the DDR test operation, in a period of inputting a command or an address, the DDR test controller outputs the write enable signal received through the first pad as the internal write enable signal.

4. The memory device according to claim 1, wherein During the DDR test operation, in the period of inputting data, the DDR test controller outputs the write enable signal received through the first pad as the internal data strobe signal.

5. The memory device according to claim 1, wherein The DDR test controller includes: a multiplexer connected to the first pad and the second pad through an input terminal and configured to output the internal data strobe signal according to control of a DDR write enable signal; an inverter configured to invert the write enable signal input to the first pad; and A NAND gate is configured to perform a NAND operation on the output of the inverter and the inverted DDR write enable signal to generate the internal write enable signal. The memory device according to claim 5 , wherein: The DDR test controller further includes a trigger, The DDR test enable signal is input to the data input terminal of the flip-flop, The data input control signal is input to the clock input terminal of the flip-flop, The column count end signal is input to the reset input terminal of the flip-flop, and The DDR write enable signal is output to an output terminal of the flip-flop.

7. The memory device according to claim 6, wherein: When the memory device receives a command for the DDR test operation, the DDR test enable signal is activated to a high state in response to the receipt of the command.

8. The memory device according to claim 6, wherein When the memory device completes reception of the address signal, the data input control signal is activated to a high state in response to completion of reception of the address signal.

9. The memory device according to claim 6, wherein: When the memory device completes receiving the data, the column count end signal is activated to a high state in response to the completion of receiving the data.

10. The memory device according to claim 6, wherein When the data input control signal transitions to high, the DDR write enable signal output to the output terminal of the flip-flop follows the DDR test enable signal.

11. The memory device according to claim 5, wherein The DDR test controller receives a DDR test enable signal in synchronization with a data input control signal to generate the DDR write enable signal.

12. The memory device according to claim 1, further comprising: A data path logic circuit is configured to receive the internal write enable signal and the internal data strobe signal and transmit the internal write enable signal and the internal data strobe signal to control logic.

13. A memory device, comprising: a memory cell array, the memory cell array comprising a plurality of memory cells; a peripheral circuit configured to perform a program operation, an erase operation, or a read operation on the memory cell array; control logic configured to control the operation of the peripheral circuit; as well as a double data rate (DDR) test controller configured to generate an internal write enable signal and an internal data strobe signal for transmission to the control logic based on signals received from the first pad and the second pad, wherein, during normal operation of the memory device, the DDR test controller generates the internal write enable signal based on a first signal received through the first pad and generates the internal data strobe signal based on a second signal received through the second pad, and In a period of input data during the DDR test operation of the memory device, the DDR test controller generates the internal data strobe signal based on the first signal received through the first pad without using the second signal received through the second pad.

14. The memory device according to claim 13, wherein: During the DDR test operation, in a period of inputting a command or an address, the DDR test controller generates the internal write enable signal based on the first signal received through the first pad.

15. The memory device according to claim 13, wherein: During the DDR test operation, the DDR test controller outputs the first signal received through the first pad as the internal data strobe signal in the period of inputting data.

16. The memory device according to claim 13, wherein The DDR test controller includes: a multiplexer connected to the first pad and the second pad through an input terminal and configured to output the internal data strobe signal under control of a third signal; an inverter configured to invert a signal input to the first pad; and A NAND gate is configured to perform a NAND operation on the output of the inverter and the inverted third signal to generate the internal write enable signal.

17. The memory device according to claim 16, wherein: The DDR test controller further includes a trigger, The fourth signal is input to the data input terminal of the flip-flop, The fifth signal is input to the clock input terminal of the flip-flop, The sixth signal is input to the reset input terminal of the flip-flop, and The third signal is output to an output terminal of the flip-flop.

18. The memory device according to claim 17, wherein: When the memory device receives a command for the DDR test operation, the fourth signal changes to an active state in response to the reception of the command.

19. The memory device according to claim 17, wherein: When the memory device completes reception of the address signal, the fifth signal changes to an active state in response to completion of reception of the address signal.

20. The memory device of claim 17, wherein: When the memory device completes receiving the data, the sixth signal changes to an active state in response to the completion of receiving the data.

21. The memory device of claim 17, wherein: The third signal output to the output terminal of the flip-flop follows the fourth signal at an edge of the fifth signal.

Images