Semiconductor package and method of manufacturing the same

Abstract

Embodiments of the present invention provide a semiconductor package and a method of manufacturing the same. A semiconductor package includes a substrate, a semiconductor die, a ring structure, and a cap. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, wherein a first side of the semiconductor die is separated from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is separated from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is smaller than the second gap. The cap is disposed on the ring structure and has a recess formed therein, and the recess overlaps the first gap in a stacking direction of the ring structure and the cap.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application provide a semiconductor package and a method of manufacturing the same. BACKGROUND

[0002] Semiconductor devices and integrated circuits (ICs) are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic devices. For example, semiconductor devices and ICs are typically fabricated on a single semiconductor wafer. Dices of the wafer can be processed and packaged with other semiconductor devices, dices, or components at the wafer level or after wafer sawing, and various techniques have been developed. Semiconductor processing for making semiconductor devices and ICs continues to advance toward increasing device density, with increasing numbers of active devices (primarily transistors) having ever-decreasing device sizes. As electronic products continue to be miniaturized, heat dissipation of packaged semiconductor devices and ICs has become useful for packaging technology. SUMMARY

[0003] Embodiments of the present application provide a semiconductor package including a substrate, a semiconductor die, a ring structure, and a cap. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, wherein a first side of the semiconductor die is spaced apart from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is spaced apart from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is smaller than the second gap. The cap is disposed on the ring structure and has a recess formed therein, and the recess overlaps the first gap in a stacking direction of the ring structure and the cap.

[0004] Embodiments of the present application provide a semiconductor package including a substrate, a semiconductor die, and an electromagnetic interference shielding structure. The semiconductor die is disposed on the substrate in an offset position toward an edge of the substrate. The electromagnetic interference shielding structure is disposed on the substrate and electrically connected to the substrate, wherein the semiconductor die is located in a space defined by the substrate and the electromagnetic interference shielding structure, and a recess formed in the electromagnetic interference shielding structure corresponds to the offset position.

[0005] A method of manufacturing a semiconductor package includes providing a semiconductor die; mounting the semiconductor die to a substrate; adhering a ring-shaped structure on the substrate to surround the semiconductor die, a first side of the semiconductor die being separated from an inner sidewall of the ring-shaped structure by a first gap, and a second side of the semiconductor die being separated from the inner sidewall of the ring-shaped structure by a second gap, wherein the first side is opposite to the second side, and the first gap is smaller than the second gap; and adhering a cap on the ring-shaped structure to form an accommodation space with the ring-shaped structure and the substrate, the semiconductor die being located in the accommodation space, and the cap including a recess formed therein, wherein the recess is in spatial communication with the accommodation space, and overlaps the first gap in a stacking direction of the ring-shaped structure and the cap. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of the disclosure will be understood with reference to the following detailed description read in light of the accompanying drawings, in which the same reference characters are used throughout the drawings to refer to same elements. It should be noted that the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity.

[0007] Figure 1 、 Figure 3 and Figure 5 shows a schematic cross-sectional view of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0008] Figure 2 、 Figure 4 and Figure 6 shows a schematic plan view of the relative positions of components included in the semiconductor package illustrated in Figure 1 、 Figure 3 and Figure 5 .

[0009] Figure 7 shows a schematic cross-sectional view of the semiconductor package illustrated in Figure 6 .

[0010] Figure 8 shows a flowchart of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0011] Figure 9 shows a schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present disclosure.

[0012] Figure 10 shows a schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present disclosure.

[0013] Figure 11 shows a schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present disclosure.

[0014] Figure 12 schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the disclosure.

[0015] Figure 13 schematic plan view showing relative positions of components included in a semiconductor package according to some alternative embodiments of the disclosure.

[0016] Figure 14 schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the disclosure. Figure 13

[0017] Figure 15 schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the disclosure.

[0018] Figure 16 schematic plan view showing relative positions of components included in a semiconductor package according to some alternative embodiments of the disclosure. Figure 15

[0019] schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the disclosure. Figure 17

[0020] schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the disclosure. Figure 18

[0021] schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the disclosure. Figure 19

[0022] schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the disclosure. Figure 20

[0023] schematic plan view showing relative positions of components included in a semiconductor package according to some alternative embodiments of the disclosure. Figure 21

[0024] schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the disclosure. Figure 22

[0025] schematic plan view showing relative positions of components included in a semiconductor package according to some alternative embodiments of the disclosure. Figure 23 Figure 22 schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the disclosure.

[0026] Figure 24 schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the disclosure.

[0027] Figure 25 ​​A schematic cross-sectional view of a semiconductor package is shown.

[0028] Figure 26 A schematic plan view showing relative positions of components included in the semiconductor package shown in Figure 25

[0029] Figure 27 A schematic cross-sectional view of a semiconductor package is shown.

[0030] Figure 28 A schematic cross-sectional view of a semiconductor package is shown.

[0031] [Explanation of symbols]

[0032] 10, 10a, 10b, 10c, 10d, 10e, 20, 20a, 20b, 20c, 20d, 20e, 30, 30a, 40, 40a: semiconductor package

[0033] 100, 900: semiconductor die

[0034] 110: semiconductor substrate

[0035] 110a: front side surface

[0036] 110b: back side surface

[0037] 120: interconnect structure

[0038] 122: interlayer dielectric layer

[0039] 124: patterned conductive layer

[0040] 130: passivation layer

[0041] 130a: surface

[0042] 140, 920: via

[0043] 202, 204: solder region

[0044] 310, 320: semiconductor device

[0045] 400: conductive terminal

[0046] 500: substrate

[0047] 500b, 600b, 800b: bottom surface

[0048] 500t, 600t, 800t: top surface

[0049] 510, 520: bond pad ​

[0050] 530: metallization layer

[0051] 600A, 600A', 600B, 600B', 600C, 600D: ring structure

[0052] 710, 720: adhesive

[0053] 730: thermal interface material

[0054] 800A, 800B, 800C, 800D: cover

[0055] C1: first component

[0056] C2: second component

[0057] CL1, CL2: center line

[0058] CT: terminal

[0059] E1: first edge

[0060] E2: second edge

[0061] E3: third edge

[0062] E4: fourth edge

[0063] G1, G2, G3, G4, W1, W2, W6, W7: gap

[0064] L1, L2: length

[0065] O1: opening

[0066] P1: part of ring structure

[0067] P2: part of cover structure

[0068] R1, R2, R2': recess

[0069] S1: first side

[0070] S2: second side

[0071] S3: third side

[0072] S4: fourth side

[0073] S5, S5', S6, S7, S8, S9, S10, S11, S12: side

[0074] S5a, S5b: planar surface

[0075] S1000, S2000, S3000, S4000: step

[0076] SC: subassembly

[0077] SW600i: inner sidewall

[0078] SW600o: outer sidewall

[0079] SW800: sidewall

[0080] T1: distance

[0081] T5, T600, T800, W3, W4, W4', W8, W9: thickness

[0082] UF: underfill layer

[0083] W5, W5': width

[0084] X, Y, Z: direction

[0085] Θ: angle DETAILED DESCRIPTION

[0086] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components, values, operations, materials, arrangements or the like are set forth in the following description for simplicity and clarity purposes only. It is contemplated that there are other components, values, operations, materials, arrangements, and the like which are within the scope of the disclosure. For example, the following description can use “over” or “on” to denote a first feature formed over or on a second feature can include embodiments where the first feature is formed in direct contact with the second feature, and also embodiments where additional features can be formed between the first and second features such that the first and second features can not be in direct contact. In addition, the present disclosure can repeatedly use reference numbers and / or letters in various instances throughout the description. Such repetition is for the purpose of simplification and clarity and does not itself dictate a relationship between various embodiments and / or configurations discussed.

[0087] Also for ease of explanation, spatially relative terms such as “beneath”, “below”, “lower”, “above”, “upper” and the like can be used herein for explaining a relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0088] In addition, for ease of explanation, terms such as "first," "second," "third," "fourth," and the like can be used herein to illustrate similar elements or features or different elements or features shown in the figures and can be used interchangeably depending on the order presented or the context of the description.

[0089] The present disclosure can also include other features and processes. For example, test structures can be included to facilitate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3DIC) devices. The test structures can include test pads formed, for example, in a redistribution layer or on a substrate to enable testing of 3D packages or 3DICs, use of probes and / or probe cards, and the like. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with testing methods that include intermediate verification of known good dies to improve yield and reduce costs.

[0090] In accordance with various exemplary embodiments, a semiconductor package and a method of manufacturing the same are provided. Prior to specifically setting forth the illustrated embodiments, certain advantageous features and aspects of the embodiments of the present disclosure will be summarized. The semiconductor package can be employed to improve stress concentration and / or delamination issues during the manufacturing process. What is set forth below is a semiconductor package having a structure with a semiconductor device disposed above a substrate in an offset position (e.g., displaced from a center axis of the substrate). Accordingly, a cap having a recess corresponding to the offset position is bonded to an annular structure mounted on the substrate and surrounding the semiconductor device, which allows the cap to have greater flexibility in deformation ability at the location of the recess, thereby avoiding or reducing stress concentration and / or delamination issues (e.g., between the cap and the annular structure). In addition to the purpose of heat dissipation, the cap, the annular structure, and an adhesive employed to secure the cap and the annular structure to the substrate together constitute an electromagnetic interference shielding structure for the semiconductor element. Intermediate stages of forming the semiconductor package are shown in accordance with some embodiments. Some variations of some embodiments are discussed. In the various views and illustrative embodiments, the same reference numbers are used to denote the same elements.

[0091] Figure 1 、 Figure 3 and Figure 5 A schematic cross-sectional view of a method of manufacturing a semiconductor package 10 in accordance with some embodiments of the present disclosure is shown. Figure 2 ,Figure 4 and Figure 6 schematic plan view showing relative positions of components included in the semiconductor package shown in Figure 1 , Figure 3 and Figure 5 schematic plan view showing relative positions of components included in the semiconductor package shown in Figure 7 schematic cross-sectional view of the semiconductor package shown in Figure 6 , wherein Figure 1 , Figure 3 and Figure 5 are cross-sectional views taken along centerline CL1 shown in Figure 2 , Figure 4 and Figure 6 , and Figure 7 is a cross-sectional view taken along centerline CL2 shown in Figure 6 . Figure 8 flowchart showing a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. Figures 9 to 12 and Figure 14 are schematic cross-sectional views showing a semiconductor package according to some alternative embodiments of the present disclosure along centerline CL1. Figure 13 schematic plan view showing relative positions of components included in the semiconductor package shown in Figure 14 , wherein Figure 14 is a cross-sectional view taken along centerline CL2 shown in Figure 13 . In some embodiments, the method of manufacturing is part of a wafer level packaging process. It should be noted that the process steps set forth herein encompass part of a manufacturing process for making a semiconductor package involving a semiconductor component such as a semiconductor die (or device / chip). The embodiments are intended to provide further explanation but not to limit the scope of the present disclosure.

[0092] Referring to Figure 1 and Figure 2 , in some embodiments, a semiconductor die 100 is provided according to step S1000 of Figure 8 . In some embodiments, the semiconductor die 100 includes a semiconductor substrate 110, an interconnect structure 120 disposed on the semiconductor substrate 110, a passivation layer 130 disposed on the interconnect structure 120, and a plurality of vias 140 extending through the passivation layer 130 and disposed on the interconnect structure 120. As shown in Figure 1 , for example, the semiconductor substrate 110 has a front side surface 110a and a back side surface 110b opposite the front side surface 110a, and the interconnect structure 120 is on the front side surface 110a of the semiconductor substrate 110, wherein the interconnect structure 120 is sandwiched between the semiconductor substrate 110 and the passivation layer 130, and is sandwiched between the semiconductor substrate 110 and the vias 140.

[0093] In some embodiments, the semiconductor substrate 110 is a silicon substrate that includes active components (e.g., transistors and / or memory (e.g., N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) devices or the like)) and / or passive components (e.g., resistors, capacitors, inductors or the like) formed therein. In some embodiments, such active and passive components are formed in a front-end-of-line (FEOL) process. In alternative embodiments, the semiconductor substrate 110 is a bulk silicon substrate, such as a bulk single-crystal silicon substrate, a doped silicon substrate, an undoped silicon substrate, or a silicon-on-insulator (SOI) substrate, where the dopant of the doped silicon substrate can be an N-type dopant, a P-type dopant, or a combination thereof. The present disclosure is not limited in this regard.

[0094] The semiconductor substrate 110 can include other semiconductor materials such as, for example, germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multi-layered substrates or gradient substrates, can also be used. For example, the semiconductor substrate 110 has an active surface (e.g., front side surface 110a) that is sometimes referred to as a top side, and a non-active surface (e.g., back side surface 110b) that is sometimes referred to as a bottom side.

[0095] In some embodiments, the interconnect structure 120 includes one or more interlayer dielectric layers 122 and one or more patterned conductive layers 124 that are alternately stacked. For example, the interlayer dielectric layers 122 are silicon oxide layers, silicon nitride layers, silicon oxynitride layers, or dielectric layers formed from other suitable dielectric materials, and are formed by deposition or the like. For example, the patterned conductive layers 124 are patterned copper layers or other suitable patterned metal layers, and are formed by electroplating or deposition. However, the present disclosure is not limited in this regard. Alternatively, the patterned conductive layers 124 can be formed by a dual-damascene method. The number of interlayer dielectric layers 122 and the number of patterned conductive layers 124 can be less than or greater than Figure 1The number of layers illustrated in the middle is not particularly limited, and can be specified based on requirements and / or design layout; the present disclosure is not particularly limited thereto. In some embodiments, the interconnect structure 120 is formed in a back-end-of-line (BEOL) process. Throughout the description, the term "copper" is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing small amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium, etc.

[0096] In certain embodiments, as Figure 1 illustrated in the middle, the patterned conductive layers 124 are sandwiched between the interlayer dielectric layers 122, where the surface of the illustrated topmost layer of the patterned conductive layers 124 is at least partially exposed by and electrically connected to active components and / or passive components included in the semiconductor substrate 110 through a plurality of openings (not labeled) formed in the illustrated topmost layer of the interlayer dielectric layers 122, and the surface of the illustrated bottommost layer of the patterned conductive layers 124 is at least partially exposed by and electrically connected to one or more components for electrical connection (e.g., through the via 140) formed later through a plurality of openings Ol formed in the illustrated bottommost layer of the interlayer dielectric layers 122. The shape and number of the openings Ol and the shape and number of the openings formed in the illustrated topmost layer of the interlayer dielectric layers 122 are not limited in the present disclosure, and can be specified based on requirements and / or design layout.

[0097] In some embodiments, as Figure 1 illustrated in the middle, the passivation layer 130 is formed on the interconnect structure 120, where some portions of the interconnect structure 120 are covered by and in contact with the passivation layer 130, and the remaining portions of the interconnect structure 120 are exposed in an accessible manner by the passivation layer 130. As Figure 1As shown, the passivation layer 130 has a surface 130a, which is, for example, substantially planar. In certain embodiments, the surface 130a of the passivation layer 130 is flush and can have a high planarity and flatness, which is beneficial for later formed layers / elements (e.g., the vias 140). In some embodiments, the passivation layer 130 includes a polyimide (PI) layer, a polybenzoxazole (PBO) layer, a silicon dioxide-based (non-organic) layer, or other suitable polymeric (or organic) layer, and is formed by deposition or similar processes. The present disclosure is not limited thereto. The present disclosure does not specifically limit the thickness of the passivation layer 130, as long as the surface 130a of the passivation layer 130 is able to maintain its high planarity and flatness. In the present disclosure, the surface 130a of the passivation layer 130 can be referred to as a front surface of the semiconductor die 100, and the backside surface 110b of the semiconductor substrate 110 can be referred to as a backside surface of the semiconductor die 100.

[0098] In some embodiments, the vias 140 are formed on the interconnect structure 120 and above the semiconductor substrate 110, and sidewalls of the vias 140 are wrapped by the passivation layer 130. In some embodiments, as shown, the vias 140 each extend through the passivation layer 130 and into the openings Ol formed in the shown bottommost layer of the interlayer dielectric layer 122 to physically contact a surface of the patterned conductive layer 124 exposed by the openings Ol of the shown bottommost layer. Through the interconnect structure 120, the vias 140 are electrically connected to active components and / or passive components included in the semiconductor substrate 110. In some embodiments, the vias 140 in physical contact with the interconnect structure 120 extend away from the surface 130a of the passivation layer 130, as shown. Figure 1 However, the present disclosure is not limited thereto; alternatively, the vias 140 in physical contact with the interconnect structure 120 can each include a surface that is substantially coplanar with and flush to the surface 130a of the passivation layer 130. For illustration purposes and simplicity, only two vias 140 are shown in Figure 1 However, the present disclosure is not limited thereto; alternatively, the vias 140 in physical contact with the interconnect structure 120 can each include a surface that is substantially coplanar with and flush to the surface 130a of the passivation layer 130. For illustration purposes and simplicity, only two vias 140 are shown in Figure 1

[0099] ​In some embodiments, the vias 140 are formed by photolithography, plating, photoresist stripping processes, or any other suitable method. The plating process can include electroplating, electroless plating, or similar processes. For example, the vias 140 are formed by, but not limited to, the following: forming a mask pattern (not shown) covering the passivation layer 130, the mask pattern having a plurality of openings (not shown) corresponding to the surfaces of the patterned conductive layer 124 exposed by the openings Ol of the lowest layer shown; patterning the passivation layer 130 to form a plurality of contact openings (not shown) therein to expose the surfaces of the patterned conductive layer 124 exposed by the openings Ol of the lowest layer shown; forming a metal material filling the openings formed in the mask pattern, the contact openings formed in the passivation layer 130, and the openings Ol to form a plurality of vias 140 by electroplating or deposition; and then removing the mask pattern. The passivation layer 130 can be patterned by an etching process, such as a dry etching process, a wet etching process, or a combination thereof. It should be noted that, for example, the contact openings formed in the passivation layer 130 are each in spatial communication with a respective one of the openings Ol covering thereon for forming the vias 140. The mask pattern can be removed by an acceptable ashing process and / or a photoresist stripping process, such as using oxygen plasma or the like. In one embodiment, the material of the vias 140 includes a metal material, such as copper or copper alloy, or the like.

[0100] In some embodiments, the vias 140 can independently be circular, elliptical, triangular, rectangular, or the like in a vertical projection on the front side surface 110a of the semiconductor substrate 110 along a stacking direction Z of the semiconductor substrate 110, the interconnect structure 120, and the passivation layer 130. The shape of the vias 140 is not limited in the present disclosure. The number and shape of the vias 140 can be specified and selected based on requirements, and adjusted by changing the number and shape of the contact openings formed in the passivation layer 130.

[0101] Alternatively, the vias 140 may be formed by forming a first mask pattern (not shown) covering the passivation layer 130, the first mask pattern having a plurality of openings (not shown) corresponding to the surface of the patterned conductive layer 124 exposed by the bottom-most opening O1 shown; patterning the passivation layer 130 to form a plurality of contact openings (not shown) therein to expose the surface of the patterned conductive layer 124 exposed by the bottom-most opening O1 shown; removing the first mask pattern; conformally forming a metal seed layer over the passivation layer 130; forming a second mask pattern (not shown) covering the metal seed layer, the second mask pattern having a plurality of openings (not shown) exposing the contact openings and the openings O1 formed in the passivation layer 130; forming a metal material filling the openings formed in the second mask pattern, the contact openings and the openings O1 formed in the passivation layer 130 by electroplating or deposition; removing the second mask pattern; and then removing the metal seed layer not covered by the metal material to form a plurality of vias 140. In some embodiments, the metal seed layer is referred to as a metal layer and includes a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the metal seed layer includes titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, combinations thereof, or the like. For example, the metal seed layer may include a titanium layer and a copper layer located above the titanium layer. The metal seed layer may be formed using, for example, sputtering, physical vapor deposition (PVD), or similar processes.

[0102] In some embodiments, for the semiconductor die 100, the sidewalls of the semiconductor substrate 110, the sidewalls of the interconnect structure 120, and the sidewalls of the passivation layer 130 are substantially aligned with each other in the direction Z. For example, the outermost surface of the via 140 is shown protruding away from the surface 130a of the passivation layer 130 (e.g., not aligned with the surface 130a of the passivation layer 130), as shown in FIG. Figure 1 Alternatively, the outermost surface of the via 140 may be substantially flush and coplanar with the surface 130 a of the passivation layer 130 (eg, aligned with the surface 130 a of the passivation layer 130 ).

[0103] like Figure 1 and Figure 2As shown, for example, the sidewall of the semiconductor die 100 connects the surface 130a of the semiconductor die 100 and the back surface 110b of the semiconductor die 100. In some embodiments, if the shape of the semiconductor die 100 in its top view (e.g., on the X-Y plane) is considered to be a rectangular shape (e.g., a square), then the sidewall of the semiconductor die 100 includes a first side SI, a second side S2, a third side S3, and a fourth side S4, where the first side SI is opposite the third side S3 along the direction X, and the second side S2 is opposite the fourth side S4 along the direction Y. The directions X and Y are different from the direction Z, where the direction X is different from the direction Y. For example, the direction X is perpendicular to the direction Y, and the directions X and Y are perpendicular to the direction Z. As Figure 2 As shown, for example, one end of the first side SI and one end of the third side S3 are connected by the second side S2, and the other end of the first side SI and the other end of the third side S3 are connected by the fourth side S4.

[0104] It should be appreciated that in some embodiments, the semiconductor die 100 set forth herein can be referred to as a semiconductor chip or an integrated circuit (IC). In some embodiments, the semiconductor die 100 is a logic chip, such as a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), a system-on-integrated-circuit (SoIC), a microcontroller, or the like. However, the present disclosure is not limited as such; alternatively, the semiconductor die 100 can include a digital chip, an analog chip, or a mixed-signal chip, such as an application-specific integrated circuit (“ASIC”) chip, a sensor chip, a wireless and radio frequency (RF) chip, a baseband (BB) chip, a memory chip (e.g., a high bandwidth memory (HBM) die), or a voltage regulator chip. In yet other alternative embodiments, the semiconductor die 100 can be a combination chip or IC, such as a WiFi chip that includes both an RF chip and a digital chip. In some embodiments, the semiconductor die 100 is in the form of a chip-size package.

[0105] Continuing Figure 1 In some embodiments, according to Figure 8At step S2000, the semiconductor die 100 is placed over and mounted on the substrate 500. For example, the semiconductor die 100 is picked and placed on the substrate 500, and then the semiconductor die 100 is bonded to the substrate 500. The substrate 500 can be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, indium gallium phosphide, combinations thereof, and the like can also be used. In some alternative embodiments, the substrate 500 is an SOI substrate, where the SOI substrate can include a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. In other alternative embodiments, the substrate 500 is based on an insulating core such as a fiberglass reinforced resin core. One exemplary core material is fiberglass resin such as flame-retardant class 4 (FR4). Alternatives to the core material can include bismaleimide triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. In yet other alternative embodiments, the substrate 500 is a build-up film such as an Ajinomoto build-up film (ABF) or other suitable build-up layer.

[0106] In one embodiment, the substrate 500 includes active and / or passive devices (not shown) such as transistors, capacitors, resistors, combinations thereof, or the like that can be used to create the structural and functional design of the semiconductor package. The active and / or passive devices can be formed using any suitable method. However, the present disclosure is not so limited; in alternative embodiments, the substrate 500 does not substantially include active and / or passive devices.

[0107] In some embodiments, substrate 500 includes a plurality of bonding pads 510, a plurality of bonding pads 520, a plurality of metallization layers 530, and a plurality of vias (not shown) interconnecting the metallization layers 530, wherein the bonding pads 510 and 520 are electrically connected to the metallization layers 530 and the vias. The metallization layers 530 and the vias together form a functional circuit system that provides routing for substrate 500. The metallization layers 530 and the vias embedded in substrate 500 can be formed by alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper) (with vias interconnecting the conductive material layers), and can be formed by any suitable process (e.g., deposition, damascene, dual damascene, or similar processes).

[0108] The bonding pads 510 and 520 are used to provide electrical connections between the substrate 500 and external components. The bonding pads 510 and the bonding pads 520 can be respectively arranged on opposite sides of the substrate 500. In some embodiments, the bonding pads 510 are located on and distributed above the top surface 500t of the substrate 500, and the bonding pads 520 are located on and distributed above the bottom surface 500b of the substrate 500. For example, Figure 1 As shown, the top surface 500t is opposite to the bottom surface 500b along the direction Z. In some embodiments, some of the bonding pads 510 are electrically connected to the bonding pads 520 through the metallization layer 530 and the through-holes. In some embodiments, some of the bonding pads 510 are electrically connected to some other bonding pads in the bonding pads 510 through the metallization layer 530 and the through-holes. In some embodiments, some of the bonding pads 520 are electrically connected to some other bonding pads in the bonding pads 520 through the metallization layer 530 and the through-holes. The present disclosure is not limited in this regard.

[0109] In the embodiment where the vias 140 protrude from the passivation layer 130, the vias 140 of the semiconductor die 100 are connected to the bonding pads 510 of the substrate 500 through the plurality of solder regions 202 by flip chip bonding. Figure 1As shown. In some embodiments, the semiconductor die 100 is mechanically and electrically connected to the substrate 500 through the bonding pads 510, the vias 140, and the solder area 202 sandwiched therebetween. In addition, the substrate 500 is considered to be a circuit structure (e.g., an organic substrate in which a circuit system structure is embedded, such as a printed circuit board (PCB)). The solder area 202 may be a pre-solder paste. However, the present disclosure is not limited thereto; alternatively, the solder area 202 may be a pre-solder block. In some embodiments, the material of the solder area 202 may include a lead-free solder material (e.g., a Sn-Ag based material or a Sn-Ag-Cu based material) with or without additional impurities (e.g., Ni, Bi, Sb, Au, or the like). In some embodiments, an underfill (not shown) is formed on the substrate 500 to fill the gap between the semiconductor die 100 and the substrate 500 and wrap around the solder area 202 and the sidewalls of the via 140. For example, the underfill may be any acceptable material, such as a polymer, epoxy, molded underfill, or the like. In one embodiment, the underfill may be formed by underfill dispensing, a capillary flow process, or any other suitable method.

[0110] Alternatively, in embodiments where the surface of via 140 is substantially coplanar with surface 130a of passivation layer 130, semiconductor die 100 is connected to substrate 500 by hybrid bonding (involving metal-to-metal bonding and dielectric-to-dielectric bonding).

[0111] like Figure 1 and Figure 2 As shown, for example, the substrate 500 has a sidewall connecting the top surface 500t of the substrate 500 and the bottom surface 500b of the substrate 500. In some embodiments, if the shape of the substrate 500 in a top view thereof (e.g., on the XY plane) is considered to be a rectangular shape, the sidewall of the substrate 500 includes a first edge E1, a second edge E2, a third edge E3, and a fourth edge E4, wherein the first edge E1 is opposite to the third edge E3 along the direction X, and the second edge E2 is opposite to the fourth edge E4 along the direction Y. Figure 2 As shown, for example, one end of the first edge E1 and one end of the third edge E3 are connected by the second edge E2, and the other end of the first edge E1 and the other end of the third edge E3 are connected by the fourth edge E4. In some embodiments, the center line CL1 is the center line of the substrate 500 substantially parallel to the short axis of the substrate 500, and the center line CL2 is the center line of the substrate 500 substantially parallel to the long axis of the substrate 500, as shown in FIG. Figure 2In other words, the centerline CL1 extends in the direction X and intersects the long sides (e.g., the first edge E1 and the third edge E3) of the substrate 500. On the other hand, the centerline CL2 extends in the direction Y and intersects the short sides (e.g., the second edge E2 and the fourth edge E4) of the substrate 500. In the present disclosure, the direction X can be referred to as the direction of extension of the second edge E2 and the fourth edge E4, while the direction Y can be referred to as the direction of extension of the first edge E1 and the third edge E3.

[0112] In the present disclosure, the semiconductor die 100 is bonded to the substrate 500 in an offset position. For example, the semiconductor die 100 is displaced from the centerline CL2 toward the first edge E1 of the substrate 500, with the first side S1 of the semiconductor die 100 being separated from the first edge E1 by a gap G1, as shown in Figure 1 and Figure 2 In some embodiments, the first side S1 of the semiconductor die 100 is offset from the first edge E1 of the substrate 500 by a gap G1, as shown in Figure 2 In some embodiments, the first side S1 of the semiconductor die 100 is offset from the first edge E1 of the substrate 500 by a gap G1, as shown in

[0113] On the other hand, along the direction Y, the sides (e.g., the second side S2 and the fourth side S4) of the semiconductor die 100 are each separated from the edges (e.g., the second edge E2 and the fourth edge E4) of the substrate 500 by an equal distance, e.g., a gap G3. That is, the centerline CL1 is further considered a centerline of the semiconductor die 100 in the direction X because the centerline CL1 passes through the middle value of the length of the first side S1 and / or the third side S3 of the semiconductor die 100. In some embodiments, the gap G3 is greater than the gap G2 and the gap G1, and the gap G2 is greater than the gap G1, as shown in Figure 2 In alternative embodiments, the gap G3 is less than the gap G2 and the gap G1, while the gap G2 is greater than the gap G1. In further alternative embodiments, the gap G3 can be substantially equal to the gap G2 or the gap G1, and the gap G2 is greater than the gap G1. The present disclosure is not limited in this regard.

[0114] Referring to Figure 3 and Figure 4 In some embodiments, the semiconductor die 100 is bonded to the substrate 500 in an offset position according to Figure 8of step S3000, a ring structure 600A is provided, and then the ring structure 600A is bonded to the substrate 500. For example, a bottom surface 600b of the ring structure 600A is bonded to a top surface 500t of the substrate 500 by an adhesive 710, with the ring structure 600A surrounding the semiconductor die 100. In some embodiments, in a top view (e.g., X-Y plane), the ring structure 600A is in the form of a full (continuous) frame ring having an inner sidewall SW600i facing the semiconductor die 100 and an outer sidewall SW600o opposite the inner sidewall SW600i, with the outer sidewall SW600o substantially aligned with the sidewall of the substrate 500 in the direction Z. For example, as shown in Figure 3 the inner sidewall SW600i and the outer sidewall SW600o of the ring structure 600A are each substantially continuous vertical sidewalls.

[0115] In a top view, the ring structure 600A can have a ring shape corresponding to the profile of the substrate 500. In some embodiments, the ring structure 600A has a rectangular ring shape in a top view, with two opposite long sides and two opposite short sides, where a center line CL1 intersects the long sides of the ring structure 600A and a center line CL2 intersects the short sides of the ring structure 600A. For example, as shown in Figure 3 and Figure 4 the inner sidewall SW600i of the ring structure 600A includes four sides S5-S8, where (long) side S5 is opposite (long) side S7 in the direction X, and (short) side S6 is opposite (short) side S8 in the direction Y. Similarly, the outer sidewall SW600o of the ring structure 600A includes four sides S9-S12, where, for example, (long) side S9 is opposite (long) side S11 in the direction X, and (short) side S10 is opposite (short) side S12 in the direction Y.

[0116] For example, as shown in Figure 3 and Figure 4As shown, inner sidewall SW600i (e.g., side S5) of ring structure 600A is spaced apart from first side S1 of semiconductor die 100 by gap W1, inner sidewall SW600i (e.g., side S7) of ring structure 600A is spaced apart from third side S3 of semiconductor die 100 by gap W2, inner sidewall SW600i (e.g., side S6) of ring structure 600A is spaced apart from second side S2 of semiconductor die 100 by gap W6, and inner sidewall SW600i (e.g., side S8) of ring structure 600A is spaced apart from fourth side S4 of semiconductor die 100 by gap W7, wherein gap W2 is greater than gap W1, and gap W6 is substantially equal to gap W7. In other words, corresponding to the offset position of semiconductor die 100 on substrate 500, semiconductor die 100 is arranged in an eccentric manner with gap W1 in direction X relative to ring structure 600A. In this disclosure, gap W1 may be referred to as an offset position of semiconductor die 100 relative to the semiconductor package.

[0117] The annular structure 600A may have substantially the same thickness in a top view. Figure 4 , where the thickness W3 between side S5 and side S9 in the extension direction (e.g., X) of the center line CL1, the thickness W4 between side S7 and side S11 in the extension direction (e.g., X) of the center line CL1, the thickness W8 between side S6 and side S10 in the extension direction (e.g., Y) of the center line CL2, and the thickness W9 between side S8 and side S12 in the extension direction (e.g., Y) of the center line CL2 are substantially the same. However, the present disclosure is not limited to this; as long as the gap W2 is greater than the gap W1 and the gaps W6 and W7 are substantially the same, the thicknesses W3, W4, W8 and W9 may be different from or equal to each other. For example, the thickness W3 may be different from the thickness W4. In some embodiments, Figure 9 The semiconductor package 10a and Figure 5 The semiconductor package 10 is similar to the semiconductor package 10; the difference is that the ring structure 600A is replaced by a ring structure 600A', wherein the ring structure 600A' has a non-uniform thickness in a top view. In the ring structure 600A', the thickness W4' may be different from the thicknesses W3, W8, and W9. For example, Figure 9 As shown, thickness W4' is greater than thickness W3, while thicknesses W3, W8, and W9 are the same (not shown). In an alternative embodiment, thickness W4 is less than thickness W3 (not shown), while thicknesses W3, W8, and W9 are the same. Alternatively, thickness W3 may be greater than, less than, or substantially equal to thickness W4, while thicknesses W4, W8, and W9 may be the same.

[0118] In some embodiments, the material of the ring-shaped structure 600A comprises an electrically conductive material, a thermally conductive material, or an electrically and thermally conductive material. In some embodiments, the material of the ring-shaped structure 600A comprises a metal or a metal alloy, such as copper, aluminum, an alloy thereof, a combination thereof, or the like. In some embodiments, the adhesive 710 comprises an electrically conductive adhesive, a thermally conductive adhesive, or an electrically and thermally conductive adhesive. The adhesive 710 can further comprise a filler. For example, the filler comprises a metal filler or a metal alloy filler. Through the adhesive 710, the ring-shaped structure 600A is electrically connected and thermally connected to the substrate 500. As shown, in some embodiments, after the ring-shaped structure 600A is mounted onto the substrate 500, the illustrated top surface (e.g., 110b) of the semiconductor die 100 is lower than the top surface 600t of the ring-shaped structure 600 by a distance T1, where the top surface 600t is opposite to the bottom surface 600b in the direction Z. Figure 3

[0119] Referring to Figure 5 and Figure 6 , in some embodiments, according to the step S4000 of Figure 8 , the lid 800A is provided and then bonded to the ring-shaped structure 600A. For example, the bottom surface 800b of the lid 800A is bonded to the top surface 600t of the ring-shaped structure 600A through the adhesive 720, where the lid 800A, the adhesive 720, the ring-shaped structure 600A, the adhesive 710, and the substrate 500 together define a recess R1 that encloses the semiconductor die 100. In this disclosure, the recess R1 is referred to as an accommodation space for accommodating the semiconductor die 100. In some embodiments, in a top view (e.g., X-Y plane), the lid 800A is in the form of a solid block, whose sidewall is substantially aligned with the sidewall of the substrate 500 in the direction Z, as shown in Figure 5 and Figure 7 Figure 6 . That is, for example, the sidewall of the lid 800A is substantially aligned with the outer sidewall SW600o of the ring-shaped structure 600A and the sidewall of the substrate 500 in the direction Z, as shown in Figures 5 to 7 . Up to this point, the semiconductor package 10 is fabricated.

[0120] In some embodiments, the lid 800A comprises a recess R2, where the recess R2 is in spatial communication with the recess R1. For example, the recess R2 has an opening (not labeled) at the bottom surface 800b of the lid 800A, where the sidewall of the recess R2 extends into the lid 800A from the opening along the direction Z. In some embodiments, as shown in Figure 5 ​​As shown, the thickness T5 of the recess R2 is greater than 0 and less than or substantially equal to the thickness T800 of the cap 800A when measured along the direction Z. For example, the thickness T5 of the recess R2 is greater than 0 and less than or substantially equal to half of the thickness T800 of the cap 800A. In other words, the recess R2 does not penetrate through the cap 800A.

[0121] In some embodiments, the recess R2 overlaps with the offset location (e.g., the gap W1) in a vertical projection on the substrate 500 along the direction Z, as shown in Figure 5 and Figure 6 As shown, in some embodiments, the recess R2 extends from the first side S1 toward the sidewall SW800 of the cap 800A, where a portion of the sidewall of the recess R2 is substantially aligned with the first side S1 of the semiconductor die 100 and a portion of the sidewall of the recess R2 is substantially aligned with the side S5 of the ring structure 600A. That is, the positioning of the recess R2 is adjacent to and between the positioning of the semiconductor die 100 and the positioning of the ring structure 600A in a vertical projection along the direction Z. For example, in a top view of Figure 6 As shown, the length L2 of the recess R2 is less than the length L1 of the cap 800A and the width W5 is greater than 0. In some embodiments, the width W5 is substantially equal to the offset location (e.g., the gap W1), as shown in Figure 5 and Figure 6 However, the present disclosure is not limited thereto; alternatively, the width W5 can be greater than 0 and less than the offset location (e.g., the gap W1). Or alternatively, the width W5 can be greater than the offset location (e.g., the gap W1). In other words, for example, the recess R2 is located between the sidewall (e.g., the first side S1) of the semiconductor die 100 and the sidewall SW800 of the cap 800A to overlap with the gap W1, as shown in Figures 5 to 7 As such, the recess R2 allows the cap 800A to have more flexibility in terms of deformation capability at the location of the recess R2, thereby avoiding, suppressing, or reducing the stress concentration and / or delamination issues at the adhesive due to CTE mismatch and / or modulus mismatch between two components (e.g., between the cap 800A and the ring structure 600A and / or between the ring structure 600A and the substrate 500). From an experimental perspective, the stress at the adhesive 720 is reduced by about 13% to 20% compared to a conventional cap without a recess corresponding to the offset location.

[0122] The recess R2 can be formed in the cap 800A by, but not limited to, milling machining, laser technology, etching technology, a combination thereof, and / or the like; the present disclosure is not limited thereto. In some embodiments, the recess R2 is formed in the cap 800A by milling machining, as shown in Figure 6As shown in the top view, the shape of the recess R2 is rectangular; however, the present disclosure is not limited thereto. Alternatively, in the top view, the shape of the recess R2 may be elliptical, oval, quadrilateral, octagonal or any suitable polygon.

[0123] The cover 800A may be referred to as a heat dissipation element of the semiconductor package 10. Alternatively, the cover 800A, the ring structure 600A, and the adhesive 720 therebetween may be collectively referred to as a heat dissipation element of the semiconductor package 10. Due to this heat dissipation element, heat dissipation of the semiconductor die 100 in the semiconductor package 10 is improved. In addition, a thermal interface material may be applied to the semiconductor die 100 to facilitate heat dissipation of the semiconductor package 10. Figure 5 and Figure 7 As shown in the semiconductor package 10 of FIG. 1 , a thermal interface material 730 is positioned between the backside surface 110 b of the semiconductor die 100 and the bottom surface 800 b of the lid 800A to thermally couple the semiconductor die 100 to the lid 800A, further facilitating heat dissipation from the semiconductor die 100 to the lid 800A. The thermal interface material 730 may include any suitable thermally conductive material, such as a polymer having a good thermal conductivity of about 3 W / (m·K) to about 10 W / (m·K) or greater than 10 W / (m·K), and may be formed on the backside surface 110 b of the semiconductor die 100 by liquid dispensing. In some embodiments, the thermal interface material 730 is a thin film thermal interface material, such as a graphene sheet, a carbon nanotube sheet, or the like, and is formed on the backside surface 110 b of the semiconductor die 100 by lamination or a similar process. The present disclosure does not particularly limit the thickness of the thermal interface material 730 , as long as the thickness of the thermal interface material 730 is sufficient to sufficiently dissipate heat from the semiconductor die 100 to the lid 800A.

[0124] However, the present disclosure is not limited thereto; alternatively, the thermal interface material 730 may be omitted. In some embodiments, Figure 10 The semiconductor package 10b and Figure 5 The semiconductor package 10 is similar to the semiconductor package 10 of FIG. 1 ; except that the thermal interface material 730 is removed, wherein the cover 800A is separated from (the backside surface 110 b of) the semiconductor die 100 by a gap (eg, an air gap).

[0125] In some embodiments, the material of the cap 800A comprises an electrically conductive material, a thermally conductive material, or an electrically and thermally conductive material. In some embodiments, the material of the cap 800A comprises a metal or a metal alloy, such as copper, aluminum, an alloy thereof, a combination thereof, or the like. In some embodiments, the adhesive 720 comprises an electrically conductive adhesive, a thermally conductive adhesive, or an electrically and thermally conductive adhesive. The adhesive 720 can further comprise a filler. For example, the filler comprises a metal filler or a metal alloy filler. The material of the adhesive 710 can be the same as the material of the adhesive 720. Alternatively, the material of the adhesive 710 can be different from the material of the adhesive 720. Furthermore, the material of the ring-shaped structure 600A can be the same as the material of the cap 800A. Alternatively, the material of the ring-shaped structure 600A can be different from the material of the cap 800A. Through the adhesive 720, the cap 800A is electrically and thermally connected to the ring-shaped structure 600A, and further electrically and thermally connected to the substrate 500 through the ring-shaped structure 600A and the adhesive 710. In some embodiments, the cap 800A, the adhesive 720, the ring-shaped structure 600A, and the adhesive 710 together constitute an electromagnetic interference (EMI) shielding structure (which is electrically connected to the substrate 500) of the semiconductor die 100. Due to the presence of such an EMI shielding structure, the impact caused by electromagnetic waves generated by other electronic elements located outside the semiconductor package 10 can be suppressed, thereby improving the reliability and performance of the semiconductor package 10.

[0126] As shown in the semiconductor package 10 of Figure 5 In some embodiments, the thickness T600 of the ring-shaped structure 600A is greater than the thickness T800 of the cap 800A when measured along the direction Z. However, the present disclosure is not limited thereto. For example, the thickness T600 of the ring-shaped structure 600A can be substantially equal to the thickness T800 of the cap 800A when measured along the direction Z. Figure 11 The semiconductor package 10c is similar to the semiconductor package 10 of Figure 5 The semiconductor package 10c is similar to the semiconductor package 10 of

[0127] In alternative embodiments, additional semiconductor devices and / or additional electrically conductive terminals can be employed. For example, Figure 12 The semiconductor package 10d is similar to the semiconductor package 10 of Figure 5 The semiconductor package 10d is similar to the semiconductor package 10 of Figure 12As shown in semiconductor package 10d, semiconductor devices 310 are disposed on the illustrated top surface 500t of substrate 500 along center line CL1 and adjacent semiconductor die 100, semiconductor devices 320 are disposed on the illustrated bottom surface 500b of substrate 500, and conductive terminals 400 are disposed on the illustrated bottom surface 500b of substrate 500 and adjacent semiconductor devices 320. In some embodiments, some of conductive terminals 400 are electrically connected to semiconductor die 100 through substrate 500, some of conductive terminals 400 are electrically connected to semiconductor devices 310, and some of conductive terminals 400 are electrically connected to semiconductor devices 320.

[0128] Semiconductor devices 310, 320 can be referred to as surface devices for providing additional functionality or programming to semiconductor die 100. For example, semiconductor devices 310, 320 include surface mount devices (SMDs) or integrated passive devices (IPDs) including passive devices such as resistors, inductors, capacitors, jumpers, combinations thereof, or the like, which are desired to be connected to and utilized in conjunction with semiconductor die 100. As shown, for example, semiconductor devices 310, 320 are electrically connected to semiconductor die 100 through bond pads 510, 520, metallization layer 530, and vias, solder regions 202, and vias 140. The number of semiconductor devices 310 and the number of semiconductor devices 320 are not limited to the illustrated embodiments and can be selected based on requirements and design layout. Figure 12

[0129] ​The conductive terminals 400 can be used to physically and electrically connect the substrate 500 to other devices, packages, connection assemblies, and the like. In this disclosure, the conductive terminals 400 are referred to as conductive connections of the substrate 500 (serving as conductive input / output terminals of the semiconductor package 10d) for providing physical and / or electrical connections to external components. For example, the conductive terminals 400 and the semiconductor die 100 are located on two opposite sides of the substrate 500, respectively, with some of the conductive terminals 400 electrically connected to the semiconductor die 100 through the bond pads 520, the metallization layer 530, and the vias, the bond pads 510, the solder regions 202, and the vias 140. The number of the conductive terminals 400 is not limited to the described embodiment and can be selected based on requirements and design layout. The conductive terminals 400 can be micro bumps, metal pillars, ENEPIG-formed bumps, C4 bumps (e.g., which can have, but are not limited to, a size of about 80 pm), BGA bumps or balls (e.g., which can have, but are not limited to, a size of about 400 pm), solder balls, or the like. The present disclosure is not limited thereto. When solder is used, the solder can include eutectic solder or non-eutectic solder. The solder can include lead or be lead-free, and can include Sn-Ag, Sn-Cu, Sn-Ag-Cu, or the like.

[0130] The present disclosure is not limited thereto. In one embodiment, only the semiconductor devices 310 are formed on the substrate 500, where the number of the semiconductor devices 310 can be one or more than one. In an alternative embodiment, only the semiconductor devices 320 are formed on the substrate 500, where the number of the semiconductor devices 320 can be one or more than one. In yet another alternative embodiment, only the conductive terminals 400 are formed on the substrate 500.

[0131] In alternative embodiments, additional semiconductor dies can be employed. For example, Figure 13 and Figure 14 The semiconductor package 10e is similar to the semiconductor package 10 of Figure 5 ; except that the semiconductor package 10e further includes a plurality of semiconductor dies 900. As shown in the semiconductor package 10e of Figure 13 and Figure 14 The semiconductor dies 900 are disposed on the illustrated top surface 500t of the substrate 500 along the center line CL2 and adjacent to the semiconductor die 100. For example, the semiconductor dies 900 are electrically connected to the semiconductor die 100 through the substrate 500 and the solder regions 202 and 204. As Figure 14As shown, for example, the semiconductor die 900 is located at two opposite sides of the semiconductor die 100 in a symmetric arrangement.

[0132] In some embodiments, the semiconductor die 900 is bonded to the substrate 500 through the solder region 204. For example, the semiconductor die 900 is picked and placed on the substrate 500 and bonded to the substrate 500 through flip-chip bonding. The formation and material of the solder region 204 are similar or substantially the same as the formation and material of the solder region 202, and thus are not repeated herein. In some embodiments, an underfill (not shown) is formed on the substrate 500 to fill the gap between the semiconductor die 900 and the substrate 500 and to wrap the sidewalls of the solder region 204 and the via 920. For example, the underfill can be any acceptable material, such as a polymer, an epoxy, a molded underfill, or the like. In one embodiment, the underfill can be formed through an underfill dispensing, a capillary flow process, or any other suitable method.

[0133] However, the present disclosure is not limited thereto; alternatively, similar to the semiconductor die 100, the semiconductor die 900 can be bonded to the substrate 500 through hybrid bonding. By using hybrid bonding, the underfill can be omitted.

[0134] In some embodiments, the semiconductor die 900 individually set forth herein can be referred to as a semiconductor chip or an integrated circuit (IC) having a plurality of vias 920, where the vias 920 act as conductive terminals of the semiconductor die 900 for electrical connection to external components. In some embodiments, the semiconductor die 900 are each a memory chip or device, such as a dynamic random-access memory (DRAM) die, a static random-access memory (SRAM) die, a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, or the like. In the present disclosure, the type of the semiconductor die 100 is different from the type of the semiconductor die 900. As Figure 13 As shown, for example, four semiconductor dies 900 are shown for illustrative purposes; however, the number of the semiconductor dies 900 is not limited to the number depicted in the present disclosure and can be selected and specified based on requirements and design layout.

[0135] It should be understood that semiconductor packages 10a through 10e may also employ modifications of semiconductor package 10. For example, semiconductor packages 10b, 10c, 10d, and / or 10e may employ modifications of semiconductor package 10 as shown in semiconductor package 10a. For example, semiconductor packages 10a, 10c, 10d, and / or 10e may employ modifications of semiconductor package 10 as shown in semiconductor package 10b. For example, semiconductor packages 10a, 10b, 10d, and / or 10e may employ modifications of semiconductor package 10 as shown in semiconductor package 10c. For example, semiconductor packages 10a, 10b, 10c, and / or 10e may employ modifications of semiconductor package 10 as shown in semiconductor package 10d. For example, semiconductor packages 10a, 10b, 10c, and / or 10d may employ modifications to semiconductor package 10 as shown in semiconductor package 10e. Figures 9 to 14 , so for the sake of brevity, it will not be repeated here.

[0136] Figure 15 A schematic cross-sectional view of a semiconductor package 20 according to some embodiments of the present disclosure is shown. Figure 16 Shown in Figure 15 A schematic plan view of the relative positions of components included in a semiconductor package shown in FIG. Figure 15 It is along Figure 16 A cross-sectional view taken along the center line CL1 shown in FIG. Figures 17 to 20 A cross-sectional view along a center line CL1 of a semiconductor package according to some alternative embodiments of the present disclosure is shown. Figure 21 Schematic plan views showing the relative positions of components included in a semiconductor package according to some alternative embodiments of the present disclosure. Elements similar or substantially identical to those described above will use the same reference numerals, and certain details or descriptions of the same elements (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated herein. In some embodiments, Figures 15 to 16 The semiconductor package 20 and Figures 5 to 7 The semiconductor package 20 is similar to the semiconductor package 10; except that the semiconductor package 20 includes a ring structure 600B and a cover 800B instead of the ring structure 600A and the cover 800A.

[0137] Reference Figure 15 and Figure 16In some embodiments, the semiconductor package 20 includes a substrate 500, a semiconductor die 100 disposed on and electrically connected to the substrate 500, a ring structure 600B, and a lid 800B. The semiconductor package 20 also includes an adhesive 710 that bonds the ring structure 600B to the substrate 500, and an adhesive 720 that bonds the lid 800B to the ring structure 600B. By way of example, the ring structure 600B is electrically and thermally connected to the substrate 500 by the adhesive 710. The lid 800B is electrically and thermally connected to the ring structure 600B by the adhesive 720, where the lid 800B is electrically and thermally connected to the substrate 500 by the ring structure 600B and the adhesives 710, 720. The lid 800B can be referred to as a heat dissipation element of the semiconductor package 20. Alternatively, the lid 800B, the ring structure 600B, and the adhesive 720 located therebetween can be referred to together as a heat dissipation element of the semiconductor package 20. Due to the presence of such a heat dissipation element, heat dissipation of the semiconductor die 100 in the semiconductor package 20 is improved. The formation and materials of each of the semiconductor die 100, the substrate 500, and the adhesives 710, 720 have been set forth in Figure 15 , and thus are not repeated herein for the sake of brevity.

[0138] The semiconductor package 20 also includes a thermal interface material 730 that bonds the semiconductor die 100 to the lid 800B. By the thermal interface material 730, thermal coupling between the semiconductor die 100 and the lid 800B is enhanced, which further helps to dissipate heat from the semiconductor die 100 to the lid 800B. The formation and materials of the thermal interface material 730 have been set forth in Figure 15 , and thus are not repeated herein for the sake of brevity. However, the present disclosure is not limited thereto. Alternatively, the thermal interface material 730 can be omitted, as shown in the semiconductor package 20a in Figure 16 .

[0139] In some embodiments, the lid 800B, the adhesive 720, the ring structure 600B, and the adhesive 710 together constitute an EMI shielding structure of the semiconductor die 100 (which is electrically connected to the substrate 500). Due to the presence of the EMI shielding structure, impact caused by electromagnetic waves generated by other electronic elements located outside of the semiconductor package 20 can be suppressed, thereby improving the reliability and performance of the semiconductor package 20.

[0140] In some embodiments, in a top view (e.g., XY plane), the ring structure 600B is in the form of a full (continuous) frame ring having an inner sidewall SW 600i facing the sidewall of the semiconductor die 100 and an outer sidewall SW 600o opposite the inner sidewall SW 600i, wherein the outer sidewall SW 600o is substantially aligned with the sidewall of the substrate 500 in the direction Z. In some embodiments, the ring structure 600B has a rectangular ring shape in a top view, the rectangular ring shape having two opposing long sides and two opposing short sides. In some embodiments, the inner sidewall SW 600i of the ring structure 600B includes side S5′, side S6, side S7, and side S8, and the outer sidewall SW 600o of the ring structure 600B includes side S9, side S10, side S11, and side S12. In some embodiments, the annular structure 600B is similar to the annular structure 600A, wherein the sides S6, S7, and S8 of the inner sidewall SW600i of the annular structure 600B and the sides S9, S10, S11, and S12 of the outer sidewall SW600o of the annular structure 600B are each substantially continuous vertical surfaces; except that the side S5' of the inner sidewall SW600i is a non-vertical surface. In other words, the side S5' of the inner sidewall SW600i can be a non-planar surface. For example, Figure 15 As shown, side S5' includes a plane surface S5a and a plane surface S5b connected to plane surface S5a, wherein plane surface S5a is substantially parallel to side S9, and plane surface S5b is not parallel to plane surface S5a. Figure 16 As shown, there is an angle θ between the extension plane of the planar surface S5a (shown as a dotted line) and the planar surface S5b. In some embodiments, the angle θ is an acute angle. In some embodiments, the angle θ is approximately in the range of 0° to 90°. For example, the planar surface S5b is an inclined surface, such as Figure 15 In some embodiments, the outer sidewall SW600o of the ring structure 600B is a substantially continuous vertical sidewall.

[0141] like Figure 16 and Figure 16 As shown, in some embodiments, the cover 800B includes a recess R2', wherein the recess R2' is spatially connected to the recess R1. For example, the recess R2' has an opening (not marked) at the bottom surface 800b of the cover 800B, wherein the sidewall of the recess R2' extends from the opening into the cover 800B along the direction Z. In some embodiments, as shown in FIG. Figure 15 and Figure 16 As shown, when measured along direction Z, the thickness T5 of recess R2' is greater than 0 and less than or substantially equal to the thickness T800 of cover 800B. For example, the thickness T5 of recess R2' is greater than 0 and less than or substantially equal to half the thickness T800 of cover 800B. In other words, recess R2' does not penetrate through cover 800B.

[0142] In some embodiments, the recess R2’ overlaps with the offset location (e.g., the gap W1) in a vertical projection on the substrate 500 along the direction Z, as shown in Figure 16 and Figure 18 In some embodiments, the recess R2’ extends from the first side S1 toward the sidewall SW800 of the lid 800B, where a portion of the sidewall of the recess R2’ is substantially aligned with the first side S1 of the semiconductor die 100, and the recess R2’ partially overlaps with the ring structure 600B. That is, in a vertical projection along the direction Z, the positioning location of the recess R2’ is adjacent to the positioning location of the semiconductor die 100 and partially within (e.g., overlaps with) the positioning location of the ring structure 600B. For example, in a top view of Figure 15 , the length L2 of the recess R2’ is less than the length L1 of the lid 800B, and the width W5’ is greater than 0. In some embodiments, the width W5’ is greater than the offset location (e.g., the gap W1), as shown in Figure 18 and Figure 15 With such a non-planar surface (e.g., the side S5’) included in the inner sidewall SW600i of the ring structure 600B, the width W5’ of the recess R2’ formed in the lid 800B is greater than the width W5 of the recess R2 formed in the lid 800A. Due to the presence of such a recess R2’, further allows the lid 800B to have greater flexibility in terms of deformation capability at the location of the recess R2’, thereby avoiding, suppressing, or reducing stress concentration and / or delamination issues at the adhesive due to CTE mismatch and / or modulus mismatch between two components (e.g., between the lid 800B and the ring structure 600B and / or the ring structure 600B and the substrate 500). From an experimental perspective, the stress at the adhesive 720 is reduced by about 13% to 20% compared to a conventional lid without a recess corresponding to the offset location.

[0143] The ring structure 600B can have substantially the same thickness in a top view. For example, as shown in a top view of Figure 19 , where the thicknesses W3, W4, W8, and W9 are substantially the same. However, the present disclosure is not limited thereto; as long as the gap W2 is greater than the gap W1 and the gaps W6 and W7 are substantially the same, the thicknesses W3, W4, W8, and W9 can be different from or equal to each other. For example, the thickness W3 can be different from the thickness W4. In some embodiments, Figure 15 the semiconductor package 20b of Figure 20The semiconductor package 20 is similar to the semiconductor package 20; the difference is that the ring structure 600B is replaced by a ring structure 600B', wherein the ring structure 600B' has a non-uniform thickness in a top view. In the ring structure 600B', the thickness W4' can be different from the thicknesses W3, W8, and W9. For example, the thickness W4' is greater than the thickness W3, such as Figure 15 As shown, thicknesses W3, W8, and W9 are the same (not shown). In an alternative embodiment, thickness W4' is less than thickness W3 (not shown), and thicknesses W3, W8, and W9 are the same. Alternatively, thickness W3 may be greater than, less than, or substantially equal to thickness W4', and thicknesses W4', W8, and W9 may be the same.

[0144] The thickness T600 of the annular structure 600B may be greater than, less than, or substantially equal to the thickness T800 of the cover 800B. Figure 20 In the semiconductor package 20, when measured along the direction Z, the thickness T600 of the ring structure 600B is greater than the thickness T800 of the cover 800B. However, the present disclosure is not limited thereto. For example, Figure 12 The semiconductor package 20c and Figure 21 The embodiment of the present invention is similar to the semiconductor package 20 of FIG. 1 , except that, when measured along the direction Z, the thickness T600 of the ring structure 600B is substantially equal to the thickness T800 of the cover 800B. Alternatively, when measured along the direction Z, the thickness T600 of the ring structure 600B may be less than the thickness T800 of the cover 800B.

[0145] In alternative embodiments, additional semiconductor devices and / or additional conductive terminals may be employed. For example, Figure 15 The semiconductor package 20d and Figure 21 The difference is that the semiconductor package 20d further includes semiconductor devices 310, 320 and a plurality of conductive terminals 400. Figure 21semiconductor device 310 is disposed on the illustrated top surface 500t of the substrate 500 along the centerline CL1 and adjacent to the semiconductor die 100, the semiconductor device 320 is disposed on the illustrated bottom surface 500b of the substrate 500, and the conductive terminals 400 are disposed on the illustrated bottom surface 500b of the substrate 500 and adjacent to the semiconductor device 320. In some embodiments, some of the conductive terminals 400 are electrically connected to the semiconductor die 100 through the substrate 500, some of the conductive terminals 400 are electrically connected to the semiconductor device 310, and some of the conductive terminals 400 are electrically connected to the semiconductor device 320. In some embodiments, the semiconductor device 310 is electrically connected to the semiconductor die 100 through the substrate 500, and the semiconductor device 320 is electrically connected to the semiconductor die 100 through the substrate 500. In some embodiments, the semiconductor device 310 is electrically connected to the semiconductor device 320 through the substrate 500. Details, formation, and materials of each of the semiconductor devices 310, 320, and the conductive terminals 400 have been set forth in Figure 13 and thus are not repeated herein for the sake of brevity.

[0146] In alternative embodiments, additional semiconductor dies can be employed. For example, Figure 14 semiconductor package 20e is similar to the semiconductor package 20 of Figures 19 to 21 ; except that the semiconductor package 20e further includes a plurality of semiconductor dies 900. As illustrated in the semiconductor package 20e of Figure 22 In some embodiments, the semiconductor dies 900 are disposed on the illustrated top surface 500t of the substrate 500 along the centerline CL2 and adjacent to the semiconductor die 100. For example, the semiconductor dies 900 are electrically connected to the semiconductor die 100 through the substrate 500. As illustrated in Figure 23 , for example, the semiconductor dies 900 are located at two opposite sides of the semiconductor die 100 in a symmetric arrangement. Details, formation, and materials of the semiconductor dies 900 have been set forth in Figure 22 and Figure 22 and thus are not repeated herein for the sake of brevity.

[0147] It should be understood that semiconductor packages 20a-20e can also employ modifications to semiconductor package 20. For example, semiconductor packages 20b, 20c, 20d, and / or 20e can employ modifications to semiconductor package 20 as shown in semiconductor package 20a. For example, semiconductor packages 20a, 20c, 20d, and / or 20e can employ modifications to semiconductor package 20 as shown in semiconductor package 20b. For example, semiconductor packages 20a, 20b, 20d, and / or 20e can employ modifications to semiconductor package 20 as shown in semiconductor package 20c. For example, semiconductor packages 20a, 20b, 20c, and / or 20e can employ modifications to semiconductor package 20 as shown in semiconductor package 20d. For example, semiconductor packages 20a, 20b, 20c, and / or 20d can employ modifications to semiconductor package 20 as shown in semiconductor package 20e. Since details of the modifications to semiconductor package 20 are set forth in Figure 23 , for the sake of brevity, they will not be repeated here.

[0148] Figure 24 A schematic cross-sectional view of a semiconductor package 30 according to some embodiments of the present disclosure is shown. Figures 22 to 23 A schematic plan view showing the relative positions of components included in the semiconductor package illustrated in Figures 5 to 7 Figure 22 is a cross-sectional view taken along centerline CL1 illustrated in Figure 23 Figure 22 A schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present disclosure is shown. Elements similar or substantially identical to those described above will use the same reference numbers, and certain details or descriptions of identical elements (e.g., formation and materials) and their relationships (e.g., relative positioning configurations and electrical connections) will not be repeated here. In some embodiments, Figure 23 Semiconductor package 30 of Figures 9 to 14 is similar to semiconductor package 10 of

[0149] As Figure 24 and Figure 24 ​​As shown, in some embodiments, the ring-shaped structure 600C has a top-down view in the form of a full (continuous) frame ring with an inner sidewall SW600i facing the sidewall of the semiconductor die 100 and an outer sidewall SW600o opposite the inner sidewall SW600i, where the outer sidewall SW600o is offset from the sidewall of the substrate 500. For example, a portion P1 of the ring-shaped structure 600C and a portion P2 of the cap 800C protrude outwardly from the sidewall (e.g., the first edge E1) of the substrate 500 with a gap G4, as shown in Figure 25 and Figure 26 As shown in the present disclosure, the portion P1 of the ring-shaped structure 600C can be referred to as an overhang (or protrusion) portion of the ring-shaped structure 600C that overhangs over the first edge E1 of the substrate 500, and the portion P2 of the cap 800C can be referred to as an overhang (or protrusion) portion of the cap 800C that overhangs over the first edge E1 of the substrate 500. In other words, for example, the outer sidewall SW600o (e.g., side S9) of the ring-shaped structure 600C is offset from the sidewall (e.g., the first edge E1) of the substrate 500 with a gap G4. In some embodiments, in a top-down view, the outer sidewall SW600o of the ring-shaped structure 600C is substantially aligned with the sidewall SW800 of the cap 800C. Due to the overhang (or protrusion) portion (e.g., the portion P1 and the portion P2), the adhesion between the two components (e.g., between the ring-shaped structure 600C and the cap 800C) can be enhanced as the contact area therebetween is increased.

[0150] It should be appreciated that the semiconductor package 30 can also employ modifications to the semiconductor package 10. Since the details of the modifications to the semiconductor package 10 are set forth in Figure 25 , for brevity, they will not be repeated. For example, the thermal interface material 730 can be omitted, see the semiconductor package 30a of Figure 25 . For example, the cap 800C is separated from the semiconductor die 100 (of the backside surface 110b) with a gap, e.g., an air gap, as shown in Figure 26 .

[0151] Figure 27 shows a schematic cross-sectional view of a semiconductor package 40 according to some embodiments of the present disclosure. Figures 25 to 26 shows a schematic plan view of the relative positions of the components included in the semiconductor package illustrated in Figures 15 to 16 , wherein Figure 25 is a cross-sectional view taken along the centerline CL1 illustrated in Figure 26 . Figure 25A schematic cross-sectional view of a semiconductor package according to some alternative embodiments of the present disclosure is shown. Elements similar or substantially identical to those described above will use the same reference numbers, and certain details or descriptions of identical elements (e.g., formation and materials) and their relationships (e.g., relative positioning configurations and electrical connections) will not be repeated herein. In some embodiments, Figure 26 semiconductor package 40 is similar to Figures 17 to 21 semiconductor package 20; the difference is that semiconductor package 40 includes a ring structure 600D and a cap 800D instead of ring structure 600B and cap 800C.

[0152] As shown in Figure 27 and Figure 27 , in some embodiments, ring structure 600D has a top-down view in the form of a full (continuous) frame ring with an inner sidewall SW600i facing the sidewall of semiconductor die 100 and an outer sidewall SW600o opposite the inner sidewall SW600i, where the outer sidewall SW600o is offset from the sidewall of substrate 500. For example, a portion P1 of ring structure 600D and a portion P2 of cap 800D protrude outwardly from the sidewall (e.g., first edge E1) of substrate 500 with a gap G4, as shown in Figure 28 and Figure 28 . In the present disclosure, portion P1 of ring structure 600D can be referred to as a cantilevered (or protruding) portion of ring structure 600D that cantilevers over the first edge E1 of substrate 500, and portion P2 of cap 800D can be referred to as a cantilevered (or protruding) portion of cap 800D that cantilevers over the first edge E1 of substrate 500. In other words, for example, the outer sidewall SW600o (e.g., side S9) of ring structure 600D is offset from the sidewall (e.g., first edge E1) of substrate 500 with a gap G4. In some embodiments, in a top-down view, the outer sidewall SW600o of ring structure 600D is substantially aligned with the sidewall SW800 of cap 800D. Due to the presence of the cantilevered (or protruding) portions (e.g., portion P1 and portion P2), the adhesion between the two components (e.g., between ring structure 600D and cap 800D) can be enhanced as the contact area between them increases.

[0153] It should be understood that semiconductor package 40 can also employ modifications to semiconductor package 20. Since the details of the modifications to semiconductor package 20 are set forth in Figure 12 , for brevity, they will not be repeated here. For example, thermal interface material 730 can be omitted, see Figure 20 semiconductor package 40a. For example, cap 800D is separated from (the backside surface 110b of) semiconductor die 100 with a gap, e.g., an air gap, as shown in ​ .

[0154] ​ A schematic cross-sectional view of a semiconductor package is shown in accordance with some embodiments of the present disclosure. For ease of understanding, the same elements are indicated by the same reference numbers, and are not described again herein. Referring to ​ In some embodiments, an assembly assembly SC is provided that includes a first component Cl and a second component C2 disposed above the first component Cl. The first component Cl can be or include a circuit structure, such as a motherboard, a package substrate, another printed circuit board (PCB), a printed wiring board, an interposer, and / or other carrier capable of carrying integrated circuits. In some embodiments, the second component C2 mounted on the first component Cl is similar to one of the semiconductor packages 10, 10a-10e, 20, 20a-20e, 30, 30a, 40, 40a and modifications thereof described above. For example, one or more semiconductor packages (e.g., 10, 10a-10e, 20, 20a-20e, 30, 30a, 40, 40a, modifications thereof) can be electrically coupled to the first component Cl through a plurality of terminals CT. The terminals CT can be electrically conductive terminals 400 as described above and ​ and ​ The electrically conductive terminals 400 described above.

[0155] In some embodiments, an underfill layer UF is formed between the gap between the first component Cl and the second component C2 to cover the terminals CT at least laterally. Alternatively, the underfill layer UF is omitted. For example, the underfill layer UF can be any acceptable material, such as a polymer, an epoxy, a molded underfill, or the like. In one embodiment, the underfill layer can be formed by an underfill dispensing, a capillary flow process, or any other suitable method. With the presence of the underfill layer UF, the joint strength between the first component Cl and the second component C2 is enhanced.

[0156] According to some embodiments, a semiconductor package includes a substrate, a semiconductor die, an annular structure, and a cap. The semiconductor die is disposed on the substrate. The annular structure is disposed on the substrate and surrounds the semiconductor die, wherein a first side of the semiconductor die is separated from an inner sidewall of the annular structure by a first gap, and a second side of the semiconductor die is separated from the inner sidewall of the annular structure by a second gap. The first side is opposite to the second side, and the first gap is smaller than the second gap. The cap is disposed on the annular structure and has a recess formed therein, and the recess overlaps the first gap in a stacking direction of the annular structure and the cap.

[0157] According to some embodiments, in the semiconductor package, a thickness of the recess is less than a thickness of the cap. According to some embodiments, in the semiconductor package, the annular structure is in the form of a rectangular ring, wherein: the first gap is a shortest distance between the first side of the semiconductor die and the inner sidewall of the annular structure measured on a minor axis of the annular structure, and the second gap is a shortest distance between the second side of the semiconductor die and the inner sidewall of the annular structure measured on the minor axis of the annular structure. According to some embodiments, in the semiconductor package, the annular structure is in the form of a rectangular ring, and the semiconductor package further comprises: one or more first semiconductor devices disposed on the substrate and electrically connected to the semiconductor die, wherein the one or more first semiconductor devices are located within the annular structure and disposed adjacent to the semiconductor die along a major axis of the annular structure. According to some embodiments, in the semiconductor package, the annular structure is in the form of a rectangular ring, and the semiconductor package further comprises: a plurality of second semiconductor devices disposed on the substrate and electrically connected to the semiconductor die, wherein: the plurality of second semiconductor devices are located within the annular structure and disposed adjacent to the semiconductor die along a minor axis of the annular structure; the plurality of second semiconductor devices are located on a side of the substrate opposite the annular structure; or a first group of the plurality of second semiconductor devices are located within the annular structure and disposed adjacent to the semiconductor die along a minor axis of the annular structure, and a second group of the plurality of second semiconductor devices are located on a side of the substrate opposite the annular structure. According to some embodiments, the semiconductor package further comprises: a thermal interface material located between the cap and the semiconductor die, wherein the cap is thermally coupled and connected to the semiconductor die through the thermal interface material. According to some embodiments, in the semiconductor package, the cap is spaced apart from the semiconductor die by an air gap. According to some embodiments, in the semiconductor package, the annular structure comprises an outer sidewall opposite the inner sidewall, and the outer sidewall is substantially aligned with a sidewall of the cap and a sidewall of the substrate. According to some embodiments, in the semiconductor package, the annular structure comprises an outer sidewall opposite the inner sidewall, and the outer sidewall is substantially aligned with a sidewall of the cap and offset from a sidewall of the substrate. According to some embodiments, in the semiconductor package, the inner sidewall of the annular structure comprises a substantially vertical sidewall. According to some embodiments, in the semiconductor package, a portion of the inner sidewall of the annular structure further comprises an inclined sidewall, wherein the inclined sidewall is located between the substantially vertical sidewall and the recess formed in the cap in the stacking direction.

[0158] According to some embodiments, a semiconductor package includes a substrate, a semiconductor die, and an electromagnetic interference shielding structure. The semiconductor die is disposed on the substrate in an offset position toward an edge of the substrate. The electromagnetic interference shielding structure is disposed on the substrate and electrically connected to the substrate, wherein the semiconductor die is located in a space defined by the substrate and the electromagnetic interference shielding structure, and a recess formed in the electromagnetic interference shielding structure corresponds to the offset position.

[0159] According to some embodiments, in the semiconductor package, the electromagnetic interference shielding structure includes: a reinforcement ring disposed on the substrate and surrounding the semiconductor die; a first conductive adhesive located between the reinforcement ring and the substrate and bonding the reinforcement ring to the substrate; a cover disposed on the reinforcement ring and having the recess formed therein, the recess corresponding to the offset position; and a second conductive adhesive located between the cover and the reinforcement ring and bonding the cover to the reinforcement ring. According to some embodiments, the semiconductor package further includes: a base substrate bonded to the substrate via a plurality of conductive terminals, wherein the substrate is located between the semiconductor die and the base substrate and electrically connected to the semiconductor die and the base substrate. According to some embodiments, in the semiconductor package, in a vertical projection onto the substrate along the stacking direction of the electromagnetic interference shielding structure and the substrate, the location of the recess is adjacent to and surrounded by the location of the reinforcement ring. According to some embodiments, in the semiconductor package, in a vertical projection onto the substrate along the stacking direction of the electromagnetic interference shielding structure and the substrate, the location of the recess overlaps with the location of the reinforcement ring.

[0160] According to some embodiments, a method for manufacturing a semiconductor package includes the following steps: providing a semiconductor die; mounting the semiconductor die to a substrate; bonding an annular structure to the substrate to surround the semiconductor die, a first side of the semiconductor die being separated from an inner sidewall of the annular structure by a first gap, and a second side of the semiconductor die being separated from the inner sidewall of the annular structure by a second gap, wherein the first side is opposite to the second side, and the first gap is smaller than the second gap; and bonding a cover to the annular structure to form an accommodating space with the annular structure and the substrate, the semiconductor die being located in the accommodating space, and the cover including a recess formed therein, wherein the recess is spatially connected to the accommodating space and overlaps with the first gap in a stacking direction of the annular structure and the cover.

[0161] According to some embodiments, in the method, before bonding the ring-shaped structure to the substrate, further comprising at least one of: mounting a plurality of first semiconductor devices on the substrate and adjacent to two opposite sides of the semiconductor die in an extension direction of the first side of the semiconductor die; mounting at least one second semiconductor device on the substrate and adjacent to the semiconductor die in a direction perpendicular to the extension direction of the first side of the semiconductor die; and mounting at least one third semiconductor device on a side of the substrate opposite to the side on which the semiconductor die is disposed. According to some embodiments, in the method, bonding the ring-shaped structure on the substrate comprises bonding the ring-shaped structure on the substrate by a first adhesive, the first adhesive being made of an electrically conductive material, bonding the cover on the ring-shaped structure comprises bonding the cover on the ring-shaped structure by a second adhesive, the second adhesive being made of an electrically conductive material, and wherein the first adhesive, the ring-shaped structure, the second adhesive and the cover constitute an electromagnetic interference shielding structure. According to some embodiments, the method further comprises: bonding the substrate to a base substrate by a plurality of electrically conductive terminals, the substrate being located between the base substrate and the semiconductor die and electrically connected to the base substrate and the semiconductor die.

[0162] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. A semiconductor package, comprising: substrate; a semiconductor die disposed on the substrate; an annular structure disposed on the substrate and surrounding the semiconductor die, wherein a first side of the semiconductor die is separated from an inner sidewall of the annular structure by a first gap, and a second side of the semiconductor die is separated from the inner sidewall of the annular structure by a second gap, wherein the first side is opposite to the second side, and the first gap is smaller than the second gap; and A cover is provided on the annular structure and has a recess formed therein, the recess overlapping the first gap in a stacking direction of the annular structure and the cover, wherein a side wall of the recess is connected to a top surface of the recess and surrounds a periphery thereof. 2 . The semiconductor package according to claim 1 , wherein a thickness of the recess is smaller than a thickness of the cover.

3. The semiconductor package according to claim 1 , wherein the annular structure is in the form of a rectangular ring, wherein: The first gap is the shortest distance between the first side of the semiconductor die and the inner sidewall of the annular structure measured on the minor axis of the annular structure, and The second gap is the shortest distance between the second side of the semiconductor die and the inner sidewall of the annular structure measured on the minor axis of the annular structure.

4. The semiconductor package according to claim 1 , wherein the annular structure is in the form of a rectangular ring, and the semiconductor package further comprises: One or more first semiconductor devices are disposed on the substrate and electrically connected to the semiconductor die, wherein the one or more first semiconductor devices are located within the ring structure and adjacent to the semiconductor die along a long axis of the ring structure.

5. The semiconductor package according to claim 1 , wherein the annular structure is in the form of a rectangular ring, and the semiconductor package further comprises: a plurality of second semiconductor devices disposed on the substrate and electrically connected to the semiconductor die, wherein: The plurality of second semiconductor devices are located within the annular structure and are disposed adjacent to the semiconductor die along a minor axis of the annular structure; The plurality of second semiconductor devices are located on a side of the substrate opposite to the annular structure; or A first group of the second plurality of semiconductor devices is located within the annular structure and disposed adjacent the semiconductor die along a minor axis of the annular structure, and a second group of the second plurality of semiconductor devices is located on an opposite side of the substrate from the annular structure.

6. The semiconductor package according to claim 1, further comprising: A thermal interface material is positioned between the lid and the semiconductor die, wherein the lid is thermally coupled and connected to the semiconductor die via the thermal interface material. 7 . The semiconductor package of claim 1 , wherein the lid is separated from the semiconductor die by an air gap. 8 . The semiconductor package of claim 1 , wherein the annular structure comprises an outer sidewall opposite to the inner sidewall, and the outer sidewall is substantially aligned with sidewalls of the cover and the substrate. 9 . The semiconductor package of claim 1 , wherein the annular structure comprises an outer sidewall opposite the inner sidewall, and the outer sidewall is substantially aligned with a sidewall of the cover and offset from a sidewall of the substrate. 10 . The semiconductor package of claim 1 , wherein the inner sidewall of the ring structure comprises a substantially vertical sidewall. 11 . The semiconductor package of claim 10 , wherein a portion of the inner sidewall of the ring structure further comprises an inclined sidewall, wherein the inclined sidewall is located between the substantially vertical sidewall and the recess formed in the cover in the stacking direction.

12. A semiconductor package, comprising: substrate; a semiconductor die disposed on the substrate in an offset position toward an edge of the substrate; and An electromagnetic interference shielding structure is arranged on the substrate and electrically connected to the substrate, wherein the semiconductor tube core is located in a space defined by the substrate and the electromagnetic interference shielding structure, and a recess formed in the electromagnetic interference shielding structure corresponds to the offset position, wherein the sidewalls of the recess are connected to the top surface of the recess and surround its periphery.

13. The semiconductor package according to claim 12, wherein the electromagnetic interference shielding structure comprises: a stiffening ring disposed on the substrate and surrounding the semiconductor die; a first conductive adhesive positioned between the reinforcement ring and the substrate and bonding the reinforcement ring to the substrate; a cover disposed on the reinforcement ring and having the recess formed therein, the recess corresponding to the offset position; and A second conductive adhesive is positioned between the cover and the reinforcement ring and bonds the cover to the reinforcement ring.

14. The semiconductor package according to claim 12, further comprising: A base substrate is bonded to the substrate through a plurality of conductive terminals, wherein the substrate is located between the semiconductor die and the base substrate and is electrically connected to the semiconductor die and the base substrate.

15. The semiconductor package according to claim 13, wherein in a vertical projection on the substrate along the stacking direction of the EMI shielding structure and the substrate, the positioning position of the recess is adjacent to the positioning position of the reinforcement ring and is surrounded by the positioning position of the reinforcement ring. 16 . The semiconductor package according to claim 13 , wherein in a vertical projection on the substrate along a stacking direction of the EMI shielding structure and the substrate, a positioning position of the recess overlaps a positioning position of the reinforcement ring.

17. A method for manufacturing a semiconductor package, comprising: providing semiconductor dies; mounting the semiconductor die to a substrate; bonding a ring structure onto the substrate to surround the semiconductor die, wherein a first side of the semiconductor die is spaced apart from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is spaced apart from the inner sidewall of the ring structure by a second gap, wherein the first side is opposite to the second side, and the first gap is smaller than the second gap; and A cover is bonded to the annular structure to form a receiving space with the annular structure and the substrate, the semiconductor die is located in the receiving space, and the cover includes a recess formed therein, wherein the recess is spatially connected to the receiving space and overlaps with the first gap in the stacking direction of the annular structure and the cover, wherein a side wall of the recess is connected to a top surface of the recess and surrounds a periphery thereof.

18. The method according to claim 17, further comprising at least one of the following before bonding the annular structure to the substrate: mounting a plurality of first semiconductor devices on the substrate and adjacent to two opposite sides of the semiconductor die in an extension direction of the first side of the semiconductor die; mounting at least one second semiconductor device on the substrate and adjacent to the semiconductor die in a direction perpendicular to the direction in which the first side of the semiconductor die extends; and At least one third semiconductor device is mounted on a side of the substrate opposite to the side on which the semiconductor die is disposed.

19. The method according to claim 17, wherein Bonding the annular structure to the substrate includes bonding the annular structure to the substrate through a first adhesive, wherein the first adhesive is made of a conductive material, Adhering the cover to the annular structure includes adhering the cover to the annular structure via a second adhesive, the second adhesive being made of a conductive material, and The first adhesive, the annular structure, the second adhesive and the cover constitute an electromagnetic interference shielding structure.

20. The method of claim 17, further comprising: The substrate is bonded to a base substrate through a plurality of conductive terminals, the substrate being located between the base substrate and the semiconductor die and electrically connected to the base substrate and the semiconductor die.

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