Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device and a manufacturing method of a semiconductor device are related. A semiconductor device includes a laminated structure including conductive patterns spaced apart from each other, a channel structure penetrating the laminated structure, and a slit insulating layer penetrating the laminated structure. An air gap is defined between the conductive patterns. The slit insulating layer includes a first intervening portion covering a sidewall of one first conductive pattern and a second intervening portion covering one air gap from a side. A minimum width of the second intervening portion is smaller than a minimum width of the first intervening portion.

Description

TECHNICAL FIELD

[0001] The disclosure relates generally to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a three-dimensional semiconductor device and a method of manufacturing a three-dimensional semiconductor device. BACKGROUND

[0002] A semiconductor device includes a memory cell capable of storing data. A three-dimensional semiconductor device includes memory cells arranged in three dimensions, so that a two-dimensional area occupied by the memory cells on a substrate can be reduced.

[0003] By increasing the number of stacked memory cells, the integration of the three-dimensional semiconductor device can be increased. However, as the number of stacked memory cells increases, the operation reliability of the three-dimensional semiconductor device can deteriorate. SUMMARY

[0004] According to an aspect of the disclosure, a semiconductor device includes a stacked structure including conductive patterns spaced apart from each other, a channel structure penetrating the stacked structure, and a slit insulating layer penetrating the stacked structure. An air gap is defined between the conductive patterns, the slit insulating layer includes a first insertion portion covering a sidewall of one conductive pattern and a second insertion portion covering one air gap from a side, and a minimum width of the second insertion portion is smaller than a minimum width of the first insertion portion.

[0005] According to another aspect of the disclosure, a semiconductor device includes a stacked structure including conductive patterns spaced apart from each other, a channel structure penetrating the stacked structure, and a slit insulating layer penetrating the stacked structure. An air gap is defined between the conductive patterns, the slit insulating layer includes a second sidewall defining the air gap and a first sidewall opposite the second sidewall, and the first sidewall and the second sidewall are curved.

[0006] According to still another aspect of the disclosure, a method of manufacturing a semiconductor device includes forming a stacked structure including alternately stacked insulating layers and sacrificial layers, forming a trench penetrating the stacked structure, replacing the sacrificial layers with conductive patterns, forming a buffer pattern on sidewalls of the conductive patterns, forming an air gap by removing the insulating layers, and forming a slit insulating layer sealing the air gap. The step of forming the slit insulating layer includes a step of oxidizing the buffer pattern. BRIEF DESCRIPTION OF DRAWINGS

[0007] Example implementations will now be described more fully with reference to the accompanying drawings; however, they can be implemented in different forms and should not be construed as limited to the implementations set forth herein. Rather, these implementations are provided as example implementations so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0008] In the drawings, the size of some of the elements can be exaggerated and not to scale for illustrative purposes. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between these two elements or one or more additional elements can also be present. Like reference numerals refer to like elements throughout the various drawings.

[0009] The various embodiments relate to a semiconductor device capable of improving operation reliability and a method for manufacturing a semiconductor device.

[0010] Figure 1A is a plan view of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 1B is a cross-sectional view taken along Figure 1A line A-A' shown in .

[0012] Figure 1C is a plan view of a semiconductor device according to an embodiment of the present disclosure. Figure 1B

[0013] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Figure 2I , Figure 2J , Figure 2K and Figure 2L are cross-sectional views illustrating a method for manufacturing a semiconductor device shown in Figures 1A to 1C .

[0014] Figure 3A , Figure 3B and Figure 3C are cross-sectional views illustrating a method for manufacturing a semiconductor device shown in Figures 1A to 1C .

[0015] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E are cross-sectional views illustrating a method for manufacturing a semiconductor device shown in Figures 1A to 1C .

[0016] Figure 5A is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 5B is a plan view of a semiconductor device according to an embodiment of the present disclosure. Figure 5A

[0018] Figure 6A , Figure 6B and​ Figure 6C is a cross-sectional view of a semiconductor device. Figure 5A and Figure 5B is a cross-sectional view of a manufacturing method of a semiconductor device.

[0019] Figure 7 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0020] Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E is a cross-sectional view of a manufacturing method of a semiconductor device. Figure 7

[0021] Figure 9 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0022] Figure 10A , Figure 10B , Figure 10C and Figure 10D is a cross-sectional view of a manufacturing method of a semiconductor device. Figure 9

[0023] Figure 11A is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0024] Figure 11B is an enlarged view of a region E illustrated in Figure 11A

[0025] Figure 12 is a block diagram illustrating a configuration of a memory system according to an embodiment of the present disclosure.

[0026] Figure 13 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] The specific structural and functional description disclosed herein are merely illustrative for the purpose of describing embodiments in accordance with the present disclosure. Embodiments can be implemented in various forms, and thus the present teachings should not be construed as being limited to the embodiments set forth herein.

[0028] Figure 1A is a plan view of a semiconductor device according to an embodiment of the present disclosure. Figure 1B is a cross-sectional view taken along line A-A’ illustrated in Figure 1A Figure 1C is an enlarged view of a region B illustrated in Figure 1B

[0029] Referring to Figure 1A and​​​​​ Figure 1B The semiconductor device can include a stack structure STA. The stack structure STA can be disposed on a source structure (not shown). The source structure can have a shape of a plate extending along a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 can intersect each other since they are not parallel. In one example, the first direction D1 and the second direction D2 can be orthogonal to each other.

[0030] The source structure can include an electrically conductive material. In one example, the source structure can include polysilicon.

[0031] In one embodiment, the source structure can be disposed on a substrate (not shown) physically supporting the source structure. In one embodiment, a peripheral circuit structure (not shown) including transistors and lines can be disposed between the source structure and the substrate.

[0032] The stack structure STA can include electrically conductive patterns CP spaced apart from each other in a third direction D3. The third direction D3 can intersect the first direction D1 and the second direction D2. In one example, the third direction D3 can be orthogonal to the first direction D1 and the second direction D2.

[0033] The electrically conductive patterns CP can include gate conductive layers GC and barrier layers BR. The gate conductive layers GC can include an electrically conductive material. In one example, the gate conductive layers GC can include at least one of a doped silicon layer, a metal silicide layer, tungsten, nickel, and cobalt. The gate conductive layers GC can function as a word line connected to a memory cell or a select line connected to a select transistor. The barrier layers BR can cover surfaces of the gate conductive layers GC. In one example, the barrier layers BR can include at least one of titanium nitride and tantalum nitride.

[0034] A channel structure CS can be provided that penetrates the stack structure STA. The channel structure CS can penetrate the electrically conductive patterns CP of the stack structure STA. The channel structure CS can extend in the third direction D3. The channel structure CS can be electrically connected to the source structure.

[0035] Each channel structure CS can include a fill layer FI and a channel layer CL surrounding the fill layer FI. The fill layer FI and the channel layer CL can penetrate the stack structure STA. The fill layer FI and the channel layer CL can penetrate the electrically conductive patterns CP of the stack structure STA. The fill layer FI and the channel layer CL can extend in the third direction D3. The channel layer CL can be electrically connected to the source structure.

[0036] The fill layer FI can comprise an insulating material. In one example, the fill layer FI can comprise an oxide. The channel layer CL can comprise a semiconductor material. In one example, the channel layer CL can comprise polysilicon.

[0037] A memory layer ML can be provided around the respective channel structure CS. The memory layer ML can penetrate the stack structure STA. The memory layer ML can penetrate the conductive pattern CP of the stack structure STA. The memory layer ML can extend in the third direction D3.

[0038] Each memory layer ML can comprise a tunnel insulating layer TL around the channel structure CS, a data storage layer DL around the tunnel insulating layer TL, and a blocking layer BKL around the data storage layer DL. The tunnel insulating layer TL, the data storage layer DL, and the blocking layer BKL can extend in the third direction D3 and penetrate the stack structure STA.

[0039] The tunnel insulating layer TL can comprise a material through which charges can tunnel. In one example, the tunnel insulating layer TL can comprise an oxide. The data storage layer DL can comprise a material capable of storing data. In one example, the data storage layer DL can comprise a nitride in which charges can be trapped. In one example, the data storage layer DL can comprise silicon, a phase change material, or nanodots. The blocking layer BKL can comprise a material capable of blocking movement of charges.

[0040] A slit structure SLS can be provided that penetrates the stack structure STA. The conductive pattern CP can be provided on both sides of the slit structure SLS. By the slit structure SLS, the conductive patterns CP provided at the same height can be spaced apart from each other in the first direction D1. The slit structure SLS can extend in the second direction D2 and the third direction D3. The channel structure CS can be symmetrically provided on both sides of the slit structure SLS. The slit structure SLS can be electrically connected to the source structure. The slit structure SLS and the channel structure CS can be electrically connected to each other through the source structure.

[0041] The slit structure SLS can comprise a source contact SC and a slit insulating layer SI on both sides of the source contact SC. The source contact SC can penetrate the stack structure STA. The source contact SC can extend in the second direction D2 and the third direction D3. The source contact SC can comprise a conductive material. In one example, the source contact SC can comprise at least one of polysilicon and tungsten. The source contact SC can be electrically connected to the source structure. The source contact SC and the channel layer CL of the channel structure CS can be electrically connected to each other through the source structure.

[0042] In another embodiment different from the embodiment shown in the accompanying drawings, the slit structure SLS can include an insulating structure instead of the source contact SC. The insulating structure can penetrate the stack structure STA. The insulating structure can extend in the second direction D2 and the third direction D3. The insulating structure can include an insulating material. In one example, the insulating structure can include an oxide.

[0043] The slit insulating layer SI can penetrate the stack structure STA. The slit insulating layer SI can extend in the second direction D2 and the third direction D3. The slit insulating layer SI can be in contact with two side walls of the source contact SC, respectively. The slit insulating layer SI can be spaced apart from each other in the first direction D1 with the source contact SC interposed therebetween. The slit insulating layer SI can be disposed between the source contact SC and the conductive pattern CP. A surface of the slit insulating layer SI in contact with the source contact SC can be curved. The slit insulating layer SI can include an insulating material. In one example, the slit insulating layer SI can include an oxide.

[0044] An air gap AR can be defined by the memory layer ML, the conductive pattern CP, and the slit structure SLS. The air gap AR can be an empty space disposed between the channel structure CS, the conductive pattern CP, and the slit structure SLS. One air gap AR can be disposed between two conductive patterns CP. The conductive patterns CP of the stack structure STA can be spaced apart from each other in the third direction D3 with the air gap AR interposed therebetween. One air gap AR can be defined by a bottom surface of the conductive pattern CP, a top surface of a next lower conductive pattern CP, a side wall of the slit insulating layer SI, and a side wall of the blocking layer BLK of the memory layer ML. A surface of the slit insulating layer SI defining the air gap AR can be curved. The phrase "air gap" refers to a gap filled with air or a different type of gas other than air for different embodiments.

[0045] Referring to Figure 1CThe slit insulating layer SI can include a first interposition part IN1 and a second interposition part IN2. The first interposition part IN1 can be a part interposed between the conductive pattern CP and the source contact SC. The first interposition part IN1 can be a part disposed at the same height as the conductive pattern CP. The second interposition part IN2 can be a part interposed between the air gap AR and the source contact SC. The second interposition part IN2 can be a part disposed at the same height as the air gap AR. The first interposition part IN1 and the second interposition part IN2 can be alternately arranged along the third direction D3. The height of a boundary between the conductive pattern CP and the air gap AR can be equal to the height of a boundary between the first interposition part IN1 and the second interposition part IN2. The first interposition part IN1 can be in contact with a sidewall of the conductive pattern CP. The first interposition part IN1 can cover the sidewall of the conductive pattern CP. The second interposition part IN2 can define the air gap AR. The second interposition part IN2 can cover the air gap AR. The second interposition part IN2 can be in contact with a bottom surface of the conductive pattern CP thereabove and a top surface of the conductive pattern CP therebelow.

[0046] The width of the first interposition part IN1 in the first direction D1 can vary according to the height. The width of the first interposition part IN1 in the first direction D1 can be equal to the distance between the conductive pattern CP and the source contact SC in the first direction D1.

[0047] The width of the first interposition part IN1 in the first direction D1 can become the smallest at the lowermost and uppermost parts of the first interposition part IN1. The width of the first interposition part IN1 in the first direction D1 can become the smallest at a part where the first interposition part IN1 is in contact with the second interposition part IN2. The smallest width of the first interposition part IN1 in the first direction D1 can be defined as a first width W1.

[0048] The width of the first interposition part IN1 in the first direction D1 can become the largest at a central height of the first interposition part IN1. In other words, the width of the first interposition part IN1 in the first direction D1 can become the largest at a height equal to a central height of the conductive pattern CP in contact with the first interposition part IN1. The largest width of the first interposition part IN1 in the first direction D1 can be defined as a second width W2. As the central height of the first interposition part IN1 approaches the uppermost and lowermost parts of the first interposition part IN1, the width of the first interposition part IN1 in the first direction D1 can become smaller.

[0049] The width of the second interposition part IN2 in the first direction D1 can vary according to the height. The width of the second interposition part IN2 in the first direction D1 can be equal to the distance between the air gap AR and the source contact SC in the first direction D1.

[0050] The width of the second intervening portion IN2 in the first direction D1 can become the smallest at the center height of the second intervening portion IN2. In other words, the width of the second intervening portion IN2 in the first direction D1 can become the smallest at a height equivalent to the center height of the air gap AR defined by the second intervening portion IN2. The smallest width of the second intervening portion IN2 in the first direction D1 can be defined as a third width W3. The third width W3 can be smaller than the first width W1. The smallest width of the second intervening portion IN2 in the first direction D1 can be smaller than the smallest width of the first intervening portion IN1 in the first direction D1. The width of the slit insulating layer SI in the first direction D1 can become the smallest at a portion intervening between the air gap AR and the source contact SC.

[0051] The width of the second intervening portion IN2 in the first direction D1 can become the largest at the lowermost and uppermost portions of the second intervening portion IN2. The width of the second intervening portion IN2 in the first direction D1 can become the largest at a portion where the second intervening portion IN2 contacts the first intervening portion IN1. The largest width of the second intervening portion IN2 in the first direction D1 can be defined as a fourth width W4. The width of the second intervening portion IN2 in the first direction D1 can become larger as approaching the uppermost and lowermost portions of the second intervening portion IN2 from the center height of the second intervening portion IN2. The width of the second intervening portion IN2 in the first direction D1 can become larger as approaching the conductive pattern CP from the center height of the second intervening portion IN2. The fourth width W4 can be greater than the second width W2. The largest width of the second intervening portion IN2 in the first direction D1 can be greater than the largest width of the first intervening portion IN1 in the first direction D1.

[0052] The second intervening portion IN2 can include a first sidewall SW1 contacting the source contact SC and a second sidewall SW2 defining the air gap AR. The first sidewall SW1 and the second sidewall SW2 can be sidewalls opposite to each other in that they are on opposite sides of the slit insulating layer SI. The first sidewall SW1 and the second sidewall SW2 can be formed asymmetrically to each other. The first sidewall SW1 and the second sidewall SW2 can be curved.

[0053] A sidewall of the conductive pattern CP contacting the first intervening portion IN1 can be defined as a third sidewall SW3. A portion of the second sidewall of the second intervening portion IN2 can be disposed closer to the source contact SC than the third sidewall SW3.

[0054] The source contact portion SC can include a first contact portion SCT1 and a second contact portion SCT2. The first contact portion SCT1 can be a portion disposed between the first insertion portions IN1. The first contact portion SCT1 can be a portion disposed at the same height as the first insertion portions IN1. The first insertion portions IN1 can be in contact with both side walls of the first contact portion SCT1. The second contact portion SCT2 can be a portion disposed between the second insertion portions IN2. The second contact portion SCT2 can be a portion disposed at the same height as the second insertion portions IN2. The second insertion portions IN2 can be in contact with both side walls of the second contact portion SCT2. The first contact portion SCT1 and the second contact portion SCT2 can be alternately arranged along the third direction D3. The height of a boundary between the conductive pattern CP and the air gap AR, the height of a boundary between the first insertion portions IN1 and the second insertion portions IN2, and the height of a boundary between the first contact portion SCT1 and the second contact portion SCT2 can be the same.

[0055] The width of the first contact portion SCT1 in the first direction D1 can vary according to the height. The width of the first contact portion SCT1 in the first direction D1 can become the greatest at the uppermost and lowermost portions of the first contact portion SCT1. The width of the first contact portion SCT1 in the first direction D1 can become the greatest at a portion where the first contact portion SCT1 is in contact with the second contact portion SCT2.

[0056] The width of the first contact portion SCT1 in the first direction D1 can become the smallest at a central height of the first contact portion SCT1. In other words, the width of the first contact portion SCT1 in the first direction D1 can become the smallest at a height equivalent to a central height of the first insertion portion IN1 in contact with the first contact portion SCT1. The smallest width of the first contact portion SCT1 can be defined as a fifth width W5. The width of the first contact portion SCT1 in the first direction D1 can become greater as closer to the uppermost and lowermost portions of the first contact portion SCT1.

[0057] The width of the second contact portion SCT2 in the first direction D1 can vary according to the height. The width of the second contact portion SCT2 in the first direction D1 can become the smallest at the uppermost and lowermost portions of the second contact portion SCT2. The width of the second contact portion SCT2 in the first direction D1 can become the smallest at a portion where the second contact portion SCT2 is in contact with the first contact portion SCT1. The smallest width of the second contact portion SCT2 can be equal to the greatest width of the first contact portion SCT1. The greatest width of the first contact portion SCT1 and the smallest width of the second contact portion SCT2 can be defined as a sixth width W6. The sixth width W6 can be greater than the fifth width W5.

[0058] The width of the second contact portion SCT2 in the first direction D1 can be maximized at its center height. In other words, the width of the second contact portion SCT2 in the first direction D1 can be maximized at a height equal to the center height of the second insertion portion IN2 that contacts the second contact portion SCT2. The maximum width of the second contact portion SCT2 can be defined as a seventh width W7. The seventh width W7 can be greater than the sixth width W6. The width of the second contact portion SCT2 in the first direction D1 can decrease as it moves closer to the uppermost or lowermost part of the second contact portion SCT2, starting from its center height. The width of the second contact portion SCT2 in the first direction D1 can be greater than the width of the first contact portion SCT1 in the first direction D1. The maximum width of the second contact portion SCT2 can be greater than the maximum width of the first contact portion SCT1.

[0059] The sidewalls of the source contact SC can be curved to correspond to the sidewalls of the slit insulation layer SI.

[0060] A semiconductor device according to an embodiment of the present disclosure includes an air gap AR between conductive patterns CP, thereby minimizing the parasitic capacitance between the conductive patterns CP.

[0061] In the semiconductor device according to embodiments of the present disclosure, the width of the slit insulating layer SI at a height equivalent to the center height of the air gap AR can be minimized. Therefore, the volume of the air gap AR can be relatively large, and the parasitic capacitance between the conductive patterns CP can be minimized.

[0062] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Figure 2I , Figure 2J , Figure 2K and Figure 2L It is shown Figures 1A to 1C A cross-sectional view of the manufacturing method of the semiconductor device shown.

[0063] For ease of description, and with reference Figures 1A to 1C The same components are represented by the same reference numerals, and repeated descriptions of them will be omitted.

[0064] The manufacturing method described below is merely... Figures 1A to 1C One embodiment of the method for manufacturing the semiconductor device shown, and Figures 1A to 1CThe manufacturing method of the semiconductor device shown can not be limited to the manufacturing method described below.

[0065] Referring to Figure 2A A stacked structure STA including a sacrificial layer FL and an insulating layer IL can be formed. The sacrificial layer FL and the insulating layer IL can be alternately stacked in the third direction D3. The insulating layer IL can include an insulating material. In one example, the insulating layer IL can include an oxide. The sacrificial layer FL can include a material different from that of the insulating layer IL. In an example, the sacrificial layer FL can include a nitride. The stacked structure STA can be formed on the source structure.

[0066] Referring to Figure 2B A first hole HO1 penetrating the stacked structure STA can be formed. The first hole HO1 can extend in the third direction D3. The first hole HO1 can penetrate the insulating layer IL and the sacrificial structure FL of the stacked structure STA. The step of forming the first hole HO1 can include forming a first mask pattern including a first opening on the stacked structure STA, and etching the stacked structure STA by using the first mask pattern as an etching mask.

[0067] Referring to Figure 2C A memory layer ML and a channel structure CS can be formed in the first hole HO1. The step of forming the memory layer ML and the channel structure CS in the first hole HO1 can include sequentially forming a blocking layer BKL, a data storage layer DL, a tunnel insulating layer TL, a channel layer CL, and a fill layer FI in the first hole HO1.

[0068] Referring to Figure 2D A first trench TR1 penetrating the stacked structure STA can be formed. The first trench TR1 can extend in the second direction D2 and the third direction D3. The insulating layer IL and the sacrificial layer FL can be isolated from each other in the first direction D1 by the first trench TR1. The step of forming the first trench TR1 can include forming a second mask pattern including a second opening on the stacked structure STA, and etching the stacked structure STA by using the second mask pattern as an etching mask.

[0069] Referring to Figure 2E The insulating layer IL can be selectively etched through the first trench TR1. A sidewall of the insulating layer IL exposed through the first trench TR1 can be etched. When the insulating layer IL is etched, a portion of each insulating layer IL can be removed. When the portion of each insulating layer IL is removed, a first recess RC1 can be formed. A space between the sacrificial layers FL adjacent to each other in the third direction D3 can be defined as the first recess RC1. The first recess RC1 can be defined by the etched sidewall of the insulating layer IL, a bottom surface of one sacrificial layer FL, and a top surface of another sacrificial layer FL. The first recess RC1 can be connected to the first trench TR1.

[0070] Referring to Figure 2F , a first seed pattern SD1 can be formed in the first recess RC1. The step of forming the first seed pattern SD1 can include forming a first seed layer filling at least a portion of the first trench TR1 and the first recess RC1, and isolating the first seed layer into the first seed pattern SD1 by etching the first seed layer. The first seed pattern SD1 can be disposed between two sacrificial layers FL adjacent to each other in the third direction D3.

[0071] The first seed pattern SD1 can include a material that can be used as a seed in a subsequent process. The first seed pattern SD1 can include a material that can be oxidized by an oxidation process. In one example, the first seed pattern SD1 can include polysilicon. A sidewall of the first seed pattern SD1 exposed through the first trench TR1 can be defined as a fourth sidewall SW4. The fourth sidewall SW4 can form a common surface with a sidewall of the sacrificial layer FL exposed through the first trench TR1.

[0072] Referring to Figure 2G , a first preliminary oxidation pattern EP1 can be formed. The step of forming the first preliminary oxidation pattern EP1 can include selectively forming the preliminary oxidation pattern EP1 by using the first seed pattern SD1 as a seed. The first preliminary oxidation patterns EP1 can be spaced apart from each other in the third direction D3. The first preliminary oxidation patterns EP1 can include the same material as the first seed pattern SD1. In one example, the first preliminary oxidation patterns EP1 can include polysilicon.

[0073] A first center line C1-C1’ of the first trench TR1 can be defined. The first center line C1-C1’ can be a virtual line representing a center of the first trench TR1 in the first direction D1. The first center line C1-C1’ can extend in the second direction D2 and the third direction D3.

[0074] The first preliminary oxidation pattern EP1 can be formed in the first trench TR1. The first preliminary oxidation pattern EP1 can be disposed closer to a center of the first trench TR1 than the sacrificial layer FL. A shortest distance between the first preliminary oxidation pattern EP1 and the first center line C1-C1’ of the first trench TR1 can be less than a shortest distance between the sacrificial layer FL and the first center line C1-C1’ of the first trench TR1. A surface of the first preliminary oxidation pattern EP1 facing the center of the first trench TR1 can be curved.

[0075] Referring to Figure 2HThe first oxidation pattern OPl can be formed by oxidizing the first seed pattern SD1 and the first initial oxidation pattern EP1. The first seed pattern SD1 and the first initial oxidation pattern EP1 can be oxidized by an oxidation process. In one example, the oxidation process includes providing oxygen into the first trench TR1.

[0076] A volume of the first oxidation pattern OPl can be greater than a sum of volumes of the first seed pattern SD1 and the first initial oxidation pattern EP1. The volumes of the first seed pattern SD1 and the first initial oxidation pattern EP1 can become greater during the oxidation of the first seed pattern SD1 and the first initial oxidation pattern EP1. The first oxidation pattern OPl can be disposed closer to a center of the first trench TR1 than the first initial oxidation pattern EP1. A shortest distance between the first oxidation pattern OPl and the first center line C1-C1’ of the first trench TR1 can be less than a shortest distance between the first initial oxidation pattern EP1 and the first center line C1-C1’ of the first trench TR1. A surface of the first oxidation pattern OPl facing the center of the first trench TR1 can be curved.

[0077] Referring to Figure 2I The conductive pattern CP can be utilized instead of the sacrificial layer FL. A step of utilizing the conductive pattern CP instead of the sacrificial layer FL can include removing the sacrificial layer FL through the first trench TR1, and forming the conductive pattern CP in a hollow space formed by the removal of the sacrificial layer FL.

[0078] A space between the first oxidation patterns OPl adjacent to each other in the third direction D3 can be defined as a second recess RC2. The second recess RC2 can be defined by sidewalls of the conductive pattern CP and the two first oxidation patterns OPl.

[0079] Referring to Figure 2J A first buffer pattern BP1 can be formed in the second recess RC2. A step of forming the first buffer pattern BP1 can include forming a first buffer layer filling at least a portion of the first trench TR1, and isolating the first buffer layer into the first buffer pattern BP1 by etching the first buffer layer. A surface of the first buffer pattern BP1 contacting the first oxidation pattern OPl can be curved corresponding to the curved surface of the first oxidation pattern OPl. A width of the first buffer pattern BP1 in the third direction D3 can not be constant. The width of the first buffer pattern BP1 in the third direction D3 can become greater as closer to the center of the first trench TR1. A width of a sidewall of the first buffer pattern BP1 facing the center of the first trench TR1 in the third direction D3 can be greater than a width of a sidewall of the first buffer pattern BP1 contacting the conductive pattern CP in the third direction D3.

[0080] The first buffer pattern BP1 can be disposed between two first oxidation patterns OP1 adjacent to each other in the third direction D3. The first buffer pattern BP1 can be formed on a sidewall of the conductive pattern CP. The first buffer pattern BP1 can be disposed farther from the center of the first trench TR1 than the first oxidation pattern OP1. A shortest distance between the sidewall of the first buffer pattern BP1 exposed between the first oxidation patterns OP1 and the first center line C1-C1’ of the first trench TR1 can be greater than a shortest distance between the first oxidation pattern OP1 and the first center line C1-C1’ of the first trench TR1.

[0081] The first buffer pattern BP1 can include a material that can be oxidized by an oxidation process. In an example, the first buffer pattern BP1 can include polysilicon. In another example, the first buffer pattern BP1 can include nitride. The nitride included in the first buffer pattern BP1 can be silicon nitride.

[0082] Referring to Figure 2K The first oxidation pattern OP1 and the insulating layer IL can be removed. The first oxidation pattern OP1 and the insulating layer IL can be selectively removed by using an etching material capable of selectively etching an oxide.

[0083] The empty space in which the first oxidation pattern OP1 and the insulating layer IL are removed can be defined as an air gap AR. The air gap AR can be connected to the first trench TR1. The air gap can be disposed between two conductive patterns CP adjacent to each other in the third direction D3. A portion of the blocking layer BKL of the memory layer ML can be exposed by the air gap AR.

[0084] Referring to Figure 2L The first buffer pattern BP1 can be oxidized. The volume of the first buffer pattern BP1 can become larger during the oxidation of the first buffer pattern BP1. As the volume of the first buffer pattern BP1 becomes larger during the oxidation of the first buffer pattern BP1, the first buffer patterns BP1 adjacent to each other in the third direction D3 can be connected to each other in the third direction D3. As the first buffer patterns BP1 are connected to each other during the oxidation, a slit insulating layer SI is formed. Since the width of the first buffer pattern BP1 in the third direction D3 becomes larger as it is closer to the center of the first trench TR1, the first sidewall SW1 and the second sidewall SW2 of the second insertion portion IN2 of the slit insulating layer SI can be asymmetrically formed (see Figure 1C ).

[0085] The first buffer pattern BP1 can be oxidized by an oxidation process. In one example, when the first buffer pattern BP1 includes polysilicon, the first buffer pattern BP1 can be oxidized by a dry oxidation process using oxygen, a wet oxidation process using water, or a radical oxidation process. In another example, when the first buffer pattern BP1 includes nitride, the first buffer pattern BP1 can be oxidized by a radical oxidation process.

[0086] When the slit insulating layer SI is formed, the air gap AR and the first trench TR1 can be isolated from each other. The air gap AR can be sealed by the slit insulating layer SI. In a case where the slit insulating layer SI is formed by expanding the volume of the first buffer pattern BP1 formed on the sidewall of the conductive pattern CP, the width of the slit insulating layer SI can become the smallest at a portion where the slit insulating layer SI and the air gap AR are located at the same height. Subsequently, the source contact SC (see FIG. 1) can be formed between two slit insulating layers SI. Figure 1B ).

[0087] In the manufacturing method of a semiconductor device according to the present disclosure, the first oxide pattern OP1 can be formed between the conductive patterns CP, and the first buffer pattern BP1 can be formed between the first oxide patterns OP1. Subsequently, the slit insulating layer SI can be formed by oxidizing the first buffer pattern BP1, and the air gap AR can be formed between the conductive patterns CP.

[0088] The semiconductor device is manufactured by the above-described process so that the width of the slit insulating layer SI can become the smallest at a height that is the same as the center height of the air gap AR. Accordingly, the volume of the air gap can be formed to become relatively large, and the parasitic capacitance between the conductive patterns CP can be minimized.

[0089] Figure 3A 、 Figure 3B and Figure 3C are cross-sectional views illustrating a manufacturing method of a semiconductor device shown in Figures 1A to 1C .

[0090] For convenience of description, components identical to those described with reference to Figures 1A to 1C will be denoted by the same reference numerals, and repeated description thereof will be omitted.

[0091] The manufacturing method described below is merely one embodiment of a manufacturing method of a semiconductor device shown in Figures 1A to 1C , and the manufacturing method of a semiconductor device shown in Figures 1A to 1C may not be limited to the manufacturing method described below.

[0092] With reference to Figure 3A , the manufacturing method can be similar to Figures 2A to 2D The layer stack STA including the sacrificial layer FL and the insulating layer IL, the channel structure CS, the memory layer ML, and the first trench TR1 are formed.

[0093] Subsequently, a second oxide pattern OP2 can be formed on the sidewall of the insulating layer IL exposed by the first trench TR1. The second oxide pattern OP2 can be selectively formed on the sidewall of the insulating layer IL. The second oxide pattern OP2 can be formed by a selective oxide deposition process. The second oxide patterns OP2 can be spaced apart from each other in the third direction D3. The surface of the second oxide pattern OP2 facing the center of the first trench TR1 can be curved.

[0094] The second oxide pattern OP2 can be formed in the first trench TR1. The second oxide pattern OP2 can be disposed closer to the center of the first trench TR1 than the sacrificial layer FL. The second oxide pattern OP2 can include the same material as the insulating layer IL. In one example, the second oxide pattern OP2 can include an oxide.

[0095] Referring to Figure 3B The conductive pattern CP can be utilized instead of the sacrificial layer FL. The space between two second oxide patterns OP2 adjacent to each other in the third direction D3 can be defined as a third recess RC3. The third recess RC3 can be defined by the sidewalls of the two second oxide patterns OP2 and the conductive pattern CP.

[0096] Referring to Figure 3C The second buffer pattern BP2 can be formed in the third recess RC3. The second buffer pattern BP2 can be formed between the second oxide patterns OP2. The second buffer pattern BP2 can be similar to the first buffer pattern BP1 described in Figures 2J to 2K .

[0097] Subsequently, the second buffer pattern BP2 can be oxidized after the second oxide pattern OP2 and the insulating layer IL are removed, similar to Figure 2K and Figure 2L . When the second buffer pattern BP2 is oxidized, a slit insulating layer SI (see Figure 1B ) can be formed, and an air gap AR (see Figure 1B ) sealed by the slit insulating layer SI can be formed. Subsequently, a source contact SC (see Figure 1B ) can be formed between the slit insulating layers SI.

[0098] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E are cross-sectional views illustrating a method of manufacturing the semiconductor device illustrated in Figures 1A to 1C .

[0099] For convenience of description, the same components as those described with reference to Figures 1A to 1C The same components described with reference to

[0100] The manufacturing method described below is merely one embodiment of a manufacturing method of a semiconductor device, and Figures 1A to 1C The manufacturing method of a semiconductor device described below can not be limited to the method described below. Figures 1A to 1C The manufacturing method of a semiconductor device described below can not be limited to the method described below.

[0101] With reference to Figure 4A , a stacked structure STA including a sacrificial layer FL and an insulating layer IL can be formed, and a first hole HO1 penetrating the stacked structure STA can be formed. Figure 2A and Figure 2B , a stacked structure STA including a sacrificial layer FL and an insulating layer IL can be formed, and a first hole HO1 penetrating the stacked structure STA can be formed.

[0102] Subsequently, the insulating layer IL can be selectively etched through the first hole HO1. A sidewall of the insulating layer IL exposed through the first hole HO1 can be etched. When the insulating layer IL is etched, a portion of each insulating layer IL can be removed. When the portion of each insulating layer IL is removed, a fourth recess RC4 can be formed. The fourth recess RC4 can be defined by an etched sidewall of the insulating layer IL, a bottom surface of one sacrificial layer FL, and a top surface of another sacrificial layer FL. The fourth recess RC4 can be disposed between two sacrificial layers FL adjacent to each other in the third direction D3. The fourth recess RC4 can be connected to the first hole HO1.

[0103] With reference to Figure 4B , a first protective pattern PP1 can be formed in the fourth recess RC4. The step of forming the first protective pattern PP1 can include forming a first protective layer by filling at least a portion of the fourth recess RC4 and the first hole HO1, and isolating the first protective layer as the first protective pattern PP1 by etching the first protective layer. The first protective pattern PP1 can be disposed between two sacrificial layers FL adjacent to each other in the third direction D3.

[0104] The first protective pattern PP1 can include a material having etching selectivity with respect to the sacrificial layer FL and the insulating layer IL. In one example, the first protective pattern PP1 can include polysilicon. A sidewall of the first protective pattern PP1 exposed through the first hole HO1 can form a common surface with a sidewall of the sacrificial layer FL.

[0105] With reference to Figure 4C , a memory layer ML and a channel structure CS can be formed in the first hole HO1. The step of forming the memory layer ML and the channel structure CS in the first hole HO1 can include sequentially forming a barrier layer BKL, a data storage layer DL, a tunnel insulating layer TL, a channel layer CL, and a fill layer FI in the first hole HO1.

[0106] The barrier layer BKL of the memory layer ML can be in contact with the first protective pattern PP1. The barrier layer BKL of the memory layer ML can be spaced apart from the insulating layer IL by the first protective pattern PP1.

[0107] Referring to Figure 4D , the conductive pattern CP can be used instead of the sacrificial layer FL, the third buffer pattern BP3 can be formed on the sidewall of the conductive pattern CP, and the insulating layer IL can be removed. The third buffer pattern BP3 can be similar to the first buffer pattern BP1 described in Figures 2J to 2K .

[0108] In one embodiment, the conductive pattern CP and the third buffer pattern BP3 can be formed and the insulating layer IL can be removed, similar to as described in Figures 2D to 2K . In another embodiment, the conductive pattern CP and the third buffer pattern BP3 can be formed and the insulating layer IL can be removed, similar to as described in Figures 3A to 3C .

[0109] When the insulating layer IL is removed, the first protective pattern PP1 can be exposed. Since the first protective pattern PP1 includes a material having etching selectivity with respect to the insulating layer IL, the first protective pattern PP1 can not be removed in a process of removing the insulating layer IL. In the process of removing the insulating layer IL, the memory layer ML can be protected by the first protective pattern PP1.

[0110] Referring to Figure 4E , the barrier layer BKL of the memory layer ML can be exposed by removing the first protective pattern PP1. Subsequently, similar to as described in Figure 2L , the third buffer pattern BP3 can be oxidized. When the third buffer pattern BP3 is oxidized, the slit insulating layer SI (see Figure 1B ) can be formed, and the air gap AR (see Figure 1B ) sealed by the slit insulating layer SI can be formed. Subsequently, the source contact SC (see Figure 1B ) can be formed between the slit insulating layers SI.

[0111] In the method of manufacturing a semiconductor device according to the embodiment of the present disclosure, the first protective pattern PP1 protecting the barrier layer BKL of the memory layer is formed so that the barrier layer BKL can be protected in a process of removing the insulating layer IL.

[0112] Figure 5A is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. Figure 5B is an enlarged view of the region D shown in Figure 5A .

[0113] Except for the parts described below, Figure 5A and Figure 5B The semiconductor device illustrated in FIG. 1A can be similar to the semiconductor device illustrated in FIG. 1B. Figures 1A to 1C The semiconductor device illustrated in FIG. 1A can be similar to the semiconductor device illustrated in FIG. 1B.

[0114] Referring to Figure 5A and Figure 5B , the semiconductor device can include a stacked structure STA having a conductive pattern CP, a channel structure CS, a memory layer ML, and a slit structure SLS. An air gap AR can be defined by the memory layer ML, the conductive pattern CP, and the slit structure SLS. The slit structure SLS can include a source contact SC and a slit insulating layer SI.

[0115] Each slit insulating layer SI can include a first insulating portion IP1 and a second insulating portion IP2. The first insulating portion IP1 and the second insulating portion IP2 can include the same material, or can include different materials. In one example, the first insulating portion IP1 can include an oxide, and the second insulating portion IP2 can include a nitride. The first insulating portions IP1 can be spaced apart from each other in a third direction D3. Each first insulating portion IP1 can be in contact with a sidewall of each conductive pattern CP, respectively. The first insulating portions IP1 can be spaced apart from the source contact SC. A bottom surface IP1B of the first insulating portion IP1 can be a surface defining the air gap AR. A top surface IP1T of the first insulating portion IP1 can be a surface defining the air gap AR. The top surface IP1T and the bottom surface IP1B of the first insulating portion IP1 can be in contact with the air gap AR. The top surface IP1T and the bottom surface IP1B of the first insulating portion IP1 can be curved.

[0116] The second insulating portion IP2 can be in contact with the plurality of first insulating portions IP1. The second insulating portion IP2 can connect the plurality of first insulating portions IP1 spaced apart from each other in the third direction D3. The second insulating portion IP2 can include a first portion IP2a and a second portion IP2b. The first portion IP2a of the second insulating portion IP2 can be a portion in contact with the first insulating portion IP1. The second portion IP2b of the second insulating portion IP2 can be a portion connecting the first portion IP2a of the second insulating portion IP2. The second portion IP2b of the second insulating portion IP2 can be a portion not in contact with the first insulating portion IP1. The first portion IP2a and the second portion IP2b of the second insulating portion IP2 can be alternately arranged in the third direction D3.

[0117] Each of the two side walls of the first portion IP2a of the second insulating portion IP2 can be in contact with the source contact SC or the first insulating portion IP1. Each of the two side walls of the first portion IP2a of the second insulating portion IP2 can be curved. One side wall of the second portion IP2b of the second insulating portion IP2 can be in contact with the source contact SC, and the other side wall of the second portion IP2b of the second insulating portion IP2 can define the air gap AR. Each of the two side walls of the second portion IP2b of the second insulating portion IP2 can be curved. The second portion IP2b of the second insulating portion IP2 can be a portion exposed by the air gap AR. The second portion IP2b of the second insulating portion IP2 can be a portion disposed at a height equivalent to a center height of the air gap AR.

[0118] A maximum width of the first insulating portion IP1 in the first direction D1 can be greater than a maximum width of the second insulating portion IP2 in the first direction D1. A portion of the slit insulating layer SI in which a width in the first direction D1 is the smallest can be the second portion IP2b of the second insulating portion IP2. The width of the slit insulating layer SI in the first direction D1 can be the smallest at a height equivalent to a center height of the air gap AR.

[0119] Figure 6A 、 Figure 6B and Figure 6C is a cross-sectional view illustrating a manufacturing method of the semiconductor device shown in Figure 5A and Figure 5B .

[0120] For convenience of description, components identical to those described with reference to Figure 5A and Figure 5B will be denoted by the same reference numerals, and repetitive description thereof will be omitted.

[0121] The manufacturing method described below is merely one embodiment of a manufacturing method of the semiconductor device shown in Figure 5A and Figure 5B , and the manufacturing method of the semiconductor device shown in Figure 5A and Figure 5B may not be limited to the manufacturing method described below.

[0122] With reference to Figure 6A , the stack structure STA including the conductive pattern CP, the memory layer ML, and the channel structure CS can be formed, and the fourth buffer pattern BP4 can be formed on a side wall of the conductive pattern CP. The processes of forming the stack structure STA, the memory layer ML, the channel structure CS, and the fourth buffer pattern BP4 can be similar to those described in Figures 2A to 2L , Figures 3A to 3C or Figures 4A to 4E .

[0123] The empty space defined between the conductive patterns CP adjacent to each other in the third direction D3 can be defined as an air gap AR. The air gap AR can be connected to the first trench TR1.

[0124] Referring to Figure 6B , the fourth buffer pattern BP4 can be oxidized. During the oxidation of the fourth buffer pattern BP4, the volume of the fourth buffer pattern BP4 can be increased. The oxidized fourth buffer pattern BP4 can be defined as a first insulating portion IP1. The first insulating portions IP1 adjacent to each other in the third direction D3 can be spaced apart from each other in the third direction D3. The air gap AR can not be sealed by the first insulating portions IP1. The air gap AR can be connected to the first trench TR1 through the space between the first insulating portions IP1.

[0125] Referring to Figure 6C , a second insulating portion IP2 connecting the first insulating portions IP1 can be formed. The step of forming the second insulating portion IP2 can include depositing a deposition material on the first insulating portions IP1. The deposition material can be selectively deposited without penetrating into the air gap AR. When the second insulating portion IP2 is formed, the air gap AR can be sealed. Subsequently, a source contact SC (see Figure 5A ) filled between the second insulating portions IP2 can be formed.

[0126] In the method of manufacturing a semiconductor device according to the embodiment, after the first insulating portions IP1 are formed by oxidizing the fourth buffer pattern BP4, the second insulating portions IP2 can be formed by depositing a deposition material until the air gap AR is sealed. Accordingly, the width of the second insulating portions IP2 can be relatively small, and the width of the slit insulating layer SI can be the smallest at a portion where the second insulating portions IP2 are located at a height equivalent to the center height of the air gap AR.

[0127] Figure 7 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0128] In addition to the portions described below, Figure 7 the semiconductor device shown can be similar to the semiconductor device shown in Figures 1A to 1C .

[0129] Referring to Figure 7 , the semiconductor device can include a stacked structure STA having conductive patterns CP, a channel structure CS, a memory layer ML, and a slit structure SLS. The air gap AR can be defined by the memory layer ML, the conductive patterns CP, and the slit structure SLS. The slit structure SLS can include a source contact SC and a slit insulating layer SI.

[0130] The semiconductor device can further include a second protective pattern PP2. The second protective patterns PP2 can be spaced apart from each other in the third direction D3. The second protective patterns adjacent to each other in the third direction D3 can be spaced apart from each other in the third direction D3 with the air gaps AR interposed therebetween. The second protective pattern PP2 can include a first portion PP2a interposed between the conductive pattern CP and the memory layer ML and a second portion PP2b interposed between the air gap AR and the conductive pattern CP. The first portion PP2a of the second protective pattern PP2 can connect the second portion PP2b of the second protective pattern PP2. A width of the first portion PP2a of the second protective pattern PP2 in the first direction D1 can be smaller than a width of the second portion PP2b of the second protective pattern PP2 in the first direction D1. The second protective pattern PP2 can be in contact with the barrier layer BKL of the memory layer ML and the conductive pattern CP. The second protective pattern PP2 can be in contact with the sidewall, the top surface, and the bottom surface of the conductive pattern CP. The first portion PP2a of the second protective pattern PP2 can be in contact with the sidewall of the conductive pattern CP and the sidewall of the barrier layer BKL of the memory layer ML. The second portion PP2b of the second protective pattern PP2 can be in contact with the top surface and the bottom surface of the conductive pattern CP. The second portion PP2b of the second protective pattern PP2 can include a surface defining the air gap AR. The second protective pattern PP2 can include the same material as the insulating layer IL (see Figure 2A ) in one example, the second protective pattern PP2 can include an oxide.

[0131] Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 8D and Figure 8E are cross-sectional views each showing a method of manufacturing the semiconductor device shown in Figure 7 .

[0132] For convenience of description, components same as those described with reference to Figure 7 are denoted by the same reference numerals, and repeated description thereof will be omitted.

[0133] The manufacturing method described below is merely one embodiment of a method of manufacturing the semiconductor device shown in Figure 7 , and Figure 7 the method of manufacturing the semiconductor device shown in can not be limited to the manufacturing method described below.

[0134] With reference to Figure 8A , a stack structure STA including a sacrificial layer FL and an insulating layer IL can be formed, and a first hole H01 penetrating the stack structure STA can be formed, similarly to as described in Figure 2A and Figure 2B .

[0135] Subsequently, the insulating layers IL can be selectively etched through the first holes HO1. The sidewalls of the insulating layers IL exposed through the first holes HO1 can be etched. The fifth recess RC5 can be formed by removing a portion of each of the insulating layers IL.

[0136] The fifth recess RC5 can be disposed between two of the sacrificial layers FL adjacent to each other in the third direction D3.

[0137] Subsequently, a second protective layer PL2 can be formed in the first holes HO1 and the fifth recess RC5. The second protective layer PL2 can be conformally formed on surfaces of the insulating layers IL and the sacrificial layers FL defining the first holes HO1 and the fifth recess RC5. The second protective layer PL2 can cover sidewalls, a top surface, and a bottom surface of the sacrificial layers FL, and can cover sidewalls of the insulating layers IL. A portion of the second protective layer PL2 covering the top surface of the sacrificial layers FL can be defined as a first portion PL2a of the second protective layer PL2, a portion of the second protective layer PL2 covering the sidewalls of the insulating layers IL can be defined as a second portion PL2b of the second protective layer PL2, and a portion of the second protective layer PL2 covering the bottom surface of the sacrificial layers FL can be defined as a third portion PL2c of the second protective layer PL2. The second protective layer PL2 can include the same material as the insulating layers IL. In one example, the second protective layer PL2 can include an oxide.

[0138] A sixth recess RC6 can be defined by the second protective layer PL2. The sixth recess RC6 can be defined by the first portion to the third portion PL2a, PL2b, and PL2c of the second protective layer PL2. The sixth recess RC6 can be defined between the first portion PL2a and the third portion PL2c of the second protective layer PL2.

[0139] Referring to Figure 8B A third protective pattern PP3 can be formed in the sixth recess RC6. The step of forming the third protective pattern PP3 can include forming a third protective layer filling the sixth recess RC6 and at least a portion of the first holes HO1, and isolating the third protective layer into the third protective pattern PP3 by etching the third protective layer. The third protective pattern PP3 can be disposed between the first portion PL2a and the third portion PL2c of the second protective layer PL2. The third protective pattern PP3 can include a material having etch selectivity with respect to the insulating layers IL and the second protective layer PL2. In one example, the third protective pattern PP3 can include a material having etch selectivity with respect to an oxide. In one example, the third protective pattern PP3 can include polysilicon.

[0140] Referring to Figure 8CThe memory layer ML and the channel structure CS can be formed in the first hole HO1. The step of forming the memory layer ML and the channel structure CS in the first hole HO1 can include sequentially forming the blocking layer BKL, the data storage layer DL, the tunnel insulating layer TL, the channel layer CL, and the fill layer FI in the first hole HO1.

[0141] The blocking layer BKL of the memory layer ML can be in contact with the third protection pattern PP3 and the second protection layer PL2. The blocking layer BKL of the memory layer ML can be spaced apart from the insulating layer IL by the third protection pattern PP3 and the second protection layer PL2.

[0142] Referring to Figure 8D The conductive pattern CP can be used instead of the sacrificial layer FL, the fifth buffer pattern BP5 can be formed on the sidewall of the conductive pattern CP, and the insulating layer IL can be removed. The fifth buffer pattern BP5 can be similar to the first buffer pattern BP1 described in Figures 2J to 2K .

[0143] In one embodiment, the conductive pattern CP and the fifth buffer pattern BP5 can be formed and the insulating layer IL can be removed, similar to as described in Figures 2D to 2K . In another embodiment, the conductive pattern CP and the fifth buffer pattern BP5 can be formed and the insulating layer IL can be removed, similar to as described in Figures 3A to 3C .

[0144] Since the second protection layer PL2 includes the same material as the insulating layer IL, a portion of the second protection layer PL2 can be removed together with the insulating layer IL. When the second portion PL2b of the second protection layer PL2 is removed, the second protection layer PL2 can be isolated as the second protection pattern PP2. The second protection pattern PP2 can be arranged to be spaced apart from each other in the third direction D3 with the third protection pattern interposed therebetween. The third protection pattern PP3 can be exposed when the second portion PL2b of the second protection layer PL2 is removed. Since the third protection pattern PP3 includes a material having etching selectivity with respect to the insulating layer IL, the third protection pattern PP3 can not be removed in a process of removing the insulating layer IL. The memory layer ML can be protected by the third protection pattern PP3 in the process of removing the insulating layer IL.

[0145] Referring to Figure 8E The blocking layer BKL of the memory layer ML can be exposed by removing the third protection pattern PP3. Subsequently, the fifth buffer pattern BP5 can be oxidized. When the fifth buffer pattern BP5 is oxidized, a slit insulating layer SI can be formed, similar to as described in Figure 2L or Figure 6B and Figure 6C (see Figure 7). An air gap AR sealed by a slit insulating layer SI can be formed (see Figure 7 ). Subsequently, a source contact SC can be formed between the slit insulating layers SI (see Figure 7 ).

[0146] In the method of manufacturing a semiconductor device according to the embodiment of the present disclosure, the barrier layer BKL of the memory layer ML can be protected by the second protection pattern PP2 and the third protection pattern PP3 protecting the barrier layer BKL of the memory layer ML in the process of removing the insulating layer IL.

[0147] Figure 9 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0148] In addition to the portions described below, Figure 9 the semiconductor device illustrated in Figures 1A to 1C can be similar to the semiconductor device illustrated in

[0149] Referring to Figure 9 , the semiconductor device can include a stacked structure STA having a conductive pattern CP, a channel structure CS, a memory layer ML, and a slit structure SLS. An air gap AR can be defined by the memory layer ML, the conductive pattern CP, and the slit structure SLS. The slit structure SLS can include a source contact SC and a slit insulating layer SI.

[0150] Each slit insulating layer SI can include a third intervening portion IN3 and a fourth intervening portion IN4. The third intervening portion IN3 can be a portion disposed between the conductive pattern CP and the source contact SC. The third intervening portion IN3 can be a portion disposed at the same height as the conductive pattern CP. The fourth intervening portion IN4 can be a portion disposed between the air gap AR and the source contact SC. The fourth intervening portion IN4 can be a portion disposed at the same height as the air gap AR. The third intervening portion IN3 and the fourth intervening portion IN4 can be alternately arranged along a third direction D3.

[0151] The width of the third intervening portion IN3 in the first direction D1 can vary according to height. The width of the third intervening portion IN3 in the first direction D1 can become smallest at the lowermost portion and the uppermost portion of the third intervening portion IN3. The width of the third intervening portion IN3 in the first direction D1 can become smallest at the portion where the third intervening portion IN3 contacts the fourth intervening portion IN4. The width of the third intervening portion IN3 in the first direction D1 can become largest at the central height of the third intervening portion IN3. In other words, the width of the third intervening portion IN3 in the first direction D1 can become largest at the height equivalent to the central height of the conductive pattern CP in contact with the third intervening portion IN3. The width of the third intervening portion IN3 in the first direction D1 can become smaller as it gets closer to the uppermost portion or the lowermost portion of the third intervening portion IN3 from the central height of the third intervening portion IN3.

[0152] The width of the fourth intervening portion IN4 in the first direction D1 can vary according to height. The width of the fourth intervening portion IN4 in the first direction D1 can be equal to the distance between the air gap AR and the source contact SC in the first direction D1. The width of the fourth intervening portion IN4 in the first direction D1 can become smallest at the central height of the fourth intervening portion IN4. In other words, the width of the fourth intervening portion IN4 in the first direction D1 can become largest at the height equivalent to the central height of the air gap AR defined by the fourth intervening portion IN4. The smallest width of the fourth intervening portion IN4 can be smaller than the smallest width of the third intervening portion IN3. The smallest width of the fourth intervening portion IN4 in the first direction D1 can be smaller than the smallest width of the third intervening portion IN3 in the first direction D1. The width of the slit insulating layer SI in the first direction D1 can become smallest at the height equivalent to the central height of the air gap AR.

[0153] The width of the fourth intervening portion IN4 in the first direction D1 can become largest at the lowermost portion and the uppermost portion of the fourth intervening portion IN4. The width of the fourth intervening portion IN4 in the first direction D1 can become largest at the portion where the fourth intervening portion IN4 contacts the third intervening portion IN3. The width of the fourth intervening portion IN4 in the first direction D1 can become larger as it gets closer to the uppermost portion or the lowermost portion of the fourth intervening portion IN4 from the central height of the fourth intervening portion IN4. The width of the fourth intervening portion IN4 in the first direction D1 can become larger as it gets closer to the conductive pattern CP from the central height of the fourth intervening portion IN4. The largest width of the fourth intervening portion IN4 in the first direction D1 can be smaller than the largest width of the third intervening portion IN3 in the first direction D1.

[0154] The fourth insertion portion IN4 may include a fifth sidewall SW5 that contacts the source contact portion SC and a sixth sidewall SW6 that defines the air gap AR. The fifth sidewall SW5 and the sixth sidewall SW6 may be sidewalls opposite to each other. The fifth sidewall SW5 and the sixth sidewall SW6 may be formed symmetrically to each other.

[0155] Figure 10A , Figure 10B , Figure 10C and Figure 10D It is shown Figure 9 A cross-sectional view of the manufacturing method of the semiconductor device shown.

[0156] For ease of description, and with reference Figure 9 The same components are represented by the same reference numerals, and repeated descriptions of them will be omitted.

[0157] The manufacturing method described below is merely... Figure 9 One embodiment of the method for manufacturing the semiconductor device shown, and Figure 9 The manufacturing method of the semiconductor device shown may not be limited to the manufacturing method described below.

[0158] Reference Figure 10A It can be similar to Figures 2A to 2D As described above, a stacked structure STA including a sacrificial layer and an insulating layer IL, a channel structure CS, a memory layer ML, and a first trench TR1 are formed.

[0159] Subsequently, a conductive pattern CP can be used to replace the sacrificial layer. The step of replacing the sacrificial layer with a conductive pattern CP may include: removing the sacrificial layer through a first trench TR1 to form a conductive pattern layer filling the space created by removing the sacrificial layer, and etching the conductive pattern layer. When the conductive pattern layer is etched, conductive patterns CP that are isolated from each other can be formed. During the etching of the conductive pattern layer, a seventh recess RC7 can be formed, defined by the sidewalls of the conductive pattern CP, the top surface of one insulating layer IL, and the bottom surface of another insulating layer IL. The seventh recess RC7 can be formed between insulating layers IL that are adjacent to each other along the third direction D3.

[0160] Reference Figure 10BThe sixth buffer pattern BP6 can be formed in the seventh recess RC7. The sixth buffer pattern BP6 can be formed between the insulating layers adjacent to each other in the third direction D3. The sixth buffer patterns BP6 can be spaced apart from each other in the third direction D3. The sixth buffer pattern BP6 can include a material that can be oxidized by an oxidation process. In one example, the sixth buffer pattern BP6 can include polysilicon or nitride. The sixth buffer pattern BP6 can have a constant width in the third direction D3. A width of a sidewall of the sixth buffer pattern BP6 that is in contact with the conductive pattern CP in the third direction D3 can be equal to a width of a sidewall of the sixth buffer pattern BP6 that faces a center of the first trench TR1 in the third direction D3.

[0161] Referring to Figure 10C The insulating layer IL can be removed. When the insulating layer IL is removed, a top surface and a bottom surface of the sixth buffer pattern BP6 can be exposed.

[0162] Referring to Figure 10D The sixth buffer pattern BP6 can be oxidized. During the oxidation of the sixth buffer pattern BP6, a volume of the sixth buffer pattern BP6 can increase. When the volume of the sixth buffer pattern BP6 increases, the sixth buffer patterns BP6 that are arranged to be spaced apart from each other in the third direction D3 can be connected to each other in the third direction D3. When the sixth buffer patterns BP6 are oxidized to be connected to each other, a slit insulating layer SI can be formed. When the slit insulating layer SI is formed, an air gap AR can be defined between the conductive patterns CP.

[0163] Since the width of the sixth buffer pattern BP6 in the third direction D3 is constant, a fifth sidewall SW5 and a sixth sidewall SW6 of the fourth intervening portion IN4 of the slit insulating layer SI can be formed symmetrically to each other. Subsequently, a source contact SC (see Figure 9 ) can be formed between the two slit insulating layers SI.

[0164] Figure 11A is a cross-sectional view of a semiconductor device according to one embodiment of the present disclosure. Figure 11B is an enlarged view of the region E shown in Figure 11A .

[0165] The semiconductor device shown in Figure 11A and Figure 11B may be similar to the semiconductor device shown in Figure 9 .

[0166] Referring to Figure 11A and Figure 11B, the semiconductor device can include a stack structure STA having a conductive pattern CP, a channel structure CS, a memory layer ML, and a slit structure SLS. An air gap AR can be defined by the memory layer ML, the conductive pattern CP, and the slit structure SLS. The slit structure SLS can include a source contact SC and a slit insulating layer SI.

[0167] Each slit insulating layer SI can include a third insulating portion IP3 and a fourth insulating portion IP4. The third insulating portion IP3 and the fourth insulating portion IP4 can include the same material or include different materials. In one example, the third insulating portion IP3 and the fourth insulating portion IP4 can include an oxide. In another example, the third insulating portion IP3 can include an oxide, and the fourth insulating portion IP4 can include a nitride. The third insulating portion IP3 can be arranged to be spaced apart from each other in a third direction D3. Each third insulating portion IP3 can be in contact with a sidewall of each conductive pattern CP, respectively. The third insulating portion IP3 can be spaced apart from the source contact SC. The third insulating portion IP3 can include a seventh sidewall SW7 and an eighth sidewall SW8. The seventh sidewall SW7 can be a sidewall facing the air gap AR. The eighth sidewall SW8 can be a sidewall facing the source contact SC. The seventh sidewall SW7 and the eighth sidewall SW8 can be opposite to each other.

[0168] The fourth insulating portion IP4 can be in contact with the plurality of third insulating portions IP3. The fourth insulating portion IP4 can connect the plurality of third insulating portions IP3 spaced apart from each other in the third direction D3. The fourth insulating portion IP4 can cover the seventh sidewall SW7 and the eighth sidewall SW8 of the third insulating portion IP3. A portion of the fourth insulating portion IP4 covering the seventh sidewall SW7 of the third insulating portion IP3 can define the air gap AR. A portion of the fourth insulating portion IP4 covering the eighth sidewall SW8 can be in contact with the source contact SC.

[0169] A portion of the fourth insulating portion IP4 interposed between the third insulating portions IP3 can be defined as a first portion IP4a. The first portion IP4a of the fourth insulating portion IP4 can define the air gap AR and can be in contact with the source contact SC. A portion of the slit insulating layer SI in which a width in the first direction is the smallest can be the first portion IP4a of the fourth insulating portion IP4.

[0170] A process of forming the third insulating portion IP3 and the fourth insulating portion IP4 will be described. A seventh buffer pattern can be formed on the sidewall of the conductive pattern CP, and the third insulating portion IP3 can be formed by oxidizing the seventh buffer pattern. Subsequently, the fourth insulating portion IP4 can be formed on the third insulating portion IP3.

[0171] Figure 12is a block diagram illustrating a configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0172] Referring to Figure 12 The memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0173] The memory device 1120 can include the semiconductor device described above. The memory device 1120 can be a multi-chip package configured with a plurality of flash memory chips.

[0174] The memory controller 1110 is configured to control the memory device 1120, and can include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction code (ECC) circuit 1114, and a memory interface 1115. The SRAM 1111 serves as an operation memory of the CPU 1112, the CPU 1112 performs an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 includes a data exchange protocol for a host connected with the memory system 1100. The ECC circuit 1114 detects and corrects an error included in data read from the memory device 1120, and the memory interface 1115 is interfaced with the memory device 1120. In addition, the memory controller 1110 can further include a ROM or the like for storing code data for interfacing with the host.

[0175] The memory system 1100 configured as described above can be a memory card or a solid state drive (SSD) in which the memory device 1120 is combined with the memory controller 1110. For example, when the memory system 1100 is an SSD, the memory controller 1110 can communicate with an external (e.g., a host) through one of various interface protocols such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA (SATA) protocol, a parallel ATA (PATA) protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol.

[0176] Figure 13 is a block diagram illustrating a configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0177] Referring to Figure 13The computing system 1200 can include a CPU 1220, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260 when the computing system 1200 is a mobile device, a battery for providing an operating voltage to the computing system 1200 can be further included, and an application chipset, a camera image processor (CIS), and a mobile D-RAM, etc. can be further included.

[0178] The memory system 1210 can be configured with a memory device 1212 and a memory controller 1211 similar to the memory device and the memory controller described with reference to Figure 12 The memory system 1210 can be configured with a memory device 1212 and a memory controller 1211 similar to the memory device and the memory controller described with reference to

[0179] In the semiconductor device according to the disclosure, the volume of the air gap between the conductive patterns can be formed to be relatively large, and the parasitic capacitance between the conductive patterns can be minimized.

[0180] In the manufacturing method of the semiconductor device according to the disclosure, the slit insulating layer is formed by oxidizing the buffer pattern so that the volume of the air gap can be formed to be relatively large.

[0181] Embodiments of the disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are used only in explaining the embodiments of the disclosure. Accordingly, the disclosure is not limited to the above-described embodiments, and there can be many variations within the spirit and scope of the disclosure. It will be obvious to those skilled in the art that various modifications can be made based on the technical scope of the disclosure disclosed herein, in addition to the embodiments disclosed herein.

[0182] Unless differently defined, all terms used herein, including technical or scientific terms, have meanings commonly understood by those skilled in the art to which the disclosure belongs. Terms having definitions defined in dictionaries should be understood to have meanings consistent with the context of the relevant technology. Unless explicitly defined in the present application, terms should not be interpreted in an ideal or overly formal manner.

[0183] Cross Reference to Related Applications

[0184] This application claims priority to Korean Patent Application No. 10-2020-0084276, filed on July 8, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A stacked structure comprising conductive patterns spaced apart from each other; A channel structure that penetrates the stacked structure; A slit insulation layer that penetrates the laminated structure; as well as The source contact portion is in contact with the slit insulating layer. An air gap is defined between the conductive patterns. The slit insulation layer includes a first insertion portion covering the sidewall of one of the conductive patterns and a second insertion portion covering one of the air gaps from the side. Wherein, the minimum width of the second insertion portion is less than the minimum width of the first insertion portion. The source contact portion includes a first contact portion covering the first insertion portion of the slit insulation layer and a second contact portion covering the second insertion portion of the slit insulation layer. The interface between the first contact portion of the source electrode contact and the first insertion portion of the slit insulating layer protrudes toward the first contact portion of the source electrode contact.

2. The semiconductor device according to claim 1, wherein, As the second insertion portion approaches the first insertion portion from its center height, the width of the second insertion portion increases.

3. The semiconductor device according to claim 1, wherein, As the width of the first insertion portion approaches the second insertion portion from its center height, the width of the first insertion portion decreases.

4. The semiconductor device according to claim 1, wherein, The width of the second insertion portion is minimum at the center height of the air gap adjacent to the second insertion portion.

5. The semiconductor device according to claim 1, in, The maximum width of the second contact portion is greater than the maximum width of the first contact portion.

6. The semiconductor device according to claim 1, wherein, The second insertion portion includes a second sidewall defining an air gap adjacent to the second insertion portion and a first sidewall opposite to the second sidewall, and The first sidewall and the second sidewall are formed asymmetrically with each other.

7. The semiconductor device according to claim 6, wherein, The first sidewall and the second sidewall are curved.

8. The semiconductor device according to claim 1, further comprising: A memory layer surrounding the channel structure; as well as A protective pattern is disposed between the memory layer and a corresponding conductive pattern.

9. The semiconductor device according to claim 8, wherein, Each of the protective patterns is in contact with the top surface, sidewalls, and bottom surface of the corresponding conductive pattern.

10. The semiconductor device according to claim 8, wherein, The protective pattern is disposed between the air gaps.

11. A semiconductor device comprising: A stacked structure comprising conductive patterns spaced apart from each other; A channel structure that penetrates the stacked structure; A slit insulation layer that penetrates the laminated structure; as well as The source contact portion is in contact with the slit insulating layer. An air gap is defined between the conductive patterns. The slit insulating layer includes a first insertion portion disposed between a conductive pattern in the conductive pattern and the source contact portion, and a second insertion portion disposed between an air gap in the air gap and the source contact portion. The first insertion portion includes a first sidewall that contacts the source contact portion and a second sidewall that contacts one of the conductive patterns in the conductive pattern. The first sidewall protrudes in a direction away from the conductive pattern in the conductive pattern.

12. The semiconductor device according to claim 11, wherein, The first and second sidewalls of the second insertion portion are formed symmetrically to each other.

13. The semiconductor device according to claim 11, wherein, The first and second sidewalls of the second insertion portion are formed asymmetrically with each other.

14. The semiconductor device according to claim 11, in, The sidewall of the source contact is curved to correspond to the first sidewall of the first insertion portion of the slit insulation layer.

15. The semiconductor device according to claim 11, wherein, The slit insulation layer includes a first insulating portion in contact with at least one of the conductive patterns and a second insulating portion covering the sidewalls of the first insulating portion.

16. The semiconductor device according to claim 15, wherein, The slit insulation layer includes multiple first insulation portions. Wherein, the plurality of first insulating portions are spaced apart from each other, and The second insulating portion is connected to the plurality of first insulating portions.

17. The semiconductor device according to claim 15, wherein, The maximum width of the first insulating portion is greater than the maximum width of the second insulating portion.

18. A method for manufacturing a semiconductor device, the method comprising the following steps: This forms a laminated structure consisting of alternating layers of insulating and sacrificial layers; Forming trenches that penetrate the stacked structure; The sacrificial layer is replaced with a conductive pattern; A buffer pattern is formed on the sidewall of the conductive pattern; An air gap is formed by removing the insulating layer; A slit insulation layer is formed to seal the air gap; as well as A source contact portion is formed that contacts the slit insulation layer. The step of forming the slit insulating layer includes the step of oxidizing the buffer pattern. The slit insulation layer includes a first insertion portion covering the sidewall of one of the conductive patterns and a second insertion portion covering one of the air gaps from the side. The source contact portion includes a first contact portion covering the first insertion portion of the slit insulation layer and a second contact portion covering the second insertion portion of the slit insulation layer. The interface between the first contact portion of the source electrode contact and the first insertion portion of the slit insulating layer protrudes toward the first contact portion of the source electrode contact.

19. The method according to claim 18, wherein, The steps for forming the slit insulation layer include the following: The first insulating portion is formed by oxidizing the buffer pattern; and A second insulating portion is deposited on the first insulating portion.

20. The method according to claim 18, wherein, The steps for forming the buffer pattern include the following: An oxide pattern is formed on the sidewall of the insulating layer; and The buffer pattern is formed between the oxide patterns.

21. The method according to claim 20, wherein, The step of forming the oxide pattern includes the following steps: selectively depositing the oxide pattern on the sidewalls of the insulating layer.

22. The method according to claim 20, wherein, The steps for forming the oxide pattern include the following: The first recess is formed by removing a portion of each of the insulating layers via the trench; A seed pattern is formed in the first depression; An initial oxidation pattern is formed on the sidewall of the seed pattern; and The seed pattern and the initial oxidation pattern are oxidized.

23. The method according to claim 22, wherein, The initial oxidation pattern is selectively formed on the sidewalls of the seed pattern.

24. The method of claim 18, further comprising the step of: Forming holes that penetrate the stacked structure; The recess is formed by removing a portion of each of the insulating layers through the holes; A protective pattern is formed in the recess; as well as A memory layer is formed in the hole. The step of removing the insulating layer includes the step of exposing the protective pattern.

25. The method of claim 18, further comprising the step of: Forming holes that penetrate the stacked structure; The recess is formed by removing a portion of each of the insulating layers through the holes; A protective layer is formed in the hole and the recess; as well as A memory layer is formed in the hole. The step of removing the insulating layer includes the step of removing a portion of the protective layer.

26. The method according to claim 18, wherein, The step of forming the buffer pattern includes the following steps: forming the buffer pattern between the insulating layers.

27. The method according to claim 18, wherein, The buffer pattern comprises polycrystalline silicon.

28. The method according to claim 18, wherein, The buffer pattern includes nitrides.

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