communication equipment

Abstract

The embodiment suppresses jitter of a multi-channel communication device. The communication device includes an oscillator (20), a signal generating circuit (30), an insulating element, a receiving circuit, and an output circuit. The oscillator outputs a carrier signal when at least one of a plurality of signals input from the outside is at a first logic level. The signal generating circuit includes a signal generating unit (31) and a driving circuit (32). If the signal generating unit detects a first logic level of a first signal among the plurality of signals, it generates a pulse signal, and adds a carrier signal immediately after the pulse signal. If the first signal is at a second logic level, no carrier signal is added, and a modulation signal is generated using the pulse signal and the carrier signal. The driving circuit amplifies the modulation signal. The insulating element is connected to the output of the driving circuit. The receiving circuit receives the modulation signal output from the driving circuit via the insulating element and demodulates it. The output circuit outputs the signal demodulated by the receiving circuit to the outside.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2020-118437 (filing date: July 9, 2020), the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments relate to a communication device. Background Art

[0003] Electrical insulation elements are well-known components used in communication devices that connect high-voltage devices to low-voltage devices. These elements prevent noise from circulating and inducting between high-voltage and low-voltage devices, ensuring electrical isolation between input and output while transmitting only signals. Examples of the media used by electrical insulation elements for signal transmission include light, electric fields, and magnetic fields.

[0004] For example, an optical coupler is a well-known electrical insulation element that uses optical signals as a signal transmission medium. It includes a light-emitting diode (LED) as a light-generating element and a photodiode (PD) as a light-receiving element. The electrical insulation of an optical coupler is ensured by a resin interposed between the LED and the PD. Therefore, the reliability of the optical coupler's insulation function is high.

[0005] However, when a communication device transmits multiple signals, the optocoupler must have the same number of LEDs and PDs as the signals being transmitted. When multiple LEDs and PDs are installed in a single optocoupler, crosstalk can occur between the transmitted signals. Furthermore, installing multiple LEDs and PDs in an optocoupler complicates assembly, reducing reliability and increasing costs.

[0006] In contrast, electrical insulating elements that use electric fields or magnetic fields as signal transmission media can eliminate the concerns about the above-mentioned optocouplers. Electrical insulating elements that use electric fields or magnetic fields as signal transmission media are also called digital isolators. When an electric field is used as a signal transmission medium, for example, an insulating capacitor having metal plates formed at both ends of an insulating layer can be used. When a magnetic field is used as a signal transmission medium, for example, an insulating transformer having coils formed at both ends of an insulating layer can be used. It is easy to mount multiple insulating capacitors or insulating transformers on the same semiconductor substrate. Therefore, a communication device that transmits multiple signals can suppress costs by using a digital isolator as an electrical insulating element compared to the case of using an optocoupler. Summary of the Invention

[0007] Embodiments suppress jitter in a multi-channel communication device.

[0008] The communication device of the embodiment includes an oscillator, a signal generating circuit, an insulating element, a receiving circuit, and an output circuit. The oscillator outputs a carrier signal when at least one of a plurality of signals input from the outside is at a first logic level. The signal generating circuit includes a signal generating unit and a driving circuit. If the signal generating unit detects the first logic level of a first signal among the plurality of signals, it generates a pulse signal and adds a carrier signal immediately after the pulse signal. If the first signal reaches a second logic level, the carrier signal is not added, and a modulation signal is generated using the pulse signal and the carrier signal. The driving circuit transmits the modulation signal to the insulating element. The insulating element is connected to the output of the driving circuit. The receiving circuit receives the modulation signal output from the driving circuit via the insulating element and demodulates it. The output circuit outputs the signal demodulated by the receiving circuit to the outside. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a block diagram showing an example of the configuration of the communication device according to the first embodiment.

[0010] Figure 2 This is a circuit diagram showing an example of a circuit configuration of an RF generator included in the communication device according to the first embodiment.

[0011] Figure 3 This is a circuit diagram showing an example of a circuit configuration of a signal generating circuit included in the communication device according to the first embodiment.

[0012] Figure 4 This is a circuit diagram showing an example of a circuit configuration of an insulating element included in the communication device according to the first embodiment.

[0013] Figure 5 This is a timing chart showing an example of the modulation operation of the input signal.

[0014] Figure 6 This is a timing chart showing an example of the operation in the communication device according to the first embodiment.

[0015] Figure 7 This is a timing chart showing an example of the operation in the communication device according to the comparative example of the first embodiment.

[0016] Figure 8 This is a block diagram showing an example of the configuration of a communication device according to a first modification of the first embodiment.

[0017] Figure 9 This is a block diagram showing an example of the configuration of a communication device according to a second modification of the first embodiment.

[0018] Figure 10This is a block diagram showing an example of the configuration of a communication device according to a third modification of the first embodiment.

[0019] Figure 11 This is a circuit diagram showing an example of a circuit configuration of a signal generating circuit included in a communication device according to the second embodiment.

[0020] Figure 12 This is a circuit diagram showing an example of a circuit configuration of an insulating element included in a communication device according to the second embodiment.

[0021] Figure 13 This is a timing chart showing an example of the operation in the communication device according to the second embodiment.

[0022] Figure 14 This is a circuit diagram showing an example of a circuit configuration of an insulating element included in a communication device according to a modification of the second embodiment.

[0023] Figure 15 This is a circuit diagram showing an example of a circuit configuration of a signal generating circuit included in a communication device according to a modification of the second embodiment.

[0024] Figure 16 This is a block diagram showing an example of the configuration of a communication device according to the third embodiment.

[0025] Figure 17 This is a circuit diagram showing an example of a circuit configuration of an RF generator included in a communication device according to a first modification of the third embodiment.

[0026] Figure 18 This is a block diagram showing an example of the configuration of a communication device according to a first modification of the third embodiment.

[0027] Figure 19 This is a circuit diagram showing an example of a circuit configuration of an RF generator included in a communication device according to a second modification of the third embodiment.

[0028] Figure 20 This is a block diagram showing an example of the configuration of a communication device according to a second modification of the third embodiment.

[0029] Figure 21 This is a circuit diagram showing an example of a circuit configuration of an RF generator included in a communication device according to a second modification of the third embodiment.

[0030] Figure 22 This is a circuit diagram showing an example of a circuit configuration of an RF generator included in a communication device according to a third modification of the third embodiment.

[0031] Figure 23 This is a circuit diagram showing an example of a circuit configuration of a signal generating circuit included in a communication device according to a fourth embodiment.

[0032] Figure 24 This is a timing chart showing an example of the operation in the communication device according to the fourth embodiment.

[0033] Figure 25 This is a timing chart showing an example of the operation in the communication device according to the fourth embodiment.

[0034] Figure 26 This is a timing chart showing an example of the operation in the communication device according to the fourth embodiment. DETAILED DESCRIPTION

[0035] The following describes the embodiments with reference to the accompanying drawings. Each embodiment exemplifies an apparatus or method for embodying the technical concept of the invention. The drawings are schematic or conceptual diagrams, and the dimensions and ratios in the drawings are not necessarily the same as those in reality. The technical concept of the present invention is not determined by the shape, structure, or arrangement of the components.

[0036] In the following description, components having substantially the same function and structure are denoted by the same reference numerals. The numerals following the characters constituting the reference numerals are referenced by the reference numerals containing the same characters and are used to distinguish between components having the same structure. Similarly, the numerals following the characters constituting the reference numerals are referenced by the reference numerals containing the same characters and are used to distinguish between components having the same structure.

[0037] [1] First embodiment

[0038] The first embodiment relates to a communication device that transmits two signals using an electrical insulating element, that is, a multi-channel communication device. Hereinafter, the communication device 1 according to the first embodiment will be described using an isolation transformer as an example of an electrical insulating element.

[0039] [1-1] Composition

[0040] [1-1-1] Overall Configuration of Communication Device 1

[0041] Figure 1 An example of the configuration of the communication device 1 according to the first embodiment is shown. Figure 1As shown, the communication device 1 according to the first embodiment includes, for example, input circuits 10A and 10B, an RF (Radio Frequency) generator 20, signal generating circuits 30A and 30B, insulating elements 40A and 40B, receiving circuits 50A and 50B, and output circuits 60A and 60B.

[0042] Input circuit 10 is used to input signals from external devices into communication device 1 and includes, for example, a buffer circuit. Input signals IN1 and IN2 are input from external devices to input circuits 10A and 10B, respectively. Input circuit 10A then outputs input signal Vin1 based on input signal IN1 to RF generator 20 and signal generation circuit 30A. Input circuit 10B outputs input signal Vin2 based on input signal IN2 to RF generator 20 and signal generation circuit 30B.

[0043] RF generator 20 is a signal generator such as a ring oscillator circuit. RF generator 20 generates and outputs a carrier signal CS based on input signal Vin1 from input circuit 10A and input signal Vin2 from input circuit 10B. Carrier signal CS is input to signal generating circuits 30A and 30B.

[0044] Signal generation circuit 30 modulates input signal Vin (modulation signal) input from input circuit 10 using carrier signal CS. Signal generation circuit 30 then outputs the modulated electrical signal (modulated signal) to insulating element 40. Specifically, signal generation circuit 30A modulates input signal Vin1 and outputs it to insulating element 40A. Signal generation circuit 30B modulates input signal Vin2 and outputs it to insulating element 40B.

[0045] The insulating element 40 is an electrical insulating element used in the OOK (On-Off Keying) method and includes, for example, an insulating transformer. In the first embodiment, the insulating element 40 utilizes magnetic field coupling to transmit signals. The insulating element 40A transmits the electrical signal input from the signal generating circuit 30A to the receiving circuit 50A. The insulating element 40B transmits the electrical signal input from the signal generating circuit 30B to the receiving circuit 50B.

[0046] Receiving circuit 50 includes a demodulation circuit. Receiving circuit 50A detects and demodulates the electrical signal transmitted from insulating element 40A and outputs it to output circuit 60A. Receiving circuit 50B detects and demodulates the electrical signal transmitted from insulating element 40B and outputs it to output circuit 60B.

[0047] Output circuit 60 is used to output signals transmitted within communication device 1 via insulating element 40 to the outside, and includes, for example, a buffer circuit. Output circuit 60A outputs output signal OUT1 to an external device based on the signal input from receiving circuit 50A. Output circuit 60B outputs output signal OUT2 to an external device based on the signal input from receiving circuit 50B.

[0048] In the configuration of the communication device 1 described above, the group consisting of the input circuit 10A, the signal generating circuit 30A, the insulating element 40A, the receiving circuit 50A, and the output circuit 60A corresponds to the first channel of the communication device 1. Similarly, the group consisting of the input circuit 10B, the signal generating circuit 30B, the insulating element 40B, the receiving circuit 50B, and the output circuit 60B corresponds to the second channel of the communication device 1. Thus, the communication device 1 according to the first embodiment is a two-channel communication device capable of transmitting two types of signals.

[0049] In the communication device 1 according to the first embodiment, for example, the set of input circuits 10A and 10B, RF generator 20, and signal generation circuits 30A and 30B is composed of semiconductor elements mounted on a first substrate. Meanwhile, the set of insulating elements 40A and 40B, receiving circuits 50A and 50B, and output circuits 60A and 60B is composed of semiconductor elements mounted on a second substrate different from the first substrate. The circuits provided on the first substrate and the circuits provided on the second substrate are electrically connected using, for example, bonding wires.

[0050] Hereinafter, the combination of the circuit mounted on the first substrate and the first substrate is referred to as chip CP1, and the combination of the circuit mounted on the second substrate and the second substrate is referred to as chip CP2. For example, the circuit within chip CP1 is connected to ground GND1, and power supply voltage VDD1 is applied to the circuit within chip CP1. The circuit within chip CP2 is connected to ground GND2, and power supply voltage VDD2 is applied to the circuit within chip CP2. For example, one of power supply voltages VDD1 and VDD2 corresponds to a high voltage system, and the other corresponds to a low voltage system.

[0051] [1-1-2] Circuit Structure of Communication Device 1

[0052] Hereinafter, an example of the circuit configuration of each of the RF generator 20 , the signal generation circuit 30 , and the insulating element 40 in the communication device 1 according to the first embodiment will be described in order.

[0053] (Circuit Structure of RF Generator 20)

[0054] Figure 2 FIG. 1 shows an example of a circuit configuration of the RF generator 20 included in the communication device 1 according to the first embodiment. Figure 2As shown, the RF generator 20 in the first embodiment includes, for example, an OR circuit 21 , a NAND circuit 22 , and inverters 23 , 24 , and 25 .

[0055] The first input terminal of OR circuit 21 receives input signal Vin1 output from input circuit 10A. The second input terminal of OR circuit 21 receives input signal Vin2 output from input circuit 10B. The output terminal of OR circuit 21 is connected to the first input terminal of NAND circuit 22. The output terminal of NAND circuit 22 is connected to the input terminal of inverter 23. The output terminal of inverter 23 is connected to the input terminal of inverter 24. The output terminal of inverter 24 is connected to the input terminal of inverter 25 and the second input terminal of NAND circuit 22. The signal output from inverter 25 corresponds to carrier signal CS.

[0056] Here, we briefly describe the method for generating carrier signal CS using RF generator 20. Hereinafter, the node corresponding to the output of NAND circuit 22 will be referred to as "N1." The node corresponding to the output of inverter 23 will be referred to as "N2." The node corresponding to the output of inverter 24 will be referred to as "N3."

[0057] When both input signals Vin1 and Vin2 are at an "L" level, OR circuit 21 outputs an "L" level voltage. Furthermore, NAND circuit 22, having an "L" level voltage input to its first input terminal, outputs an "H" level voltage. Consequently, the voltages at nodes N1, N2, and N3 become "H," "L," and "H," respectively, and inverter 25 outputs an "L" level voltage. Furthermore, when the voltage at node N3 is at an "H" level, the output of NAND circuit 22 remains at an "H" level because the input voltages at the first and second input terminals of NAND circuit 22 differ. Consequently, when both input signals Vin1 and Vin2 are at an "L" level, carrier signal CS remains at an "L" level.

[0058] On the other hand, when at least one of the input signals Vin1 and Vin2 is at an "H" level, OR circuit 21 outputs an "H" level voltage. Furthermore, NAND circuit 22, to which an "H" level voltage is input at its first input terminal, outputs an "L" level voltage when, for example, the voltage at its second input terminal is at an "H" level. Consequently, the voltages at nodes N1, N2, and N3 become "L," "H," and "L" levels, respectively, and inverter 25 outputs an "H" level voltage.

[0059] Furthermore, when the voltage at node N3 reaches an "L" level, an "H" level voltage is input to the first input terminal and an "L" level voltage is input to the second input terminal of NAND circuit 22, so the output voltage of NAND circuit 22 changes from an "L" level to an "H" level. Consequently, the voltages at nodes N1, N2, and N3 reach "H," "L," and "H," respectively, and inverter 25 outputs an "L" level voltage. This operation is repeated while at least one of input signals Vin1 and Vin2 is at an "H" level, causing the output of carrier signal CS to oscillate.

[0060] As described above, the RF generator 20 in the first embodiment can generate the carrier signal CS using the OR signal of the input signals Vin1 and Vin2. However, the circuit configuration of the RF generator 20 described above is merely an example. As long as the RF generator 20 can generate the carrier signal CS when at least one of the input signals Vin1 and Vin2 reaches an "H" level, other circuit configurations are acceptable.

[0061] (Circuit Structure of Signal Generating Circuit 30)

[0062] Figure 3 FIG. 1 shows an example of a circuit configuration of the signal generating circuit 30 included in the communication device 1 according to the first embodiment. Figure 3 As shown, the signal generating circuit 30 in the first embodiment includes, for example, a signal generating unit 31 and a driving unit 32. The signal generating circuit 30 includes, for example, an AND circuit 311, a delay circuit 312, a NAND circuit 313, and an AND circuit 314. The driving unit 32 includes, for example, a driving circuit 321.

[0063] The first input terminal of AND circuit 311 receives input signal Vin (modulation signal). The second input terminal of AND circuit 311 receives input signal Vind, which corresponds to input signal Vin and has been delayed by delay circuit 312. Delay circuit 312 is, for example, an even number of inverters connected in series. Other circuits may also be used as delay circuit 312.

[0064] A first input terminal of NAND circuit 313 is connected to the output terminal of AND circuit 311. A carrier signal CS is input to a second input terminal of NAND circuit 313. An input signal Vin is input to a first input terminal of AND circuit 314. A second input terminal of AND circuit 314 is connected to the output terminal of NAND circuit 313. AND circuit 314 outputs a modulated signal MS. Drive circuit 321 amplifies modulated signal MS and outputs an output voltage Vout.

[0065] The signal generation circuit 30 in the first embodiment described above can modulate the input signal Vin based on the carrier signal CS. For example, the output voltage Vout of the signal generation circuit 30 is at an "L" level when the input signal Vin is at an "L" level, and at a voltage based on the carrier signal CS generated by the RF generator 20 when the input signal Vin is at an "H" level. The circuit configuration of the signal generation circuit 30 described above is merely an example. The signal generation circuit 30 may have another circuit configuration as long as it can modulate the input signal Vin based on the carrier signal CS.

[0066] (Circuit Structure of Insulating Element 40)

[0067] Figure 4 An example of the circuit configuration of the insulating element 40 included in the communication device 1 according to the first embodiment is shown. Figure 4 As shown, the insulating element 40 in the first embodiment includes coils 41 and 42 , for example.

[0068] Coil 41 and coil 42 face each other, separated by an insulating layer ISO. The insulating layer ISO can be made of an oxide film or polyimide. One end of coil 41 is applied with output voltage Vout by signal generation circuit 30 within chip CP1. The other end of coil 41 is grounded, for example, via chip CP1. One end of coil 42 is connected to receiving circuit 50. The other end of coil 42 is grounded, for example, via chip CP2.

[0069] In the insulating element 40 of the first embodiment described above, magnetic field coupling is established between the coil 41 and the coil 42. Consequently, the output voltage Vout applied to the coil 41 is transmitted to the coil 42 via magnetic field coupling, and the transmitted output voltage Vout is applied to the receiving circuit 50. The circuit configuration of the insulating element 40 described above is merely an example. The insulating element 40 may have another circuit configuration as long as it can transmit the output voltage Vout using magnetic field coupling.

[0070] [1-2] Action

[0071] [1-2-1] Regarding input signal modulation

[0072] Communication methods using isolation transformers or isolation capacitors can improve efficiency by modulating input signals to a high-frequency band. Known modulation methods for digital isolators include edge coding and OOK (On-Off Keying). Edge coding is advantageous in terms of current consumption during low-speed communication, while OOK is advantageous in terms of current consumption and transmission delay during high-speed communication. The communication device 1 according to the first embodiment uses the OOK method.

[0073] Figure 5 An example of the basic modulation operation of the input signal is shown. Figure 5 As shown, the input signal is a voltage at either an "L" or "H" level, containing one bit of information. If the input signal is at an "H" level, the RF generator 20 is turned on, and if the input signal is at an "L" level, the RF generator 20 is turned off. Since the RF generator 20 operates based on the input signal being at an "H" level, the carrier signal oscillates during the period when the input signal is at an "H" level. The modulated signal is generated based on the carrier signal during the period when the input signal is at an "H" level. Therefore, during the period when the input signal is at an "H" level, the modulated signal oscillates, for example, similarly to the carrier signal.

[0074] [1-2-2] Operation of Communication Device 1

[0075] Figure 6 An example of a timing chart for the operation of the communication device 1 according to the first embodiment is shown. "MSA" represents the modulated signal corresponding to the input signal Vin1. "MSB" represents the modulated signal corresponding to the input signal Vin2. (1) to (4) represent the phase of the carrier signal CS when the input signal Vin transitions from the "L" level to the "H" level.

[0076] like Figure 6 As shown in (1), when input signal Vin1 is at an "H" level while input signal Vin2 is at an "L" level, RF generator 20 is turned on, and carrier signal CS oscillates. At this time, in signal generation circuit 30A, the voltage at the first input terminal of AND circuit 314 is at an "H" level based on input signal Vin1, and the voltage at the second input terminal of AND circuit 314 is at a level based on carrier signal CS, AND circuit 311, delay circuit 312, and NAND circuit 313.

[0077] Specifically, AND circuit 311 outputs an "L" level signal because an "H" level voltage is applied to its first input terminal and an "L" level voltage is applied to its second input terminal until the delay time td associated with delay circuit 312 has elapsed. Consequently, the voltage at the first input terminal of NAND circuit 313 reaches an "L" level. Therefore, NAND circuit 313 inputs an "H" level voltage to the second input terminal of AND circuit 314, regardless of the state of carrier signal CS. Consequently, the output of AND circuit 314 is maintained at an "H" level.

[0078] Meanwhile, after delay time td, "H"-level voltages are applied to the first and second inputs of AND circuit 311. As a result, AND circuit 311 outputs an "H"-level signal, and the voltage at the first input of NAND circuit 313 reaches an "H" level. Since carrier signal CS is oscillating, NAND circuit 313 inputs an inverted signal of carrier signal CS to the second input of AND circuit 314. As a result, the output of AND circuit 314 oscillates based on carrier signal CS.

[0079] As described above, the output of AND circuit 314, modulated signal MSA, becomes "H" when input signal Vin1 becomes "H" and then remains at "H" until delay time td elapses. Once delay time td has elapsed, modulated signal MSA oscillates based on carrier signal CS. Then, when input signal Vin1 becomes "L," RF generator 20 is turned off, and the oscillation of carrier signal CS and modulated signal MSA ceases.

[0080] like Figure 6 As shown in (2), if the input signal Vin2 becomes "H" level while the input signal Vin1 is "L", the RF generator 20 becomes on and the carrier signal CS oscillates. The operation of the signal generating circuit 30B at this time is the same as Figure 6 The operation of the signal generating circuit 30A in (1) is the same as that in Figure 6 In each of (1) and (2), the carrier signal CS oscillates based on the input signal Vin at the "H" level. That is, since the input signal Vin and the carrier signal CS are synchronized, the phase of the carrier signal CS when the input signal Vin transitions from the "L" level to the "H" level is 0°.

[0081] like Figure 6 As shown in (3), when input signal Vin1 reaches an "H" level while input signal Vin2 is at an "H" level, input signal Vin1 is modulated based on the already oscillating carrier signal CS. In other words, carrier signal CS from RF generator 20 and input signal Vin1 from input circuit 10A become asynchronous. Therefore, depending on the timing of the transition of input signal Vin1 from an "L" level to an "H" level, a phase shift occurs between that timing and the phase of carrier signal CS. Figure 6 (3) shows a case where the phase of the carrier signal CS is 90° when the input signal Vin1 is input.

[0082] In this case, in signal generating circuit 30A, AND circuit 314 immediately outputs an "H" voltage in response to input signal Vin1 going "H." That is, modulated signal MSA goes "H" in response to input signal Vin1 going "H." Furthermore, after delay time td, modulated signal MSA oscillates based on carrier signal CS.

[0083] After both input signals Vin1 and Vin2 reach an "H" level, only input signal Vin2 changes to an "L" level. In this case, the oscillation of the modulated signal MSB stops due to the transition of input signal Vin2 from an "H" level. Meanwhile, since input signal Vin1 remains at an "H" level, RF generator 20 remains on. That is, while either input signal Vin remains at an "H" level, RF generator 20 maintains the oscillation of carrier signal CS.

[0084] like Figure 6 As shown in (4), when input signal Vin2 reaches an "H" level while input signal Vin1 is at an "H" level, input signal Vin2 is modulated based on the already oscillating carrier signal CS. In other words, carrier signal CS from RF generator 20 and input signal Vin2 from input circuit 10B become asynchronous. Figure 6 (4) and Figure 6 Similarly, (3) shows a case where the phase of the carrier signal CS is 90° when the input signal Vin2 is input.

[0085] In this case, in signal generating circuit 30B, AND circuit 314 immediately outputs an "H" voltage in response to input signal Vin2 going "H." That is, modulated signal MSB goes "H" in response to input signal Vin2 going "H." Furthermore, after delay time td, modulated signal MSB oscillates based on carrier signal CS.

[0086] After both input signals Vin1 and Vin2 return to an "H" level, only input signal Vin1 changes to an "L" level. In this case, the oscillation of modulated signal MSA stops due to the transition of input signal Vin1 from an "H" level to an "L" level. On the other hand, since input signal Vin2 remains at an "H" level, RF generator 20 remains on. Subsequently, when input signal Vin2 goes "L", oscillation of modulated signal MSB stops. Furthermore, when input signals Vin1 and Vin2 each go "L", RF generator 20 goes off, causing carrier signal CS to go "L".

[0087] As described above, in the communication device 1 according to the first embodiment, when the input signal Vin reaches an "H" level, the corresponding modulated signal MS immediately reaches an "H" level. Furthermore, after the delay time td has elapsed, that is, after a pulse corresponding to the delay time td has been applied, the modulated signal MS becomes a pulse based on the carrier signal CS.

[0088] [1-3] Effects of the First Embodiment

[0089] According to the communication device 1 according to the first embodiment described above, jitter can be suppressed in a communication device using a single RF generator.

[0090] As a modulation method for communication devices using the OOK scheme, methods utilizing an AND signal between an RF carrier (e.g., carrier signal CS) and an input signal are known. In multi-channel communication devices, it is preferable to provide an RF generator for each channel to generate the RF carrier. However, providing multiple RF generators increases power consumption and chip area. Therefore, to reduce power consumption in multi-channel communication devices, methods are being considered where multiple channels share a single RF generator.

[0091] Here, as a comparative example of the first embodiment, a communication device having multiple inputs uses a single RF generator 20 and uses a signal obtained by performing an AND operation on an input signal Vin and a carrier signal CS as a modulated signal MS. In short, the communication device according to the comparative example of the first embodiment has, for example, Figure 3 The signal generating circuit 30 described in FIG. 3 omits the AND circuit 311 , the delay circuit 312 , and the NAND circuit 313 , and the RF generator 20 is directly connected to the second input terminal of the AND circuit 314 .

[0092] Figure 7 An example of a timing chart showing the operation of the communication device according to the comparative example of the first embodiment is shown. Figure 6 When the input signals Vin1 and Vin2 become "H" level at the same time, the RF generator 20 operates using the AND signal of the input signals Vin1 and Vin2. Figure 7 The modulated signals MSA and MSB are shown.

[0093] like Figure 7As shown, when either one of the input signals Vin1 and Vin2 changes to "H" level from the state where both the input signals Vin1 and Vin2 are at "L" level, for example, the modulated signal MSA or MSB oscillates in the same manner as the carrier signal CS. Figure 7 As shown in (1) and (2), when the input signal Vin is synchronized with the carrier signal CS, the phase of the carrier signal CS at the timing when the input signal Vin transitions from the “L” level to the “H” level is 0°.

[0094] On the other hand, Figure 7 As shown in (3) and (4), when one input signal Vin is at an "H" level and the other input signal Vin transitions from an "L" level to an "H" level, the input signal Vin and the carrier signal CS become asynchronous. In this case, the timing of the input signal Vin transitioning from an "L" level to an "H" level causes a phase shift between that timing and the phase of the carrier signal CS. Figure 7 (3) shows the case where the phase of the carrier signal CS is 90° when the input signal Vin1 is input. Figure 7 (4) shows a case where the phase of the carrier signal CS is 90° when the input signal Vin2 is input.

[0095] In the communication device 1 according to the comparative example of the first embodiment, when the transition timing of the input signal Vin is synchronized with the carrier signal CS, that is, when the input signal Vin is input while the RF generator 20 is in the off state, the rising waveform of the carrier signal CS and the rising waveform of the modulated signal MS can be made substantially identical. In this case, the communication device 1 can make the waveforms of the output signals OUT1 and OUT2 substantially identical.

[0096] On the other hand, in the communication device 1 according to the comparative example of the first embodiment, when the input signal Vin is input while the RF generator 20 is in the on state, the transition timing of the input signal Vin is not synchronized with the carrier signal CS. This causes a phase shift between the rising edge of the input signal Vin and the phase of the carrier signal CS. This phase shift between the rising edge of the input signal Vin and the carrier signal CS causes variations in the voltage value of the carrier signal CS input to the AND circuit 314, resulting in a random waveform shape in the rising edge of the modulated signal MS. This variation in the waveform shape of the modulated signal MS is reflected in the waveform variations of the output signals OUT1 and OUT2. Furthermore, variations in the waveform shape of the modulated signal MS based on the timing of the input signal Vin and the carrier signal CS can cause jitter and reduce the operational stability of the receiving circuit 50.

[0097] In contrast, the communication device 1 according to the first embodiment utilizes a signal generation circuit 30 having a delay circuit 312 to modulate the input signal Vin. In short, the communication device 1 according to the first embodiment includes an AND circuit 311 having an input terminal receiving the input signal Vin and a second input terminal receiving the input signal Vin via the delay circuit 312; and a NAND circuit 313 having a first input terminal connected to the output of the AND circuit 311, a second input terminal connected to the output of the RF generator 20, and an output terminal connected to the second input terminal of the AND circuit 314.

[0098] In the signal generating circuit 30 of the first embodiment, when the input signal Vin reaches an "H" level, the AND circuit 314 sets the modulated signal MS to an "H" level, regardless of the state of the carrier signal CS. Furthermore, the RF generator 20 is turned on in response to the input signal Vin. Meanwhile, the AND circuit 311, the delay circuit 312, and the NAND circuit 313 delay the input of the signal oscillating based on the carrier signal CS to the AND circuit 314. Therefore, the modulated signal MS is maintained at an "H" level from the time the input signal Vin reaches an "H" level until the delay time td associated with the delay circuit 312 has elapsed. Furthermore, after the delay time td has elapsed, the output of the AND circuit 311 reaches an "H" level, and the NAND circuit 313 outputs the signal oscillating based on the carrier signal CS. As a result, the input signal Vin is modulated based on the carrier signal CS after the delay time td has elapsed since it reached an "H" level.

[0099] As described above, the communication device 1 according to the first embodiment causes the modulated signal MS to be at an "H" level based on the input signal Vin, regardless of whether the RF generator 20 is turned on or off. Specifically, unlike the comparative example, the communication device 1 according to the first embodiment maintains the same rising waveform of the modulated signal MS regardless of whether the input signal Vin is synchronized with the carrier signal CS or not.

[0100] Thus, in the communication device 1 according to the first embodiment, since variations in the rise of the modulated signal MS can be suppressed, variations in the waveforms of the output signals OUT1 and OUT2 are suppressed. Furthermore, since the communication device 1 according to the first embodiment can output a signal oscillated based on the carrier signal CS to the AND circuit 314 after the delay time td of the delay circuit 312 has elapsed, it can perform OOK communication similar to the comparative example.

[0101] As a result, the communication device 1 according to the first embodiment can suppress jitter in the output signal OUT and stabilize the operation of the receiving circuit 50. Therefore, the communication device 1 according to the first embodiment can transmit high-quality signals using a single RF carrier generation circuit in a multi-channel digital isolator that uses the OOK method for signal transmission. Furthermore, because the communication device 1 according to the first embodiment operates multiple channels using only a single RF generator 20, power consumption can be suppressed and the chip area can be reduced.

[0102] Furthermore, as described above, the communication device 1 according to the first embodiment synchronously uses the carrier signal CS associated with each isolation device. Therefore, the communication device 1 according to the first embodiment can adjust the phase of each isolation device. By adjusting the phase of each isolation device, the communication device 1 according to the first embodiment can suppress EMI (ElectroMagneticInterference).

[0103] [1-4] Modification of the First Embodiment

[0104] The communication device 1 according to the first embodiment described above can be modified in various ways. Hereinafter, a first modification, a second modification, and a third modification of the first embodiment will be described, with reference to differences from the first embodiment.

[0105] [1-4-1] First Modification of the First Embodiment

[0106] Figure 8 An example of the configuration of the communication device 1 according to the first modification of the first embodiment is shown. Figure 8 As shown, the communication device 1 according to the first modification of the first embodiment differs from the first embodiment in the combination of the circuits included in the chip CP1 and the circuits included in the chip CP2.

[0107] Specifically, in the communication device 1 according to the first modified example of the first embodiment, the set of input circuits 10A and 10B, RF generator 20, signal generation circuits 30A and 30B, and insulating elements 40A and 40B is mounted on chip CP1. Meanwhile, the set of receiving circuits 50A and 50B, and output circuits 60A and 60B is mounted on chip CP2.

[0108] In this manner, in communication device 1, insulating elements 40A and 40B can be mounted on chip CP1 instead of chip CP2. Regardless of whether insulating elements 40A and 40B are mounted on chips CP1 or CP2, communication device 1 can achieve the same effects as in the first embodiment. This configuration of communication device 1 in which one insulating element 40 is provided for each channel and one insulating element 40 is mounted on either chip CP1 or CP2 is also referred to as a single-insulation configuration.

[0109] [1-4-2] Second Modification of the First Embodiment

[0110] Figure 9 An example of the configuration of the communication device 1 according to the second modification of the first embodiment is shown. Figure 9 As shown, insulating elements 40A and 40B may be mounted on both chips CP1 and CP2.

[0111] Specifically, in the communication device 1 according to the second modified example of the first embodiment, a set of input circuits 10A and 10B, an RF generator 20, signal generation circuits 30A and 30B, and insulating elements 40A-1 and 40B-1 is mounted on chip CP1. Meanwhile, a set of insulating elements 40A-2 and 40B-2, receiving circuits 50A and 50B, and output circuits 60A and 60B is mounted on chip CP2.

[0112] Furthermore, insulating elements 40A-1 and 40B-2 are connected in series between signal generating circuit 30A and receiving circuit 50A. Insulating elements 40B-1 and 40B-2 are connected in series between signal generating circuit 30B and receiving circuit 50B. In other words, insulating element 40 of chip CP1 and insulating element 40 of chip CP2 are connected in series between signal generating circuit 30 within chip CP1 and receiving circuit 50 within chip CP2. This configuration of communication device 1 in which two insulating elements 40 are provided per channel and insulating elements 40 are installed on both chips CP1 and CP2 is also referred to as a double-insulation configuration.

[0113] [1-4-3] Third Modification of the First Embodiment

[0114] Figure 10 An example of the configuration of the communication device 1 according to the third modified example of the first embodiment is shown. Figure 10 As shown, the communication device 1 involved in the third variant of the first embodiment has a structure in which input circuits 10C and 10D, signal generating circuits 30C and 30D, insulating elements 40C and 40D, receiving circuits 50C and 50D, and output circuits 60C and 60D are added to the communication device 1 involved in the first embodiment.

[0115] Input circuits 10C and 10D receive input signals IN3 and IN4 from external devices, respectively. Furthermore, input circuits 10C and 10D output input signals Vin3 and Vin4, respectively. Input signal Vin3 is input to RF generator 20 and signal generation circuit 30C. Input signal Vin4 is input to RF generator 20 and signal generation circuit 30D.

[0116] In the RF generator 20 of the third modified example of the first embodiment, although not shown in the figure, the first, second, third, and fourth input terminals of the OR circuit 21 receive input signals Vin1, Vin2, Vin3, and Vin4, respectively. Furthermore, the RF generator 20 of the third modified example of the first embodiment generates and outputs a carrier signal CS based on the input signals Vin1, Vin2, Vin3, and Vin4. The remaining configuration and operation of the RF generator 20 of the third modified example of the first embodiment are the same as those of the first embodiment.

[0117] Signal generation circuit 30C modulates input signal Vin3 and outputs it to insulating element 40C. Signal generation circuit 30D modulates input signal Vin4 and outputs it to insulating element 40D. Insulating element 40C transmits the electrical signal input from signal generation circuit 30C to receiving circuit 50C. Insulating element 40D transmits the electrical signal input from signal generation circuit 30D to receiving circuit 50D.

[0118] Receiving circuit 50C demodulates the electrical signal transmitted from insulating element 40C and outputs it to output circuit 60C. Receiving circuit 50D demodulates the electrical signal transmitted from insulating element 40D and outputs it to output circuit 60D. Output circuit 60C outputs output signal OUT3 to an external device based on the signal input from receiving circuit 50C. Output circuit 60D outputs output signal OUT4 to an external device based on the signal input from receiving circuit 50D. The remaining configuration of communication device 1 according to the third modified example of the first embodiment is the same as that of the first embodiment.

[0119] As described above, the communication device 1 according to the third variation of the first embodiment includes four sets (channels) of input circuits 10, signal generation circuits 30, insulation elements 40, receiving circuits 50, and output circuits 60. Furthermore, a single RF generator 20 is shared by the signal generation circuits 30 included in each channel. Thus, the RF generator 20 in the first embodiment can be shared by four channels or by N channels (N is an integer greater than or equal to 3). By operating the RF generator 20 based on an OR signal of the N input signals, the communication device 1 can achieve the same effects as the first embodiment.

[0120] [2] Second embodiment

[0121] The communication device 2 according to the second embodiment has a configuration in which a signal generating circuit 30 generates and outputs a differential signal. Hereinafter, the communication device 2 according to the second embodiment will be described with respect to points that are different from the first embodiment.

[0122] [2-1] Composition

[0123] Figure 11 FIG. 2 shows an example of a circuit configuration of the signal generating circuit 30 included in the communication device 2 according to the second embodiment. Figure 11 As shown, the signal generating circuit 30 in the second embodiment has a structure in which an inverter 315 and an AND circuit 316 are added to the signal generating part 31, and the driving circuit 321 of the driving part 32 is replaced by transistors 322, 323, 324 and 325, and a current source 326, compared to the signal generating circuit 30 in the first embodiment.

[0124] The input terminal of inverter 315 is connected to the output terminal of NAND circuit 313. The first input terminal of AND circuit 316 receives input signal Vin. The second input terminal of AND circuit 316 is connected to the output terminal of inverter 315. AND circuits 314 and 316 output modulated signals MS1 and MS2, respectively. Modulated signals MS1 and MS2 are complementary, for example, corresponding to positive and negative phase signals, respectively.

[0125] Transistors 322 and 323 are, for example, P-type MOS transistors. Power supply voltage VDD1 is applied to the sources of each of transistors 322 and 323. The gate of transistor 322 is connected to the output of AND circuit 316. The gate of transistor 323 is connected to the output of AND circuit 314.

[0126] Transistors 324 and 325 are, for example, N-type MOS transistors. The drain of transistor 324 is connected to the drain of transistor 322. The drain of transistor 325 is connected to the drain of transistor 323. The gate of transistor 324 is connected to the output of AND circuit 316. The gate of transistor 325 is connected to the output of AND circuit 314.

[0127] The input terminal of the current source 326 is connected to the sources of the transistors 324 and 325. The output terminal of the current source 326 is connected to the ground GND1. Thus, the current source 326 maintains the sum of the currents flowing through the transistors 322 and 324 and the currents flowing through the transistors 323 and 325 constant.

[0128] In the signal generating circuit 30 of the second embodiment described above, output current Iout1 is output from the node between transistors 323 and 325, and output current Iout2 is output from the node between transistors 322 and 324. Output currents Iout1 and Iout2 correspond to differential signals, which are input to the insulating element 40.

[0129] In other words, the signal generating unit 31 of the signal generating circuit 30 outputs a differential output voltage based on the input signal Vin from the input circuit 10 and the carrier signal CS from the RF generator 20. Furthermore, the driver 32 of the signal generating circuit 30 transmits this differential output voltage to the insulating element 40. In the second embodiment, as a typical example for driving an insulating transformer, the driver 32 of the signal generating circuit 30 is an H-bridge type with current limiting.

[0130] Figure 12 An example of a circuit configuration of the insulating element 40 included in the communication device 2 according to the second embodiment is shown. Figure 12 As shown, the insulating element 40 in the second embodiment is different from that in the first embodiment in connection with the coils 41 and 42 .

[0131] Specifically, the signal generating circuit 30 in chip CP1 supplies output current Iout1 to one end of coil 41 and output current Iout2 to the other end of coil 41. One end and the other end of coil 42 are connected to receiving circuit 50.

[0132] In the insulating element 40 of the second embodiment described above, as in the first embodiment, magnetic field coupling is formed between the coils 41 and 42. Specifically, such an insulating transformer generates a magnetic field when current is input. The direction of this magnetic field changes as the path through which current flows is switched between the path through which current flows when transistors 323 and 324 are turned on and the path through which current flows when transistors 322 and 325 are turned on.

[0133] Thus, the voltage based on the output currents Iout1 and Iout2 applied to coil 41 is transmitted to coil 42 through magnetic field coupling, and the transmitted voltage is applied to receiving circuit 50. In other words, insulating element 40 can transmit the modulated signal based on the principle of electromagnetic induction between coils 41 and 42, and apply the voltage to receiving circuit 50. Furthermore, receiving circuit 50 demodulates the voltage based on the voltages at one end and the other end of coil 42 and outputs it to output circuit 60. The remaining configuration of communication device 2 according to the second embodiment is the same as that of the first embodiment.

[0134] [2-2] Action

[0135] Figure 13 An example of a timing chart showing the operation of the communication device 2 according to the second embodiment is shown. Figure 6 Input signals Vin1 and Vin2 reach the "H" level at the same time. "MS1A" and "MS2A" represent the positive-phase modulated signal MS and the negative-phase modulated signal MS, respectively, for input signal Vin1. "MS1B" and "MS2B" represent the positive-phase modulated signal MS and the negative-phase modulated signal MS, respectively, for input signal Vin2.

[0136] like Figure 13 As shown, in the second embodiment, the positive-phase modulated signal MS1A for the input signal Vin1 and the positive-phase modulated signal MS1B for the input signal Vin2 change in the same manner as the modulated signals MSA and MSB described in the first embodiment, respectively. On the other hand, the negative-phase modulated signal MS2A for the input signal Vin1 and the negative-phase modulated signal MS2B for the input signal Vin2 become inverted signals of the modulated signals MS1A and MS1B, respectively.

[0137] Simply put, AND circuit 314, which corresponds to the positive direction, operates similarly to AND circuit 314 of the first embodiment. Furthermore, AND circuit 316, which corresponds to the negative direction, receives input signal Vin at its first input terminal and a signal obtained by inverting the output of NAND circuit 313 via inverter 315 at its second input terminal. In other words, the same signal is input to the first input terminal of AND circuit 314 and the first input terminal of AND circuit 316. Meanwhile, inverted signals are input to the second input terminals of AND circuit 314 and the second input terminal of AND circuit 316. As a result, AND circuit 316 outputs the inverted signal of AND circuit 314.

[0138] Furthermore, in the communication device 2 according to the second embodiment, when the input signal Vin is at an "L" level, AND circuits 314 and 316 each output an "L" level signal. Consequently, the current path between the power supply and ground is interrupted in the driver 32 of the signal generation circuit 30. As a result, the driver 32 of the signal generation circuit 30 stops applying voltage to the insulating element 40. The rest of the operation of the communication device 2 according to the second embodiment is the same as that of the first embodiment.

[0139] [2-3] Effects of the Second Embodiment

[0140] When driving the insulating element 40 using an H-bridge circuit, as in the communication device 2 according to the second embodiment, a differential signal is required. However, when the input signal Vin is at an "L" level, applying current and voltage to the insulating element 40 increases power consumption and generates noise, which is not desirable.

[0141] In contrast, when the input signal Vin is at an "L" level, the communication device 2 according to the second embodiment sets both the positive-phase voltage of the modulated signal (i.e., modulated signal MS1) and the negative-phase voltage of the modulated signal (i.e., modulated signal MS2) to an "L" level. This allows the communication device 2 according to the second embodiment to suppress power consumption and noise when driving the insulating element 40 via the H-bridge circuit.

[0142] Furthermore, similar to the first embodiment, the communication device 2 according to the second embodiment maintains a constant rising waveform of the positive-phase modulated signal MS1, regardless of whether the input signal Vin and the carrier signal CS are synchronized. Furthermore, because the modulated signal MS2 used to drive the H-bridge circuit is an inverted version of the modulated signal MS1, it maintains an "L" level when the input signal Vin reaches an "H" level. This also suppresses the generation of noise in the modulated signal MS2. Consequently, the communication device 2 according to the second embodiment can suppress jitter in the output signal of the signal generating circuit 30, thereby improving operational stability.

[0143] [2-4] Modification of the Second Embodiment

[0144] The communication device 2 according to the second embodiment can be modified in various ways. For example, the signal generation circuit 30 can also have a circuit configuration that causes the modulated signals MS1 and MS2 to be at an "H" level when the input signal Vin is at an "L" level. In this case, for example, the AND circuits 314 and 316 can be replaced with NAND circuits. In this case, the communication device 2 can also achieve the same effects as the second embodiment.

[0145] In addition, the communication device 2 according to the second embodiment can be combined with the third modification example of the first embodiment. Figure 14 FIG. 4 shows an example of a circuit configuration of the insulating element 40 included in the communication device 2 according to a modification of the second embodiment. Figure 14 As shown, the insulating element 40 in the modified example of the second embodiment has a configuration in which the coils 41 and 42 in the second embodiment are replaced with capacitors 43 and 44 .

[0146] Specifically, output current Iout1 is applied to one electrode of capacitor 43 by signal generation circuit 30 within chip CP1. The other electrode of capacitor 43 is connected to one end of receiving circuit 50. Output current Iout2 is supplied to one electrode of capacitor 44 by signal generation circuit 30 within chip CP1. The other electrode of capacitor 44 is connected to the other end of receiving circuit 50. In this case, the insulator provided between one electrode and the other electrode of capacitor 43 and the insulator provided between one electrode and the other electrode of capacitor 44 correspond to insulator layer ISO, respectively.

[0147] In the insulating element 40 of the modified example of the second embodiment, electric field coupling is formed between one electrode and the other electrode of the capacitor 43, and between one electrode and the other electrode of the capacitor 44. Consequently, the voltage based on the output current Iout1 supplied to one electrode of the capacitor 43 is transmitted to the other electrode of the capacitor 43 through electric field coupling, and the transmitted output voltage Vout is applied to one end of the receiving circuit 50. Similarly, the voltage based on the output current Iout2 supplied to one electrode of the capacitor 44 is transmitted to the other electrode of the capacitor 44 through electric field coupling, and the transmitted output voltage Vout is applied to the other end of the receiving circuit 50.

[0148] Thus, the insulating element 40 used in the communication device 2 according to the second embodiment can be an insulating capacitor rather than an insulating transformer. Even when using an insulating capacitor as the insulating element 40, the communication device 2 can achieve the same effects as the second embodiment. The circuit structure of the insulating element 40 described above is merely an example. The insulating element 40 may have other circuit structures as long as it can transmit the output currents Iout1 and Iout2 using electric field coupling.

[0149] Figure 15 FIG. 1 shows an example of a circuit configuration of a signal generating circuit 30 included in the communication device 2 according to a modification of the second embodiment. Figure 15 As shown, the signal generating circuit 30 in the modification of the second embodiment has a configuration in which the current source 326 is omitted from the signal generating circuit 30 in the second embodiment, using capacitive coupling with the insulating element 40. Specifically, the sources of the transistors 324 and 325 are connected to the ground GND1.

[0150] In this manner, when using an insulating capacitor as the insulating element, for example, the driver 32 of the signal generating circuit 30 uses an inverter circuit. Furthermore, the insulating capacitor (capacitors 43 and 44) ​​within the insulating element 40 is driven by the voltage of the inverter circuit. The remaining configuration and operation of the communication device 2 according to the modified example of the second embodiment are the same as those of the second embodiment. Thus, the communication device 2 according to the modified example of the second embodiment can achieve the same effects as the second embodiment.

[0151] [3] Third embodiment

[0152] The communication device 3 according to the third embodiment has a configuration in which an RF generator 20 generates and outputs a plurality of types of carrier signals CS. Hereinafter, the communication device 3 according to the third embodiment will be described with respect to differences from the first and second embodiments.

[0153] [3-1] Composition

[0154] Figure 16 An example of the configuration of the communication device 3 according to the third embodiment is shown. Figure 16 As shown, the communication device 3 according to the third embodiment has four channels, similar to the third modification of the first embodiment. Furthermore, the communication device 3 according to the third embodiment differs from the third modification of the first embodiment in that the RF generator 20 outputs four types of carrier signals CS.

[0155] Specifically, the RF generator 20 of the third embodiment generates and outputs carrier signals CS1, CS2, CS3, and CS4 based on an input signal Vin1 from an input circuit 10A, an input signal Vin2 from an input circuit 10B, an input signal Vin3 from an input circuit 10C, and an input signal Vin4 from an input circuit 10D. The carrier signals CS1, CS2, CS3, and CS4 are input to signal generating circuits 30A, 30B, 30C, and 30D, respectively.

[0156] Figure 17 FIG. 1 shows an example of a circuit configuration of the RF generator 20 included in the communication device 3 according to the third embodiment. Figure 17 As shown, for example, the signal output from node N1 corresponds to carrier signal CS4. The signal output from node N2 corresponds to carrier signal CS2. The signal output from node N3 corresponds to carrier signal CS1. The signal output from inverter 25 corresponds to carrier signal CS3.

[0157] In the RF generator 20 described above, the phases of carrier signals CS1 to CS4 differ from one another. In the third embodiment, the distribution of carrier signal CS to nodes N1, N2, and N3 and the output of the inverter can be arbitrarily modified. The remaining configuration of the communication device 3 according to the third embodiment is the same as that of the third modified example of the first embodiment.

[0158] [3-2] Effects of the Third Embodiment

[0159] In a communication device capable of inputting N-bit signals, N signal generation circuits 30 operate synchronously, and synchronized carrier signals flow through N insulating elements 40. As a result, the EMI radiated from the signal generation circuits 30 and insulating elements 40 is also multiplied by N. In the first and second embodiments, the signals (pulses) output by each signal generation circuit 30 are completely synchronized with the carrier signal CS. As a method for improving EMI, varying the phase of the driving between the multiple insulating elements 40 can be considered.

[0160] To address this issue, the communication device 3 according to the third embodiment includes an RF generator 20 capable of generating multiple types of carrier signals CS. In short, the RF generator 20 of the third embodiment extracts four types of carrier signals CS1 to CS4 from four different nodes among a plurality of nodes connected to any of the series-connected inverters 23 to 25. Signal generation circuits 30A, 30B, 30C, and 30D modulate the input signal Vin using carrier signals CS1, CS2, CS3, and CS4, respectively, to drive the corresponding insulating elements 40.

[0161] Here, the carrier signal flowing through insulating element x (corresponding to insulating element 40, where x is an integer from 1 to 4) is represented by Ax sin(ω0 t + φx). In this case, the EMI signal radiated from the four insulating elements is expressed as shown in the following equation (1). Here, ω0 corresponds to the oscillation angular frequency of RF generator 20. Ax corresponds to the one-sided amplitude of the carrier signal flowing through insulating element x.

[0162]

[0163] In formula (1), when φ1 = 0 [rad], φ2 = 2π / 3 [rad], φ3 = π [rad], and φ4 = 4π / 3 [rad]. Furthermore, the composite amplitude A in formula (1) is expressed as formula (2A) below, and the phase φ in formula (1) is expressed as formula (2B) below.

[0164]

[0165]

[0166] When φ1 = 0 [rad], φ2 = 2π / 3 [rad], φ3 = π [rad], and φ4 = 4π / 3 [rad], and A1 = 0 and A2 = A3 = A4 = 1, the maximum combined amplitude A = 2. On the other hand, when φ1 = φ2 = φ3 = φ4 = 0 [rad], and A1 = A2 = A3 = A4 = 1, the maximum combined amplitude A = 4. Comparing these cases, the communication device 3 according to the third embodiment can halve the combined amplitude A by setting φ1 = 0 [rad], φ2 = 2π / 3 [rad], φ3 = π [rad], and φ4 = 4π / 3 [rad], thereby improving EMI by 6 dB.

[0167] Based on the same discussion, the discussion about the EMI of the double wave can also be carried out. When considering the EMI of the higher harmonic wave, for example, the formula (1) is rewritten as the following formula (3A).

[0168]

[0169] That is, for the doubled wave, ω = 2ω0. Therefore, the phase for the doubled wave is doubled compared to the fundamental wave. Considering ω = nω0 as the Nth-fold wave, the carrier signal flowing through the insulating element x is expressed as shown in the following equation (3B).

[0170]

[0171] The combined amplitude A of the equation (3B) is expressed as the following equation (4A), and the phase φ of the equation (3B) is expressed as the following equation (4B).

[0172]

[0173]

[0174] When φ1 = 0 [rad], φ2 = 2π / 3 [rad], φ3 = π [rad], and φ4 = 4π / 3 [rad], and A1 = A3 = 1 and A2 = A4 = 1, the maximum combined amplitude A = 2. On the other hand, when φ1 = φ2 = φ3 = φ4 = 0 [rad], and A1 = A2 = A3 = A4 = 1, the maximum combined amplitude A = 4. Comparing these cases, the communication device 3 according to the third embodiment can halve the combined amplitude A by setting φ1 = 0 [rad], φ2 = 2π / 3 [rad], φ3 = π [rad], and φ4 = 4π / 3 [rad], similarly to the case for the fundamental wave, and can improve harmonic EMI by 6 dB.

[0175] [3-3] Modification of the Third Embodiment

[0176] The communication device 3 described above in the third embodiment is capable of various variations. For example, the third embodiment illustrates the use of four carrier signals with different phases: φ1 = 0 [rad], φ2 = 2π / 3 [rad], φ3 = π [rad], and φ4 = 4π / 3 [rad]. However, the present invention is not limited to this embodiment. The communication device 3 can also improve harmonic EMI even when using carrier signals other than the four types. The following describes the differences between the first and second variations of the third embodiment and the third embodiment.

[0177] [3-3-1] First Modification of the Third Embodiment

[0178] Figure 18 An example of the configuration of the communication device 3 according to the first modified example of the third embodiment is shown. Figure 18 As shown, the communication device 3 according to the first modified example of the third embodiment is different from the third embodiment in that the RF generator 20 outputs three types of carrier signals CS.

[0179] Specifically, the RF generator 20 in the first modified example of the third embodiment generates and outputs carrier signals CS1, CS2, and CS3 based on input signal Vin1 from input circuit 10A, input signal Vin2 from input circuit 10B, input signal Vin3 from input circuit 10C, and input signal Vin4 from input circuit 10D. For example, carrier signal CS1 is input to signal generating circuits 30A and 30B. Carrier signals CS2 and CS3 are input to signal generating circuits 30C and 30D, respectively.

[0180] Figure 19 FIG. 1 shows an example of a circuit configuration of the RF generator 20 included in the communication device 3 according to the first modified example of the third embodiment. Figure 19 As shown, the RF generator 20 in the first modified example of the third embodiment has a configuration in which the inverter 25 is omitted from the RF generator 20 in the first embodiment, and outputs a plurality of carrier signals CS from a plurality of nodes.

[0181] Specifically, in the first modified example of the third embodiment, for example, the signal output from node N1 corresponds to carrier signal CS3. The signal output from node N2 corresponds to carrier signal CS2. The signal output from node N3 corresponds to carrier signal CS1. In the first modified example of the third embodiment, the distribution of carrier signal CS to nodes N1, N2, and N3 can be arbitrarily changed. The remaining configuration of the communication device 3 according to the first modified example of the third embodiment is the same as that of the third embodiment.

[0182] In the communication device 3 according to the first modified example of the third embodiment described above, φ1 = φ2 = 0 [rad], φ3 = 2π / 3 [rad], and φ4 = 4π / 3 [rad]. Thus, similar to the third embodiment, the communication device 3 according to the first modified example of the third embodiment can improve the EMI performance of the fundamental wave and the doubled wave by 6 dB compared to the case where φ1 = φ2 = φ3 = φ4 = 0 [rad].

[0183] Furthermore, in the first modified example of the third embodiment, a case where carrier signal CS1 is input to two signal generating circuits 30A and 30B is illustrated. However, another carrier signal CS may be input to both signal generating circuits 30A and 30B. When carrier signal CS2 is input to signal generating circuits 30A and 30B, φ1 = 0 [rad], φ2 = φ3 = 2π / 3 [rad], and φ4 = 4π / 3 [rad]. When carrier signal CS3 is input to signal generating circuits 30A and 30B, φ1 = 0 [rad], φ2 = 2π / 3 [rad], and φ3 = φ4 = 4π / 3 [rad]. In either case, communication device 3 can achieve a 6dB improvement in EMI performance for the fundamental wave and the doubled wave, similar to the third embodiment.

[0184] [3-3-2] Second Modification of the Third Embodiment

[0185] Figure 20 An example of the configuration of the communication device 3 according to the second modified example of the third embodiment is shown. Figure 20 As shown, the communication device 3 according to the second modification of the third embodiment is different from the third embodiment in that the RF generator 20 outputs two types of carrier signals CS.

[0186] Specifically, the RF generator 20 in the second modified example of the third embodiment generates and outputs carrier signals CS1 and CS2 based on input signal Vin1 from input circuit 10A, input signal Vin2 from input circuit 10B, input signal Vin3 from input circuit 10C, and input signal Vin4 from input circuit 10D. For example, carrier signal CS1 is input to signal generating circuits 30A and 30B. Carrier signal CS2 is input to signal generating circuits 30C and 30D.

[0187] Figure 21 FIG. 2 shows an example of a circuit configuration of the RF generator 20 included in the communication device 3 according to the second modified example of the third embodiment. Figure 21 As shown, the RF generator 20 in the second modified example of the third embodiment has a configuration in which the output of the carrier signal CS from the node N2 is omitted, compared to the RF generator 20 in the first modified example of the third embodiment.

[0188] In the second modified example of the third embodiment, for example, the signal output from node N1 corresponds to carrier signal CS2. The signal output from node N3 corresponds to carrier signal CS1. In the second modified example of the third embodiment, the distribution of carrier signal CS to nodes N1 and N3 can be arbitrarily changed. The remaining configuration of the communication device 3 according to the second modified example of the third embodiment is the same as that of the first modified example of the third embodiment.

[0189] In the communication device 3 according to the second modified example of the third embodiment described above, φ1 = φ2 = 0 [rad] and φ3 = φ4 = 2π / 3 [rad]. Thus, similar to the third embodiment, the communication device 3 according to the second modified example of the third embodiment can improve the EMI performance of the fundamental wave and the doubled wave by 6 dB compared to the case where φ1 = φ2 = φ3 = φ4 = 0 [rad].

[0190] [3-3-3] Third Modification of the Third Embodiment

[0191] Figure 22 FIG. 2 shows an example of a circuit configuration of the RF generator 20 included in the communication device 3 according to the third modification of the third embodiment. Figure 22 As shown, the RF generator 20 in the third modified example of the third embodiment has a configuration in which the output of the carrier signal CS from the node N1 is omitted compared to the RF generator 20 in the first modified example of the third embodiment.

[0192] In the third variation of the third embodiment, for example, the signal output from node N2 corresponds to carrier signal CS1. The signal output from node N3 corresponds to carrier signal CS2. In the third variation of the third embodiment, the distribution of carrier signal CS to nodes N2 and N3 can be arbitrarily changed. The remaining configuration of the communication device 3 according to the third variation of the third embodiment is the same as that of the first variation of the third embodiment.

[0193] In the communication device 3 according to the third modified example of the third embodiment described above, φ1 = φ2 = 0 [rad] and φ3 = φ4 = 4π / 3 [rad]. Thus, similar to the third embodiment, the communication device 3 according to the third modified example of the third embodiment can improve the EMI performance of the fundamental wave and the doubled wave by 6 dB compared to the case where φ1 = φ2 = φ3 = φ4 = 0 [rad].

[0194] [4] Fourth embodiment

[0195] The communication device 4 according to the fourth embodiment is a modification of the signal generating circuit 30 using the positive-phase and negative-phase modulated signals described in the second embodiment.

[0196] [4-1] Composition

[0197] Figure 23 FIG. 4 shows an example of a circuit configuration of the signal generating circuit 30 included in the communication device 4 according to the fourth embodiment. Figure 23 As shown, the signal generating circuit 30 in the fourth embodiment includes a signal generating unit 31 having a different circuit configuration than that in the second embodiment. The signal generating unit 31 in the fourth embodiment includes, for example, a first delay circuit 330, a second delay circuit 331, a clock transition detection circuit 332, a pulse generating circuit 333, a NAND circuit 334, a phase detection circuit 335, a selection circuit 336, an OR circuit 337, and a NOR circuit 338.

[0198] The first delay circuit 330 receives the input signal Vin. Furthermore, the first delay circuit 330 inputs the delayed input signal Vin to the pulse generation circuit 333. The delay amount of the first delay circuit is designed to be, for example, equivalent to the delay amount of the signal passing through the clock transition detection circuit 332. Hereinafter, the input signal Vin delayed by the first delay circuit is referred to as a delayed input signal VinD.

[0199] The carrier signal CS is input to the second delay circuit 331. The second delay circuit 331 then inputs the delayed carrier signal CS to the selection circuit 336. The delay amount of the second delay circuit is designed to be equal to the sum of the delay amount of the signal passing through the clock transition detection circuit 332 and the delay amount of the signal passing through the phase detection circuit 335. Hereinafter, the carrier signal CS delayed by the second delay circuit is referred to as a delayed carrier signal CSd.

[0200] The clock transition detection circuit 332 receives input signals Vin and a carrier signal CS, and generates clock transition signals CT1 and CT2 based on the input signals Vin and CS. The clock transition detection circuit 332 then inputs the generated clock transition signals CT1 and CT2 to each of the pulse generation circuit 333, the NAND circuit 334, and the phase detection circuit 335.

[0201] The pulse generation circuit 333 generates a positive phase input signal VinNP based on the input delayed input signal VinD and the clock transition signals CT1 and CT2 , and inputs the generated positive phase input signal VinNP to the OR circuit 337 .

[0202] The NAND circuit 334 performs a NAND operation on the input clock transition signals CT1 and CT2 and inputs the operation result to the NOR circuit 338 as an inverted input signal VinRP.

[0203] The phase detection circuit 335 generates phase detection signals PD1 and PD2 based on the input clock transition signals CT1 and CT2 , and inputs the generated phase detection signals PD1 and PD2 to the selection circuit 336 .

[0204] The selection circuit 336 generates an internal carrier signal Vcs based on the input phase detection signals PD1 and PD2 and the delayed carrier signal CSd, and inputs the generated internal carrier signal Vcs to the OR circuit 337 and the NOR circuit 338 .

[0205] OR circuit 337 corresponds to the positive-phase output of signal generation circuit 30. Specifically, OR circuit 337 performs an OR operation on the positive-phase input signal VinNP and the internal carrier signal Vcs. OR circuit 337 then outputs the result of the operation as the positive-phase modulated signal MS1 to driver 32.

[0206] NOR circuit 338 corresponds to the inverse phase output of signal generation circuit 30. Specifically, NOR circuit 338 performs a NOR operation on the inverse phase input signal VinRP and internal carrier signal Vcs. NOR circuit 338 then outputs the result of the operation as inverse phase modulated signal MS2 to driver 32.

[0207] The rest of the configuration of the communication device 4 according to the fourth embodiment is the same as that of the second embodiment. Specifically, the modulated signals MS1 and MS2 generated by the signal generating unit 31 are input to the driver unit 32 (not shown). The driver unit 32 then differentially amplifies the modulated signals MS1 and MS2 and outputs the amplified voltage to the insulating element 40. The signal generating circuit 30 according to the fourth embodiment may have other circuit configurations as long as it can perform the operations described below.

[0208] [4-2] Action

[0209] The operation of the communication device 4 according to the fourth embodiment varies according to the state of the RF generator 20 and the timing of the rise of the input signal Vin. Figures 24 to 26 A specific example of the operation of the communication device 4 according to the fourth embodiment will be described. Figures 24 to 26 An example of a timing chart showing the operation of the communication device 4 according to the fourth embodiment is shown, and the voltage of each signal corresponding to one signal generating circuit 30 is shown.

[0210] In the following description, the RF generator 20 is in the on state when at least one input signal Vin corresponding to the signal generating circuit 30 is rising, indicating that the carrier signal CS is oscillating. On the other hand, the RF generator 20 is in the off state when all other input signals Vin corresponding to the signal generating circuit 30 are falling, indicating that the carrier signal CS is not oscillating.

[0211] Furthermore, the initial voltages of input signal Vin, delayed input signal VinD, clock transition signals CT1 and CT2, phase detection signals PD1 and PD2, internal carrier signal Vcs, and positive-phase input signal VinNP are each set to an "L" level. At this time, NAND circuit 334 outputs negative-phase input signal VinRP at an "H" level. OR circuit 337 outputs modulated signal MS1 at an "L" level. NOR circuit 338 outputs modulated signal MS2 at an "L" level.

[0212] (When the RF generator 20 is on and CS is at "L" level, Vin rises)

[0213] Figure 24This corresponds to the operation when the RF generator 20 is on and the carrier signal CS is at "L" level and the input signal Vin rises (RF: on, detection "L" → "H"). Figure 24 As shown, in the initial state of this example, the carrier signal CS oscillates, and the delayed carrier signal CSd oscillates with a delay relative to the carrier signal CS.

[0214] When the input signal Vin rises, the first delay circuit 330 causes the delayed input signal VinD to transition from the “L” level to the “H” level with a delay compared to the input signal Vin. Figure 24 (1)). Then, based on the delayed input signal VinD becoming "H," the pulse generation circuit 333 changes the positive phase input signal VinNP from "L" to "H." As a result, the "H" positive phase input signal VinNP is input to the OR circuit 337, which causes the modulated signal MS1 to become "H."

[0215] Furthermore, when the input signal Vin rises, the clock transition detection circuit 332 starts monitoring the state of the carrier signal CS. At this time, the clock transition detection circuit 332 first changes the clock transition signal CT1 from the "L" level to the "H" level based on the fact that the carrier signal CS rises ( Figure 24 (2)). Then, the clock transition detection circuit 332 changes the clock transition signal CT2 from the "L" level to the "H" level based on the fact that the carrier signal CS falls ( Figure 24 (3)). If both the clock transition signals CT1 and CT2 are at the "H" level, the pulse generation circuit 333 causes the positive phase input signal VinNP to transition from the "H" level to the "L" level, and the NAND circuit 334 causes the negative phase input signal VinRP to transition from the "H" level to the "L" level. In addition, the phase detection circuit 335 causes the phase detection signal PD1 to transition from the "L" level to the "H" level based on the fact that the clock transition signal CT1 transitions to the "H" level earlier than the clock transition signal CT2. ( Figure 24 (4)).

[0216] Then, the selection circuit 336 outputs a signal having the same phase as that of the delayed carrier signal CSd as the internal carrier signal Vcs ( Figure 24(5)). When the positive-phase input signal VinNP at an "L" level is input to OR circuit 337, OR circuit 337 sets the modulated signal MS1 to an "L" level and then outputs the modulated signal MS1 having a phase that maintains the phase of the internal carrier signal Vcs. When the negative-phase input signal VinRP at an "L" level is input to NOR circuit 338, NOR circuit 338 outputs the modulated signal MS2 having a phase that is the inverted phase of the internal carrier signal Vcs.

[0217] As described above, in this example, when the input signal Vin rises, the first pulse signal of the modulated signal MS1 is immediately generated by the pulse generation circuit 333. The second and subsequent pulse signals are generated based on the internal carrier signal Vcs corresponding to the same phase as the carrier signal CS. Then, when the input signal Vin falls, the first delay circuit 330 transitions the delayed input signal VinD from the "H" level to the "L" level, and the clock transition detection circuit 332 transitions the clock transition signals CT1 and CT2 from the "H" level to the "L" level. Figure 24 (6)). Based on the fact that both clock transition signals CT1 and CT2 are at "L" level, NAND circuit 334 outputs "H" level reverse phase input signal VinRP, phase detection circuit 335 transitions phase detection signal PD1 from "H" level to "L" level, and selection circuit 336 maintains internal carrier signal Vcs at "L" level. As a result, signal generation circuit 30 returns to its initial state.

[0218] (When the RF generator 20 is on and CS is at "H" level, Vin rises)

[0219] Figure 25 This corresponds to the operation when the RF generator 20 is on and the carrier signal CS is at "H" level and the input signal Vin rises (RF: on, detection "H" → "L"). Figure 25 As shown, in the initial state of this example, the carrier signal CS oscillates, and the delayed carrier signal CSd oscillates with a delay relative to the carrier signal CS.

[0220] When the input signal Vin rises, the first delay circuit 330 delays the delayed input signal VinD relative to the input signal Vin and causes the delayed input signal VinD to transition from the “L” level to the “H” level ( Figure 25 (1)). Then, based on the delayed input signal VinD becoming "H," the pulse generation circuit 333 changes the positive phase input signal VinNP from "L" to "H." As a result, the "H" level positive phase input signal VinNP is input to the OR circuit 337, which causes the modulated signal MS1 to become "H."

[0221] Furthermore, when the input signal Vin rises, the clock transition detection circuit 332 starts monitoring the state of the carrier signal CS. At this time, the clock transition detection circuit 332 first changes the clock transition signal CT2 from the "L" level to the "H" level based on the fact that the carrier signal CS falls. Figure 25 (2)). Then, the clock transition detection circuit 332 changes the clock transition signal CT1 from the "L" level to the "H" level based on the fact that the carrier signal CS rises ( Figure 25 (3)). If both the clock transition signals CT1 and CT2 become "H" level, the pulse generation circuit 333 changes the positive phase input signal VinNP from "H" level to "L" level, and the NAND circuit 334 changes the negative phase input signal VinRP from "H" level to "L" level. In addition, the phase detection circuit 335 changes the phase detection signal PD2 from "L" level to "H" level based on the fact that the clock transition signal CT2 changes to "H" level earlier than the clock transition signal CT1. ( Figure 25 (4)).

[0222] Then, the selection circuit 336 outputs a signal having a phase inverted from the phase of the delayed carrier signal CSd as the internal carrier signal Vcs ( Figure 25 (5)). When the positive-phase input signal VinNP at an "L" level is input to OR circuit 337, OR circuit 337 sets the modulated signal MS1 to an "L" level and then outputs the modulated signal MS1 having the same phase as the internal carrier signal Vcs. When the negative-phase input signal VinRP at an "L" level is input to NOR circuit 338, NOR circuit 338 outputs the modulated signal MS2 having a phase that is the inverted phase of the internal carrier signal Vcs.

[0223] As described above, in this example, when the input signal Vin rises, the first pulse signal of the modulated signal MS1 is immediately generated by the pulse generation circuit 333, and the second and subsequent pulse signals are generated based on the internal carrier signal Vcs corresponding to the inverted output of the carrier signal CS. Then, when the input signal Vin falls, the first delay circuit 330 transitions the delayed input signal VinD from the "H" level to the "L" level, and the clock transition detection circuit 332 transitions the clock transition signals CT1 and CT2 from the "H" level to the "L" level ( Figure 25(6)). Based on the fact that both clock transition signals CT1 and CT2 are at "L" level, NAND circuit 334 outputs "H" level reverse phase input signal VinRP, phase detection circuit 335 transitions phase detection signal PD2 from "H" level to "L" level, and selection circuit 336 maintains internal carrier signal Vcs at "L" level. As a result, signal generation circuit 30 returns to its initial state.

[0224] (When Vin rises when the RF generator 20 is off)

[0225] Figure 26 This corresponds to the operation when the input signal Vin rises when the RF generator 20 is in the off state (RF: off → on). Figure 26 As shown, in the initial state of this example, the carrier signal CS is in the OFF state ("L" level).

[0226] When the input signal Vin rises, the RF generator 20 turns on and begins oscillating the carrier signal CS (RF ON). In this case, the clock transition detection circuit 332 detects the rise of the carrier signal CS first and then the fall of the carrier signal CS. That is, in this example, after the input signal Vin rises, the clock transition signal CT1 goes high first, and the clock transition signal CT2 goes high later. Figure 26 Other actions and uses shown Figure 24 However, when the input signal Vin falls while the other input signal Vin is maintained at the "L" level, the RF generator 20 enters the OFF state (RF OFF).

[0227] [4-3] Effects of the Fourth Embodiment

[0228] As described above, the signal generating circuit 30 included in the communication device 4 according to the fourth embodiment includes the signal generating unit 31 that changes the phase of the internal carrier signal Vcs according to the rising timing of the input signal Vin.

[0229] Simply put, when the signal generator 31 in the fourth embodiment detects a rising edge of the input signal Vin, it generates a first pulse signal (modulated signal MS1), regardless of whether the RF generator 20 is in the on or off state. The pulse width of this first pulse signal is 0.5 to 1.0 times the period of the carrier signal CS, depending on the timing of the rising edge of the input signal Vin. Furthermore, when the rising edge of the input signal Vin is detected while the carrier signal CS is at an "L" level, the signal generator 31 in the fourth embodiment generates an internal carrier signal Vcs based on the phase of the delayed carrier signal CS. On the other hand, when the rising edge of the input signal Vin is detected while the carrier signal CS is at an "H" level, the signal generator 31 in the fourth embodiment generates an internal carrier signal Vcs based on the phase of the delayed carrier signal CS, which is the inverted phase of the delayed carrier signal CS.

[0230] As described above, by generating the first pulse signal regardless of the state of the RF generator 20, the rising waveform of the positive-phase modulated signal MS1 remains constant, regardless of whether the input signal Vin and the carrier signal CS are synchronized. In other words, even when the input signal Vin and the carrier signal CS operate asynchronously, the leading waveforms of the modulated signal MS used in the OOK scheme can be aligned. Consequently, the communication device 4 according to the fourth embodiment stabilizes the rise time of the detection circuit and, similar to the first and second embodiments, suppresses jitter in the output signal of the signal generating circuit 30.

[0231] Furthermore, by generating the second and subsequent pulse signals based on the inverted or non-inverted internal carrier signal Vcs corresponding to the rising timing of the input signal Vin, the falling edge of the first pulse signal smoothly connects with the rising edge of the second and subsequent pulse signals. In other words, the signal generation unit 31 of the fourth embodiment can stably generate the second and subsequent pulses. As a result, the communication device 4 of the fourth embodiment can suppress the generation of high-frequency pulses such as glitches. Therefore, the communication device 4 of the fourth embodiment can improve operational stability compared to the second embodiment.

[0232] In addition, in the fourth embodiment, the signal generating circuit 30 uses the positive phase modulated signal MS1 and the negative phase modulated signal MS2, but the present invention is not limited to this. For example, the signal generating circuit 30 may process a single modulated signal MS in the same manner as in the first embodiment. In this case, the signal generating unit 31 has a signal generator 31, for example, Figure 23 The illustrated configuration omits the NAND circuit 334 and the NOR circuit 338. A communication device including such a signal generating circuit 30 can achieve the same effects as those of the fourth embodiment and can improve operational stability compared to the first embodiment.

[0233] [5] Other

[0234] The above-mentioned embodiments can be combined. For example, the second embodiment can be combined with any one of the first to fourth variations of the first embodiment. The third embodiment can be combined with the first embodiment, the first and second variations of the first embodiment, the second embodiment, and any one of the variations of the second embodiment. The fourth embodiment can be combined with the third embodiment and any one of the first to third variations of the third embodiment. The signal generating circuit 30 of the fourth embodiment can be applied to each of the N channels, such as the third variation of the first embodiment. A communication device 1 composed of a combination of multiple embodiments and variations can obtain the effects of each of the combined embodiments and variations. Adjusting the phase of each insulating element 40 to suppress EMI, as in the third embodiment, can also be applied to the first and second embodiments. In other words, the third embodiment can be applied regardless of the configuration of the signal generating circuit 30, the number of channels provided by the communication device 1, or the type of insulating element used.

[0235] In this specification, an "H" level voltage is a voltage that turns on an N-type transistor to which the voltage is applied, and turns off a P-type transistor to which the voltage is applied. An "L" level voltage is a voltage that turns off an N-type transistor to which the voltage is applied, and turns on a P-type transistor to which the voltage is applied. A "first logic level" and a "second logic level" correspond to either an "H" level or an "L" level, respectively. The oscillating signal output by the RF generator 20 may be referred to as an "RF signal" or a "clock signal." The RF generator 20 may be referred to as an "oscillator." The combination of the receiving circuit 50 and the output circuit 60 may be referred to as an "output circuit."

[0236] In this specification, "connection" means electrical connection, and does not exclude the situation where other elements are interposed in between. In addition, in the specification, "on state" means that a voltage greater than the threshold voltage of the transistor is applied to the gate of the corresponding transistor. "Off state" means that a voltage less than the threshold voltage of the transistor is applied to the gate of the corresponding transistor, and does not exclude the situation where a small current such as leakage current flowing through the transistor is applied. "Signal rise" means that the voltage of the signal changes from "L" level to "H" level. "Signal fall" means that the voltage of the signal changes from "H" level to "L" level. "The state after the signal rises" corresponds to the "H" level. "The state after the signal falls" corresponds to the "L" level. "One pulse signal" corresponds to, for example, the part where the signal changes from "L" level → "H" level → "L" level. "Pulse width" corresponds to, for example, the period when the signal changes from "L" level → "H" level → "L" level.

[0237] The technical aspects of this specification are described below.

[0238] <1> A communication device includes an oscillator, a first signal generating circuit, a second signal generating circuit, a first insulating element, a second insulating element, a first output circuit, and a second output circuit. The oscillator outputs a carrier signal when at least one of a first signal and a second signal input from an external source is at a first logic level. The first signal generating circuit includes a first signal generating unit and a first driving circuit. Upon detecting a rising edge of the first signal, the first signal generating unit generates a first pulse signal. If the carrier signal is at a second logic level different from the first logic level when the rising edge of the first signal is detected, the first signal generating unit outputs a signal having the same phase as the carrier signal as the second and subsequent pulse signals. If the carrier signal is at the first logic level when the rising edge of the first signal is detected, the first driving circuit outputs a signal with the carrier signal inverted in phase as the second and subsequent pulse signals. The first driving circuit amplifies the output signal of the first signal generating unit. The second signal generating circuit includes a second signal generating unit and a second driving circuit. The second signal generating unit generates a first pulse signal upon detecting a rise in the second signal. When the carrier signal is at the second logic level upon detecting a rise in the second signal, the second signal generating unit outputs a signal having the same phase as the carrier signal as the second and subsequent pulse signals. When the carrier signal is at the first logic level upon detecting a rise in the first signal, the second signal generating unit outputs a signal having a phase that is the inverted phase of the carrier signal as the second and subsequent pulse signals. The second drive circuit amplifies the output signal of the second signal generating unit. A first insulating element is connected to the output of the first drive circuit. A second insulating element is connected to the output of the second drive circuit. The first output circuit receives a signal based on the output signal of the first drive circuit via the first insulating element and outputs it externally. The second output circuit receives a signal based on the output signal of the second drive circuit via the second insulating element and outputs it externally.

[0239] <2> The communication device described in <1> has the following configuration. The first signal generating unit includes a clock transition detection circuit, a pulse generating circuit, a phase detection circuit, a selection circuit, and a first OR circuit. The clock transition detection circuit receives inputs of a first signal and a carrier signal, and generates a first control signal and a second control signal based on the input first signal and the carrier signal. The pulse generating circuit generates a first input signal based on the first signal, the first control signal, and the second control signal. The phase detection circuit generates a third control signal and a fourth control signal based on the first control signal and the second control signal. The selection circuit generates an internal carrier signal based on the third control signal, the fourth control signal, and the carrier signal. The first OR circuit performs an OR operation on the first input signal and the internal carrier signal, and the result of the operation is output by the first driver circuit. The clock transition detection circuit transitions the first control signal from the second logic level to the first logic level if it detects a rise in the carrier signal after the first signal rises, and transitions the second control signal from the second logic level to the first logic level if it detects a fall in the carrier signal. The pulse generation circuit transitions the first input signal from the second logic level to the first logic level upon detecting a rising edge of the first signal. The pulse generation circuit transitions the first input signal from the first logic level to the second logic level in response to both the first control signal and the second control signal reaching the first logic level after detecting a rising edge of the first signal. When both the third control signal and the fourth control signal reach the first logic level, the phase detection circuit generates an internal carrier signal having the same phase as the carrier signal if the third control signal transitions to the first logic level before the fourth control signal. When the fourth control signal transitions to the first logic level before the third control signal, the phase detection circuit generates an internal carrier signal having a phase that is the inverted phase of the carrier signal.

[0240] <3> The communication device described in <2> has the following configuration. The first signal generating unit further includes a first delay circuit and a second delay circuit. The first delay circuit generates a delay equivalent to the delay of the clock transition detection circuit. The second delay circuit generates a delay equivalent to the combined delay of the clock transition detection circuit and the phase detection circuit. The pulse generating circuit receives the first signal passed through the first delay circuit as input, and generates the first input signal based on the delayed first signal. The selection circuit receives the carrier signal passed through the second delay circuit as input, and generates the internal carrier signal based on the delayed carrier signal.

[0241] <4> The communication device described in <2> or <3> has the following configuration. The first signal generating unit further includes a first NAND circuit and a first NOR circuit. The first NAND circuit performs a NAND operation on the first control signal and the second control signal, and outputs the result as the second input signal. The first NOR circuit performs a NOR operation on the second input signal and the internal carrier signal, and the result is output by the first driver circuit. The first driver circuit differentially amplifies the output of the first OR circuit and the output of the first NOR circuit.

[0242] <5> The communication device according to any one of <1> to <4> has the following configuration: The first signal generating unit outputs a signal of a second logic level to the first driving circuit upon detecting a fall of the first signal after detecting a rise of the first signal.

[0243] <6> The communication device includes an oscillator, a first signal generating circuit, a second signal generating circuit, a first insulating element, a second insulating element, a first output circuit, and a second output circuit. The oscillator outputs a carrier signal when at least one of a first signal and a second signal inputted from the outside is at a first logic level. The first signal generating circuit includes a first delay circuit, a first logic circuit, a second logic circuit, a third logic circuit, and a first driver circuit. The first logic circuit receives the first signal as input to its first input terminal, and the first signal, via the first delay circuit, as input to its second input terminal. The second logic circuit receives the first signal as input to its first input terminal, and the carrier signal as input to its second input terminal. The third logic circuit receives the first signal as input to its first input terminal, and the second signal, via the second delay circuit, as input to its second input terminal. The first driver circuit amplifies the voltage outputted by the third logic circuit. The second signal generating circuit includes a second delay circuit, a fourth logic circuit, a fifth logic circuit, a sixth logic circuit, and a second driver circuit. The fourth logic circuit receives the second signal as input to its first input terminal, and the second signal, via the second delay circuit, as input to its second input terminal. The fifth logic circuit has a first input connected to the output of the fourth logic circuit, and a carrier signal is input to the second input. The sixth logic circuit has a first input connected to the second signal, and a second input connected to the output of the fifth logic circuit. The second drive circuit amplifies the voltage output by the sixth logic circuit. The first insulating element is connected to the output of the first drive circuit. The second insulating element is connected to the output of the second drive circuit. The first output circuit receives a signal based on the output signal of the first drive circuit via the first insulating element and outputs it externally. The second output circuit receives a signal based on the output signal of the second drive circuit via the second insulating element and outputs it externally.

[0244] <7> In the communication device described in <6>, the first logic circuit, the third logic circuit, the fourth logic circuit, and the sixth logic circuit are AND circuits, and the second logic circuit and the fifth logic circuit are NAND circuits.

[0245] <8> The communication device described in <6> or <7> has the following configuration. The first signal generating circuit further includes a fourth inverter and a thirteenth logic circuit. The input of the fourth inverter is connected to the output of the second logic circuit. For the thirteenth logic circuit, the first input is input to the first signal, and the second input is connected to the output of the fourth inverter. The second signal generating circuit further includes a fifth inverter and a fourteenth logic circuit. The input of the second signal generating circuit is connected to the output of the fifth logic circuit. For the fourteenth logic circuit, the first input is input to the second signal, and the second input is connected to the output of the fifth inverter. The first drive circuit differentially amplifies the output of the third logic circuit and the output of the thirteenth logic circuit. The second drive circuit differentially amplifies the output of the sixth logic circuit and the output of the fourteenth logic circuit.

[0246] <9> The communication device described in any one of <1> to <8> has the following configuration. The first insulating element includes a first coil and a second coil. The first coil is connected to the output of the first drive circuit. The second coil is opposite the first coil through an insulating layer and is connected to the first output circuit. The second insulating element includes a third coil and a fourth coil. The third coil is connected to the output of the second drive circuit. The fourth coil is opposite the third coil through an insulating layer and is connected to the second output circuit.

[0247] <10> The communication device described in any one of <1> to <8> has the following configuration. The first insulating element includes a first capacitor. One electrode of the first capacitor is connected to the output of the first drive circuit, and the other electrode is connected to the first output circuit. The second insulating element includes a second capacitor. One electrode of the second capacitor is connected to the output of the second drive circuit, and the other electrode is connected to the second output circuit.

[0248] <11> The communication device according to any one of <1> to <10> further includes a first substrate and a second substrate. The oscillator, the first signal generating circuit, and the second signal generating circuit are mounted on the first substrate. The first output circuit and the second output circuit are mounted on the second substrate. The first insulating element and the second insulating element are mounted on either the first substrate or the second substrate.

[0249] <12> In the communication device described in <1> or <6>, a phase of the carrier signal input to the first signal generating circuit is different from a phase of the carrier signal input to the second signal generating circuit.

[0250] <13> In the communication device described in <12>, the oscillator includes a second OR circuit, a second NAND circuit, a first inverter, and a second inverter. The second OR circuit has a first input terminal inputted with a first signal, and a second input terminal inputted with a second signal. The first input terminal of the second NAND circuit is connected to the output terminal of the second OR circuit. The input terminal of the first inverter is connected to the output terminal of the second NAND circuit. The second inverter has an input terminal connected to the output terminal of the first inverter, and an output terminal connected to the second input terminal of the second NAND circuit. The output terminal of the second NAND circuit is connected to the second signal generating circuit. The output terminal of the second inverter is connected to the first signal generating circuit.

[0251] <14> In the communication device described in <12>, the oscillator includes a second OR circuit, a second NAND circuit, a first inverter, and a second inverter. The second OR circuit has a first input terminal connected to a first signal and a second input terminal connected to a second signal. The first input terminal of the second NAND circuit is connected to the output terminal of the second OR circuit. The input terminal of the first inverter is connected to the output terminal of the second NAND circuit. The second inverter has an input terminal connected to the output terminal of the first inverter, and an output terminal connected to the second input terminal of the second NAND circuit. The output terminal of the first inverter is connected to the second signal generating circuit. The output terminal of the second inverter is connected to the first signal generating circuit.

[0252] <15> The communication device described in <6> further includes a third signal generating circuit, a third insulating element, and a third output circuit. The third signal generating circuit includes a third delay circuit, a seventh logic circuit, an eighth logic circuit, a ninth logic circuit, and a third driving circuit. For the seventh logic circuit, a third signal is input from outside the communication device to the first input terminal, and the third signal passed through the third delay circuit is input to the second input terminal. For the eighth logic circuit, the first input terminal is connected to the output terminal of the seventh logic circuit, and a carrier signal is input to the second input terminal. For the ninth logic circuit, the third signal is input to the first input terminal, and the second input terminal is connected to the output terminal of the eighth logic circuit. The third driving circuit amplifies the voltage output by the ninth logic circuit. The third insulating element is connected to the output of the third driving circuit. The third output circuit receives a signal based on the output signal of the third driving circuit via the third insulating element and outputs it to the outside.

[0253] <16> The communication device described in <15> has the following configuration. The oscillator outputs a carrier signal when at least one of the first signal, the second signal, and the third signal is at a first logic level. The phase of the carrier signal input to the first signal generating circuit, the phase of the carrier signal input to the second signal generating circuit, and the phase of the carrier signal input to the third signal generating circuit are different from each other.

[0254] <17> The communication device described in <16> has the following configuration. The oscillator includes a second OR circuit, a second NAND circuit, a first inverter, and a second inverter. The second OR circuit receives a first signal as input to its first input, a second signal as input to its second input, and a third signal as input to its third input. The first input of the second NAND circuit is connected to the output of the second OR circuit. The input of the first inverter is connected to the output of the second NAND circuit. The second inverter has an input connected to the output of the first inverter, and an output connected to the second input of the second NAND circuit. The output of the second NAND circuit is connected to the third signal generating circuit. The output of the first inverter is connected to the second signal generating circuit. The output of the second inverter is connected to the first signal generating circuit.

[0255] <18> The communication device described in <15> further includes a fourth signal generating circuit, a fourth insulating element, and a fourth output circuit. The fourth signal generating circuit includes a fourth delay circuit, a tenth logic circuit, an eleventh logic circuit, a twelfth logic circuit, and a fourth drive circuit. For the tenth logic circuit, the fourth signal is input from outside the communication device to the first input terminal, and the fourth signal via the fourth delay circuit is input to the second input terminal. For the eleventh logic circuit, the first input terminal is connected to the output terminal of the tenth logic circuit, and the carrier signal is input to the second input terminal. For the twelfth logic circuit, the fourth signal is input to the first input terminal, and the second input terminal is connected to the output terminal of the eleventh logic circuit. The fourth drive circuit amplifies the voltage output by the twelfth logic circuit. The fourth insulating element is connected to the output of the fourth drive circuit. The fourth output circuit receives a signal based on the output signal of the fourth drive circuit via the fourth insulating element and outputs it to the outside.

[0256] <19> The communication device described in <18> has the following configuration. The oscillator outputs a carrier signal when at least one of the first signal, the second signal, the third signal, and the fourth signal is at a first logic level. The phase of the carrier signal input to the first signal generating circuit, the phase of the carrier signal input to the second signal generating circuit, the phase of the carrier signal input to the third signal generating circuit, and the phase of the carrier signal input to the fourth signal generating circuit are different from each other.

[0257] <20> The communication device described in <19> has the following configuration. The oscillator includes a second OR circuit, a second NAND circuit, a first inverter, a second inverter, and a third inverter. The second OR circuit receives a first signal at its first input, a second signal at its second input, a third signal at its third input, and a fourth signal at its fourth input. The first input of the second NAND circuit is connected to the output of the second OR circuit. The input of the first inverter is connected to the output of the second NAND circuit. The second inverter has an input connected to the output of the first inverter, and an output connected to the second input of the second NAND circuit. The input of the third inverter is connected to the output of the second inverter. The output of the second NAND circuit is connected to the fourth signal generating circuit. The output of the first inverter is connected to the second signal generating circuit. The output of the second inverter is connected to the first signal generating circuit. The output of the third inverter is connected to the third signal generating circuit.

[0258] <21> The communication device includes an oscillator, an N-th signal generating circuit, an N-th insulating element, an N-th receiving circuit, and an N-th output circuit. The oscillator outputs a carrier signal when at least one of a first signal and a second signal input from the outside is at a first logic level. If the N-th signal generating unit detects the first logic level of the N-th signal (N is an integer greater than 1) among a plurality of signals, it generates a first pulse signal, which is followed by a carrier signal, and outputs a pulse signal such that the carrier signal stops when the N-th signal becomes a second logic level. The N-th driving circuit amplifies the output signal of the N-th signal generating unit. The N-th insulating element is connected to the output of the N-th driving circuit. The N-th receiving circuit receives a signal based on the output signal of the N-th driving circuit via the N-th insulating element, and demodulates the signal according to the received signal. The N-th output circuit outputs a signal based on the output signal of the N-th receiving circuit to the outside.

[0259] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention and are included in the invention described in the technical solution and its equivalents.

Claims

1. A communication device, characterized in that: have: an oscillator that outputs a first carrier signal when at least one input signal among a plurality of input signals input from the outside is at a first logic level; a first signal generating circuit, to which a first input signal and the first carrier signal from among the plurality of input signals are input, generates a first signal when the first input signal changes from a second logic level to the first logic level, outputs a signal based on the first carrier signal after outputting a signal based on the first signal, and outputs a signal at the second logic level when the first input signal changes from the first logic level to the second logic level; a first insulating element connected to an output of the first signal generating circuit; a first receiving circuit that receives and demodulates the signal output from the first signal generating circuit via the first insulating element; as well as The first output circuit outputs the signal demodulated by the first receiving circuit to the outside.

2. The communication device according to claim 1, wherein The first signal is a single pulse signal.

3. The communication device according to claim 1, wherein A signal based on the first signal is continuously connected to a signal based on the first carrier signal.

4. The communication device according to claim 1, wherein: The first signal generating circuit outputs a differential signal. The communication device according to claim 1 , wherein: Also features: a second signal generating circuit, which receives a second input signal from among the plurality of input signals and a second carrier signal output by the oscillator, generates a second signal when the second input signal changes from the second logic level to the first logic level, outputs a signal based on the second carrier signal after outputting a signal based on the second signal, and outputs a signal at the second logic level when the second input signal changes from the first logic level to the second logic level; a second insulating element connected to an output of the second signal generating circuit; a second receiving circuit that receives and demodulates the signal output from the second signal generating circuit via the second insulating element; as well as The second output circuit outputs the signal demodulated by the second receiving circuit to the outside. The communication device according to claim 5 , wherein: The first carrier signal and the second carrier signal have different phases.

7. The communication device according to claim 1, wherein: In the state where the first carrier signal is output by the oscillator, when the first carrier signal is at the second logic level, if the first signal generating circuit detects that the first input signal changes from the second logic level to the first logic level, then after outputting a signal based on the first signal, it outputs a signal based on the first carrier signal that is in phase with the first carrier signal.

8. The communication device according to claim 1, wherein: In the state where the first carrier signal is output by the oscillator, when the first carrier signal is at the first logic level, if the first signal generating circuit detects that the first input signal changes from the second logic level to the first logic level, then after outputting the signal based on the first signal, the phase of the signal based on the first carrier signal is inverted and output.

9. The communication device according to claim 1, wherein: The first signal generating circuit generates the first signal based on a signal obtained by delaying the first input signal.

10. A communication device, characterized in that: have: an oscillator configured to output a carrier signal when at least one of a first input signal and a second input signal inputted from the outside is at a first logic level; a first signal generating circuit comprising a first signal generating unit and a first driving circuit for amplifying an output signal of the first signal generating unit, wherein the first signal generating unit generates a first pulse upon detecting a rise of the first input signal, outputs a signal based on the carrier signal that is in phase with the carrier signal as a second pulse signal and subsequent pulse signals when the carrier signal is at a second logic level different from the first logic level when the rise of the first input signal is detected, and outputs a signal based on the carrier signal that is in phase with the carrier signal and inverted from the carrier signal as a second pulse signal and subsequent pulse signals when the carrier signal is at the first logic level when the rise of the first input signal is detected; a second signal generating circuit comprising a second signal generating unit and a second driving circuit for amplifying an output signal of the second signal generating unit, wherein the second signal generating unit generates a first pulse upon detecting a rising edge of the second input signal, outputs a signal based on the carrier signal that is in phase with the carrier signal as a signal for the second pulse and subsequent pulses when the carrier signal is at the second logic level upon detecting a rising edge of the second input signal, and outputs a signal based on the carrier signal that is in phase with the carrier signal as a signal for the second pulse and subsequent pulses when the carrier signal is at the first logic level upon detecting a rising edge of the first input signal; a first insulating element connected to an output of the first driving circuit; a second insulating element connected to an output of the second driving circuit; a first output circuit that receives a signal based on an output signal of the first drive circuit via the first insulating element and outputs the signal to the outside; as well as The second output circuit receives a signal based on the output signal of the second drive circuit via the second insulating element and outputs the signal to the outside. The communication device according to claim 10 , wherein: The first signal generating unit includes: a clock transition detection circuit to which the first input signal and the carrier signal are input, and to generate a first control signal and a second control signal based on the input first input signal and the carrier signal; a pulse generating circuit, configured to generate a first signal based on the first input signal, the first control signal, and the second control signal; a phase detection circuit, generating a third control signal and a fourth control signal based on the first control signal and the second control signal; a selection circuit generating an internal carrier signal according to the third control signal, the fourth control signal, and a signal based on the carrier signal; as well as A first OR circuit performs an OR operation on the first signal and the internal carrier signal, and the operation result is amplified and output by the first driving circuit. After the first input signal rises, the clock transition detection circuit transitions the first control signal from the second logic level to the first logic level when detecting a rise in the carrier signal, and transitions the second control signal from the second logic level to the first logic level when detecting a fall in the carrier signal. The pulse generating circuit changes the first signal from the second logic level to the first logic level when detecting a rising edge of the first input signal, and changes the first signal from the first logic level to the second logic level when both the first control signal and the second control signal reach the first logic level after detecting a rising edge of the first input signal. When both the first control signal and the second control signal are at the first logic level, the phase detection circuit causes the third control signal to transition from the second logic level to the first logic level if the first control signal transitions to the first logic level before the second control signal, and causes the fourth control signal to transition from the second logic level to the first logic level if the second control signal transitions to the first logic level before the first control signal. When the third control signal is at the first logic level, the selection circuit generates a signal based on the carrier signal that is in phase with the carrier signal as the internal carrier signal, and when the fourth control signal is at the first logic level, the selection circuit generates a signal based on the carrier signal that is inverted in phase with the carrier signal as the internal carrier signal.

12. The communication device according to claim 11, wherein: The first signal generating unit further comprises: a first delay circuit that generates a delay equivalent to the delay amount of the clock transition detection circuit; and a second delay circuit that generates a delay equivalent to the total delay of the clock transition detection circuit and the phase detection circuit; The pulse generating circuit receives the first input signal passed through the first delay circuit, and generates the first signal based on the delayed first input signal. The carrier signal passed through the second delay circuit is input to the selection circuit, and the selection circuit generates the internal carrier signal based on the delayed carrier signal.

13. The communication device according to claim 11, wherein: The first signal generating unit further comprises: a first NAND circuit that performs a NAND operation on the first control signal and the second control signal and outputs the operation result as a second signal; and A first NOR circuit performs a NOR operation on the second signal and the internal carrier signal, and the operation result is amplified and output by the first driving circuit. The first driving circuit differentially amplifies the output of the first OR circuit and the output of the first NOR circuit.

14. The communication device according to claim 10, wherein: The first signal generating unit outputs the signal of the second logic level to the first driving circuit when detecting a fall of the first input signal after detecting a rise of the first input signal.

15. A communication device, characterized in that: have: an oscillator that outputs a first carrier signal and a second carrier signal when at least one of a first input signal and a second input signal inputted from the outside is at a first logic level; The first signal generating circuit includes a first delay circuit, a first logic circuit having the first input signal input to a first input terminal and the first input signal via the first delay circuit input to a second input terminal, a second logic circuit having a first input terminal connected to an output terminal of the first logic circuit and the first carrier signal input to a second input terminal, a third logic circuit having the first input signal input to a first input terminal and the output terminal of the second logic circuit connected to a second input terminal, and a first drive circuit for amplifying a voltage output by the third logic circuit. a second signal generating circuit including a second delay circuit, a fourth logic circuit having the second input signal input to a first input terminal and the second input signal via the second delay circuit input to a second input terminal, a fifth logic circuit having the second input terminal connected to an output terminal of the fourth logic circuit and the second carrier signal input to a second input terminal, a sixth logic circuit having the second input signal input to a first input terminal and the output terminal of the fifth logic circuit connected to a second input terminal, and a second drive circuit for amplifying a voltage output by the sixth logic circuit; a first insulating element connected to an output of the first driving circuit; a second insulating element connected to an output of the second driving circuit; a first output circuit that receives a signal based on an output signal of the first drive circuit via the first insulating element and outputs the signal to the outside; as well as The second output circuit receives a signal based on the output signal of the second drive circuit via the second insulating element and outputs the signal to the outside. The communication device according to claim 15 , wherein: The first logic circuit, the third logic circuit, the fourth logic circuit, and the sixth logic circuit are AND circuits, The second logic circuit and the fifth logic circuit are NAND circuits.

17. The communication device according to claim 15, characterized in that The first signal generating circuit further includes: a fourth inverter having an input terminal connected to the output terminal of the second logic circuit; and a seventh logic circuit, wherein the first input terminal is input with the first input signal, and the second input terminal is connected to the output terminal of the fourth inverter, The second signal generating circuit further includes: a fifth inverter having an input terminal connected to the output terminal of the fifth logic circuit; and an eighth logic circuit, wherein the second input signal is input to a first input terminal and a second input terminal is connected to the output terminal of the fifth inverter, The first driving circuit differentially amplifies the output of the third logic circuit and the output of the seventh logic circuit. The second driving circuit differentially amplifies the output of the sixth logic circuit and the output of the eighth logic circuit.

18. The communication device according to claim 15, wherein: The first insulating element includes a first coil connected to the output of the first drive circuit, and a second coil facing the first coil with an insulating layer interposed therebetween and coupled to the first output circuit. The second insulating element includes a third coil connected to the output of the second drive circuit, and a fourth coil facing the third coil with an insulating layer interposed therebetween and coupled to the second output circuit.

19. The communication device according to claim 15, wherein: The first insulating element includes a first capacitor having one electrode connected to the output of the first driving circuit and the other electrode coupled to the first output circuit. The second insulating element includes a second capacitor having one electrode connected to the output of the second driving circuit and the other electrode coupled to the second output circuit.

20. The communication device according to claim 15, wherein The first carrier signal and the second carrier signal have different phases.

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