A time-delay relay

Abstract

The present invention provides a delay relay, which includes a voltage conversion module, an automatic reset module, a timing module, and an electronic switch module; a power conversion module for converting the power supply voltage into a fixed voltage to supply power to the automatic reset module and the timing module; an automatic reset module for automatically resetting the timing module to enable the timing module to start timing; a timing module for generating a delay control signal after being reset by the automatic reset module to control the on and off of the electronic switch module; and an electronic switch module for realizing the switching of the on and off between the power supply and the load. The present invention has the functions of delay conduction and delay turn-off, high delay accuracy, and good delay stability.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor hybrid integrated circuit design, and particularly relates to a delay relay for delay control required by a power supply system. Background Art

[0002] Domestic spacecraft generally use electromagnetic relays as delay relays for pyrotechnic device control. Electromagnetic relays have low power consumption and no leakage, but there is an arc during the switching process, large electromagnetic interference, large volume, heavy mass, and limited number of uses. To ensure the effectiveness and reliability of the operation of various instruments and equipment in the power distribution systems of satellites, aircraft, and space stations, higher requirements are put forward for the safety and reliability of the overall system. Therefore, it is necessary to develop a delay relay with miniaturization, high delay accuracy, and good delay stability. Summary of the Invention

[0003] In view of the problems existing in the prior art, the present invention provides a delay relay, which has functions of delay conduction and turn-off, high delay accuracy, and good delay stability.

[0004] The present invention is realized through the following technical solutions:

[0005] A delay relay includes a voltage conversion module, an automatic reset module, a timing module, and an electronic switch module;

[0006] The power conversion module is used to convert the power supply voltage into a fixed voltage to supply power to the automatic reset module and the timing module;

[0007] The automatic reset module is used to automatically reset the timing module to enable the timing module to start timing operation;

[0008] The timing module is used to generate a delay control signal after being reset by the automatic reset module to control the connection and disconnection of the electronic switch module;

[0009] The electronic switch module is used to realize the switching of the connection and disconnection between the power supply and the load.

[0010] The voltage conversion module includes a diode D1, a current-limiting resistor R1, a reference source DZ1, a resistor R2, and a resistor R3;

[0011] The positive electrode of the diode D1 is connected to the power supply V CC The negative electrode of the diode D1 is connected to one end of the current-limiting resistor R1, the other end of the current-limiting resistor R1 is connected to the negative electrode of the reference source DZ1, the positive electrode of the reference source DZ1 and one end of the resistor R3 are both grounded, the other end of the resistor R3 is connected to the reference terminal of the reference source DZ1 and one end of the resistor R2, the other end of the resistor R2 is connected to the other end of the resistor R1 and the negative electrode of the reference source DZ1, and the negative electrode of the reference source DZ1 is the voltage output terminal V D .

[0012] Further, the automatic reset module includes a triode T1, a resistor R4, a resistor R5, a resistor R6, and a capacitor C1; one ends of the resistor R4 and the resistor R5 are both connected to the negative electrode of the reference source DZ1, the other end of the resistor R4 is connected to one end of the resistor R6, one end of the capacitor C1, and the base of the triode T1, the other end of the resistor R6 is grounded together with the other end of the capacitor C1 and the emitter of the triode T1, the other end of the resistor R5 is connected to the collector of the triode T1, and one end of the collector of the triode T1 is the reset terminal R D .

[0013] Further, the timing module includes a counter U1, a counter U2, a counter U3, a counter U4, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a capacitor C2, a capacitor C3, a dual D flip-flop U5, and a two-input exclusive-OR gate U6; the power supply terminals of the counters U1, U2, U3, and U4 are all connected to the negative electrode of the reference source DZ1, and the reset terminals of the counters U1, U2, U3, and U4 are all connected to the collector of the triode T1; the resistor R7, R8 and the capacitor C2 form an oscillation network of the counter U1, and the counter U1 is connected in series with the U2; the resistor R9, R10 and the capacitor C3 form an oscillation network of the counter U3, and the counter U3 is connected in series with the U4; the output terminals of the counters U2 and U4 are respectively connected to two clock terminals of the dual D flip-flop U5, and the two output terminals sgn1 and sgn2 of the dual D flip-flop U5 are respectively connected to two input terminals of the two-input exclusive-OR gate U6, the power supply terminal of the dual D flip-flop U5 is connected to the negative electrode of the reference source DZ1, and the reset terminal of the dual D flip-flop U5 is connected to the collector of the triode T1; the power supply terminal of the two-input exclusive-OR gate U6 is connected to the negative electrode of the reference source DZ1, and the grounding terminal of the two-input exclusive-OR gate U6 is grounded.

[0014] Further, the electronic switch module includes a resistor R11, a resistor R12, a resistor R13, a resistor R14, a triode T2, a voltage stabilizing diode D2, and a P-channel VDMOS transistor Q1; one end of the resistor R11 is connected to the signal output terminal of the two-input exclusive-OR gate U6, the other end of the resistor R11 is connected to one end of the resistor R12 and the base of the triode T2, the other end of the resistor R12 and the emitter of the triode T2 are grounded, the collector of the triode T2 is connected to one end of the resistor R14, the other end of the resistor R14 is connected to one end of the resistor R13 and the positive electrode of the voltage stabilizing diode D2, and the other end of the resistor R13 and the negative electrode of the voltage stabilizing diode D2 are both connected to the power supply V CC is connected, the gate of the P-channel VDMOS transistor Q1 is connected to the positive electrode of the voltage stabilizing diode D2, the drain of the P-channel VDMOS transistor Q1 is connected to the load R L is connected, and the source of the P-channel VDMOS transistor Q1 is connected to the power supply V CC is connected.

[0015] Furthermore, the reference source DZ1, counters U1 to U4, dual D flip-flop U5, two-input exclusive-OR gate U6, and VDMOS transistor Q1 are all radiation-hardened chips.

[0016] Furthermore, resistors R7, R8, R9, and R10 are precision thin-film resistor blocks with an accuracy of ±0.5% and a temperature coefficient of <50 ppm / °C.

[0017] Furthermore, the accuracy of capacitor C2 and capacitor C3 is ±1%, and the temperature coefficient is 30 ppm / °C.

[0018] Furthermore, the voltage output terminal V of the reference source DZ1 D , reset terminal R D , and the two output terminals sgn1 and sgn2 of the dual D flip-flop U5 are all lead-out terminals of the delay relay, and electrostatic protection zener diodes are respectively set for the four lead-out terminals to ground.

[0019] Furthermore, diode D1 is an anti-reverse diode.

[0020] Compared with the prior art, the present invention has the following beneficial technical effects:

[0021] For the delay relay of the present invention, the power conversion module converts the bus voltage V CC into a fixed voltage V that can supply the subsequent automatic reset module and timing module to work. D , when the bus voltage changes, V D can remain stable, without affecting the delay accuracy of the circuit, and has good delay stability; when the automatic reset module resets, a delay control signal is generated through the counting module to control the on and off of the electronic switch module, thereby realizing the delay conduction and off functions of the circuit, and the delay accuracy is high. The relay of the present invention can avoid the problems of arc and electromagnetic interference of electromagnetic relays.

[0022] Furthermore, for the timing module of the present invention, without changing the circuit structure and layout, by adjusting the output stage number and resistance value of the counter part in the timing module, the adjustability of the delay time can be realized, and the maximum delay can reach 500 s.

[0023] Furthermore, by using radiation-hardened chips, the delay relay can have radiation resistance.

[0024] Furthermore, by using precision thin-film resistors, when the output stage number of the counter and the capacitor have been selected, by performing functional trimming on the precision thin-film resistors, the high delay accuracy of the delay relay can be ensured.

[0025] Furthermore, by setting an anti-static network, the delay relay can have anti-static ability.

[0026] Further, diode D1 is an anti-reverse diode, which can prevent damage to the circuit when the power supply voltage is reversed. Description of the Drawings

[0027] Figure 1 is the electrical principle block diagram of the time-delay relay of the present invention;

[0028] Figure 2 is the detailed schematic diagram of the voltage conversion module, automatic reset module and electronic switch module of the time-delay relay of the present invention;

[0029] Figure 3 is the detailed schematic diagram of the timing module of the time-delay relay of the present invention;

[0030] Figure 4 is the functional timing diagram of the timing module of the time-delay relay of the present invention. Detailed Embodiments

[0031] The following further describes the present invention in detail with specific embodiments, which are explanations rather than limitations of the present invention.

[0032] As Figure 1 shown, the circuit structure of the time-delay relay of the present invention includes a voltage conversion module, an automatic reset module, a timing module and an electronic switch module, which can realize the functions of delayed conduction and cut-off. The delay times are taken as t1 = 100 ms and t2 = 100 ms as examples.

[0033] The power conversion module converts the bus voltage V CC into a fixed voltage V D for the subsequent automatic reset module and timing module to work through a reference source and a current-limiting resistor. When the bus voltage changes, V D can remain stable and does not affect the delay accuracy of the circuit.

[0034] The automatic reset module automatically resets the subsequent timing module after the bus is powered on, so that the timing module starts timing. The reset time can be set by changing the RC value according to the user's requirements.

[0035] The timing module generates a delay control signal through a counter, a flip-flop and an exclusive-OR gate circuit after the automatic reset module resets, and controls the on and off of the electronic switch module, thereby realizing the functions of delayed conduction and cut-off of the circuit, and having high delay accuracy. Without changing the circuit structure and layout, the delay time can be adjusted by adjusting the output stage number and resistance value of the counter part in the timing module.

[0036] The electronic switch module can realize the switching of the on and off of the power supply and the load.

[0037] Figure 2The voltage conversion module in it is to convert the system bus voltage V CC When it is 18V to 32V (nominal value 28V), convert its voltage to the voltage V D for the subsequent automatic reset module and timing module to work. The voltage conversion module consists of diode D1, current-limiting resistor R1, reference source DZ1 and its voltage-dividing resistors R2, R3. The positive electrode of diode D1 is connected to power supply V CC The negative electrode of diode D1 is connected to one end of current-limiting resistor R1. The other end of current-limiting resistor R1 is connected to the negative electrode of reference source DZ1. The positive electrode of reference source DZ1 and one end of resistor R3 are both grounded. The other end of resistor R3 is connected to the reference terminal of reference source DZ1 and one end of resistor R2. The other end of resistor R2 is connected to the other end of resistor R1 and the negative electrode of reference source DZ1. One end of the negative electrode of reference source DZ1 is the voltage output terminal. By adjusting the resistance values of resistors R2 and R3, set the output voltage V D of reference source DZ1 to 5V; adjust the resistance value of R1. While limiting the input current of the circuit, make the cathode current passing through reference source DZ1 greater than 1mA to make reference source DZ1 work properly. The voltage regulation rate of reference source DZ1 is less than 2mV / V. When the power supply voltage fluctuates (18V to 32V), the output V D of reference source DZ1 changes little, which can keep the delay time of the relay stable. Diode D1 is an anti-reverse diode, which can prevent damage to the circuit when the power supply voltage is reversed.

[0038] Figure 2 The automatic reset module in it is to automatically reset the subsequent timing module after the bus is powered on, so that the timing module starts timing work. The automatic reset module consists of triode T1, resistors R4, R5, R6 and capacitor C1. One end of resistor R4 and resistor R5 are both connected to the negative electrode of reference source DZ1. The other end of resistor R4 is connected to one end of resistor R6, one end of capacitor C1 and the base of triode T1. The other end of resistor R6 is connected to the other end of capacitor C1 and the emitter of triode T1 and both are grounded. The other end of resistor R5 is connected to the collector of triode T1. One end of the collector of triode T1 is the reset terminal R D . After the bus is powered on, reference source DZ1 generates a reference voltage of 5V. Since capacitor C1 starts to charge at this time, triode T1 is in the off state, and the reset terminal R D is a high level of 5V; after a certain period of time, capacitor C1 is fully charged, the emitter of triode T1 is forward-biased, making T1 saturated and conducting, and the reset terminal R D becomes a low level, thus completing the automatic reset function of the subsequent counter, flip-flop and exclusive-OR gate. According to the actual usage requirements of users, the time required for automatic reset can be adjusted by adjusting R6 and C1.

[0039] Figure 3 The timing module in Figure 3 generates a delay control signal through a counter, a flip-flop, and an exclusive-OR gate circuit after the automatic reset module is reset, controlling the on and off of the electronic switch module, thereby realizing the delay conduction and off functions of the circuit. The timing module consists of two groups of counters, their oscillation networks, flip-flops, and exclusive-OR gates. Each group of counters is connected in series with two to increase the frequency division times, so that the delay time can reach more than 500s. Specifically, it includes counter U1, counter U2, counter U3, counter U4, resistor R7, resistor R8, resistor R9, resistor R10, capacitor C2, capacitor C3, dual D flip-flop U5, and two-input exclusive-OR gate U6. The power supply terminals of counters U1, U2, U3, and U4 are all connected to the negative pole of the reference source DZ1, and the reset terminals of counters U1, U2, U3, and U4 are all connected to the collector of the triode T1. Resistors R7, R8, and capacitor C2 form the oscillation network of counter U1, and the output waveform period of the series connection of counters U1 and U2 is T1; resistors R9, R10, and capacitor C3 form the oscillation network of counter U3, and the output waveform period of the series connection of counters U3 and U4 is T2. The output terminals of counters U2 and U4 are respectively connected to the two clock terminals of the dual D flip-flop U5, and the two output signals sgn1 and sgn2 of the dual D flip-flop U5 are respectively connected to the two input terminals of the two-input exclusive-OR gate U6. The power supply terminal of the dual D flip-flop U5 is connected to the negative pole of the reference source DZ1, and the reset terminal of the dual D flip-flop U5 is connected to the collector of the triode T1. The power supply terminal of the two-input exclusive-OR gate U6 is connected to the negative pole of the reference source DZ1, the grounding terminal of the two-input exclusive-OR gate U6 is grounded, and the output signal of the two-input exclusive-OR gate U6 is the delay control signal, realizing the delay conduction and off functions of the electronic switch module. The functional timing diagram of the timing module is as Figure 4 shown.

[0040] The delay accuracy of the delay relay mainly depends on the resistance and capacitance configuration in the counter oscillation network, that is, resistors R7, R8, R9, R10, and capacitors C2, C3. The resistors are selected as precision thin-film resistor blocks with an accuracy of ±0.5% and a temperature coefficient <50ppm / ℃; the capacitors are selected with an accuracy of ±1% and a temperature coefficient of 30ppm / ℃. Under the condition that the output stage number of the counter and the capacitor have been selected, by performing functional trimming on the precision thin-film resistor, the high delay accuracy of the delay relay can be ensured. Without changing the components, by adjusting the output stage number of the counter and the resistance value of the precision thin-film resistor, the adjustability of the delay time can be realized.

[0041] Figure 2 The electronic switch module in Figure 2 can realize the power supply V CC and the load R LSwitching of on / off. The electronic switch module consists of resistors R11 to R14, transistor T2, zener diode D2, and P-channel VDMOS transistor Q1. One end of resistor R11 is connected to the output terminal of two-input exclusive-OR gate U6, and the other end of resistor R11 is connected to one end of resistor R12 and the base of transistor T2. The other end of resistor R12 and the emitter of transistor T2 are grounded. The collector of transistor T2 is connected to one end of resistor R14. The other end of resistor R14 is connected to one end of resistor R13 and the positive pole of zener diode D2. The other end of resistor R13 and the negative pole of zener diode D2 are both connected to power supply V CC connection. The gate of P-channel VDMOS transistor Q1 is connected to the positive pole of zener diode D2. The drain of P-channel VDMOS transistor Q1 is connected to load R L connection. The source of P-channel VDMOS transistor Q1 is connected to power supply V CC connection. When the output terminal of two-input exclusive-OR gate U6 is at a low level, transistor T2 is in the off state. There is a zero voltage difference between the gate and the source of P-channel VDMOS transistor Q1, and Q1 is turned off. There is no current in load R L ; When the output terminal of two-input exclusive-OR gate U6 is at a high level, transistor T2 is saturated and conducting. The bus voltage is divided by resistors R13 and R14, making the gate-source voltage difference of P-channel VDMOS transistor Q1 greater than its turn-on threshold voltage, and Q1 is turned on, forming a current path. Zener diode D2 is used as a protection tube, which can make the gate-source voltage difference of P-channel VDMOS transistor Q1 less than 20V to ensure that its gate is not broken down.

[0042] Figure 2 and Figure 3 The reference source DZ1, counters U1 to U4, dual D flip-flop U5, two-input exclusive-OR gate U6, and VDMOS transistor Q1 in 2 / mg are all selected as radiation-resistant chips, which can make the total dose of delay relay against γ ≥ 1E5 rad(Si), and the single-particle LET threshold: ≥ 75 MeV·cm

[0043] Figure 2 The output terminal V D , reset terminal R D , and the two output terminals sgn1 and sgn2 of dual D flip-flop U5 of

[0044] The present invention adopts thick film hybrid integrated circuit design technology to miniaturize and integrate the delay relay circuit; it has the functions of delayed conduction and shutdown. After the bus is powered on for a time t1, the relay output terminal conducts and works. After continuously working for a time t2, the relay output terminal shuts down; it has high delay accuracy; good delay stability, and the delay time can be kept stable within the range of bus voltage from 18V to 32V; without changing the circuit structure and layout, by adjusting the output stage number and resistance value of the counter part in the timing module, the delay time can be adjusted, and the maximum delay of 500s can be achieved; an anti-static network is set, which can make the anti-static ability of the delay relay greater than 2000V.

Claims

1. A time-delay relay, characterized in that, It includes a voltage conversion module, an automatic reset module, a timing module, and an electronic switch module; A power conversion module, which is used to convert the power supply voltage into a fixed voltage to supply power to the automatic reset module and the timing module; An automatic reset module, which is used to automatically reset the timing module to enable the timing module to start timing work; A timing module, which is used to generate a delay control signal after being reset by the automatic reset module to control the on and off of the electronic switch module; An electronic switch module, which is used to realize the switching of the on and off of the power supply and the load; The voltage conversion module includes a diode D1, a current-limiting resistor R1, a reference source DZ1, a resistor R2, and a resistor R3; the positive electrode of the diode D1 is connected to the power supply V CC The negative electrode of the diode D1 is connected to one end of the current-limiting resistor R1, the other end of the current-limiting resistor R1 is connected to the negative electrode of the reference source DZ1, the positive electrode of the reference source DZ1 and one end of the resistor R3 are both grounded, the other end of the resistor R3 is connected to the reference terminal of the reference source DZ1 and one end of the resistor R2, the other end of the resistor R2 is connected to the other end of the resistor R1 and the negative electrode of the reference source DZ1, and the negative electrode of the reference source DZ1 is the voltage output terminal V D ; The automatic reset module includes a triode T1, a resistor R4, a resistor R5, a resistor R6, and a capacitor C1; one ends of the resistor R4 and the resistor R5 are both connected to the negative pole of the reference source DZ1, the other end of the resistor R4 is connected to one end of the resistor R6, one end of the capacitor C1, and the base of the triode T1, the other end of the resistor R6 and the other end of the capacitor C1 and the emitter of the triode T1 are grounded, the other end of the resistor R5 is connected to the collector of the triode T1, and one end of the collector of the triode T1 is the reset terminal R D ; The timing module includes a counter U1, a counter U2, a counter U3, a counter U4, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a capacitor C2, a capacitor C3, a dual D flip-flop U5, and a two-input exclusive-OR gate U6; the power supply terminals of the counters U1, U2, U3, and U4 are all connected to the negative electrode of the reference source DZ1, and the reset terminals of the counters U1, U2, U3, and U4 are all connected to the collector of the triode T1; the resistors R7, R8, and the capacitor C2 form an oscillation network of the counter U1, and the counter U1 is connected in series with the U2; the resistors R9, R10, and the capacitor C3 form an oscillation network of the counter U3, and the counter U3 is connected in series with the U4; the output terminals of the counters U2 and U4 are respectively connected to two clock terminals of the dual D flip-flop U5, and the two output terminals sgn1 and sgn2 of the dual D flip-flop U5 are respectively connected to two input terminals of the two-input exclusive-OR gate U6, the power supply terminal of the dual D flip-flop U5 is connected to the negative electrode of the reference source DZ1, and the reset terminal of the dual D flip-flop U5 is connected to the collector of the triode T1; the power supply terminal of the two-input exclusive-OR gate U6 is connected to the negative electrode of the reference source DZ1, and the grounding terminal of the two-input exclusive-OR gate U6 is grounded.

2. The time delay relay according to claim 1, characterized in that, The electronic switch module includes a resistor R11, a resistor R12, a resistor R13, a resistor R14, a triode T2, a zener diode D2, and a P-channel VDMOS transistor Q1; one end of the resistor R11 is connected to the signal output terminal of the two-input exclusive-OR gate U6, and the other end of the resistor R11 is connected to one end of the resistor R12 and the base of the triode T2. The other end of the resistor R12 and the emitter of the triode T2 are grounded, the collector of the triode T2 is connected to one end of the resistor R14, the other end of the resistor R14 is connected to one end of the resistor R13 and the positive electrode of the zener diode D2, and the other end of the resistor R13 and the negative electrode of the zener diode D2 are both connected to the power supply V CC connection, the gate of the P-channel VDMOS transistor Q1 is connected to the positive electrode of the zener diode D2, the drain of the P-channel VDMOS transistor Q1 is connected to the load R L connection, the source of the P-channel VDMOS transistor Q1 is connected to the power supply V CC connection.

3. The time-delay relay according to claim 2, wherein, The reference source DZ1, the counters U1-U4, the dual D flip-flop U5, the two-input exclusive-OR gate U6, and the VDMOS transistor Q1 are all selected as radiation-resistant chips.

4. The delay relay according to claim 1, wherein The resistors R7, R8, R9, and R10 are precision thin-film resistor blocks with an accuracy of ±0.5% and a temperature coefficient <50 ppm / °C.

5. The time-delay relay according to claim 1, wherein The capacitors C2 and C3 have an accuracy of ±1% and a temperature coefficient of 30 ppm / °C.

6. The time delay relay according to claim 1, wherein, The voltage output terminal V of the reference source DZ1 D , the reset terminal R D , the two output terminals sgn1 and sgn2 of the dual D flip-flop U5 are both the lead-out terminals of the delay relay, and electrostatic protection voltage stabilizing diodes are respectively set for the four lead-out terminals to the ground.

7. The time delay relay according to claim 1, characterized in that, The diode D1 is an anti-reverse diode.

Images