Analog-to-Digital Conversion Device and Battery Management System

Abstract

The present disclosure provides an analog-to-digital conversion device, including: a first integration unit configured to receive an analog input signal and perform modulation conversion on the analog input signal to generate a first integration signal; a second integration unit configured to receive the first integration signal and perform modulation conversion on the first integration signal to generate a second integration signal; a quantization unit configured to compare the second integration signal with a reference signal and generate a digital bit stream with information of the analog input signal based on the second integration signal and the reference signal; and a low-pass filtering unit configured to perform shaping filtering on out-of-band noise in the digital bit stream output by the quantization unit. The present disclosure also provides a battery management system.

Description

Technical Field

[0001] The present disclosure relates to an analog-to-digital conversion device and a battery management system. Background Art

[0002] In a battery management system, an analog-to-digital conversion device is required to perform analog-to-digital conversion on a battery voltage or a detection signal in order to obtain a digital signal for digital processing.

[0003] In a conventional analog-to-digital conversion device, the output of the analog-to-digital conversion device may be subject to some interference, so the output of the analog-to-digital conversion device may not be stable. In the prior art, a filter such as a low-pass filter is also used to eliminate interference. However, in the existing method, the method of only filtering through a low-pass filter is not particularly ideal, and sometimes it cannot eliminate conversion errors and the like.

[0004] In the present disclosure, by improving the analog-to-digital conversion device itself and the filtering part, a novel low-noise and low-power analog-to-digital converter can be realized. Summary of the Invention

[0005] In order to solve one of the above technical problems, the present disclosure provides an analog-to-digital conversion device and a battery management system.

[0006] According to one aspect of the present disclosure, an analog-to-digital conversion device includes:

[0007] A first integration unit configured to receive an analog input signal and perform modulation conversion on the analog input signal to generate a first integration signal;

[0008] A second integration unit configured to receive the first integration signal and perform modulation conversion on the first integration signal to generate a second integration signal;

[0009] A quantization unit configured to compare the second integration signal with a reference signal and generate a digital code stream with information of the analog input signal based on the second integration signal and the reference signal;

[0010] A low-pass filtering unit configured to perform shaping filtering on out-of-band noise in the digital code stream output by the quantization unit; and

[0011] A random jitter filtering unit configured to perform filtering processing on the signal after shaping filtering by the low-pass filtering unit to eliminate random jitter data existing in the signal after shaping filtering and generate a digital output signal corresponding to the analog input signal.

[0012] According to at least one embodiment of the present disclosure, the random jitter filtering unit is configured to process a plurality of historical data in the shaped filtered signal and generate a digital output signal corresponding to the analog input signal based on the plurality of historical data, wherein the random jitter filtering unit removes random jitter data in the plurality of historical data and generates the digital output signal based on the historical data without random jitter, or the random jitter filtering unit reduces the influence of random jitter in the plurality of historical data so as to generate the digital output signal.

[0013] According to at least one embodiment of the present disclosure, the random jitter filtering unit is configured to eliminate random jitter in data of m valid bits out of N valid bits in the shaped filtered signal, where N≥2 and 1≤m≤N.

[0014] According to at least one embodiment of the present disclosure, the random jitter filtering unit is configured to eliminate random jitter in data of each valid bit out of N valid bits in the shaped filtered signal.

[0015] According to at least one embodiment of the present disclosure, in the first integration unit, one end of the first switch is connected to the first analog input signal terminal, and the other end is connected to one end of the first sampling capacitor. The other end of the first sampling capacitor is connected to the positive input terminal of the first operational amplifier via the second switch. One end of the third switch is connected to the first analog signal input terminal, and the other end is connected to one end of the second sampling capacitor. The other end of the second sampling capacitor is connected to the negative input terminal of the first operational amplifier via the fourth switch. One end of the fifth switch is connected to the second analog input signal terminal, and the other end is connected to one end of the second sampling capacitor. The other end of the second sampling capacitor is connected to the negative input terminal of the first operational amplifier via the fourth switch. The other end of the seventh switch is connected to the second analog input signal terminal, and the other end is connected to one end of the first sampling capacitor. The other end of the first switch is connected to the positive reference voltage terminal via the seventh switch and is connected to the negative reference voltage terminal via the eighth switch. The other end of the fifth switch is connected to the positive reference voltage terminal via the ninth switch and is connected to the negative reference voltage terminal via the tenth switch. The connection node of the first sampling capacitor and the second switch is connected to the regulation voltage via the eleventh switch, and the connection node of the second sampling capacitor and the fourth switch is connected to the regulation voltage via the twelfth switch. The negative output terminal of the first operational amplifier is connected to its positive input terminal via the first integration capacitor, and the positive output terminal of the first operational amplifier is connected to its negative input terminal via the second integration capacitor.

[0016] According to at least one embodiment of the present disclosure, in the second integration unit, one end of a thirteenth switch is connected to the positive output terminal of a first operational amplifier, and the other end is connected to one end of a third sampling capacitor. The other end of the third sampling capacitor is connected to the positive input terminal of a second operational amplifier via a fourteenth switch. The other end of the thirteenth switch is connected to an external voltage via a fifteenth switch. The other end of the third sampling capacitor is connected to an adjustment voltage via a sixteenth switch. One end of a seventeenth switch is connected to the negative output terminal of the first operational amplifier, and the other end is connected to one end of a fourth sampling capacitor. The other end of the fourth sampling capacitor is connected to the negative input terminal of the second operational amplifier via an eighteenth switch. The other end of the seventeenth switch is connected to the external voltage via a nineteenth switch. The other end of the fourth sampling capacitor is connected to the adjustment voltage via a twentieth switch. The negative output terminal of the second operational amplifier is connected to its positive input terminal via a third integration capacitor, and the positive output terminal of the second operational amplifier is connected to its negative input terminal via a fourth integration capacitor.

[0017] According to at least one embodiment of the present disclosure, the structure of the first operational amplifier is as follows:

[0018] The source of a first PMOS transistor is connected to a system voltage. The gate of the first PMOS transistor is connected to a control voltage to control its conduction and cutoff. The drain of the first PMOS transistor is connected to the sources of a second PMOS transistor and a third PMOS transistor. The gates of the second PMOS transistor and the third PMOS transistor are respectively connected to the positive input terminal and the negative input terminal. The drains of the second PMOS transistor and the third PMOS transistor are respectively connected to the negative input terminal and the positive input terminal of a first amplifier. The negative input terminal and the positive input terminal of the first amplifier are respectively grounded through a first NMOS transistor and a second NMOS transistor, and the gates of the first NMOS transistor and the second NMOS transistor are connected. The negative output terminal and the positive output terminal of the first amplifier are respectively connected to the gates of a third NMOS transistor and a fourth NMOS transistor. The sources of the third NMOS transistor and the fourth NMOS transistor are respectively connected to the positive input terminal and the negative input terminal of the first amplifier. The drains of the third NMOS transistor and the fourth NMOS transistor serve as the output terminals of the operational amplifier. The sources of a fourth PMOS transistor and a fifth PMOS transistor are connected to the system voltage. The gates of the fourth PMOS transistor and the fifth PMOS transistor are connected. The drains of the fourth PMOS transistor and the fifth PMOS transistor are respectively connected to the negative input terminal and the positive input terminal of a second amplifier and are respectively connected to the sources of a sixth PMOS transistor and a seventh PMOS transistor. The gates of the sixth PMOS transistor and the seventh PMOS transistor are respectively connected to the positive output terminal and the negative output terminal of the second amplifier and are respectively connected to the drains of the third NMOS transistor and the fourth NMOS transistor.

[0019] According to at least one embodiment of the present disclosure, the structure of the second operational amplifier is as follows:

[0020] The source of the first PMOS transistor is connected to the system voltage. The gate of the first PMOS transistor is connected to the control voltage to control its conduction and cutoff. The drain of the first PMOS transistor is connected to the sources of the second PMOS transistor and the third PMOS transistor. The gates of the second PMOS transistor and the third PMOS transistor are respectively connected to the positive input terminal and the negative input terminal. The drains of the second PMOS transistor and the third PMOS transistor are respectively connected to the negative input terminal and the positive input terminal of the first amplifier. And the negative input terminal and the positive input terminal of the first amplifier are respectively grounded through the first NMOS transistor and the second NMOS transistor. And the gates of the first NMOS transistor and the second NMOS transistor are connected. The negative output terminal and the positive output terminal of the first amplifier are respectively connected to the gates of the third NMOS transistor and the fourth NMOS transistor. The sources of the third NMOS transistor and the fourth NMOS transistor are respectively connected to the positive input terminal and the negative input terminal of the first amplifier. The drains of the third NMOS transistor and the fourth NMOS transistor serve as the output terminals of the operational amplifier. The sources of the fourth PMOS transistor and the fifth PMOS transistor are connected to the system voltage. The gates of the fourth PMOS transistor and the fifth PMOS transistor are connected. The drains of the fourth PMOS transistor and the fifth PMOS transistor are respectively connected to the negative input terminal and the positive input terminal of the second amplifier and are respectively connected to the sources of the sixth PMOS transistor and the seventh PMOS transistor. The gates of the sixth PMOS transistor and the seventh PMOS transistor are respectively connected to the positive output terminal and the negative output terminal of the second amplifier and are respectively connected to the drains of the third NMOS transistor and the fourth NMOS transistor.

[0021] According to at least one embodiment of the present disclosure, the quantization unit includes a preamplification circuit and a latch. Wherein the preamplification circuit amplifies the output signal of the second integration unit by a predetermined gain, and the latch latches the signal after being amplified by the predetermined gain.

[0022] According to at least one embodiment of the present disclosure, a chopper circuit is further included. The chopper circuit is used to eliminate the offset voltage of the operational amplifier and is connected between the operational amplifier and the integration capacitor. The chopper circuit performs two modulations to modulate the offset voltage to the position of the clock phase frequency.

[0023] According to at least one embodiment of the present disclosure, the low-pass filtering unit includes two cascaded digital filters. Each data filter includes an adder and a register. When each new data is input into each data filter, it is added to the previous data through the adder, and the result after addition is saved by the register, and then waits for the next data input, and the addition and saving are performed periodically.

[0024] According to at least one embodiment of the present disclosure, the dither filter unit performs filtering processing on each bit of data among the N valid bits of the analog-to-digital conversion device, and each bit of data is respectively connected to a dither filter unit.

[0025] According to at least one embodiment of the present disclosure, the dither filter unit simultaneously performs filtering processing on m bits of data among the N valid bits of the analog-to-digital conversion device, and the m bits of data are connected to a dither filter unit.

[0026] According to at least one embodiment of the present disclosure, the dither filter unit receives i historical data and determines its output signal according to the repetition times and / or change trends of the input data, where i is greater than or equal to 2.

[0027] According to another aspect of the present disclosure, a battery management system includes:

[0028] The analog-to-digital conversion device as described above;

[0029] A battery voltage acquisition unit, which is used to acquire the voltage of a battery / battery pack and provide the acquired voltage signal to the analog-to-digital conversion device;

[0030] A control logic unit, which receives the digital signal converted by the analog-to-digital conversion device and generates a driving signal for a charge and discharge switch so as to control the charging and discharging of the battery.

[0031] According to at least one embodiment of the present disclosure, it further includes a charge and discharge current detection resistor, and the charge and discharge measurement signal generated by the charge and discharge current detection resistor is provided to the analog-to-digital conversion device and is subjected to analog-to-digital conversion by the analog-to-digital conversion device, and the converted signal is sent to the control logic unit, so that the control logic unit controls the charge and discharge switch according to the charge and discharge measurement signal. Brief Description of the Drawings

[0032] The drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, are used to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure, and the drawings are included in this specification and form a part of this specification.

[0033] Figure 1 A schematic diagram of an analog-to-digital conversion device according to an embodiment of the present disclosure is shown.

[0034] Figure 2 A circuit diagram of a first-stage integration unit according to an embodiment of the present disclosure is shown. Figure 3 A circuit diagram of a second-stage integration unit according to an embodiment of the present disclosure is shown.

[0035] Figure 4 Shows a circuit diagram of an operational amplifier according to an embodiment of the present disclosure.

[0036] Figure 5 Shows a circuit diagram of a quantization unit according to an embodiment of the present disclosure.

[0037] Figure 6 Shows a circuit diagram of a clock generation unit according to an embodiment of the present disclosure.

[0038] Figure 7 Shows a circuit diagram of a chopper circuit according to an embodiment of the present disclosure.

[0039] Figure 8 Shows a circuit diagram of a low-pass filter unit according to an embodiment of the present disclosure.

[0040] Figure 9 Shows a schematic diagram of a battery management system according to an embodiment of the present disclosure. Detailed Embodiments

[0041] The present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the relevant content and do not limit the present disclosure. Additionally, it should be noted that for the sake of description, only parts related to the present disclosure are shown in the drawings.

[0042] It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. The technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings and embodiments.

[0043] Unless otherwise specified, the exemplary embodiments / Examples shown will be understood to provide exemplary features of various details of some ways in which the technical concept of the present disclosure can be implemented in practice. Therefore, unless otherwise specified, without departing from the technical concept of the present disclosure, the features of various embodiments / Examples can be additionally combined, separated, interchanged, and / or rearranged.

[0044] In the drawings, the use of hatching and / or shading is generally used to make the boundaries between adjacent components clear. Thus, unless otherwise stated, the presence or absence of hatching or shading does not convey or imply any preference or requirement for the specific material, material properties, dimensions, proportions, commonality between the components shown, and / or any other characteristics, attributes, properties, etc. of the components. In addition, in the drawings, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be exaggerated. When the exemplary embodiments can be implemented differently, the specific process sequences may be performed in an order different from that described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to that described. In addition, the same reference numerals denote the same components.

[0045] When a component is referred to as being "on" or "above" another component, "connected to" or "coupled to" another component, the component can be directly on the other component, directly connected to or directly coupled to the other component, or there may be intervening components. However, when a component is referred to as being "directly on" another component, "directly connected to" or "directly coupled to" another component, there are no intervening components. For this reason, the term "connected" can refer to physical connection, electrical connection, etc., and with or without intervening components.

[0046] For descriptive purposes, the present disclosure may use spatial relative terms such as "under", "below", "beneath", "lower", "above", "upper", "on", "over", "higher", and "side (e.g., as in "sidewall")" to describe the relationship of one component to another (other) component as shown in the drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacturing. For example, if the device in the drawing is flipped, the component described as being "under" or "beneath" another component or feature will then be positioned "above" the other component or feature. Thus, the exemplary term "under" can encompass both "above" and "below" orientations. In addition, the device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations), and accordingly, the spatial relative descriptors used herein are to be interpreted.

[0047] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an" and "the" are also intended to include the plural forms. Further, when the terms "comprises" and / or "comprising" and variations thereof are used in this specification, it is specified that there are the stated features, integers, steps, operations, components, elements, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, elements, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and not as terms of degree, so they are used to explain the inherent deviations of measured values, calculated values and / or provided values that would be recognized by those of ordinary skill in the art.

[0048] According to one embodiment of the present disclosure, an analog-to-digital conversion device is provided.

[0049] Figure 1 A schematic block diagram of an analog-to-digital conversion device according to one embodiment of the present disclosure is shown. As Figure 1 shown, the analog-to-digital conversion circuit 10 may include an analog modulation section 100, a low-pass filtering unit 200, and a dither filtering unit 300.

[0050] The analog modulation section 100 may include a first integration unit 110, a second integration unit 120, and a quantization unit 130.

[0051] The first integration unit 110 is configured to receive an analog input signal and perform a modulation conversion on the analog input signal to generate a first integration signal.

[0052] The second integration unit 120 receives the first integration signal and performs a modulation conversion on the first integration signal to generate a second integration signal.

[0053] The quantization unit 130 is configured to compare the second integration signal with a reference signal and generate a digital code stream with information of the analog input signal based on the second integration signal and the reference signal.

[0054] The low-pass filtering unit 200 may be configured to perform shaping filtering on out-of-band noise in the digital code stream output by the quantization unit 130.

[0055] The dither filtering unit 300 performs filtering processing on the signal after shaping filtering by the low-pass filtering unit 200 to eliminate the dither data existing in the signal after shaping filtering and generate a digital output signal corresponding to the analog input signal.

[0056] The first integration unit 110 may be in the form of a switched-capacitor integrator. According to a preferred example of the present disclosure, there is provided asFigure 2 The shown switched-capacitor integrator, where the novel switched-capacitor integrator has advantages such as high time-constant accuracy, good temperature characteristics, and easy clock control.

[0057] As Figure 2 shown, the first integration unit 110 can be composed of switches, capacitors, and operational amplifiers.

[0058] One end of the first switch S1-1 is connected to the first analog input signal terminal Vip, and the other end is connected to one end of the first sampling capacitor C1. The other end of the first sampling capacitor C1 is connected to the positive input terminal of the first operational amplifier OP1 via the second switch S6-1. One end of the third switch S2-1 is connected to the first analog signal input terminal, and the other end is connected to one end of the second sampling capacitor C2. The other end of the second sampling capacitor C2 is connected to the negative input terminal of the first operational amplifier OP1 via the fourth switch S6-2. One end of the fifth switch S1-2 is connected to the second analog input signal terminal Vin, and the other end is connected to one end of the second sampling capacitor C2. The other end of the second sampling capacitor C2 is connected to the negative input terminal of the first operational amplifier OP1 via the fourth switch S6-2. The other end of the seventh switch S2-2 is connected to the second analog input signal terminal Vin, and the other end is connected to one end of the first sampling capacitor C1.

[0059] The other end of the first switch S11 is connected to the positive reference voltage terminal Vr+ via the seventh switch S3-1 and is connected to the negative reference voltage terminal Vr- via the eighth switch S4-1.

[0060] The other end of the fifth switch S1-2 is connected to the positive reference voltage terminal Vr+ via the ninth switch S3-2 and is connected to the negative reference voltage terminal Vr- via the tenth switch S4-2.

[0061] The connection node of the first sampling capacitor C1 and the second switch S6-1 is connected to the adjustment voltage Vcmi via the eleventh switch, and the connection node of the second sampling capacitor C2 and the fourth switch S6-2 is connected to the adjustment voltage Vcmi via the twelfth switch (the adjustment voltage can be determined according to the actual situation).

[0062] In addition, the negative output terminal of the first operational amplifier OP1 is connected to the positive input terminal via the first integration capacitor C3, and the positive output terminal of the first operational amplifier OP1 is connected to the negative input terminal via the second integration capacitor C4.

[0063] Through the first integration unit 110, at the first phase of the switch control signal, by controlling the on and off of the switches, the integration capacitor in the first integration unit 110 samples the analog input signal. At the second phase of the switch control signal, by controlling the on and off of the switches, the signal of the integration capacitor in the first integration unit 110 is transmitted to the integration capacitor, and it works periodically in this way.

[0064] Preferably, the first sampling capacitor and the second sampling capacitor are symmetric and have equal capacitance values, and the first integrating capacitor and the second integrating capacitor are symmetric and have equal capacitance values. With this structure, smaller sampling capacitors can be used and the stability is better. This is because Figure 2 the structure shown adopts a structure insensitive to parasitics, so it can also achieve better adaptability to some physical parasitics and some non-ideal factors, and correspondingly smaller capacitors are also used.

[0065] Figure 3 FIG. shows a specific circuit diagram of the second integrating unit 120 according to an embodiment of the present disclosure. Among them, according to this novel switched-capacitor integrator, it has the advantages of high time-constant accuracy, good temperature characteristics, and easy clock control.

[0066] One end of the thirteenth switch W1-1 is connected to the positive output terminal V1+ of the first operational amplifier OP1, and the other end is connected to one end of the third sampling capacitor C5. The other end of the third sampling capacitor C5 is connected to the positive input terminal of the second operational amplifier OP2 via the fourteenth switch W3-1. The other end of the thirteenth switch W1-1 is connected to the external voltage Vcm via the fifteenth switch W2-1. The other end of the third sampling capacitor C5 is connected to the adjustment voltage Vcmi via the sixteenth switch W4-1. One end of the seventeenth switch W1-2 is connected to the negative output terminal V1- of the first operational amplifier OP1, and the other end is connected to one end of the fourth sampling capacitor C6. The other end of the fourth sampling capacitor C6 is connected to the negative input terminal of the second operational amplifier OP2 via the eighteenth switch W3-2. The other end of the seventeenth switch W1-2 is connected to the external voltage Vcm via the nineteenth switch W2-2. The other end of the fourth sampling capacitor C6 is connected to the adjustment voltage Vcmi via the twentieth switch W4-2.

[0067] In addition, the negative output terminal V2- of the second operational amplifier OP2 is connected to the positive input terminal via the third integrating capacitor C7, and the positive output terminal V2+ of the second operational amplifier OP2 is connected to the negative input terminal via the fourth integrating capacitor C8.

[0068] To meet the precise measurement requirements, according to a preferred embodiment of the present disclosure, a gain-enhanced operational amplifier structure is also provided in the present disclosure, where this operational amplifier structure can be used as the first operational amplifier structure and the second operational amplifier structure described above.

[0069] Figure 4 FIG. shows a schematic diagram of the operational amplifier structure according to the present disclosure.

[0070] The structure of this operational amplifier is:

[0071] The source of the first PMOS transistor M0 is connected to the system voltage. The gate of the first PMOS transistor M0 is connected to a control voltage to control its conduction and cutoff. The drain of the first PMOS transistor is connected to the source of the second PMOS transistor M1 and the source of the third PMOS transistor M2. The gates of the second PMOS transistor M1 and the third PMOS transistor M2 are respectively connected to the positive input terminal and the negative input terminal. The drains of the second PMOS transistor M1 and the third PMOS transistor M2 are respectively connected to the negative input terminal and the positive input terminal of the first amplifier An. And the negative input terminal and the positive input terminal of the first amplifier An are respectively grounded through the first NMOS transistor M4 and the second NMOS transistor M3, and the gates of the first NMOS transistor M4 and the second NMOS transistor M3 are connected.

[0072] The negative output terminal and the positive output terminal of the first amplifier An are respectively connected to the gates of the third NMOS transistor M5 and the fourth NMOS transistor M6. The sources of the third NMOS transistor M5 and the fourth NMOS transistor M6 are respectively connected to the positive input terminal and the negative input terminal of the first amplifier An. The drains of the third NMOS transistor M5 and the fourth NMOS transistor M6 serve as the output terminals of the operational amplifier.

[0073] The sources of the fourth PMOS transistor M9 and the fifth PMOS transistor M10 are connected to the system voltage. The gates of the fourth PMOS transistor M9 and the fifth PMOS transistor M10 are connected. The drains of the fourth PMOS transistor M9 and the fifth PMOS transistor M10 are respectively connected to the negative input terminal and the positive input terminal of the second amplifier Ap and are respectively connected to the sources of the sixth PMOS transistor M7 and the seventh PMOS transistor M8. The gates of the sixth PMOS transistor M7 and the seventh PMOS transistor M8 are respectively connected to the positive output terminal and the negative output terminal of the second amplifier Ap and are respectively connected to the drains of the third NMOS transistor M5 and the fourth NMOS transistor M6.

[0074] Figure 5 The circuit diagram of the quantization unit according to the present disclosure is provided. In this quantizer, a preamplification circuit and a latch may be included. The preamplification circuit amplifies the input signal (the output signal of the second integration unit) to a predetermined level (predetermined gain), and the latch latches the amplified signal. And as Figure 5 shown in the circuit structure, the output terminals Q and QB serve as the output terminals of the quantizer.

[0075] For the first integration unit as Figure 2 shown and the second integration unit as Figure 3 shown, the switching control can be performed using the clock signal generated by the clock generation circuit as Figure 6 shown.

[0076] Through Figure 6 The clock generation circuit described above can generate three two-phase non-overlapping clocks (clk1, clk2; clk1', clk2'; clk1", clk2"), which can ensure the correctness of the timing of the analog-to-digital conversion device. Through these overlapping signals, for example, the Figure 2 and Figure 3 shown switches can be controlled. In this way, the circuit can work alternately under different control signals.

[0077] In addition, according to a preferred embodiment of the present disclosure, a chopper circuit can be provided in the analog modulation unit 100. Figure 7 The circuit diagram of the chopper circuit is shown.

[0078] Wherein the chopper circuit can be provided between the operational amplifier and the integrating capacitor as shown in Figure 2 The offset voltage of the operational amplifier can be eliminated by selecting or turning off the chopper circuit. Through the chopper circuit of the present disclosure, a lower offset voltage can be achieved. Specifically, the chopper circuit can modulate the offset voltage to a high frequency and then filter it out. While the original signal remains in its original state and is not affected.

[0079] The chopper circuit mainly consists of two switches and is controlled by a certain timing. In the first phase, INP is connected to OUTP, and INN is connected to OUTN. And in the second phase, INP is connected to OUTN, and INN is connected to OUTP. In this way, two modulations are achieved, and the offset voltage is modulated to the position of the clock phase frequency. And the original signal also undergoes modulation, but the second modulation modulates it back to its original position and is not affected.

[0080] The low-pass filtering unit 200 is used to shape and filter out-of-band noise in the digital bit stream output by the quantization unit.

[0081] Figure 8 The schematic diagram of the low-pass filtering unit 200 according to an embodiment of the present disclosure is given.

[0082] As shown in Figure 8 The low-pass filtering unit 200 can include two cascaded digital filters, a first-stage digital filter 210 and a second-stage digital filter 220. The digital filter used can be a FIR low-pass digital filter.

[0083] Wherein the structures of the first-stage digital filter 210 and the second-stage digital filter 220 can be the same.

[0084] The first-stage digital filter 210 may only include a first-stage adder 211 and a first-stage register 212, and there is no need for a multiplication unit in the first-stage digital filter 210.

[0085] The first-stage adder 211 receives the output Q of the quantizer 130, and the first-stage adder 211 is connected to the first-stage register 212, and the first-stage adder 211 is also connected to the output of the first-stage register 212. Through the first-stage digital filter 210, when receiving an output data of the quantizer 130, the first-stage adder 211 adds the output data with the previous output data (obtained from the output of the first-stage register 212), and the added data is transmitted from the first-stage adder 211 to the first-stage register 212 and saved by the first-stage register 212, then waits for the next input data. When receiving a new data from the quantizer 130 again, the first-stage adder 211 adds the new data with the data saved in the register, and the added data is output to the first-stage register 212 and saved by the first-stage register 212. It works cyclically in this way to complete the process of accumulation and saving.

[0086] The second-stage adder 221 receives the output of the first-stage register 212, and the second-stage adder 221 is connected to the second-stage register 222, and the second-stage adder 221 is also connected to the output of the second-stage register 222. Through the second-stage digital filter 220, when receiving an output data of the first-stage register 212, the second-stage adder 221 adds the output data with the previous output data (obtained from the output of the second-stage register 222), and the added data is transmitted from the second-stage adder 221 to the second-stage register 222 and saved by the second-stage register 222, then waits for the next input data. When receiving a new data from the first-stage register 212 again, the second-stage adder 221 adds the new data with the data saved in the register, and the added data is output to the second-stage register 222 and saved by the second-stage register 222. It works cyclically in this way to complete the process of accumulation and saving.

[0087] In addition, the output of the second-stage adder 221 can be used as the output of the low-pass filtering unit 200.

[0088] In addition, a downsampling module and a gain module can be added at the back end of the low-pass filter 200.

[0089] In such a digital filter of the low-pass filter, there is no need to use a multiplication unit, and the filter is only composed of adders and registers, so it can have the advantages of small hardware resources, high execution efficiency, and small group delay.

[0090] InFigure 8 It is also shown that the low-pass filtering unit 200 may further include a third-stage digital filter 230 and a fourth-stage digital filter 240. In this case, the output of the adder 241 of the fourth-stage digital filter 240 may be used as the output of the low-pass filtering unit 200.

[0091] The third-stage adder 231 receives the output of the second-stage register 222, and the third-stage adder 231 is connected to the third-stage register 232, and the third-stage adder 231 is also connected to the output of the third-stage register 232. Through the third-stage digital filter 230, when receiving an output data of the second-stage filter 220, the output data is added to the previous output data (obtained from the output of the third-stage register 232) by the third-stage adder 231. The added data is transmitted from the third-stage adder 231 to the third-stage register 232 and saved by the third-stage register 232, and then waits for the next input data. When receiving a new data from the second-stage digital filter 220 again, the new data is added to the data saved in the register by the third-stage adder 231. The added data is output to the third-stage register 232 and saved by the third-stage register 232. Such periodic operation is performed to complete the process of accumulation and saving.

[0092] The fourth-stage adder 241 receives the output of the third-stage register 232, and the fourth-stage adder 241 is connected to the fourth-stage register 242, and the fourth-stage adder 241 is also connected to the output of the fourth-stage register 242. Through the fourth-stage digital filter 240, when receiving an output data of the third-stage register 232, the output data is added to the previous output data (obtained from the output of the fourth-stage register 242) by the fourth-stage adder 241. The added data is transmitted from the fourth-stage adder 241 to the fourth-stage register 242 and saved by the fourth-stage register 242, and then waits for the next input data. When receiving a new data from the third-stage register 232 again, the new data is added to the data saved in the register by the fourth-stage adder 241. The added data is output to the fourth-stage register 242 and saved by the fourth-stage register 242. Such periodic operation is performed to complete the process of accumulation and saving.

[0093] The random jitter filtering unit 300 will be described below.

[0094] The random jitter filtering unit 300 may process the shaped and filtered signal of the low-pass filtering unit through a noise coefficient matrix, where the noise coefficient matrix may be expressed as N(a) = (a 1 、a 2 、……、a i) where i is an integer greater than or equal to 2.

[0095] The noise factor matrix is determined by the system noise characteristics of the analog-to-digital conversion device and varies according to the system noise characteristics.

[0096] The random dither filtering unit can filter each bit of data among the N valid bits of the analog-to-digital conversion device, and each bit of data is respectively connected to a random dither filtering unit.

[0097] The random dither filtering unit can also filter m bits of data among the N valid bits of the analog-to-digital conversion device simultaneously, and the m bits of data are connected to a random dither filtering unit. For example, if N is 12 bits and m is set to 3 bits, then each 3 bits out of the 12 bits can be connected to a random dither filtering unit, and a total of 4 random dither filtering units can be connected in this way.

[0098] The processing of one bit (such as the least significant bit LSM) of data will be described below. Among them, the historical data of this bit of data is n, where n is greater than or equal to 2.

[0099] Obtain n historical data of the least significant bit: D 1 、D 2 、……、D n . And combine the n historical data with the above-mentioned noise factor matrix to determine the output data D out , for example, it can be through the following formula:

[0100] (a 1 ×D 1 +a 2 ×D 2 +……+a n ×D n ) / G = D out .

[0101] Among them, the value of the coefficient G can be selected as an appropriate value according to the actual requirements of the analog-to-digital conversion device.

[0102] Even if the data has a certain perturbation in this way, from the outside, the data still remains stable and unchanged.

[0103] According to the present disclosure, a battery management system is also provided. The battery management system can be used to manage a battery or a battery pack, and the battery management system can be in the form of a chip. It should be noted that in the present disclosure, the charge and discharge control switch can be integrated inside the chip or arranged outside the chip. In the drawings of the present disclosure, the form in which the charge and discharge control switch is arranged inside the chip is described. In addition, an external charger or an external load can be connected to the positive and negative terminals of the battery or the battery pack to perform a charging operation or a discharging operation on the battery or the battery pack.

[0104] As Figure 9 shown, the battery management system may include a VDD generator, a voltage acquisition unit, a logic control unit, a driving unit, a charge and discharge control circuit, and the above-mentioned analog-to-digital conversion device.

[0105] The VDD generator generates a VDD voltage for internal use of the chip according to the highest voltage of the battery pack.

[0106] The voltage acquisition unit is used to acquire the voltage of the battery or the battery pack. When it is in the form of a battery pack, the voltage acquisition unit acquires the voltage of each battery, and the voltage acquisition unit provides the acquired battery voltage to the control logic unit, and the control logic unit controls the charge and discharge control switch through the driving unit.

[0107] In addition, a detection resistor R may also be included. The detection resistor is used to detect the charging current and the discharging current.

[0108] Among them, the signals detected by the voltage acquisition unit and the detection resistor can be provided to the analog-to-digital conversion device of the present disclosure for analog-to-digital conversion, and then the signals converted by the analog-to-digital conversion device are provided to the control logic unit.

[0109] In the description of this specification, the description with reference to terms such as "one embodiment / way", "some embodiments / ways", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment / way or example are included in at least one embodiment / way or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment / way or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments / ways or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments / ways or examples described in this specification and the features of different embodiments / ways or examples.

[0110] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0111] Those skilled in the art should understand that the above embodiments are merely for clearly illustrating the present disclosure and are not intended to limit the scope of the present disclosure. For those skilled in the art, other changes or modifications can be made based on the above disclosure, and these changes or modifications are still within the scope of the present disclosure.

Claims

1. An analog-to-digital conversion device, characterized in that, comprising: a first integration unit configured to receive an analog input signal and perform modulation conversion on the analog input signal to generate a first integration signal; a second integration unit configured to receive the first integration signal and perform modulation conversion on the first integration signal to generate a second integration signal; a quantization unit configured to compare the second integration signal with a reference signal and generate a digital bit stream with information of the analog input signal based on the second integration signal and the reference signal; a low-pass filtering unit configured to perform shaping filtering on out-of-band noise in the digital bit stream output by the quantization unit; and a random jitter filtering unit configured to process the signal after shaping filtering by the low-pass filtering unit through a noise coefficient matrix; the random jitter filtering unit is configured to process multiple historical data in the signal after shaping filtering by the low-pass filtering unit and generate a digital output signal corresponding to the analog input signal based on the multiple historical data, wherein the random jitter filtering unit removes random jitter data in the multiple historical data and generates the digital output signal based on the historical data without random jitter, or the random jitter filtering unit reduces the influence of random jitter data in the multiple historical data so as to generate the digital output signal.

2. The analog-to-digital conversion device according to claim 1, characterized in that, the random jitter filtering unit is configured to eliminate random jitter in data of m valid bits among N valid bits in the signal after shaping filtering, where N≥2 and 1≤m≤N.

3. The analog-to-digital conversion device according to claim 1, characterized in that, the random jitter filtering unit is configured to eliminate random jitter in data of each of the N valid bits in the signal after shaping filtering.

4. The analog-to-digital conversion device according to claim 1, characterized in that, In the first integration unit, one end of the first switch is connected to the first analog input signal terminal, and the other end is connected to one end of the first sampling capacitor. The other end of the first sampling capacitor is connected to the positive input terminal of the first operational amplifier via the second switch. One end of the third switch is connected to the first analog signal input terminal, and the other end is connected to one end of the second sampling capacitor. The other end of the second sampling capacitor is connected to the negative input terminal of the first operational amplifier via the fourth switch. One end of the fifth switch is connected to the second analog input signal terminal, and the other end is connected to one end of the second sampling capacitor. The other end of the second sampling capacitor is connected to the negative input terminal of the first operational amplifier via the fourth switch. The other end of the seventh switch is connected to the second analog input signal terminal, and the other end is connected to one end of the first sampling capacitor. The other end of the first switch is connected to the positive reference voltage terminal via the seventh switch and is connected to the negative reference voltage terminal via the eighth switch. The other end of the fifth switch is connected to the positive reference voltage terminal via the ninth switch and is connected to the negative reference voltage terminal via the tenth switch. The connection node of the first sampling capacitor and the second switch is connected to the adjustment voltage via the eleventh switch, and the connection node of the second sampling capacitor and the fourth switch is connected to the adjustment voltage via the twelfth switch. The negative output terminal of the first operational amplifier is connected to its positive input terminal via the first integration capacitor, and the positive output terminal of the first operational amplifier is connected to its negative input terminal via the second integration capacitor.

5. The analog-to-digital conversion device according to claim 4, characterized in that, in the second integration unit, one end of the thirteenth switch is connected to the positive output terminal of the first operational amplifier, and the other end is connected to one end of the third sampling capacitor. The other end of the third sampling capacitor is connected to the positive input terminal of the second operational amplifier via the fourteenth switch. The other end of the thirteenth switch is connected to an external voltage via the fifteenth switch. The other end of the third sampling capacitor is connected to the adjustment voltage via the sixteenth switch. One end of the seventeenth switch is connected to the negative output terminal of the first operational amplifier, and the other end is connected to one end of the fourth sampling capacitor. The other end of the fourth sampling capacitor is connected to the negative input terminal of the second operational amplifier via the eighteenth switch. The other end of the seventeenth switch is connected to an external voltage via the nineteenth switch. The other end of the fourth sampling capacitor is connected to the adjustment voltage via the twentieth switch. The negative output terminal of the second operational amplifier is connected to its positive input terminal via the third integration capacitor, and the positive output terminal of the second operational amplifier is connected to its negative input terminal via the fourth integration capacitor.

6. The analog-to-digital conversion device according to claim 4, characterized in that, the structure of the first operational amplifier is: The source of the first PMOS transistor is connected to the system voltage, the gate of the first PMOS transistor is connected to the control voltage to control its conduction and cutoff, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor and the source of the third PMOS transistor, the gates of the second PMOS transistor and the third PMOS transistor are respectively connected to the positive input terminal and the negative input terminal, the drains of the second PMOS transistor and the third PMOS transistor are respectively connected to the negative input terminal and the positive input terminal of the first amplifier, and the negative input terminal and the positive input terminal of the first amplifier are respectively grounded through the first NMOS transistor and the second NMOS transistor, and the gates of the first NMOS transistor and the second NMOS transistor are connected. The negative output terminal and the positive output terminal of the first amplifier are respectively connected to the gates of the third NMOS transistor and the fourth NMOS transistor. The sources of the third NMOS transistor and the fourth NMOS transistor are respectively connected to the positive input terminal and the negative input terminal of the first amplifier. The drains of the third NMOS transistor and the fourth NMOS transistor serve as the output terminal of the operational amplifier. The sources of the fourth PMOS transistor and the fifth PMOS transistor are connected to the system voltage, the gates of the fourth PMOS transistor and the fifth PMOS transistor are connected, the drains of the fourth PMOS transistor and the fifth PMOS transistor are respectively connected to the negative input terminal and the positive input terminal of the second amplifier and are respectively connected to the sources of the sixth PMOS transistor and the seventh PMOS transistor. The gates of the sixth PMOS transistor and the seventh PMOS transistor are respectively connected to the positive output terminal and the negative output terminal of the second amplifier and are respectively connected to the drains of the third NMOS transistor and the fourth NMOS transistor.

7. The analog-to-digital conversion device according to claim 5, characterized in that the structure of the second operational amplifier is: The source of the first PMOS transistor is connected to the system voltage, the gate of the first PMOS transistor is connected to the control voltage to control its conduction and cutoff, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor and the source of the third PMOS transistor, the gates of the second PMOS transistor and the third PMOS transistor are respectively connected to the positive input terminal and the negative input terminal, the drains of the second PMOS transistor and the third PMOS transistor are respectively connected to the negative input terminal and the positive input terminal of the first amplifier, and the negative input terminal and the positive input terminal of the first amplifier are respectively grounded through the first NMOS transistor and the second NMOS transistor, and the gates of the first NMOS transistor and the second NMOS transistor are connected. The negative output terminal and the positive output terminal of the first amplifier are respectively connected to the gates of the third NMOS transistor and the fourth NMOS transistor. The sources of the third NMOS transistor and the fourth NMOS transistor are respectively connected to the positive input terminal and the negative input terminal of the first amplifier. The drains of the third NMOS transistor and the fourth NMOS transistor are used as the output terminals of the operational amplifier. The sources of the fourth PMOS transistor and the fifth PMOS transistor are connected to the system voltage. The gates of the fourth PMOS transistor and the fifth PMOS transistor are connected. The drains of the fourth PMOS transistor and the fifth PMOS transistor are respectively connected to the negative input terminal and the positive input terminal of the second amplifier and are respectively connected to the sources of the sixth PMOS transistor and the seventh PMOS transistor. The gates of the sixth PMOS transistor and the seventh PMOS transistor are respectively connected to the positive output terminal and the negative output terminal of the second amplifier and are respectively connected to the drains of the third NMOS transistor and the fourth NMOS transistor.

8. The analog-to-digital conversion device according to claim 1, characterized in that the quantization unit includes a pre-amplification circuit and a latch. Wherein the pre-amplification circuit amplifies the output signal of the second integration unit by a predetermined gain, and the latch latches the signal after being amplified by the predetermined gain.

9. The analog-to-digital conversion device according to claim 4, characterized in that the analog-to-digital conversion device further includes a chopper circuit. The chopper circuit is used to eliminate the offset voltage of the operational amplifier and is connected between the operational amplifier and the integration capacitor. The chopper circuit performs two modulations to modulate the offset voltage to the position of the clock phase frequency.

10. The analog-to-digital conversion device according to claim 1, characterized in that the low-pass filtering unit includes two cascaded digital filters. Each data filter includes an adder and a register. When each new data is input into each data filter, it is added to the previous data through the adder, and the result after addition is saved by the register, and then waits for the next data input, and the addition and saving are performed periodically.

11. The analog-to-digital conversion device according to claim 3, characterized in that the random dither filtering unit filters each bit of data in the N valid bits of the analog-to-digital conversion device, and each bit of data is respectively connected to a random dither filtering unit.

12. The analog-to-digital conversion device according to claim 2, wherein, the random dithering filter unit simultaneously filters m bits of data among the N valid bits of the analog-to-digital conversion device, and the m bits of data are connected to one random dithering filter unit.

13. The analog-to-digital conversion device according to claim 1, wherein, the random dithering filter unit receives n historical data, and determines the removal of the random dithering data or reduces the influence of the random dithering data in the n historical data according to the system noise of the analog-to-digital conversion device to determine its output signal, where n is greater than or equal to 2.

14. A battery management system, wherein, comprising: the analog-to-digital conversion device according to any one of claims 1 to 13; a battery voltage acquisition unit configured to acquire the voltage of a battery / battery pack and provide the acquired voltage signal to the analog-to-digital conversion device; a control logic unit that receives the digital signal converted by the analog-to-digital conversion device and generates a drive signal for a charge and discharge switch to control the charging and discharging of the battery.

15. The battery management system according to claim 14, wherein, it further includes a charge and discharge current detection resistor, and the charge and discharge measurement signal generated by the charge and discharge current detection resistor is provided to the analog-to-digital conversion device and undergoes analog-to-digital conversion by the analog-to-digital conversion device, and the converted signal is sent to the control logic unit, so that the control logic unit controls the charge and discharge switch according to the charge and discharge measurement signal.

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