Memory device including voltage generating system

Abstract

A memory device includes a memory array, a plurality of voltage generation systems, and a controller. The memory array includes a plurality of planes. Each of the plurality of voltage generation systems is electrically coupled to a corresponding plane in the plurality of planes. The controller is configured to turn on each of the plurality of voltage generation systems in response to a first command to access a first plane in the plurality of planes.

Description

Technical Field

[0001] The present disclosure relates generally to control of voltage generation systems, and more particularly, in one or more embodiments, the present disclosure relates to apparatus and methods for controlling a voltage generation system in a memory device. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuit devices in computers or other electronic devices. There are many different types of memory, including random-access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0003] Flash memory devices have evolved into a popular source of nonvolatile memory for a variety of electronic applications. Flash memory devices typically use a single-transistor memory cell that allows for high memory density, high reliability, and low power consumption. Programming of a charge storage structure (e.g., a floating gate or charge well), which is often referred to as writing, or other physical phenomena (e.g., phase change or polarization), causes a change in the threshold voltage of the memory cell, which determines the data value of each cell. Common uses of flash memory include personal computers, tablet computers, digital cameras, digital media players, cellular phones, solid-state drives, and removable memory modules, and such uses continue to grow.

[0004] A memory device may include a voltage generation system that supplies voltage for operating the memory device. The voltage generation system may need to be turned on and warmed up before use, and turned off and placed in an idle state when not in use. These on and off cycles of the voltage generation system may increase the time required to access the memory device.

[0005] For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative methods for controlling voltage generation systems in memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a simplified block diagram of one example of a memory device in communication with a processor as part of an electronic system.

[0007] Figures 2A to 2D It is available in the reference Figure 1A schematic diagram of a portion of a memory cell array depicting a type of memory device used.

[0008] Figure 3 is a simplified block diagram of another example of a memory device that includes a voltage generation system.

[0009] Figure 4 is a graph showing an example of voltage generation by a voltage generation system.

[0010] Figures 5A to 5B is a diagram showing another example of voltage generation by the voltage generation system.

[0011] Figures 6A to 6B is a schematic diagram of an example of a charge pump and discharge circuit system.

[0012] Figures 7A to 7E is a flow chart illustrating one example of a method for accessing a memory. DETAILED DESCRIPTION

[0013] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document and in which specific embodiments are shown by way of illustration. In the drawings, the same reference numerals throughout the several views describe substantially similar components. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered in a limiting sense.

[0014] Disclosed herein is an apparatus and method for controlling a voltage generation system of a memory device to reduce the time required to access the memory device for read, program and / or erase operations. A memory device may include a memory array, the memory array including a plurality of planes and a plurality of voltage generation systems, wherein each voltage generation system corresponds to a plane. In this context, the term plane includes the concept of a plane group (e.g., a group of a single plane). Each voltage generation system of the memory device may be turned on and preheated in response to a first command to access any of the planes of the memory array. Each voltage generation system may remain turned on until no command to access any plane of the memory array is being processed. Once all commands have been processed, each voltage generation system may be turned off and slowly discharged to an idle state. By turning on each voltage generation system in response to a first command, subsequent commands may be processed without delay. In addition, by slowly discharging each voltage generation system in response to no command being processed, if a subsequent command is received before the voltage generation system reaches an idle state, the preheating period may be shortened.

[0015] Figure 11 is a simplified block diagram of a first device in the form of a memory device 100 communicating with a second device in the form of a processor 130 as part of a third device in the form of an electronic system according to an embodiment. Some examples of electronic systems include personal computers, tablet computers, digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, cellular phones, etc. The processor 130, such as a controller external to the memory device 100, may be a memory controller or other external host device.

[0016] The memory device 100 includes a power circuit system 102. The power circuit system 102 may include a plurality of voltage generation systems that receive a power supply voltage (eg, V CC ) and provides a regulated voltage (e.g., a boosted voltage) for operating the memory device 100. The voltage generation system can be controlled to reduce the time required for read, program, and / or erase operations. In one example, the power supply voltage V CC In another example, the power supply voltage V CC Between 2.35 volts and 2.7 volts or another suitable voltage depending on the application.

[0017] Memory device 100 includes a memory cell array 104 that is logically arranged in rows and columns. Memory cells of a logical row are typically coupled to the same access line (commonly referred to as a word line), while memory cells of a logical column are typically selectively coupled to the same data line (commonly referred to as a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. Memory cells of at least a portion of memory cell array 104 ( Figure 1 ) can be programmed into one of at least two data states.

[0018] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 100 also includes I / O control circuitry 112 to manage the input of commands, addresses, and data to memory device 100 and the output of data and status information from memory device 100. Address register 114 communicates with I / O control circuitry 112 and row decoding circuitry 108 and column decoding circuitry 110 to latch address signals prior to decoding. Command register 124 communicates with I / O control circuitry 112 and control logic 116 to latch incoming commands.

[0019] The internal controller (e.g., control logic 116) controls access to the memory cell array 104 in response to a command and generates state information for the external processor 130, i.e., the control logic 116 is configured to perform access operations according to the embodiments described herein. The control logic 116 communicates with the row decoding circuit system 108 and the column decoding circuit system 110 to control the row decoding circuit system 108 and the column decoding circuit system 110 in response to an address.

[0020] Control logic 116 also communicates with cache registers 118. Cache registers 118 latch incoming or outgoing data as directed by control logic 116 to temporarily store the data while memory cell array 104 is busy writing or reading other data, respectively. During a programming operation (e.g., a write operation), data is transferred from cache registers 118 to data registers 120 for transfer to memory cell array 104; then, new data from I / O control circuitry 112 is latched in cache registers 118. During a read operation, data is transferred from cache registers 118 to I / O control circuitry 112 for output to external processor 130; then, new data is transferred from data registers 120 to cache registers 118. Status registers 122 communicate with I / O control circuitry 112 and control logic 116 to latch status information for output to processor 130.

[0021] The memory device 100 receives control signals at the control logic 116 from the processor 130 via a control link 132. The control signals may include at least chip enable CE#, command latch enable CLE, address latch enable ALE, and write enable WE#. Depending on the nature of the memory device 100, additional control signals (not shown) may be further received via the control link 132. The memory device 100 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the processor 130 via a multiplexed input / output (I / O) bus 134 and outputs the data to the processor 130 via the I / O bus 134.

[0022] For example, a command is received via input / output (I / O) pins [7:0] of the I / O bus 134 at the I / O control circuitry 112 and written into the command register 124. An address is received via input / output (I / O) pins [7:0] of the bus 134 at the I / O control circuitry 112 and written into the address register 114. Data is received via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices at the I / O control circuitry 112 and written into the cache register 118. The data is then written into the data register 120 for programming the memory cell array 104. For another embodiment, the cache register 118 may be omitted and the data is written directly into the data register 120. The data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices.

[0023] It will be appreciated by those skilled in the art that additional circuitry and signals may be provided and Figure 1 The memory device has been simplified. It should be recognized that the reference Figure 1 The functionality of the various block components described may not necessarily be separated into different components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device may be adapted to perform Figure 1 Alternatively, one or more components or component parts of an integrated circuit device may be combined to perform Figure 1 The functionality of a single block component.

[0024] Additionally, although specific I / O pins are described according to general conventions of receipt and output of various signals, it should be noted that other combinations or other numbers of I / O pins may be used in various embodiments.

[0025] Figure 2A FIG. 2 is a schematic diagram of a NAND memory array 200A, for example, as a portion of the memory cell array 104. The memory array 200A includes, for example, word lines 2020 to 202 N The access lines and bit lines 2040 to 204 M The word lines 202 may be coupled to the data lines in a many-to-one relationship. Figure 2A For some embodiments, memory array 200A may be formed over a semiconductor, which may be conductively doped to have a conductivity type such as p-type conductivity, such as to form a p-well, or to have n-type conductivity, such as to form an n-well.

[0026] The memory array 200A may be arranged in rows (each row corresponds to a word line 202) and in columns (each column corresponds to a bit line 204). Each column may include a string of memory cells coupled in series, such as NAND strings 2060 to 2064. M Each NAND string 206 may be coupled to a common source 216 and may include memory cells 2080 to 208 N Memory cell 208 represents a non-volatile memory cell for storing data. Memory cell 208 in each NAND string 206 may be connected in series between a select transistor 210 (eg, a field effect transistor) and a select transistor 212 (eg, a field effect transistor), wherein select transistor 210 is, for example, select transistors 2100 to 2101. M One of the select transistors 2120 to 21211 (eg, a source select transistor, usually referred to as a select gate source), the select transistor 212 is, for example, a select transistor 2120 to 21212 M One of the select transistors 2100 to 2101 (eg, may be a drain select transistor, often referred to as a select gate drain). M can be commonly coupled to a select line 214, such as a source select line, and select transistors 2120 to 212 M May be commonly coupled to a select line 215, such as a drain select line.

[0027] The source of each select transistor 210 may be connected to the common source 216. The drain of each select transistor 210 may be connected to the source of the memory cell 2080 in the corresponding NAND string 206. For example, the drain of the select transistor 2100 may be connected to the source of the memory cell 2080 of the corresponding NAND string 2060. Thus, each select transistor 210 may be configured to selectively couple the corresponding NAND string 206 to the common source 216. The control gate of each select transistor 210 may be connected to a select line 214.

[0028] The drain of each select transistor 212 can be connected to the bit line 204 of the corresponding NAND string 206. For example, the drain of the select transistor 2120 can be connected to the bit line 2040 of the corresponding NAND string 2060. The source of each select transistor 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select transistor 2120 may be connected to the memory cell 208 of the corresponding NAND string 2060. N Thus, each select transistor 212 can be configured to selectively couple a corresponding NAND string 206 to a corresponding bit line 204. A control gate of each select transistor 212 can be connected to a select line 215.

[0029] Figure 2A The memory array in may be a quasi-two-dimensional memory array and may have a substantially planar structure, for example, where the common source 216, the string 206, and the bit line 204 extend in substantially parallel planes. Alternatively, Figure 2A The memory array in can be a three-dimensional memory array, for example, where the strings 206 can extend substantially perpendicular to a plane containing the common source 216 and a plane containing the bit lines 204, and the plane containing the bit lines can be substantially parallel to the plane containing the common source 216.

[0030] The typical construction of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, a charge well, etc.) that can determine the data value of the cell (e.g., by a change in threshold voltage), and a control gate 236, such as Figure 2A Memory cell 208 may further have a defined source 230 and a defined drain 232. Memory cell 208 has its control gate 236 coupled to (and in some cases forms) word line 202.

[0031] A column of memory cells 208 is a NAND string 206 or multiple NAND strings 206 coupled to a given bit line 204. A row of memory cells 208 is the memory cells 208 that are commonly coupled to a given word line 202. A row of memory cells 208 may, but need not, include all of the memory cells 208 that are commonly coupled to a given word line 202. A row of memory cells 208 may generally be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 generally includes every other memory cell 208 that is commonly coupled to a given word line 202. For example, a row of memory cells 208 that is commonly coupled to a word line 202 may be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 generally includes every other memory cell 208 that is commonly coupled to a given word line 202. N The memory cells 208 selectively coupled to the even bit lines 204 (eg, bit lines 2040, 2042, 2044, etc.) may be one physical page of memory cells 208 (eg, even memory cells), while the memory cells 208 commonly coupled to the word line 202 may be one physical page of memory cells 208 (eg, even memory cells). N And the memory cells 208 selectively coupled to the odd bit lines 204 (eg, bit lines 2041, 2043, 2045, etc.) may be another physical page of memory cells 208 (eg, odd memory cells). Figure 2A The bit lines 2043 and 2045 are not explicitly depicted in the figure, but it is obvious from the figure that the bit line 204 of the memory cell array 200A can be from the bit line 2040 to the bit line 204 MContinuously numbered. Other groupings of memory cells 208 commonly coupled to a given word line 202 may also define a physical page of memory cells 208. For some memory devices, all memory cells commonly coupled to a given word line may be considered a physical page. Portions (e.g., upper or lower page memory cells) of a physical page (which may still be an entire row in some embodiments) that are read during a single read operation or programmed during a program operation may be considered a logical page.

[0032] Figure 2B is another schematic diagram of a portion of a memory cell array 200B, which may be used as a portion of the memory cell array 104 for reference purposes, for example. Figure 1 The type of memory described. Figure 2B The same numbered components in Figure 2A The description provided corresponds. Figure 2B Additional details of one example of a three-dimensional NAND memory array structure are provided. The three-dimensional NAND memory array 200B can incorporate a vertical structure that can include semiconductor pillars, where a portion of the pillars can serve as a channel region for the memory cells of the NAND strings 206. The NAND strings 206 can each be selectively connected to bit lines 2040 to 2044 through select transistors 212 (e.g., which can be drain select transistors, often referred to as select gate drains). M , and is selectively connected to a common source 216 through a select transistor 210 (e.g., which may be a source select transistor, often referred to as a select gate source). Multiple NAND strings 206 may be selectively connected to the same bit line 204. Subsets of NAND strings 206 may be selectively connected to the same bit line 204 by biasing select lines 2150 to 215 L The word lines 202 are connected to their respective bit lines 204 to selectively activate a particular select transistor 212 each between the NAND string 206 and the bit line 204. The select transistors 210 may be activated by applying a bias to the select line 214. Each word line 202 may be connected to multiple rows of memory cells in the memory array 200B. The rows of memory cells commonly connected to each other by a particular word line 202 may be collectively referred to as a layer.

[0033] Figure 2C is another schematic diagram of a portion of a memory cell array 200C, which may be used as a portion of the memory cell array 104 for reference purposes, for example. Figure 1 The type of memory described. Figure 2C The same numbered components in Figure 2A The memory cell array 200C may include the following: Figure 2A2 , an access (e.g., word) line 202, a data (e.g., bit) line 204, a select line 214 (e.g., a source select line), a select line 215 (e.g., a drain select line), and a source 216 are depicted in FIG. 2 . For example, a portion of the memory cell array 200A may be a portion of the memory cell array 200C. Figure 2C The grouping of NAND strings 206 into memory cell blocks 250 is depicted. A memory cell block 250 can be a grouping of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as an erase block. Each memory cell block 250 can represent those NAND strings 206 that are typically associated with a single select line 215, such as select line 2150. The sources 216 of a memory cell block 250 can be the source of the memory cell block 250. L For example, each memory cell block 2500 to 250 L They may be selectively commonly connected to the source 216. The access line 202 and the selection lines 214 and 215 of one memory cell block 250 may not be directly connected to the access line 202 and the selection lines 214 and 215 of any other memory cell block 250, respectively.

[0034] Data lines 2040 to 204 M The buffer portion 240 may be connected (eg, selectively connected) to a buffer portion 240, which may be part of a page buffer of a memory. The buffer portion 240 may be connected to a memory plane (eg, memory cell blocks 2500 to 250 L The buffer portion 240 may include a sensing device (not shown) for sensing the data value indicated on the corresponding data line 204, and a corresponding register (not shown) for storing the sensed data value from its corresponding memory plane.

[0035] Figure 2D It is available in the reference Figure 1 Schematic block diagram of a portion of a memory cell array used in a memory of the type described. The memory cell array 260 is depicted as having four memory planes 270 (e.g., memory planes 2700-2703) each in communication with a corresponding buffer portion 240, which may collectively form a page buffer 272. Although four memory planes 270 are depicted, other numbers of memory planes 270 may collectively communicate with the page buffer 272. Each memory plane 270 is depicted as including L+1 memory cell blocks 250 (e.g., memory cell blocks 2500-2503). L ).

[0036] Although combined with NAND flash Figures 2A to 2DExamples of, but the embodiments described herein are not limited to a particular array architecture or structure, and may include other structures (e.g., cross point memory, DRAM, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0037] Figure 3 3 is a simplified block diagram of another example of a memory device 300. The memory device 300 includes a memory array 302, a power circuit system 306, a detector 316, and a controller 318. The memory array 302 may include a power circuit system 306, a detector 316, and a controller 318. Figures 2A to 2D The NAND memory array described and shown. Power circuit system 306 and detector 316 can provide Figure 1 The controller 318 may provide Figure 1 portion of the control logic 116 .

[0038] The memory array 302 may include a plurality of planes 3040 to 304 N , where "N+1" is any suitable number of planes (e.g., 2, 4, 6, 8, or more). Each plane 3040-3044 may be accessed in response to an asynchronous command (e.g., a command to access a single plane of the memory array) or a synchronous command (e.g., a command to access multiple planes of the memory array in parallel). N The power circuit system 306 may include a plurality of voltage generating systems 3080 to 308 N Each voltage generating system 3080 to 308 N may include analog circuits 3100 to 310 respectively N , charge pump 3120 to 312 N and voltage regulators 3140 to 314 N In each voltage generating system 3080 to 308 N Within the analog circuits 3100 to 310 N can be respectively passed through signal paths 3110 to 311 N Electrically coupled to the charge pump 3120 to 312 N , and through the signal path 3150 to 315 N Electrically coupled to voltage regulators 3140 to 314 N . Charge pump 3120 to 312 N can be respectively transmitted through signal paths 3130 to 313 N Electrically coupled to voltage regulators 3140 to 314 N Each voltage generating system 3080 to 308 N Respectively through signal paths 3050 to 305 N Electrically coupled to corresponding planes 3040 to 304 NThe input of detector 316 is electrically coupled to power circuit system 306 via signal path 307 . The output of detector 316 is electrically coupled to controller 318 via signal path 317 . Controller 318 is electrically coupled to power circuit system 306 via signal path 319 .

[0039] Each voltage generating system 3080 to 308 N Analog circuits 3100 to 310 N The power supply voltage can be received to provide input voltage to each charge pump 3120 to 312 N . See below for reference Figures 6A to 6B Each of the charge pumps 3120 to 312 is described in more detail. N The charge pumps 3120 to 3121 are configured to receive an input voltage and provide an output voltage (eg, a voltage higher than the input voltage of a positive charge pump or a voltage lower than the input voltage of a negative charge pump) when enabled. N Multiple stages may be included, where each stage provides a portion of the output voltage. Each stage may include a diode and a capacitive element (e.g., a capacitor), where the capacitor is charged and discharged in response to a clock signal. Each charge pump 3120 to 312 N Gradually more charge is stored on the capacitors of each successive stage to achieve the desired voltage output. Each charge pump 3120 to 312 N The output voltage of the input voltage is provided to the voltage regulators 3140 to 314 respectively. N Each analog circuit 3100 to 310 N The input voltage may be provided to the voltage regulators 3140 to 3144 for control purposes. N . Voltage regulator 3140 to 314 N An input voltage may be received to provide a regulated voltage (eg, a pass gate voltage, a read voltage, and / or a program voltage) to planes 3040 to 3044, respectively. N .

[0040] As referenced below Figures 4 to 5B More specifically, when each voltage generating system 3080 to 308 N When turned on (eg, enabled), each charge pump 3120 to 312 N When each voltage generating system 3080 to 308 N When turned off (eg, disabled), each charge pump 3120 to 312 N is disabled and slowly discharged until each charge pump 3120 to 312 N The planes 3040 to 3044 of the memory array 302 may not be accessed. N, until the corresponding voltage generating system 3080 to 308 N The charge pump 3120 to 312 N is enabled and produces the desired output voltage.

[0041] The controller 318 is configured to access the plurality of planes 3040 to 304 in response to N The first plane (e.g., plane 3040, 3041, ..., or 304 N ) and turns on each voltage generating system 3080 to 308 N In one example, the controller 318 can be configured to switch on the plurality of planes 3040 to 304 in the first power mode. N The first plane corresponds to a plurality of voltage generating systems 3080 to 308 N A voltage generating system is provided, and is connected to the plurality of planes 3040 to 304 in a second power mode configured to consume less power than the first power mode. N The other planes correspond to the plurality of voltage generating systems 3080 to 308 N The first power mode may include: operating the plurality of planes 3040 to 304 at a first clock frequency. N The first plane corresponds to the charge pumps 3120 to 312 N and operating with the plurality of planes 3040 to 304 at a second clock frequency less than the first clock frequency N The other planes correspond to the charge pumps 3120 to 312 N .

[0042] Operating the other voltage generating systems in the second power mode may increase the amount of time required for the charge pumps of the other voltage generating systems to reach the desired output voltage. N The second asynchronous or synchronous command of the second plane will be connected to the plurality of planes 3040 to 304 N The second plane corresponds to a plurality of voltage generating systems 3080 to 308 N The power mode of the voltage generating system is changed from the second power mode to the first power mode.

[0043] The voltage generation system corresponding to the first plane may be ready within a first cycle. In one example, the first cycle is from the time when the voltage generation system is turned on to the time when the charge pump of the voltage generation system reaches the desired output voltage. The controller 318 is configured to execute the first command in response to the first cycle passing. After the first cycle passes and the plurality of voltage generation systems 3080 to 308 NWhen the controller 318 is turned on, the controller 318 is configured to respond to accessing the plurality of planes 3040 to 304 N Any subsequent commands of the corresponding plane in are executed without a delay cycle.

[0044] The controller 318 may be configured to shut down the plurality of voltage generating systems 3080 to 308 in response to no command being processed. N Each voltage generating system of the present invention is configured to be discharged to an idle state. In one example, discharging each voltage generating system includes discharging a charge pump of each voltage generating system. The idle state may include a fully discharged state such that the capacitance of each stage of the charge pump of each voltage generating system is fully discharged. In other examples, the idle state may include a partially discharged state such that the capacitance of one or more stages of the charge pump of each voltage generating system maintains a residual charge.

[0045] The detector 316 is configured to detect the plurality of voltage generating systems 3080 to 308 N In one example, the detector 316 is configured to detect the discharge level of the voltage generating system 3080 to 308 N Each charge pump 3120 to 312 N The detector 316 can detect the discharge level of each charge pump 3120 to 312 by comparing the output voltage of each charge pump with the reference voltage. N The difference between the output voltage and the reference voltage indicates the discharge level of the charge pump.

[0046] In one example, in the plurality of voltage generating systems 3080 to 308 N In the case of shutdown, the controller 318 can be configured to respond to access to the plurality of planes 3040 to 304 N The second command of the second plane turns on the plurality of voltage generating systems 3080 to 308 N Each voltage generating system. With multiple planes 3040 to 304 N The voltage generation system corresponding to the second plane is ready in the second cycle. In response to the plurality of voltage generation systems 3080 to 308 N The detected discharge level is higher than the level in the idle state, and the second period is shorter than the first period. The second period is the time from when the voltage generating system is turned on to when the charge pump of the voltage generating system reaches the desired output voltage.

[0047] In another example, in the plurality of voltage generating systems 3080 to 308 N In the case of shutdown, the controller 318 can be configured to respond to access to the plurality of planes 3040 to 304 N The second command of the second plane turns on the plurality of voltage generating systems 3080 to 308N In response to the plurality of voltage generating systems 3080 to 308 N The detected discharge level is at the idle state level, and the plurality of planes 3040 to 304 N The voltage generating system corresponding to the second plane in is ready within the first cycle.

[0048] In yet another example, in the plurality of voltage generating systems 3080 to 308 N In the case of shutdown, the controller 318 can be configured to respond to access to the plurality of planes 3040 to 304 N The second command of the first plane turns on the plurality of voltage generating systems 3080 to 308 N In response to the plurality of voltage generating systems 3080 to 308 N The detected discharge level is higher than the level of the idle state, and the plurality of planes 3040 to 304 N The voltage generation system corresponding to the first plane in is ready without a delay period.

[0049] Therefore, the controller 318 is configured to respond to accessing the plurality of planes 3040 to 304 N The first command of the first plane turns on the plurality of voltage generating systems 3080 to 308 N Each voltage generating system in the first cycle executes the first command in response to the first cycle lapse, and shuts down the plurality of voltage generating systems 3080 to 308 in response to no command being processed. N The controller 318 is configured to respond to the first cycle elapsed and in the plurality of voltage generating systems 3080 to 308 N Accessing the plurality of planes 3040 to 304 is performed without a delay cycle when each voltage generating system in the N The first command may include a read operation, a program operation, or an erase operation.

[0050] Figure 4 is shown by a voltage generating system such as Figure 3 Voltage generating system 3080 to 308 N, to generate a graph 400 of an example of a voltage. Graph 400 includes a transfer gate voltage 402, a word line voltage (e.g., a read voltage) 404, and a current (Icc) 406 versus time. Current 406 indicates the current drawn to generate voltages 402 and 404. When a command to access a plane of a memory array (e.g., a read command) is received, the voltage generation system turns on and preheats, as indicated at 408. The preheat delay at 408 may be in the range of 1 μs to 2 μs or more to allow the charge pump of the voltage generation system to reach a desired output voltage sufficient to generate the transfer gate voltage 402 and the word line voltage 404. Current 406 includes a first peak at 412 due to the charge pump charging during the preheat period at 408 to generate the desired output voltage. Once the charge pump of the voltage generation system has reached the desired output voltage, the transfer gate voltage 402 and the word line voltage 404 may be applied to the memory array to perform an operation (e.g., a read operation). When the pass gate voltage 402 and the word line voltage 404 are applied to the memory array, the current 406 includes a second peak at 414 due to charging the capacitance of the memory array to which the pass gate voltage 402 and the word line voltage 404 are applied.

[0051] After the operation is completed, the voltage generation system can be turned off and the charge pump can be discharged. The discharge period is indicated at 410 and can be in the range of 1 μs to 2 μs or more to allow the charge pump of the voltage generation system to reliably reach an idle state. If the preheat period at 408 and / or the discharge period at 410 can be avoided, the time for completing the operation of accessing the memory array can be shortened by up to 6% in some embodiments.

[0052] Figures 5A to 5B is a diagram showing another example of voltage generation by the voltage generation system. Figure 5A Graph 500 includes a transfer gate voltage 502 and a word line voltage (e.g., read voltage) 504 for a first plane of a memory array, and a transfer gate voltage 512 and a word line voltage (e.g., read voltage) 514 for a second plane of the memory array. In response to a first command to access a first plane of the memory array, the voltage generation system for all planes of the memory array is turned on and preheated, as indicated at 508. The preheat delay at 508 may be in the range of 1 μs to 2 μs or more to allow the charge pump of the voltage generation system to reach a desired output voltage sufficient to generate the transfer gate voltage and word line voltage for each plane.

[0053] Once the charge pump of the voltage generation system for the first plane to be accessed in response to the first command has reached the desired output voltage, the transfer gate voltage 502 and the word line voltage 504 can be applied to the memory array to perform an operation (e.g., a read operation). After the operation is completed, if other commands are being processed to access any plane of the memory array, the voltage generation system of the first plane (and other planes) remains turned on instead of being turned off and discharged as indicated at 510. In this way, if another command is received to access the first plane, the transfer gate voltage 502 and the word line voltage 504 can be applied to the memory array without delay during the turn-on period 508.

[0054] In response to a second or subsequent command to access a second plane of the memory array, the transfer gate voltage 512 and the word line voltage 514 can be applied to the memory array without delay in the turn-on cycle at 516 because the voltage generation device for the second plane has already been turned on with the first plane during cycle 508. After the operation is completed, if other commands are being processed to access any plane of the memory array, the voltage generation system of the second plane (and other planes) remains turned on rather than turned off and discharged as indicated at 518. In this way, if another command to access the second plane is received, the transfer gate voltage 512 and the word line voltage 514 can be applied to the memory array without delay in the turn-on cycle 508.

[0055] As described above, the voltage generation system for the first plane to be accessed in response to the first command may be turned on in the first power mode during the on-period 508, and the voltage generation systems for the other planes may be turned on in the second power mode configured to consume less power than the first power mode. In this case, the on-period of the other planes may be longer than the on-period 508 of the first plane. However, by turning on the voltage generation systems of the other planes in the second power mode, the peak current 412 ( Figure 4 ) can be reduced during the on-period.

[0056] Figure 5B550 is a diagram indicating the slow discharge of the voltage generated by the voltage generation system before the voltage generation system is turned on and after the voltage generation system is turned off. The diagram 550 includes the relationship between the transfer gate voltage 552 and the word line voltage (e.g., read voltage) 554 for the plane of the memory array and time. After the voltage generation system is turned off due to no processing of commands for any plane of the memory array, the voltage generation system is slowly discharged as indicated at 558. If another command is received before the voltage generation system reaches the idle state, the voltage generation system is turned on but the on period can be reduced because the charge pump of the voltage generation system may take less time to reach the desired output voltage. Once the charge pump of the voltage generation system for the plane to be accessed has reached the desired output voltage, the transfer gate voltage 552 and the word line voltage 554 can be applied to the memory array to perform an operation (e.g., a read operation). After the operation is completed, if no other commands are processed for any plane of the memory array, all voltage generation systems are turned off and slowly discharged to the idle state, as indicated at 560. In one example, the voltage generating system may be slowly discharged to an idle state over a period of, for example, up to 300 μs.

[0057] Fig. 6A is a schematic diagram showing an example of a charge pump 600. The charge pump 600 may provide Figure 3 Each charge pump 3120 to 312 N . In this example, the charge pump 600 includes pumping stages 610A, 610B, and 610C. In other examples, the charge pump 600 may include additional pumping stages or fewer pumping stages. The pumping stages 610A, 610B, and 610C are connected in series so that the output terminal 616A or 616B of one pumping stage is connected to the input of the next pumping stage. In this example, the output terminal 616C from the last pumping stage 610C in the series connection is the output terminal of the charge pump 600. Each of these pumping stages 610A, 610B, and 610C may include a low voltage device. When disabled, the charge pump 600 may use a finely adjustable current source 620 to discharge at least a portion of the remaining charge on the pumping stage.

[0058] References below Figure 6BThe further described trimmable current source 620 may be connected between the common node 622 and the reference terminal 630. In some examples, the current provided by the trimmable current source 620 is between 100 microamperes and 20 milliamperes. The reference terminal 630 may be grounded or maintained at another reference voltage. The trimmable current source 620 may be configured to drain at least a portion of the remaining charge from the pump stages 610A, 610B, and 610C. Thus, the current source may include a control input 624 configured to receive information to control (e.g., enable / disable, provide a configurable or selectable current, etc.) the trimmable current source 620. The control input 624 may be connected to the input of the charge pump via an inverter so that the trimmable current source 620 may be enabled when the charge pump is disabled and disabled when the charge pump is enabled.

[0059] The common node 622 may be common to multiple pump stages and may be connected to the output terminals 616A, 616B, and 616C of each of the pump stages 610A, 610B, and 610C via passive devices (e.g., diodes) 614A, 614B, and 614C. In various examples, the passive devices 614A, 614B, and 614C may include high voltage devices (e.g., high voltage diodes). The discharge speed may be based on the size of the passive devices 614A, 614B, and 614C, which may vary across examples to vary the discharge speed. The discharge speed may be affected by the amount of current provided by the trimmable current source 620. The amount of current from the trimmable current source 620 may be selected or configured using a diode transfer curve.

[0060] The charge pump 600 may include diodes 612A, 612B, and 612C connected between output terminals 616A, 616B, and 616C and capacitor nodes within pumping stages 610A, 610B, and 610C. In an example, if a pumping stage includes multiple capacitor nodes, a diode for the pumping stage may be connected to each capacitor node. In other examples, the pumping stage may have one or more diodes, at least one of which is connected to each capacitor node. Diodes 612A, 612B, and 612C may help discharge the internal capacitor nodes of pumping stages 610A, 610B, and 610C. When the charge pump 600 operates in boost mode, diodes 612A, 612B, and 612C allow boosted charge to be transferred from pumping stages 610A to 610B and from 610B to 610C, etc. Diodes 612A, 612B, and 612C block the reverse path to provide boost behavior. However, when pumping stages 610A, 610B, and 610C are discharging, if the internal voltage of pumping stages 610A, 610B, and 610C is higher than the voltage on output terminals 616A, 616B, and 616C, respectively, then diodes 612A, 612B, and 612C are turned on.

[0061] When the charge pump is enabled and the trimmable current source 620 is disabled, the passive devices 614A, 614B, and 614C may not play a role in discharging. In addition, the diodes 612A, 612B, and 612C may be selected to minimize current leakage. The number of diodes at each pump stage and the size of the diodes may be selected to ensure that the diodes 612A, 612B, and 612C do not affect the performance of the charge pump. In addition, the diodes 612A, 612B, and 612C do not add significant parasitic capacitance to any internal node of the pump stages 610A, 610B, and 610C. Finally, the additional circuitry used to control the discharge speed (e.g., the trimmable current source 620 and the passive devices 614A, 614B, and 614C, etc.) is relatively small so that the size of the charge pump is not significantly affected.

[0062] Figure 6B Show Fig. 6A 656A to 656N may be multiples of the reference current 652. For example, the current 656A may be equal to the reference current 652, the current 656B may be equal to twice the reference current 652, the current 656C may be equal to four times the reference current 652, the current 656D may be equal to eight times the reference current 652, and so on.

[0063] Figures 7A to 7E is a flow chart illustrating an example of a method 700 for accessing a memory. In one example, the method 700 may be performed by Figure 1 The memory device 100 or Figure 3 The memory device 300 is implemented as shown in FIG. Fig. 7A As shown in, at 702, method 700 includes receiving a first command to access a first plane of a plurality of planes of a memory array. At 704, method 700 includes turning on each of a plurality of voltage generation systems in response to receiving the first command, each voltage generation system in the plurality of voltage generation systems corresponding to a plane of the plurality of planes. At 706, method 700 includes waiting for a first cycle. At 708, method 700 includes executing the first command once the first cycle has elapsed. In one example, turning on each of a plurality of voltage generation systems in response to receiving the first command includes turning on a voltage generation system corresponding to a first plane of the plurality of planes in a first power mode, and turning on voltage generation systems corresponding to other planes of the plurality of planes in a second power mode configured to consume less power than the first power mode.

[0064] like Figure 7B As shown in , at 710, method 700 may further include receiving a second command to access a second plane of the plurality of planes. At 712, method 700 may further include executing the second command without a delay cycle in response to the first cycle expiring. Figure 7C As shown in , at 714, the method 700 may further include receiving a subsequent command to access a corresponding plane in the plurality of planes. At 716, the method 700 may further include executing the subsequent command without a delay period. Fig.7D As shown in , at 718 , method 700 may further include discharging each of the plurality of voltage generation systems to an idle state in response to no commands being processed.

[0065] like Fig. 7E As shown in , at 720, method 700 may further include detecting the discharge level of the plurality of voltage generating systems in response to receiving a second command to access a plane in the plurality of planes. At 722, method 700 may further include turning on each of the plurality of voltage generating systems in response to receiving the second command. At 724, method 700 may further include selecting one of a first cycle and a second cycle, the second cycle being selected in response to the detected discharge level being greater than a level of an idle state, and the first cycle being selected in response to the detected discharge level being at a level of an idle state. At 726, method 700 may further include waiting for the selected one of the first cycle and the second cycle. At 728, method 700 may further include executing the second command once the selected one of the first cycle and the second cycle has elapsed.

[0066] in conclusion

[0067] Although specific embodiments have been shown and described herein, it will be appreciated by those skilled in the art that any arrangement that is expected to achieve the same purpose may be substituted for the specific embodiments shown. Many modifications of the embodiments will be clear to those skilled in the art. Therefore, this application is intended to cover any modifications or variations of the embodiments.

Claims

1. A memory device, comprising: a memory array comprising a plurality of planes; a plurality of voltage generating systems, each voltage generating system of the plurality of voltage generating systems being electrically coupled to a corresponding plane of the plurality of planes; as well as a controller configured to turn on each of the plurality of voltage generating systems in response to a first command to access a first plane of the plurality of planes, wherein the controller is configured to operate the voltage generating system among the multiple voltage generating systems corresponding to the first plane among the multiple planes at a first clock frequency, and to operate the remaining voltage generating systems among the multiple voltage generating systems corresponding to other planes among the multiple planes at a second clock frequency that is less than the first clock frequency.

2. The memory device of claim 1 , further comprising: A detector is configured to detect discharge levels of the plurality of voltage generating systems.

3. The memory device of claim 1 , wherein the controller is configured to change a clock frequency of the voltage generating system among the plurality of voltage generating systems corresponding to the second plane among the plurality of planes to the first clock frequency in response to receiving a second command to access a second plane among the plurality of planes.

4. The memory device of claim 1 , wherein each of the plurality of voltage generating systems comprises: an analog circuit for receiving a power supply voltage and providing an input voltage; A charge pump, configured to receive the input voltage and provide an output voltage higher than the input voltage; as well as A regulator is configured to receive the output voltage and provide a regulated voltage to the corresponding plane of the plurality of planes.

5. A memory device comprising: a memory array comprising a plurality of planes; a plurality of voltage generating systems, each voltage generating system of the plurality of voltage generating systems being electrically coupled to a corresponding plane of the plurality of planes and each voltage generating system comprising a corresponding charge pump; as well as a controller configured to turn on each of the plurality of voltage generating systems in response to a first command to access a first plane of the plurality of planes, wherein the controller is configured to operate the charge pump corresponding to the voltage generating system among the multiple voltage generating systems corresponding to the first plane among the multiple planes at a first clock frequency, and to operate the remaining charge pumps corresponding to the voltage generating systems among the multiple voltage generating systems corresponding to other planes among the multiple planes at a second clock frequency less than the first clock frequency.

6. The memory device of claim 5 , wherein the controller is configured to change a clock frequency of the charge pump corresponding to the voltage generating system among the plurality of voltage generating systems corresponding to the second plane among the plurality of planes to the first clock frequency in response to receiving a second command to access a second plane among the plurality of planes. 7 . The memory device of claim 5 , wherein the controller is configured to shut down and discharge each of the plurality of voltage generation systems to an idle state in response to no command being processed.

8. The memory device of claim 5, further comprising: A detector is configured to detect discharge levels of the plurality of voltage generating systems.

9. The memory device of claim 8, wherein the voltage generation system corresponding to the first plane is ready within a first cycle, wherein the controller is configured to shut down and discharge each of the plurality of voltage generating systems to an idle state in response to no command being processed; wherein, in a case where the plurality of voltage generating systems are turned off, the controller is configured to turn on each of the plurality of voltage generating systems in response to a second command to access a second plane among the plurality of planes, and The voltage generation system corresponding to the second plane among the plurality of planes is ready within a second period, and in response to the detected discharge level of the plurality of voltage generation systems being higher than the level of the idle state, the second period is shorter than the first period.

10. The memory device of claim 5, wherein each voltage generation system of the plurality of voltage generation systems comprises a corresponding analog circuit for receiving a supply voltage and providing an input voltage to the corresponding charge pump.

11. The memory device of claim 5, wherein each voltage generation system of the plurality of voltage generation systems comprises a corresponding voltage regulator for receiving an output voltage from the corresponding charge pump and providing a regulated voltage to the corresponding plane of the plurality of planes.

12. The memory device of claim 5, wherein each charge pump of each voltage generating system of the plurality of voltage generating systems comprises: Multiple pump stages; as well as A trimmable current source is configured to drain at least a portion of the remaining charge from the plurality of pumping stages when the charge pump is disabled.

13. The memory device of claim 12, wherein the trimmable current source comprises a digitally programmable current mirror.

14. A memory device comprising: a memory array comprising a plurality of planes; a plurality of voltage generating systems, each voltage generating system of the plurality of voltage generating systems being electrically coupled to a corresponding plane of the plurality of planes; a detector configured to detect a discharge level of the plurality of voltage generating systems; as well as A controller configured to: receiving a first command to access a first plane of the plurality of planes; turning on each of the plurality of voltage generating systems in response to receiving the first command; Wait for the first cycle; and Once the first cycle elapses, the first command is executed.

15. The memory device of claim 14, wherein the controller is configured to: receiving a second command to access a second plane of the plurality of planes; and The second command is executed without a delay cycle in response to the first cycle elapsing.

16. The memory device of claim 15, wherein the controller is configured to: receiving a subsequent command to access a corresponding plane of the plurality of planes; and The subsequent command is executed without a delay period. 17 . The memory device of claim 14 , wherein the controller is configured to discharge each of the plurality of voltage generation systems to an idle state in response to no commands being processed.

18. The memory device of claim 17, wherein the controller is configured to: detecting discharge levels of the plurality of voltage generating systems in response to receiving a second command to access a plane of the plurality of planes; turning on each of the plurality of voltage generating systems in response to receiving the second command; selecting one of the first period and a second period, the second period being selected in response to the detected discharge level being greater than a level of the idle state, and the first period being selected in response to the detected discharge level being at the level of the idle state; waiting for the selected one of the first cycle and the second cycle; and Once the selected one of the first cycle and the second cycle elapses, the second command is executed.

19. The memory device of claim 14, wherein the controller is configured to: turning on the voltage generation system corresponding to the first plane among the plurality of planes in a first power mode; and The voltage generation systems corresponding to other planes of the plurality of planes are turned on in a second power mode configured to consume less power than the first power mode.

20. The memory device of claim 14, wherein the controller is configured to: turning on the voltage generating system corresponding to the first plane among the plurality of planes at a first clock frequency; and The voltage generation systems corresponding to other planes of the plurality of planes are turned on at a second clock frequency that is lower than the first clock frequency.

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