Power control and its methods for radar applications

Abstract

A radar system includes a hybrid power amplifier and a power control unit coupled to the hybrid power amplifier. The power control unit is configured to control the amplification of a chirped signal output by the radar system based on an evaluation of the chirp interval time provided by a chirp characteristic curve. The chirp interval time is the time difference between a first chirped signal and a second chirped signal to be output by the hybrid power amplifier. When the power control unit determines that the chirp interval time is less than a chirp interval time threshold, a fast power loop control configuration is used to control the output power transmitted at the hybrid amplifier stage. When the power control unit determines that the chirp interval time is equal to or greater than the chirp interval time threshold, a slow power loop configuration or a combination of a slow loop configuration and a fast loop configuration is used to control the output power transmitted at the hybrid power amplifier. A lookup table generated by the power control unit in the controller is used to determine the control signals and values ​​to be amplified by the hybrid power amplifier and voltage regulator for the chirped signal.

Description

Technical Field

[0001] This invention relates to a power control method for radar applications. Background Technology

[0002] Frequency modulated continuous wave (FMCW) radar systems for automotive applications utilize various power levels to transmit and receive frequency-modulated signals known as chirps. Several types of frequency modulation are known in the field of high-end FMCW radar systems. For example, in slow frequency modulation, the frequency of the transmitted continuous wave is modulated according to a triangular wave. In fast frequency modulation, the frequency of the transmitted continuous wave is modulated according to a sawtooth wave. The power used to transmit chirps in high-end FMCW radar systems (e.g., long-range radar (LRR) applications, low-end radar systems, short-range radar (SRR), and ultra-short-range radar (USRR) applications) varies based on different constraints regarding the output power and maximum power allocated to each application. Due to the limited space available for energy sources in automobiles, the amount of power that can be consumed for FMCW radar systems in automotive applications is extremely limited. Therefore, there is a need to improve the handling of power consumption for various radar applications. Summary of the Invention

[0003] The appended claims define all aspects of this disclosure.

[0004] In a first aspect, a radar system is provided, comprising a hybrid power amplifier and a power control unit. The power control unit is coupled to the hybrid power amplifier. The power control unit is configured to select a power control configuration based on an evaluation of chirp interval time, the power control configuration being applied to the hybrid power amplifier to amplify chirped signals transmitted by the radar system.

[0005] In one or more embodiments, the radar system may further include a chirp generator coupled to the power control unit, wherein the chirp generator generates a chirp signal amplified by the hybrid power amplifier and output by the radar system.

[0006] In one or more embodiments, the chirp interval time can be the time difference between the end of the first chirp signal output by the hybrid power amplifier and the start of the second chirp signal.

[0007] In one or more embodiments, when the chirp interval time is less than a chirp interval time threshold, the power control configuration may be a fast power control loop configuration for adjusting the amount of power used to amplify the chirp signal.

[0008] In one or more embodiments, when the chirp interval time is equal to or greater than the chirp interval time threshold, the power control configuration may be a slow power control loop configuration for adjusting the amount of power used to amplify the chirp signal, or a combination of the slow power control loop configuration and the fast power control loop configuration.

[0009] In one or more embodiments, the fast power control loop configuration may utilize a first cascode arrangement coupled to a second cascode arrangement to amplify the chirped signal transmitted by the radar system.

[0010] In one or more embodiments, the slow power control loop configuration may utilize a voltage regulator and control signals from the power control unit to provide a power supply voltage value, which is used as the power supply voltage for the hybrid power amplifier amplifying the chirped signal.

[0011] In one or more embodiments, the first cascode arrangement and the second cascode arrangement may be located in the first stage of the hybrid power amplifier, and the power control unit may use the first stage of the hybrid power amplifier to adjust the amount of power to be transmitted by the radar system after the chirped signal is amplified by the hybrid power amplifier.

[0012] In one or more embodiments, the radar system may further include a lookup table used by a power control unit to determine an output control signal and an output value, the output control signal and the output value being used by a hybrid power amplifier to amplify the chirped signal output by the radar system.

[0013] In a second aspect, a method is provided comprising: providing a chirp interval time to a power control unit of a radar system; and adjusting the output power of a chirped signal transmitted by the radar system based on an evaluation of the chirp interval time and a lookup table.

[0014] In one or more embodiments, the evaluation of the chirp interval time may include determining whether the chirp interval time between the first chirp signal and the second chirp signal is greater than, equal to or less than a chirp interval threshold.

[0015] In one or more embodiments, when the chirp interval is less than a chirp interval threshold, a fast power control loop configuration can be used to reduce the amount of power consumed by amplifying the chirp signal.

[0016] In one or more embodiments, when the chirp interval time is equal to or greater than a chirp interval time threshold, a slow power control loop configuration or a combination of the slow power control loop configuration and the fast power control loop configuration can be used to reduce the amount of power consumed by amplifying the chirp signal.

[0017] In one or more embodiments, the fast power control loop configuration may utilize a first cascode arrangement coupled to a second cascode arrangement to amplify the chirped signal output by the radar system.

[0018] In one or more embodiments, the lookup table can provide the output value to the first stage of a voltage regulator and a hybrid power amplifier for amplifying the chirped signal.

[0019] In one or more embodiments, the lookup table can provide an output value including a power supply voltage value, at least one first gate voltage value, and at least one second gate voltage value.

[0020] In a third aspect, a transceiver is provided, comprising a hybrid power amplifier and a power control unit. The power control unit is coupled to the hybrid power amplifier. The power control unit is configured to evaluate chirp interval time and lookup table, and based on the evaluation, the hybrid power amplifier uses a first stage of the hybrid power amplifier to adjust the amount of power used to amplify the chirped signal transmitted by the transceiver.

[0021] In one or more embodiments, during the amplification of a chirped signal transmitted by the transceiver, a first transistor arranged in a first cascode configuration may be turned off to reduce the amount of power used to amplify the chirped signal.

[0022] In one or more embodiments, before amplifying the chirped signal transmitted by the transceiver, a lookup table may be generated by a power control unit in the controller to determine a control signal, which is provided to the first stage of the hybrid power amplifier to amplify the chirped signal.

[0023] In one or more embodiments, a voltage regulator for the output power supply voltage may be used in combination with a first cascode arrangement and a second cascode arrangement to amplify the chirped signal, the value of which is provided from a lookup table. Attached Figure Description

[0024] The present disclosure will be better understood by referring to the accompanying drawings, which will make the numerous features and advantages of the disclosure clear to those skilled in the art. The same reference numerals are used in different drawings to indicate similar or identical items.

[0025] Figure 1 This is a block diagram of a radar system according to some embodiments.

[0026] Figure 2 According to some embodiments Figure 1 A block diagram of the power amplifier power control configuration in a radar system.

[0027] Figure 3 This is a flowchart of a power amplification control method for a radar system according to some embodiments.

[0028] Figure 4 According to some embodiments, it is used for Figure 1 An example of a lookup table in a power amplification control method for a radar system. Detailed Implementation

[0029] Figures 1-4 A system and method are illustrated for adjusting the amount of power transmitted and consumed by a hybrid power amplifier in a radar system. In some embodiments, a selected power control configuration is used to adjust the amount of power supplied at the output of the radar system for transmitting a chirped signal. In some embodiments, depending on the amount of time between transmitted chirped signals (i.e., chirp interval time) and the output power transition between chirped signals, a power control unit provides a control signal to the hybrid power amplifier, which implements a selected power control configuration, such as a slow power control configuration, a fast power control configuration, or a combination thereof. The slow power control loop configuration is a power control configuration that uses a voltage source control signal provided to a voltage regulator to control the amplification of the chirped signal supplied to the hybrid power amplifier. The fast power control configuration is a power control configuration that uses a digital control signal of the gate voltage of a cascode transistor provided to the hybrid power amplifier to control the amplification level (output power) of the chirped signal further transmitted by the radar system.

[0030] In some embodiments, to select a slow power control configuration, a fast power control configuration, or a combination thereof, the power control unit first generates a lookup table (LUT), which it further uses to set the voltage value to be provided as a control signal to the hybrid power amplifier. The LUT includes the voltage value to be provided to a first stage (and optionally an additional stage, such as a second stage) of the hybrid power amplifier for amplifying the chirped signal. In some embodiments, after the LUT has been generated, the power control unit evaluates the chirped signal via, for example, its characteristic curve information to determine the amount of time available between chirped signals. That is, in some embodiments, the power control unit compares the chirped interval time to a chirped interval time threshold to determine whether to use a fast power control loop configuration or a combination of a slow power control loop configuration and a fast power control loop configuration as the power control method, which saves power during the amplification of the chirped signal. In some embodiments, when the chirped interval time is less than the chirped interval time threshold (due to the limited amount of time available for power reduction), only the fast power control loop configuration is selected to change the transmitted power during the amplification of the chirped signal. In some embodiments, when the chirp interval time is greater than or equal to a chirp interval time threshold (due to an increase in the amount of time available for power reduction), both a slow power control configuration and a fast power control configuration are selected to change the transmitted power during chirp signal amplification.

[0031] In some embodiments, the fast power control configuration utilizes the gate voltage of a cascode transistor to control the amplification level of the chirped signal, compared to a slow power mode configuration that uses a voltage regulator and associated voltage regulation loop to control amplification by utilizing the hybrid power amplifier's power supply value. Therefore, the power control unit can switch transistors in the hybrid power amplifier on and off more quickly to adjust power amplification. By combining both the slow and fast power control configurations, the hybrid power amplifier can provide sufficient power amplification while turning off unnecessary transistors during idle periods, such as when the radar system is not used for continuous transmission. This combined hybrid power control technique allows for dynamic scaling of the transmitted output power through fast and slow time responses, allowing the same radar system to operate in different applications while achieving an optimal trade-off between transmitted power and power consumption.

[0032] Figure 1 A radar system 100 according to some embodiments is shown. In some embodiments, the radar system 100 includes a controller 130, a voltage regulator 113, a chirp generator 120, transmitters 150-1 to 150-N, a receiver (not shown), and power detectors 180-1 to 180-N. The controller 130 includes a power control unit 125, a timing engine 126, and a memory 127. Transmitters 150-1 to 150-N include hybrid power amplifiers 160-1 to 160-N. Hybrid power amplifier 160-1 includes a driver 172-1, a first stage 170-1, and a second stage 171-1. In some embodiments, the hybrid power amplifier is considered "hybrid" because the amplification level of the hybrid power amplifier can be controlled via its power supply control (analog control) and / or via 'on / off' control of the gate voltage of a cascode device (digital control). In some embodiments, the plurality of power amplifiers N include a driver 172-N, a first stage 170-N, and a second stage 171-N. In some embodiments, the number of hybrid power amplifiers is equal to the number of power detectors in the radar system 100.

[0033] In some embodiments, in order to initiate the process of generating a chirp to be transmitted by the radar system 100 as an RF output signal 143, a chirp characteristic curve 177 is provided from the memory 127 to the timing engine 126 via the output signal 140. The chirp characteristic curve is a characteristic curve that includes a set of chirp parameters of the chirp to be transmitted by the radar system 100. For example, the chirp characteristic curve 177 includes parameters specifying the amount of time between chirps (chirp-to-chirp time or Tdwell time), the power level of each chirp to be transmitted, an enable parameter indicating which transmitters 150-1 to 150-N will be enabled to transmit the chirp, a start frequency parameter specifying the initial frequency of the chirp, a ramp slope parameter specifying the slope of the frequency ramp of the chirp, etc. Using a chirp characteristic curve, the chirp transmitted as an RF output signal 143 is configured to be transmitted by the radar system 100 based on the radar application type to be implemented by the radar system 100, such as long-range radar (LRR), short-range radar (SRR), and ultra-short-range radar (USRR), as described in the chirp characteristic curve.

[0034] A timing engine 126, configured to control the timing of the radar system 100, includes the function of reading chirp parameters. The timing engine 126 receives a chirp characteristic curve 177 from a memory 127 and uses the chirp characteristic curve 177 to control the start and stop times of the chirp signal 131 output by the chirp generator 120 to the hybrid power amplifier 160-1. In some embodiments, the timing engine 126 provides the chirp generator 120 with a chirp control signal 132, for example, indicating the start of each chirp and controlling the frequency ramp of each chirp output by the chirp generator 120. In some embodiments, the timing engine 126 is also configured to provide a timing engine control signal 139 to the power control unit 125 to provide chirp parameters indicating the amount of time between chirs (i.e., inter-chirp time or Tdwell time) and the power level to be transmitted for each chirp. In some embodiments, the power control unit 125 uses the amount of chirp interval time and a lookup table (LUT) 117 (described in further detail below) that includes the power level of each chirp to determine which power control configuration or mode among a plurality of power control configurations (e.g., slow power control loop mode and / or fast power control loop mode, discussed in further detail below) is selected for power amplification and to reduce the amount of power consumed by the radar system 100. Reducing the transmit power, for example, during the chirp interval time, allows the radar system 100 to reduce power consumption, which is critical for an efficient automotive radar system due to the limited battery space or power available in the vehicle.

[0035] Chirp generator 120 receives chirp control signal 132 and generates chirp signal 131 based on control parameters (e.g., start, stop, duration) provided by timing engine 126. That is, chirp generator 120 is configured to generate frequency-modulated continuous wave (FMCW) chirp signal 131 at a frequency that may be, for example, 77 GHz or some other frequency typically used by radar systems in automotive applications. Based on the chirp control signal 132 provided from timing engine 126, chirp generator 120 generates, for example, an FMCW chirp signal 131 for transmission by radar system 100. Chirp generator 120 provides chirp signal 131 to hybrid power amplifier 160-1 for amplification according to a power control configuration indicated by power control unit 125. In some embodiments, chirp signal 131 is provided as chirp signal 188 to the first stage 170-1 of hybrid power amplifier 160-1 for amplification via driver 172-1. In some embodiments, the chirp signal 131 is provided directly to the first stage 170-1 of the hybrid power amplifier 160-1 for amplification (this means that in some embodiments, no driver stage, such as driver 172-1, is required or not used for power amplification).

[0036] The power control unit 125 receives the timing engine control signal 139 and generates a LUT 117 including an output voltage value (the power supply voltage represented by the voltage regulator input control signal 133 and the cascode voltage represented by the digital signal 134). This output voltage value is provided to the voltage regulator 113 and the first stage 170-1 of the hybrid power amplifier 160-1 (and optionally an additional stage, such as a second stage 171-1) for amplifying the chirped signal 131. Figure 4 For example, the LUT 117 generated by the power control unit 125 includes a power supply voltage value VDDA, a digital logic voltage value VC1, and a digital logic voltage value VC2, as well as an output power value to be transmitted by the radar system 100 at 143. In some embodiments, the power control unit 125 is configured to control the hybrid power amplifier 160-1 to operate in a fast power control mode (fast power control loop configuration), a slow power control mode (slow power control loop configuration), or a fast-slow power control combination mode (fast-slow power control loop configuration).

[0037] The slow power control loop mode utilizes voltage regulator 113 and matching circuit ( Figure 2(As described in further detail below) The configuration of controlling the power of the RF output signal 143 output by the hybrid power amplifier 160-1 is combined with LUT 117. The slow power control loop configuration operates in conjunction with the fast power control loop configuration by controlling the amount of the supply voltage 137 (i.e., VDDA) provided to the first stage 170-1 (and optionally the second stage 171-1 in an alternative multi-stage embodiment) of the hybrid power amplifier 160-1 using the voltage regulator input control signal 133 from the power control unit 125. That is, in the slow power control mode, the power of the RF output signal 143 output by the hybrid power amplifier 160-1 is controlled by adjusting the supply voltage 137 using the voltage regulator 113 controlled by the voltage regulator input control signal 133.

[0038] In some embodiments, a slow power control loop mode is used where the power control unit 125 determines that the time between chirped signals (chirped interval time or Tdwell time) is at or above a chirped interval time threshold. Specifically, the power control unit 125 receives a timing engine control signal 139 (which includes information indicating the amount of time between chirped signals) and determines whether the chirped interval time is at or above the chirped interval time threshold. When the power control unit 125 determines that the chirped interval time is at or above the chirped interval time threshold (e.g., 21 microseconds for some LRR applications), the power control unit 125 utilizes a slow power control loop mode that outputs a voltage regulator input control signal 133 based on, for example, a pre-programmed supply voltage specified in the LUT 117, corresponding to the supply voltage to be generated by the voltage regulator 113 for amplifying the chirped signal 131. Therefore, in some embodiments, a slow power control loop configuration is used, whereby the power control unit 125 uses the voltage regulator input control signal 133 to control the power supply voltage 137 supplied at the output of the voltage regulator 113. That is, when the power control unit 125 selects the slow power loop configuration, the power control unit 125 is configured to use the LUT 117 to select the amount of power supply voltage to be supplied to the hybrid power amplifier 160-1.

[0039] As previously described, in addition to using a slow power control loop mode to control the power delivered and consumed by the hybrid power amplifier 160-1, the power control unit 125 is also capable of using a fast power control loop mode to control the power delivered and thus consumed by the hybrid power amplifier 160-1. The fast power control loop mode controls the configuration of the power of the RF output signal 143 output by the hybrid power amplifier 160-1 by controlling the gate voltage of the cascode transistor in the first stage 170-1 or optionally the second stage 171-1 of the hybrid power amplifier 160-1. (Cascode transistor - reference) Figure 2(Further detailed description) includes an NMOS transistor that uses digital signal 134 to turn on or off based on the duration of the time between chirps (inter-chirp time) provided by timing engine control signal 139 of timing engine 126. That is, as previously described, a fast power control loop mode is used in instances where power control unit 125 determines the time between chirps (Tdwell time) to be very little or below a certain minimum threshold. For example, in some embodiments, when power control unit 125 determines the inter-chirp time to be less than tmax (e.g., 4 microseconds for some LRR applications), a fast power control loop configuration is used to adjust the amount of power to be transmitted by hybrid power amplifier 160-1. Therefore, in instances where slow power control loop mode is too slow to reduce the transmitted power within a given time range or inter-chirp time, fast power control loop mode can adjust or reduce the transmitted power.

[0040] For example, in the interleaved multimode use case, when the chirp interval time is very short (below the chirp interval threshold), the radar system 100 uses a fast power control loop configuration. In some embodiments, interleaved multimode is a mode in which the chirp sequence has a typical or normal Tdwell time (e.g., 4 microseconds) and an associated chirp time (e.g., 10 microseconds) and where at least two characteristic curves alternate between each chirp. The chirp transmission time is very short compared to the chirp transmission time during the slow mode configuration. Importantly, it should be noted that in some embodiments, for chirp interval times equal to or higher than the chirp interval time threshold, the fast power control loop mode is combined with the slow power control loop mode to reduce the power consumption (or resource consumption) of the radar system 100. Turning off the transistors during chirp transmission when they are not in use or are in silent mode saves power in the radar system 100. By using both slow power control loop configuration and fast power control loop configuration, radar system 100 can reduce the amount of power consumed by hybrid power amplifier 160-1 during the chirp interval while still providing the required transmit output power for the RF output signal 143 of radar system 100.

[0041] In some embodiments, a power detector output signal 135 may also be used in the process of controlling, monitoring, or maintaining an appropriate amount of power consumed and output by the hybrid power amplifier 160-1. The power detector output signal 135 is provided from the power detector 180-1 to the power control unit 125. The power detector 180-1 is configured to detect the amount of power output and transmitted by the hybrid power amplifier 160-1. In some embodiments, the power detector 180-1 is implemented using power sensor circuitry and systems known in the art. The power detector 180-1 receives the output of the hybrid power amplifier 160-1 and detects or measures the power of the RF output signal 143. The power detector 180-1 provides the detected power level via the power detector output signal 135 to the power control unit 125, which uses the detected power level to control or maintain the amount of power consumed and output by the hybrid power amplifier 160-1.

[0042] Figure 2 Illustrations based on some embodiments Figure 1 The radar system 100 includes a hybrid power amplifier power control configuration 200. In some embodiments, the hybrid power amplifier power control configuration 200 is implemented in a first stage 170-1 of the hybrid power amplifier 160-1. In some embodiments, the hybrid power amplifier power control configuration 200 is implemented in a first stage 170-1 and a second stage 171-1 of the hybrid power amplifier 160-1. In alternative embodiments, the hybrid power amplifier power control configuration 200 may be implemented in an additional stage of the hybrid power amplifier 160-1 or in additional stages of the transmitters 150-1 to 150-N. The hybrid power amplifier power control configuration 200 includes a slow power control loop configuration 281 and a fast power control loop configuration 282. The slow power control loop configuration 281 includes a matching circuit 210 coupled to a voltage regulator 113 (not shown) and the drains of a first transistor 220 (NMOS transistor 220 or NMOS cascode transistor 220) and a second transistor 221 (NMOS transistor 221 or NMOS cascode transistor 221). In some embodiments, matching circuit 210 is used to tune hybrid power amplifier 160-1 to the desired center frequency (e.g., 77 GHz) of radar system 100.

[0043] The fast power control loop configuration 282 includes a first cascode arrangement (or group) 291 and a second cascode arrangement (or group) 292. The first cascode arrangement 291 includes a first cascode transistor 220 (NMOS cascode transistor 220) and a first input transistor (NMOS transistor 222). The second cascode arrangement 292 includes a second cascode transistor 221 (NMOS cascode transistor 221) and a second input transistor (NMOS transistor 223). The gate of the NMOS cascode transistor 220 is coupled to the power control unit 125, the source of the NMOS cascode transistor 220 is coupled to the drain of the NMOS input transistor 222, and the drain of the NMOS cascode transistor 220 is coupled to the matching circuit 210 and, at the output node providing the RF output signal 143, to the drain of the NMOS cascode transistor 221. The gate of NMOS cascode transistor 221 is coupled to power control unit 125. The source of NMOS cascode transistor 221 is coupled to the drain of NMOS input transistor 223. The drain of NMOS cascode transistor 221 is coupled to matching circuit 210 and to the drain of NMOS cascode transistor 220 at the output node providing RF output signal 143. The gate of NMOS input transistor 222 is coupled to chirp generator 120 or to driver 172-1. The source of NMOS input transistor 222 is coupled to ground, and the drain of NMOS input transistor 222 is coupled to the source of NMOS cascode transistor 220. The gate of NMOS input transistor 223 is coupled to chirp generator 120 via driver 172-1 (not shown). The source of NMOS input transistor 223 is coupled to ground, and the drain of NMOS input transistor 223 is coupled to the source of NMOS cascode transistor 221.

[0044] In the operation of the hybrid power amplifier power control configuration 200, NMOS transistor 220 receives VC digital signal 134-1 from power control unit 125, NMOS transistor 222 receives chirp signal 131 from chirp generator 120 (or input chirp signal 188 from driver 172-1), and matching circuit 210 receives power supply voltage 137 from voltage regulator 113. As previously described, the amount of power supply voltage 137 supplied to first stage 170-1 and whether the VC digital signals 134-1 and VC digital signals 134-2 received by first stage 170-1 are logic high or logic low are determined by power control unit 125 for a selected power configuration (e.g., slow power control loop configuration, fast power control loop configuration, or a combination thereof) by selecting the output power values ​​(i.e., VDDA, VC1, and VC2 of LUT 117) stored in LUT 117.

[0045] In some embodiments, for a given power configuration selection made by the power control unit 125 based on the chirp interval time (indicated by the time engine control signal 139) and the power conversion from the first chirp output power to the second chirp output power, the power control unit 125 provides the associated power supply voltage value 137, the cascode control voltage VC1 (i.e., VC digital signal 134-1) and VC2 (i.e., VC digital signal 134-2) to the matching circuit 210, the NMOS transistor 220 and the NMOS transistor 221, respectively.

[0046] In some embodiments, for example, when the power control unit 125 determines that the power conversion from the first chirp to the second chirp is from POUT1 to POUT2 (see below) Figure 4 (Detailed description) The power control unit 125 only adjusts the output VC2 (for the VC digital signal 134-1) from high to low, and does not adjust VDDA. In this case, since VDDA remains the same (i.e., from VDDA_MAX to VDDA_MAX) and only VC2 changes (i.e., from high to low), the power control configuration is considered to be a fast power control loop configuration used in the case where the power control unit 125 determines that the chirp interval time (set by, for example, the chirp characteristic curve) between the first chirp and the second chirp is less than the chirp interval time threshold.

[0047] In some embodiments, for example, when the power control unit 125 determines that the power transition from the first chirp to the second chirp is from POUT1 to POUT3, the power control unit 125 does not adjust the output VC2 (for VC digital signal 134-1) from high to low, but instead adjusts VDDA. In this case, since VDDA changes (i.e., from VDDA_MAX to VDDA_MID) and VC2 does not change (i.e., remains at logic high, and NMOS transistor 221 remains on), and since neither NMOS transistor 220 nor NMOS transistor 221 is turned off, the use of a fast power control loop configuration does not reduce the transmitted power.

[0048] In some embodiments, the power control unit 125 reduces the amount of power consumed during the amplification of the chirp signal 131 provided as an RF input by turning off the NMOS transistor 221 when the chirp inter-time is very short (below a chirp inter-time threshold) in a pre-selected or pre-configured chirp characteristic curve 177 and by turning off the NMOS transistor 221 when the chirp inter-time is above a threshold. That is, digital signals (VC1 and VC2) with logic high or logic low values ​​are used to turn the cascode devices in the first stage 170-1 or 171-2 on or off to increase or decrease the power supplied (transmitted) by the hybrid power amplifier 160-1. When the cascode stage is turned off, current no longer circulates in the cascode stage, and there is no amplification provided by the turned-off cascode stage (either the first cascode arrangement 291 or the second cascode arrangement 292), i.e., the transmitted power is reduced.

[0049] Figure 3 The illustration shows a method for using, according to some embodiments, in Figure 1 Method 300 for reducing power consumption in the hybrid power amplifier 160-1 during the amplification of the chirped signal in the radar system 100. Figure 1 , 2 Blocks 310 and 315 are used to describe method 300. At blocks 310 and 315, radar system 100 is turned on and power detector 180-1 is calibrated. At block 320, power control unit 125 generates or constructs a LUT 117 for hybrid power amplifier 160-1. As previously described, LUT 117 includes output values ​​(VDDA, VC1, and VC2) provided by power control unit 125 to hybrid power amplifier 160-1 to control the first stage 170-1 (and optionally, the second stage 170-2) of hybrid power amplifier 160-1 to generate corresponding output power during power amplification. The output values ​​(VDDA, VC1, and VC2) are mapped to the output power of radar system 100 for power conversion between chirps provided by chirp characteristic curve 177 from memory 127.

[0050] In some embodiments, at block 325, the chirp interval time is received from timing engine 126. At block 330, power control unit 125 compares the chirp interval time with a chirp interval time threshold to determine whether to use a fast power control loop configuration or a combination of a slow power control loop configuration and a fast power control loop configuration to conserve power consumed during the amplification of chirp signal 131. In some embodiments, at block 340, when the chirp interval time is less than the chirp interval time threshold, only the fast power control loop configuration is selected to reduce the transmitted power during the amplification of chirp signal 131 (attributed to, for example, the limited amount of time available for power reduction between chirps). In some embodiments, the chirp interval time is indicated by the use case or application, while the chirp interval time threshold is determined or fixed by implementation limitations of the power control loop (e.g., using a slow power control loop configuration via supply voltage, or, for example, using a fast power control loop configuration via cascode voltage digital selection). In some embodiments, at block 335, when the chirp interval is greater than or equal to a chirp interval threshold, a slow power control configuration and a fast power control configuration are selected to reduce the power during the amplification of the chirp signal 131. At block 345, the power control unit 125 maps the selected configuration to the output power conversion stored in the LUT 117. At block 350, the power control configuration selected at block 340 or 335 is applied using the LUT 117. That is, the output voltage values ​​of VDDA, VC1, and VC2 are provided to, for example, the first stage 170-1 of the hybrid power amplifier 160-1. At block 355, the chirp generator 120 initiates a chirp sequence, and the hybrid power amplifier 160-1 applies the specified output voltage values ​​(e.g., VDDA, VC1, VC2) from block 350.

[0051] Figure 4 A power supply unit (LUT) 117, according to some embodiments, is shown for adjusting the amount of power transmitted by a hybrid power amplifier 160-1 of a radar system 100. The LUT 117 includes: a configuration number column 410 indicating a configuration number associated with a first output power POUT1 of an output power column 450; a voltage source column 420 indicating a supply voltage associated with the first output power POUT1; a digital voltage column 430 indicating a VC digital signal 134-1 (logic high or logic low) associated with the first output power POUT1 of the output power column 450; a digital voltage column 440 indicating a VC digital signal 134-2 associated with the first output power POUT1 of the output power column 450; and an output power column 450 including first output powers POUT1 to sixth output powers POUT6 mapped to corresponding supply voltages 137, VC digital signals 134-1, and VC digital signals 134-2. In some embodiments, Figure 4The LUT 117 depicted includes six output power options; however, the number of output power options can vary depending on, for example, the output power range, power step size, and power step size accuracy of the radar system 100.

[0052] For the corresponding power control configuration (slow power control configuration and / or fast power control configuration), the power control unit 125 uses LUT 117 to determine the output values ​​of the power control unit 125 supplied to the hybrid power amplifier 160-1 and the voltage regulator 113. Specifically, the power control unit 125 uses LUT 117 to determine the values ​​of the power supply voltage 137, VC digital signal 134-1, and VC digital signal 134-2 to be output by the power control unit 125 and supplied to each stage (e.g., first stage 170-1, second stage 171-1) of the hybrid power amplifier 160-1. In some embodiments, by evaluating the power output transformation (i.e., from the first output power in the output power column 450 to the second output power in the output power column 450), the power control unit 125 can determine the control signals (e.g., VDDA, VC1, VC2) to be supplied to the hybrid power amplifier 160-1.

[0053] In some embodiments, for example, when the power control unit 125 determines that the power conversion from the first chirp to the second chirp is from POUT1 to POUT2, the power control unit 125 outputs VDDA_MAX for the supply voltage 137, outputs a logic level high for the VC digital signal 134-1, and outputs a logic level low for the VC digital signal 134-2. The VC digital signal 134-2 is used to provide power to the NMOS cascode transistor 221. Figure 2 A low logic level (as depicted in the diagram) turns off the transistor during power conversion, and thus triggers a chirp signal 131 (i.e., Figure 2 Power is saved during the amplification period of RF_IN.

[0054] In some embodiments, when the power control unit 125 determines that the power conversion from the first chirp to the second chirp is from POUT1 to POUT3, the power control unit 125 outputs VDDA_MID for the supply voltage 137, outputs a logic level high for the VC digital signal 134-1, and outputs a logic level high for the VC digital signal 134-2. The VC digital signal 134-2 is then used to supply power to the NMOS cascode transistor 221. Figure 2 The logic level high (as depicted in the text) keeps the NMOS cascode transistor 221 on during power conversion and amplification of the chirp signal 131.

[0055] In some embodiments, when the power control unit 125 determines that the power conversion from the first chirp to the second chirp is from POUT1 to POUT4, the power control unit 125 outputs VDDA_MID for the supply voltage 137, outputs a logic level low for the VC digital signal 134-1, and outputs a logic level high for the VC digital signal 134-2. The VC digital signal 134-2 is used to supply power to the NMOS cascode transistor 221. Figure 2 The low logic level (described in the figure) turns off the NMOS cascode transistor 221 during power conversion and amplification of the chirp signal 131, thereby saving power during the amplification of the chirp signal 131.

[0056] In some embodiments, when the power control unit 125 determines that the power conversion from the first chirp to the second chirp is POUT1 to POUT6, the power control unit 125 outputs VDDA_MIN for the supply voltage 137, outputs a low logic level for the VC digital signal 134-1, and outputs a high logic level for the VC digital signal 134-2. The low logic level provided to the NMOS cascode transistor 221 using the VC digital signal 134-2 turns off the NMOS transistor 221 during the power conversion and amplification of the chirp signal 131, thereby saving power during the amplification of the chirp signal 131. In some embodiments, the logic value used to control the gate of the cascode transistor (e.g., VC1, VC2...VCN) may not necessarily be a low logic value of zero, but rather a logic value capable of turning off the cascode stage utilizing the NMOS cascode transistors 220 and 221, in such a way that the logic value of the cascode stage utilizing the first cascode arrangement 291 or the second cascode arrangement 292 (…) Figure 2 No current flows in the (as depicted). Similarly, in some embodiments, the output values ​​from the power control unit 125 for use in other power conversions (POUT2 to POUT5, POUT3 to POUT6, etc.) are determined by the power control unit 125 using LUT 117.

[0057] In some embodiments, a radar system includes a hybrid power amplifier and a power control unit coupled to the hybrid power amplifier. The power control unit is configured to select a power control configuration based on an evaluation of the chirp interval time. The power control configuration is applied to the hybrid power amplifier to amplify the chirped signal transmitted by the radar system.

[0058] In some embodiments, the radar system includes a chirp generator coupled to the power control unit. The chirp generator generates a chirp signal that is amplified by a hybrid power amplifier and output by the radar system.

[0059] In some embodiments of the radar system, the chirp interval time is the time difference between the end of the first chirp signal output by the hybrid power amplifier and the start of the second chirp signal.

[0060] In some embodiments of the radar system, when the chirp interval time is less than a chirp interval time threshold, the power control configuration is a fast power control loop configuration for adjusting the amount of power used to amplify the chirp signal.

[0061] In some embodiments of the radar system, when the chirp interval time is equal to or greater than the chirp interval time threshold, the power control configuration is a slow power control loop configuration or a combination of the slow power control loop configuration and the fast power control loop configuration for adjusting the amount of power used to amplify the chirp signal.

[0062] In some embodiments of the radar system, the fast power control loop is configured to amplify the chirped signal transmitted by the radar system using a first cascode arrangement coupled to a second cascode arrangement.

[0063] In some embodiments of the radar system, the slow power control loop is configured to provide a power supply voltage value using a voltage regulator and control signals from the power control unit, the power supply voltage value being used as the power supply voltage for the hybrid power amplifier that amplifies the chirped signal.

[0064] In some embodiments of the radar system, a first cascode arrangement and a second cascode arrangement are located in the first stage of the hybrid power amplifier, and the power control unit uses the first stage of the hybrid power amplifier to adjust the amount of power to be transmitted by the radar system after the chirped signal is amplified by the hybrid power amplifier.

[0065] In some embodiments, the radar system includes a lookup table used by a power control unit to determine an output control signal and an output value, which are then amplified by a hybrid power amplifier to amplify the chirped signal output by the radar system.

[0066] In some embodiments, a method includes: providing a chirp interval time to a power control unit of a radar system; and adjusting the output power of a chirped signal transmitted by the radar system based on an evaluation of the chirp interval time and a lookup table.

[0067] In some embodiments of the method, the evaluation of the chirp interval time includes determining whether the chirp interval time between the first chirp signal and the second chirp signal is greater than, equal to, or less than a chirp interval threshold.

[0068] In some embodiments of the method, when the chirp interval is less than a chirp interval threshold, a fast power control loop configuration is used to reduce the amount of power consumed by amplifying the chirp signal.

[0069] In some embodiments of the method, when the chirp interval is equal to or greater than a chirp interval threshold, a slow power control loop configuration or a combination of the slow power control loop configuration and the fast power control loop configuration is used to reduce the amount of power consumed by amplifying the chirp signal.

[0070] In some embodiments of the method, the fast power control loop configuration utilizes a first cascode arrangement coupled to a second cascode arrangement to amplify the chirped signal output by the radar system.

[0071] In some embodiments of the method, a lookup table provides output values ​​to the first stage of the voltage regulator and the hybrid power amplifier for amplifying the chirped signal.

[0072] In one or more embodiments of the method, the lookup table provides an output value including a power supply voltage value, at least one first gate voltage value, and at least one second gate voltage value.

[0073] In some embodiments, a transceiver includes a hybrid power amplifier and a power control unit coupled to the hybrid power amplifier. The power control unit is configured to evaluate chirp interval time and lookup table, and based on the evaluation, the hybrid power amplifier uses a first stage of the hybrid power amplifier to adjust the amount of power used to amplify the chirped signal transmitted by the transceiver.

[0074] In some embodiments of the transceiver, during the amplification of the chirped signal transmitted by the transceiver, a first transistor arranged in a first cascode configuration can be turned off to reduce the amount of power used to amplify the chirped signal.

[0075] In some embodiments of the transceiver, a lookup table is generated by a power control unit in the controller to determine a control signal before the chirped signal transmitted by the transceiver is amplified. This control signal is provided to the first stage of the hybrid power amplifier to amplify the chirped signal.

[0076] In some embodiments of the transceiver, a voltage regulator for the output power supply voltage is used in combination with a first cascode arrangement and a second cascode arrangement to amplify the chirped signal, the value of which is provided from a lookup table. In one or more embodiments, a radar system is provided. The radar system includes a hybrid power amplifier and a power control unit coupled to the hybrid power amplifier. The power control unit is configured to control the amplification of the chirped signal output by the radar system based on an evaluation of the chirped interval time provided by a chirped characteristic curve. The chirped interval time is the time difference between a first chirped signal and a second chirped signal to be output by the hybrid power amplifier. When the power control unit determines that the chirped interval time is less than a chirped interval time threshold, a fast power loop control configuration is used to control the output power transmitted at the hybrid amplifier stage. When the power control unit determines that the chirped interval time is equal to or greater than the chirped interval time threshold, a slow power loop configuration or a combination of a slow loop configuration and a fast loop configuration is used to control the output power transmitted at the hybrid power amplifier. The lookup table generated by the power control unit in the controller is used to determine the control signals and values ​​to be amplified by the hybrid power amplifier and voltage regulator.

[0077] In some embodiments, certain aspects of the techniques described above may be implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and certain data that, when executed by one or more processors, manipulate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, disk or optical disk storage devices, solid-state storage devices such as flash memory, cache memory, random access memory (RAM), or other non-volatile memory devices or multiple devices. The executable instructions stored on the non-transitory computer-readable storage medium may be in the form of source code, assembly language code, object code, or other instruction formats that can be interpreted or otherwise executed by one or more processors.

[0078] Computer-readable storage media may include any storage medium or combination of storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact disc (CD), digital versatile disc (DVD), Blu-ray disc), magnetic media (e.g., floppy disk, magnetic tape, or magnetic hard disk), volatile memory (e.g., random access memory (RAM) or cache memory), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical systems (MEMS) based storage media. Computer-readable storage media may be embedded in a computing system (e.g., system RAM or ROM), permanently attached to a computing system (e.g., magnetic hard disk), removably attached to a computing system (e.g., optical disc or USB-based flash memory), or coupled to a computer system via a wired or wireless network (e.g., network accessible storage device (NAS)).

[0079] It should be noted that not all of the activities or elements described in the general description above are necessary, and a particular activity or element may not be required. Furthermore, one or more additional activities or elements may be performed in addition to those described. Moreover, the order in which the activities are listed is not necessarily the order in which they are performed. Additionally, concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and changes can be made without departing from the scope of this disclosure as set forth in the following claims. Therefore, this specification and drawings should be viewed in an illustrative rather than restrictive sense, and all such modifications are contemplated to be included within the scope of this disclosure.

[0080] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, these benefits, advantages, solutions to problems, and any features that may make any benefit, advantage, or solution occur or become more significant should not be construed as essential, necessary, or fundamental features of any or all claims. Furthermore, the specific embodiments disclosed above are illustrative only, as the disclosed subject matter can be modified and practiced in different but equivalent ways that will be apparent to those skilled in the art from the teachings herein. No limitation is intended to be made on the details of the constructions or designs shown herein other than those described in the appended claims. Therefore, it will be apparent that the specific embodiments disclosed above may be altered or modified, and all such changes are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is as set forth in the appended claims.

Claims

1. A power control system for a radar, characterized by, comprising: a hybrid power amplifier; a power control unit coupled to the hybrid power amplifier, wherein the power control unit is configured to select a power control configuration based on an evaluation of an inter-chirp time, the power control configuration applied to the hybrid power amplifier to amplify a chirp signal transmitted by the power control system for radar; and a chirp generator coupled to the power control unit, wherein the chirp generator generates the chirp signal, the chirp signal amplified by the hybrid power amplifier and output by the power control system for radar; wherein the inter-chirp time is a difference in time between an end of a first chirp signal and a start of a second chirp signal output by the hybrid power amplifier; and when the inter-chirp time is less than an inter-chirp time threshold, the power control configuration is a fast power control loop configuration for adjusting an amount of power used to amplify the chirp signal.

2. The power control system for radar of claim 1, wherein: when the inter-chirp time is equal to or greater than the inter-chirp time threshold, the power control configuration is a slow power control loop configuration or a combination of the slow power control loop configuration and the fast power control loop configuration for adjusting the amount of power used to amplify the chirp signal.

3. The power control system for radar of claim 1, wherein, further comprising: a lookup table used by the power control unit to determine an output control signal and an output value used by the hybrid power amplifier to amplify the chirp signal output by the power control system for radar.

4. A power control method for a radar, characterized by, comprising: providing an inter-chirp time to a power control unit of a radar system; and adjusting an output power of a chirp signal transmitted by the radar system based on an evaluation of the inter-chirp time and a lookup table.

5. The method of claim 4, wherein: the evaluation of the inter-chirp time includes determining whether the inter-chirp time between a first chirp signal and a second chirp signal is greater than, equal to, or less than an inter-chirp threshold.

6. The method of claim 5, wherein: when the inter-chirp time is less than an inter-chirp time threshold, a fast power control loop configuration is used to reduce an amount of power consumed to amplify a chirp signal; when the inter-chirp time is equal to or greater than an inter-chirp time threshold, a slow power control loop configuration or a combination of the slow power control loop configuration and the fast power control loop configuration is used to reduce the amount of power consumed to amplify a chirp signal; the fast power control loop configuration utilizes a first cascode arrangement coupled to a second cascode arrangement to amplify the chirp signal output by the radar system.

7. A radar transceiver with power control, characterized by comprising: a hybrid power amplifier; and a power control unit coupled to the hybrid power amplifier, wherein the power control unit is configured to evaluate an inter-chirp time and a lookup table, and based on the evaluation, the hybrid power amplifier uses a first stage of the hybrid power amplifier to adjust an amount of power used to amplify a chirp signal transmitted by the transceiver.

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