Processor and startup method thereof

Abstract

A processor and a boot method thereof. The processor includes at least one package and at least one memory. Each of the at least one package includes a first bare die and a second bare die. The first bare die receives a boot enable signal and an internal boot enable signal to execute a boot program, and outputs a boot completion signal after completing the boot program. The second bare die receives the boot enable signal and the boot completion signal from the first bare die to execute the boot program. The second bare die is electrically connected to the first bare die through a communication bus. At least one memory is electrically connected to the second bare die. When the first bare die executes the boot program, the first bare die accesses the at least one memory through the communication bus and the second bare die.

Description

Technical Field

[0001] The invention relates to an electronic device, and in particular to a processor and a startup method thereof. Background Art

[0002] With the advancement of semiconductor process technology, a processor often includes multiple packages (sockets), each package includes multiple dies, and each die may include one or more cores, so that the processor can process multiple functional programs at the same time, increasing the processor's computing efficiency. As the internal structure of the processor becomes increasingly complex, how to efficiently communicate between cores or between dies, and how to execute the boot program inside the processor become increasingly important. In particular, how to enable a processor with multiple packages and multiple dies to boot efficiently has become an important issue. Summary of the invention

[0003] A processor according to an embodiment of the present invention includes at least one package and at least one memory. The at least one package includes a first die and a second die. The first die receives a power-on enable signal and an internal power-on enable signal to execute a power-on program, and outputs a power-on completion signal after completing the power-on program. The second die receives the power-on enable signal and the power-on completion signal from the first die to execute the power-on program. The second die is electrically connected to the first die via a communication bus. At least one memory is electrically connected to the second die. When the first die executes the power-on program, the first die accesses the at least one memory via the communication bus and the second die.

[0004] As in the processor mentioned above, the first bare die includes a first communication controller, the second bare die includes a second communication controller, and the first communication controller and the second communication controller are used to control access to at least one memory.

[0005] As in the processor mentioned above, when the first bare die executes the boot program, the first communication controller accesses at least one memory through the communication bus, and the second communication controller does not access the at least one memory.

[0006] As in the processor mentioned above, when the second bare die executes the boot program, the first communication controller does not access the at least one memory through the communication bus, and the second communication controller accesses the at least one memory.

[0007] A processor according to an embodiment of the present invention includes at least two packages and a memory. One of the at least two packages includes a first die and a second die. The first die receives a power-on enable signal and an internal power-on enable signal to execute a power-on program. After completing the power-on program, the first die outputs a first power-on completion signal. The second die receives the power-on enable signal and the first power-on completion signal from the first die to execute the power-on program. After completing the power-on program, the second die outputs a second power-on completion signal. The second die is electrically connected to the first die via a first communication bus. The other of the at least two packages includes a third die and a fourth die. The third die receives the second power-on completion signal and the internal power-on enable signal from the second die to execute the power-on program. After completing the power-on program, the third die outputs a third power-on completion signal. The fourth die receives the second power-on completion signal from the second die and the third power-on completion signal from the third die to execute the power-on program. The fourth die is electrically connected to the third die via a second communication bus. The memory is electrically connected to the second die and the fourth die. When the first die executes the booting procedure, the first die accesses the memory via the first communication bus and the second die.

[0008] As in the processor described above, when the first die executes the boot program, the second die does not access the memory, the third die does not access the memory through the second communication bus, and the fourth die does not access the memory.

[0009] As in the processor described above, when the second die executes the boot program, the second die accesses the memory, the first die does not access the memory through the first communication bus, the third die does not access the memory through the second communication bus, and the fourth die does not access the memory.

[0010] As in the processor described above, when the third die executes the boot procedure, the second die cuts off the electrical connection between itself and the memory, the third die accesses the memory through the second communication bus, and the fourth die does not access the memory.

[0011] As in the processor described above, when the fourth die executes the boot program, the third die does not access the memory through the second communication bus, and the fourth die accesses the memory.

[0012] For example, in the processor mentioned above, the booting sequence of the processor is the first die, the second die, the third die, and the fourth die.

[0013] A method for booting a processor according to an embodiment of the present invention is applicable to the processor having at least one package and at least one memory. The at least one package includes a first die and a second die, the at least one memory is electrically connected to the second die, and the second die is electrically connected to the first die via a communication bus. The booting method includes: receiving a booting enable signal and an internal booting enable signal, so that the first die executes a booting program; after completing the booting program of the first die, outputting a booting completion signal; receiving a booting enable signal and a booting completion signal from the first die, so that the second die executes the booting program; when the first die executes the booting program, the first die accesses the at least one memory via the communication bus and the second die.

[0014] As in the above-mentioned boot method, the first bare die includes a first communication controller, the second bare die includes a second communication controller, and the first communication controller and the second communication controller are used to control access to at least one memory.

[0015] The boot method as described above further includes: when the first bare die executes the boot program, the first communication controller accesses at least one memory through the communication bus, and the second communication controller does not access the at least one memory.

[0016] The boot method as described above further includes: when the second bare die executes the boot program, the first communication controller does not access the at least one memory through the communication bus, and the second communication controller accesses the at least one memory.

[0017] A method for starting up a processor according to an embodiment of the present invention is applicable to a processor having at least two packages and a memory. One of the at least two packages includes a first bare die and a second bare die, and the other of the at least two packages includes a third bare die and a fourth bare die. The memory is electrically connected to the second bare die and the fourth bare die. The second bare die is electrically connected to the first bare die via a first communication bus. The fourth bare die is electrically connected to the third bare die via a second communication bus. A boot method includes: receiving a boot enable signal and an internal boot enable signal, so that a first bare crystal executes a boot program; after completing the boot program of the first bare crystal, outputting a first boot completion signal; receiving the boot enable signal and a first boot completion signal from the first bare crystal, so that a second bare crystal executes the boot program; after completing the boot program of the second bare crystal, outputting a second boot completion signal; receiving a second boot completion signal from the second bare crystal and an internal boot enable signal, so that a third bare crystal executes the boot program; after completing the boot program of the third bare crystal, outputting a third boot completion signal; receiving a second boot completion signal from the second bare crystal and a third boot completion signal from the third bare crystal, so that a fourth bare crystal executes the boot program; when the first bare crystal executes the boot program, the first bare crystal accesses a memory through a first communication bus and the second bare crystal.

[0018] The power-on method as described above also includes: when the first bare die executes the power-on program, the second bare die does not access the memory, the third bare die does not access the memory through the second communication bus, and the fourth bare die does not access the memory.

[0019] The power-on method as described above also includes: when the second bare die executes the power-on program, the second bare die accesses the memory, the first bare die does not access the memory through the first communication bus, the third bare die does not access the memory through the second communication bus, and the fourth bare die does not access the memory.

[0020] The power-on method as described above also includes: when the third bare die executes the power-on program, the second bare die cuts off the electrical connection between itself and the memory, the third bare die accesses the memory through the second communication bus, and the fourth bare die does not access the memory.

[0021] The power-on method as described above further includes: when the fourth bare die executes the power-on program, the third bare die does not access the memory through the second communication bus, and the fourth bare die accesses the memory.

[0022] As in the above-mentioned booting method, the booting order of the processors is the first bare die, the second bare die, the third bare die, and the fourth bare die. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 FIG. 1 is a schematic diagram of a processor 100 according to an embodiment of the present invention.

[0024] Figure 2 FIG. 2 is a schematic diagram of a processor 200 according to an embodiment of the present invention.

[0025] Figure 3 For the embodiment of the present invention Figure 1 A signal timing diagram when the processor 100 is powered on.

[0026] Figure 4 For the embodiment of the present invention Figure 2 A signal timing diagram of the processor 200 when it is turned on.

[0027] Figure 5 For the embodiment of the present invention, it is applicable to Figure 1 Flowchart of a method for powering on the processor 100 .

[0028] Figure 6 For the embodiment of the present invention, it is applicable to Figure 2 Flowchart of a method for powering on the processor 200 . DETAILED DESCRIPTION

[0029] In order to make the above-mentioned purposes, features and advantages of some embodiments of the present disclosure more obvious and understandable, the following is a detailed description with reference to the accompanying drawings.

[0030] It must be understood that the words "comprise", "include" and the like used in this specification are intended to indicate the existence of specific technical features, values, method steps, operation processes, elements and / or components, but do not exclude the addition of more technical features, values, method steps, operation processes, elements, components, or any combination of the above.

[0031] The words “first”, “second”, “third”, “fourth”, etc. are used to modify elements and are not used to indicate a priority order or a prior relationship between them. Instead, they are used to distinguish elements with the same name.

[0032] It should be noted that the following embodiments can replace, reorganize, or mix the technical features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features between the embodiments can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0033] Figure 1 FIG. 1 is a schematic diagram of a processor 100 according to an embodiment of the present invention. Figure 1 As shown, the processor 100 includes a socket 110, a package 120, a memory 160, and a memory 170. Although the present invention is exemplified by a processor 100 having two packages, the present invention is not limited to the number of packages included in the processor. The package 110 includes a die 112 and a die 114. The package 120 includes a die 122 and a die 124. In some embodiments, each of the dies 112, 114, 122, 124 includes at least one processor core. In some embodiments, the configuration of the package 120, the die 122, the die 124, and the memory 170 is the same as the configuration of the package 110, the die 112, the die 114, and the memory 160.

[0034] Taking package 110 as an example, bare die 112 and bare die 114 have six ports respectively, which are a port BOOT_EN, a port BOOT_EN_INTER, a port SPI_PAD, a port SPI_INTER_PAD, a port BOOT_DONE, and a port GPIO_PAD. Bare die 112 and bare die 114 receive a boot enable signal 130 through their port BOOT_EN respectively. In some embodiments, the boot enable signal 130 may come from other functional blocks in processor 100, or from other circuits outside processor 100. Bare die 112 receives an internal boot enable signal 140 through its port BOOT_EN_INTER. In some embodiments, the internal boot enable signal 140 may come from other functional blocks in package 110, but the present invention is not limited thereto. The port BOOT_DONE of bare die 112 is electrically connected to the port BOOT_EN_INTER of bare die 114. The port SPI_PAD of the die 112 is electrically connected to the port SPI_INTER_PAD of the die 114 . The port SPI_PAD of the die 114 is electrically connected to the memory 160 .

[0035] Similarly, the die 122 and the die 124 receive the boot enable signal 130 through their ports BOOT_EN respectively. The die 122 receives the internal boot enable signal 140 through its port BOOT_EN_INTER. The port BOOT_DONE of the die 122 is electrically connected to the port BOOT_EN_INTER of the die 124. The port SPI_PAD of the die 122 is electrically connected to the port SPI_INTER_PAD of the die 124. The port SPI_PAD of the die 124 is electrically connected to the memory 170. In some embodiments, the memory 160 and the memory 170 are both a serial peripheral interface read-only memory (SPI ROM), but the present invention is not limited thereto.

[0036] In some embodiments, the bare die 112 receives a boot enable signal 130 (e.g., the boot enable signal 130 is "1") through the port BOOT_EN, and receives an internal boot enable signal 140 (e.g., the internal boot enable signal 140 is "1") through the port BOOT_EN_INTER, to execute a boot procedure. After completing the boot procedure, the bare die 112 correspondingly outputs a boot completion signal 150 (e.g., the boot completion signal 150 is "1") through the port BOOT_DONE. The bare die 114 receives the boot enable signal 130 through the port BOOT_EN, and receives the boot completion signal 150 from the bare die 112 through the port BOOT_EN_INTER, to execute the boot procedure. The port SPI_PAD of the bare die 112 is electrically connected to the port SPI_INTER_PAD of the bare die 114 through a communication bus 180. In some embodiments, when the die 112 executes a boot process, the die 112 accesses the memory 160 through the communication bus 180 and the die 114 .

[0037] In detail, the die 112 includes a first communication controller (not shown), and the die 114 includes a second communication controller (not shown). The first communication controller and the second communication controller are used to control access to the memory 160. In some embodiments, when the die 112 executes the boot program, the first communication controller of the die 112 accesses the memory 160 through the communication bus 180, and the second communication controller of the die 114 does not access the memory 160. In other words, when the die 112 executes the boot program, the second communication controller of the die 114 disconnects the electrical connection between the port SPI_PAD of the die 114 and the SPI communication interface inside the die 114, so that the die 114 cannot access the memory 160. On the other hand, when the die 112 executes the boot program, the first communication controller of the die 112 can access the memory 160 through the port SPI_PAD of the die 112, the communication bus 180, the port SPI_INTER_PAD of the die 114, and the port SPI_PAD.

[0038] Then, when the die 114 executes the booting procedure, the first communication controller of the die 112 does not access the memory 160 through the communication bus 180, and the second communication controller of the die 114 can access the memory 160 through the port SPI_PAD of the die 114. In other words, when the die 114 executes the booting procedure, the first communication controller of the die 112 disconnects the electrical connection between the port SPI_PAD of the die 112 and the SPI communication interface inside the die 112, so that the die 112 cannot access the memory 160.

[0039] In some embodiments, while the bare die 112 receives the boot enable signal 130 and the internal boot enable signal 140 to execute the boot program, the bare die 122 also receives the boot enable signal 130 through the port BOOT_EN and receives the internal boot enable signal 140 through the port BOOT_EN_INTER to execute the boot program. After completing the boot program, the bare die 122 outputs a boot completion signal 152 through the port BOOT_DONE. The bare die 124 receives the boot enable signal 130 through the port BOOT_EN and receives the boot completion signal 152 from the bare die 122 through the port BOOT_EN_INTER to execute the boot program. The port SPI_PAD of the bare die 122 is electrically connected to the port SPI_INTER_PAD of the bare die 124 through a communication bus 182. In some embodiments, when the bare die 122 executes the boot program, the bare die 122 accesses the memory 170 through the communication bus 182 and the bare die 124.

[0040] Specifically, the die 122 includes a third communication controller (not shown), and the die 124 includes a fourth communication controller (not shown). The third communication controller and the fourth communication controller are used to control access to the memory 170. In some embodiments, when the die 122 executes the boot program, the third communication controller of the die 122 accesses the memory 170 through the communication bus 182, and the fourth communication controller of the die 124 does not access the memory 170. In other words, when the die 122 executes the boot program, the fourth communication controller of the die 124 disconnects the electrical connection between the port SPI_PAD of the die 124 and the SPI communication interface inside the die 124, so that the die 124 cannot access the memory 170. On the other hand, when the die 122 executes the boot procedure, the third communication controller of the die 122 can access the memory 170 through the port SPI_PAD of the die 122 , the communication bus 182 , the port SPI_INTER_PAD of the die 124 , and the port SPI_PAD.

[0041] Then, when the die 124 executes the booting procedure, the third communication controller of the die 122 does not access the memory 170 through the communication bus 182, and the fourth communication controller of the die 124 can access the memory 170 through the port SPI_PAD of the die 124. In other words, when the die 124 executes the booting procedure, the third communication controller of the die 122 disconnects the electrical connection between the port SPI_PAD of the die 122 and the SPI communication interface inside the die 122, so that the die 122 cannot access the memory 170.

[0042] Figure 1The configuration of the processor 100 enables the package 110 and the package 120 to perform the boot process at the same time, thereby saving the boot time of the processor 100. Figure 1 The bare die 112, bare die 114, bare die 122, and bare die 124 all have a port GPIO_PAD for electrically connecting to a device supporting a GPIO communication interface. Since the present invention does not utilize the port GPIO_PAD, it will not be described in detail here.

[0043] Figure 2 FIG. 2 is a schematic diagram of a processor 200 according to an embodiment of the present invention. Figure 2 As shown, the processor 200 includes a package 210, a package 220, and a memory 260. Although the present invention is exemplified by a processor 200 having two packages, the present invention is not limited to the number of packages included in the processor. The package 210 includes a bare die 212 and a bare die 214. The package 220 includes a bare die 222 and a bare die 224. In some embodiments, each of the bare die 212, 214, 222, 224 includes at least one processor core.

[0044] Same as Figure 1 , the bare die 212, 214, 222, and 224 respectively have six ports, which are port BOOT_EN, port BOOT_EN_INTER, port SPI_PAD, port SPI_INTER_PAD, port BOOT_DONE, and port GPIO_PAD. The bare die 212 and the bare die 214 respectively receive a boot enable signal 230 through their port BOOT_EN. In some embodiments, the boot enable signal 230 may come from other functional blocks in the processor 200, or from other circuits outside the processor 200. The bare die 212 receives an internal boot enable signal 240 through its port BOOT_EN_INTER. In some embodiments, the internal boot enable signal 240 may come from other functional blocks in the package 210, but the present invention is not limited thereto. The port BOOT_DONE of the bare die 212 is electrically connected to the port BOOT_EN_INTER of the bare die 214. The port SPI_PAD of the die 212 is electrically connected to the port SPI_INTER_PAD of the die 214 . The port SPI_PAD of the die 214 is electrically connected to the memory 260 .

[0045] The ports BOOT_EN of the die 222 and the die 224 are respectively electrically connected to the port BOOT_DONE of the die 214. The die 222 receives the internal boot enable signal 240 through its port BOOT_EN_INTER. The port BOOT_DONE of the die 222 is electrically connected to the port BOOT_EN_INTER of the die 224. The port SPI_PAD of the die 222 is electrically connected to the port SPI_INTER_PAD of the die 224. The port SPI_PAD of the die 224 is electrically connected to the memory 260.

[0046] In some embodiments, the bare die 212 receives a boot enable signal 230 through the port BOOT_EN and receives an internal boot enable signal 240 through the port BOOT_EN_INTER to execute a boot procedure. After completing the boot procedure, the bare die 212 outputs a boot completion signal 250 through its port BOOT_DONE accordingly. The bare die 214 receives the boot enable signal 230 through the port BOOT_EN and receives the boot completion signal 250 from the bare die 212 through the port BOOT_EN_INTER to execute the boot procedure. After completing the boot procedure, the bare die 214 outputs a boot completion signal 252 through the port BOOT_DONE. The bare die 214 is electrically connected to the bare die 212 via a communication bus 280.

[0047] Next, the die 222 receives a boot completion signal 252 from the die 214 through the port BOOT_EN, and receives an internal boot enable signal 240 through the port BOOT_EN_INTER, to execute the boot procedure. After completing the boot procedure, the die 222 correspondingly outputs a boot completion signal 254 from the port BOOT_DONE. The die 224 receives a boot completion signal 252 from the die 214 through the port BOOT_EN, and receives a boot completion signal 254 from the die 222 through the port BOOT_EN_INTER, to execute the boot procedure. The die 224 is electrically connected to the die 222 through a communication bus 282. In some embodiments, when the die 212 executes the boot procedure, the die 212 accesses the memory 260 through the communication bus 280 and the die 214. The same as Figure 1 Bare crystals 112, 114, 122, 124, Figure 2 Each of the bare chips 212 , 214 , 222 , 224 has a communication controller (not shown) for allocating and controlling access to the memory 260 .

[0048] In some embodiments, when the die 212 executes the boot program, the die 214 does not access the memory 260, the die 222 does not access the memory 260 through the communication bus 282, and the die 224 does not access the memory 260. In detail, when the die 212 executes the boot program, the die 212 accesses the memory 260 through its port SPI_PAD, the communication bus 280, the port SPI_INTER_PAD of the die 214, and the port SPI_PAD. When the die 212 executes the boot program, the die 214 disconnects the electrical connection between the port SPI_PAD of the die 214 and the SPI communication interface inside the die 214, so that the die 214 cannot access the memory 260.

[0049] Similarly, when the die 212 executes the boot program, the die 222 disconnects the electrical connection between the port SPI_PAD of the die 222 and the SPI communication interface inside the die 222, so that the die 222 cannot access the memory 260. When the die 212 executes the boot program, the die 224 also disconnects the electrical connection between the port SPI_PAD of the die 224 and the SPI communication interface inside the die 224, so that the die 224 cannot access the memory 260.

[0050] In some embodiments, when die 214 executes the booting procedure, die 214 accesses memory 260, die 212 does not access memory 260 through communication bus 280, die 222 does not access memory 260 through communication bus 282, and die 224 does not access memory 260. In some embodiments, when die 222 executes the booting procedure, die 214 cuts off the electrical connection between itself and memory 260, die 222 accesses memory 260 through communication bus 282, and die 224 does not access memory 260. When die 224 executes the booting procedure, die 222 does not access memory 260 through communication bus 282, and die 224 accesses memory 260.

[0051] In summary, the booting sequence of the processor 200 is the bare die 212 , the bare die 214 , the bare die 222 , and the bare die 224 . Figure 2 The configuration of the processor 200 enables the package 210 and the package 220 to share the memory 260, so as to save the cost of hardware configuration.

[0052] Figure 3 For the embodiment of the present invention Figure 1 The signal timing diagram when the processor 100 is turned on. Figure 3As shown, at time point t1, the signal PCIRST_ changes from low level to high level, indicating that the PCI communication interface of the processor 100 is reset. At time point t1, the bare die 112 receives a high level boot enable signal 130 through the port BOOT_EN, and receives a high level internal boot enable signal 140 through the port BOOT_EN_INTER, and then starts to execute the boot program and access the memory 160. Since the intermediate path for bare die 112 to access memory 160 is from port SPI_PAD of bare die 112, port SPI_INTER_PAD of bare die 114, to port SPI_PAD of bare die 114, it can be observed that the signal of port SPI_PAD of bare die 112 (including signal SPI_PAD_CLK, SPI_PAD_CS, SPI_PAD_DO, SPI_PAD_DI) is exactly the same as the signal of port SPI_INTER_PAD of bare die 114 (including signal SPI_INTER_PAD_CLK, SPI_INTER_PAD_CS, SPI_INTER_PAD_DO, SPI_INTER_PAD_DI) and the signal of port SPI_PAD (including signal SPI_PAD_CLK, SPI_PAD_CS, SPI_PAD_DO, SPI_PAD_DI). This proves that the same data is being transmitted between bare die 112 and memory 160.

[0053] At time point t2, the die 112 completes the boot process and correspondingly outputs a boot completion signal 150 from the port BOOT_DONE to the port BOOT_EN_INTER of the die 114. At time point t2, the die 114 receives a high-level boot enable signal 130 through the port BOOT_EN, and receives a high-level boot completion signal 150 from the die 112 through the port BOOT_EN_INTER, and then starts to execute the boot process and access the memory 160. Since the die 114 accesses the memory 160 through the port SPI_PAD, the signal of the port SPI_PAD of the die 114 (including the signals SPI_PAD_CLK, SPI_PAD_CS, SPI_PAD_DO, and SPI_PAD_DI) can be observed. At time point t3, the die 114 completes the boot process, so that a high-level signal can be observed at the port BOOT_DONE of the die 114.

[0054] Figure 4 For the embodiment of the present invention Figure 2 The signal timing diagram when the processor 200 is turned on. Figure 4As shown, at time point t4, the signal PCIRST_ changes from low level to high level, indicating that the PCI communication interface of the processor 200 is reset. At time point t4, the bare die 212 receives the high-level boot enable signal 230 through the port BOOT_EN, and receives the high-level internal boot enable signal 240 through the port BOOT_EN_INTER, and then starts to execute the boot program and access the memory 260. Since the intermediate path for the bare die 212 to access the memory 260 is the port SPI_PAD of the bare die 212, the port SPI_INTER_PAD of the bare die 214, and the port SPI_PAD of the bare die 214, it can be observed that the signal (or data) of the port SPI_PAD of the bare die 212 is exactly the same as the signal (or data) of the port SPI_INTER_PAD of the bare die 214 and the signal (or data) of the port SPI_PAD.

[0055] At time point t5, the die 212 completes the boot process and correspondingly outputs a boot completion signal 250 from the port BOOT_DONE to the port BOOT_EN_INTER of the die 214. At time point t5, the die 214 receives the high-level boot enable signal 230 through the port BOOT_EN, and receives the high-level boot completion signal 250 from the die 212 through the port BOOT_EN_INTER, and then starts to execute the boot process and access the memory 260. Since the die 214 accesses the memory 260 through the port SPI_PAD, the signal of the port SPI_PAD of the die 214 can be observed.

[0056] At time point t6, the die 214 completes the boot process and correspondingly outputs a boot completion signal 252 from the port BOOT_DONE to the port BOOT_EN of the die 222. At time point t6, the die 222 receives the high-level boot completion signal 252 from the die 214 through the port BOOT_EN, and receives the high-level internal boot enable signal 240 through the port BOOT_EN_INTER, and then starts to execute the boot process and access the memory 260. Since the intermediate path for the die 222 to access the memory 260 is the port SPI_PAD of the die 222, the port SPI_INTER_PAD of the die 224, and the port SPI_PAD of the die 224, it can be observed that the signal of the port SPI_PAD of the die 222 is exactly the same as the signal of the port SPI_INTER_PAD and the signal of the port SPI_PAD of the die 224.

[0057] At time point t7, the bare die 222 completes the boot procedure and correspondingly outputs the boot completion signal 254 from the port BOOT_DONE to the port BOOT_EN_INTER of the bare die 224. At time point t7, the bare die 224 receives the high-level boot completion signal 252 from the bare die 214 through the port BOOT_EN, and receives the high-level boot completion signal 254 from the bare die 222 through the port BOOT_EN_INTER, and then starts to execute the boot procedure and access the memory 260. Since the bare die 224 accesses the memory 260 through the port SPI_PAD, the signal of the port SPI_PAD of the bare die 224 can be observed. At time point t8, the bare die 224 completes the boot procedure, so that the port BOOT_DONE of the bare die 224 can observe a high-level signal.

[0058] Figure 5 For the embodiment of the present invention, it is applicable to Figure 1 Flow chart of the method for starting up the processor 100. Figure 5 As shown, the power-on method of the processor 100 of the present invention includes: receiving a power-on enable signal (eg Figure 1 A power-on enable signal 130) and an internal power-on enable signal (eg Figure 1 The internal power-on enable signal 140 of the first die (eg Figure 1 After the first die 112 is powered on, a power-on completion signal (eg, Figure 1 Receive the power-on enable signal and the power-on completion signal from the first die, so that the second die (eg Figure 1 When the first bare die executes the booting procedure, the first bare die communicates with the user through the communication bus (eg, Figure 1 communication bus 180) and the second die to at least one memory (eg Figure 1 Memory 160) is accessed (step S506).

[0059] Figure 6 For the embodiment of the present invention, it is applicable to Figure 2 Flow chart of the method for starting up the processor 200. Figure 6 As shown, the power-on method of the processor 200 of the present invention includes: receiving a power-on enable signal (eg Figure 2 A power-on enable signal 230) and an internal power-on enable signal (eg Figure 2 The internal power-on enable signal 240 of the first die (eg Figure 2After the first bare die boot process is completed, a first boot completion signal (eg, Figure 2 Receive the power-on enable signal and the first power-on completion signal from the first die, so that the second die (eg Figure 2 After the second die 214 is powered on, a second power-on completion signal (eg, Figure 2 Receive the second power-on completion signal and the internal power-on enable signal from the second die, so that the third die (eg Figure 2 After the booting procedure of the third die is completed, a third booting completion signal (eg, Figure 2 receiving a second power-on completion signal from the second die and a third power-on completion signal from the third die, so that the fourth die ( Figure 2 When the first bare die executes the booting procedure, the first bare die communicates with the first bare die via the first communication bus (eg Figure 2 communication bus 280) and a second die to a memory (eg Figure 2 Memory 260) is accessed (step S614).

[0060] Other booting methods of the processor 100 and the processor 200 of the present invention have been described in the previous paragraphs, so they will not be repeated here. Figure 1 The processor 100 and Figure 2 After the boot procedure of each bare die in the processor 200, the processor 100 and the processor 200 can start the initialization power-on process of the ZPI / ZDI link. Among them, ZPI is a package-package (socket-to-socket) interconnection, and ZDI is a bare die-to-die interconnection. For example, the processor 100 and the processor 200 can configure the physical address, link width, link speed and other related registers of the ZPI / ZDI, release the reset of the software, and the ZPI / ZDI starts the linkup process.

[0061] During the ZPI / ZDI connection process, the software will read the status of the ZPI / ZDI LTSSM (Link Training and Status State Machine), wait for the LTSSM to enter the L0 state and the DLL file to be activated. If the current link speed is not the fastest, the software can configure the LCRL register to trigger the ZPI / ZDI link speed to the highest speed, and wait for the LTSSM state to reach the L0 state again, and the ZPI / ZDI completes the connection process.

[0062] Although the embodiments of the present invention are described above, it should be understood that what is presented above is only an example and not a limitation. Many changes to the above exemplary embodiments can be implemented without violating the spirit and scope of the invention according to this embodiment. Therefore, the breadth and scope of the present invention should not be limited by the embodiments described above. Rather, the scope of the present invention should be defined by the claims and their equivalents. Although the above invention has been illustrated and described by one or more related executions, equivalent changes and modifications will be thought of by others who are familiar with this field based on the above specifications and drawings. In addition, although a particular feature of the present invention has been demonstrated by one of the related multiple executions, the above feature may be combined with one or more other features so that there may be a need and help for any known or special application.

[0063] The professional terms used in this specification are only for the purpose of describing specific embodiments and are not intended to be used as limitations of the present invention. Unless the context clearly indicates otherwise, the singular, the one, the above and the above also include the plural. Furthermore, the words "include", "comprise", "have", "have", or their variations are either used as detailed descriptions or as the scope of protection required by the application. The above words mean to include, and to some extent are equivalent to the word "include". Unless there are different definitions, all the terms used in this article (including technical or scientific terms) can be generally understood by those skilled in the art. We should be more aware that the above words, such as those defined in commonly used dictionaries, should be interpreted as the same meaning in the context of the relevant technology. Unless explicitly defined in this article, the above words will not be interpreted as idealized or overly formal.

Claims

1. A processor, comprising: At least one package, each of which comprises: The first bare die receives a power-on enable signal and an internal power-on enable signal to execute a power-on procedure; after completing the power-on procedure, outputs a power-on completion signal; A second bare die receives the boot enable signal and the boot completion signal from the first bare die to execute the boot procedure; wherein the second bare die is connected to the first bare die via a communication bus; at least one memory connected to the second die; When the first bare die executes the booting procedure, the first bare die accesses the at least one memory through the communication bus and the second bare die.

2. The processor of claim 1, wherein: The first bare die includes a first communication controller, and the second bare die includes a second communication controller. The first communication controller and the second communication controller are used to control access to the at least one memory.

3. The processor of claim 2, wherein: When the first bare die executes the booting procedure, the first communication controller accesses the at least one memory through the communication bus, and the second communication controller does not access the at least one memory.

4. The processor of claim 2, wherein: When the second bare die executes the booting procedure, the first communication controller does not access the at least one memory through the communication bus, and the second communication controller accesses the at least one memory.

5. A processor, comprising: At least two packages, one of which includes: The first bare die receives a power-on enable signal and an internal power-on enable signal to execute a power-on procedure; after completing the power-on procedure, outputs a first power-on completion signal; A second bare die receives the boot enable signal and the first boot completion signal from the first bare die to execute the boot procedure; after completing the boot procedure, outputs a second boot completion signal; wherein the second bare die is connected to the first bare die via a first communication bus; Another package of the at least two packages includes: A third bare die receives the second boot completion signal and the internal boot enable signal from the second bare die to execute the boot procedure; after completing the boot procedure, outputs a third boot completion signal; a fourth bare die, receiving the second boot completion signal from the second bare die and the third boot completion signal from the third bare die, for executing the boot procedure; wherein the fourth bare die is connected to the third bare die via a second communication bus; A memory connected to the second die and the fourth die; When the first bare die executes the booting program, the first bare die accesses the memory through the first communication bus and the second bare die.

6. The processor of claim 5, wherein: When the first bare die executes the boot program, the second bare die does not access the memory, the third bare die does not access the memory through the second communication bus, and the fourth bare die does not access the memory.

7. The processor of claim 5, wherein: When the second bare die executes the boot program, the second bare die accesses the memory, the first bare die does not access the memory through the first communication bus, the third bare die does not access the memory through the second communication bus, and the fourth bare die does not access the memory.

8. The processor of claim 5, wherein: When the third bare die executes the boot program, the second bare die cuts off the connection between itself and the memory, the third bare die accesses the memory through the second communication bus, and the fourth bare die does not access the memory.

9. The processor of claim 8, wherein: When the fourth die executes the booting procedure, the third die does not access the memory through the second communication bus, and the fourth die accesses the memory.

10. The processor of claim 5, wherein: The booting sequence of the processor is the first bare die, the second bare die, the third bare die, and the fourth bare die.

11. A method for starting a processor, applicable to a processor having at least one package and at least one memory, wherein: The at least one package includes a first bare die and a second bare die, the at least one memory is connected to the second bare die, and the second bare die is connected to the first bare die via a communication bus; the boot method includes: Receiving a power-on enable signal and an internal power-on enable signal, so that the first bare die executes a power-on procedure; After completing the booting procedure of the first bare die, outputting a booting completion signal; receiving the boot enable signal and the boot completion signal from the first bare die, so that the second bare die executes the boot procedure; When the first die executes the booting procedure, the first die accesses the at least one memory through the communication bus and the second die.

12. The startup method according to claim 11, wherein: The first bare die includes a first communication controller, and the second bare die includes a second communication controller. The first communication controller and the second communication controller are used to control access to the at least one memory.

13. The startup method according to claim 12, further comprising: When the first bare die executes the booting procedure, the first communication controller accesses the at least one memory through the communication bus, and the second communication controller does not access the at least one memory.

14. The startup method according to claim 12, further comprising: When the second bare die executes the booting procedure, the first communication controller does not access the at least one memory through the communication bus, and the second communication controller accesses the at least one memory.

15. A method for starting a processor, applicable to the processor having at least two packages and a memory, wherein: One of the at least two packages includes a first die and a second die, the other of the at least two packages includes a third die and a fourth die, the memory is connected to the second die and the fourth die, the second die is connected to the first die via a first communication bus, and the fourth die is connected to the third die via a second communication bus; the startup method includes: Receiving a power-on enable signal and an internal power-on enable signal, so that the first bare die executes a power-on procedure; After completing the boot procedure of the first bare die, outputting a first boot completion signal; receiving the boot enable signal and the first boot completion signal from the first bare die, so that the second bare die executes the boot procedure; After completing the booting procedure of the second bare die, outputting a second booting completion signal; receiving the second boot completion signal and the internal boot enable signal from the second bare die, so that the third bare die executes the boot procedure; After completing the booting procedure of the third bare die, outputting a third booting completion signal; receiving the second boot completion signal from the second die and the third boot completion signal from the third die, so that the fourth die executes the boot procedure; When the first die executes the booting procedure, the first die accesses the memory through the first communication bus and the second die.

16. The startup method according to claim 15, further comprising: When the first bare die executes the boot program, the second bare die does not access the memory, the third bare die does not access the memory through the second communication bus, and the fourth bare die does not access the memory.

17. The startup method according to claim 15, further comprising: When the second bare die executes the boot program, the second bare die accesses the memory, the first bare die does not access the memory through the first communication bus, the third bare die does not access the memory through the second communication bus, and the fourth bare die does not access the memory.

18. The startup method according to claim 15, further comprising: When the third bare die executes the boot program, the second bare die cuts off the connection between itself and the memory, the third bare die accesses the memory through the second communication bus, and the fourth bare die does not access the memory.

19. The startup method according to claim 18, further comprising: When the fourth die executes the booting procedure, the third die does not access the memory through the second communication bus, and the fourth die accesses the memory.

20. The startup method according to claim 15, wherein: The booting sequence of the processor is the first bare die, the second bare die, the third bare die, and the fourth bare die.

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