A method for simulating SPI interface based on GPIO interface

Abstract

The present invention discloses a method for simulating an SPI interface based on a GPIO interface, the method comprising the following steps: step 1: selecting four GPIO interfaces in a microprocessor chip to simulate an SPI interface; step 2: simulating the SPI interface to send data through a delay unit; step 3: simulating the SPI interface to receive data through the delay unit. The present invention implements configuration of four interfaces for simulating SPI communication, reducing the complexity of configuration.

Description

Technical Field

[0001] The invention belongs to the technical field of interfaces of embedded systems, and in particular relates to a method for simulating an SPI interface based on a GPIO interface. Background Art

[0002] GPIO (General purpose Input Output) ports are widely used in embedded systems. Users can program the GPIO ports to output high and low levels to transmit some signals, such as clock signals, chip select signals, etc.

[0003] SPI is the abbreviation of Serial Peripheral Interface, which is a synchronous serial interface technology. It occupies up to four wires on the chip pins and can realize full-duplex serial communication with industrial standard encoders, decoders, analog interface chips, etc.

[0004] Common microprocessor chips usually have only one or two SPI interfaces. For example, the commonly used chip tms320F28335 has only one SPI interface. For complex systems, one or two SPI interfaces are not enough. For example, in order to achieve precise control of robot joint control, the robot needs to be equipped with twenty or thirty sensors. Even if the sensor data acquisition is optimized, the SPI interface of the microprocessor chip cannot meet the system requirements. Simply expanding the number of microprocessor chips will bring difficulties to spatial layout. Summary of the invention

[0005] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art, to provide a method for simulating an SPI interface based on a GPIO interface, to configure four interfaces for simulating SPI communication, and to reduce the complexity of the configuration.

[0006] The object of the present invention is achieved through the following technical scheme: a method for simulating an SPI interface based on a GPIO interface, the method comprising the following steps: step one: selecting four GPIO interfaces in a microprocessor chip to simulate an SPI interface; step two: simulating the SPI interface to send data through a delay unit; step three: simulating the SPI interface to receive data through a delay unit.

[0007] In the above method of simulating SPI interface based on GPIO interface, in step one, one GPIO interface simulates the SPI interface of chip select signal CS; one GPIO interface simulates the SPI interface of clock signal SCLK; one GPIO interface simulates the SPI interface of output signal Dout; and one GPIO interface simulates the SPI interface of input signal Din.

[0008] In the above-mentioned method of simulating SPI interface based on GPIO interface, in step one, the GPIO interface of the SPI interface that simulates chip select signal CS is set to data output mode; the GPIO interface of the SPI interface that simulates clock signal SCLK is set to data output mode; the GPIO interface of the SPI interface that simulates output signal Dout is set to data output mode; the GPIO interface of the SPI interface that simulates input signal Din is set to data input mode.

[0009] In the above method for simulating an SPI interface based on a GPIO interface, the delay unit is a functional unit for adjusting the frequency of the simulated clock.

[0010] In the above method of simulating SPI interface based on GPIO interface, in step 2, simulating SPI interface to send data through delay unit includes the following steps: step P21: pull down the SPI interface level of analog chip select signal CS to a valid level; step P22: when the analog chip select signal CS is valid, a time interval of t1 is required before the falling edge signal of analog clock signal SCLK; wherein, the time interval of t1 is implemented by calling delay unit; step P23: set the SPI interface of analog clock signal SCLK to a low level, indicating that the sending of one bit of data can be started; step P24: after the falling edge of the clock, a time interval greater than t5 is required to transmit the output signal, wherein, the time interval of t5 is implemented by calling delay unit; step P25: according to the waiting Sending bit data sets the level of the SPI interface of the analog output signal Dout; Step P26: After the SPI interface of the analog output signal Dout sends out a bit of data, a time interval greater than (t3-t5) is required to set the analog clock signal SCLK interface to a high level; wherein, the (t3-t5) time interval is implemented by calling the delay unit; Step P27: Setting the SPI interface of the analog clock signal SCLK to a high level to prepare for transmitting the next bit of data; Step P28: When the SPI interface of the analog clock signal SCLK changes from a high level to a low level, a time interval greater than t2 is required to set the high level of the SPI interface of the analog clock signal SCLK to a low level, wherein, the t2 time interval is implemented by calling the delay unit.

[0011] In the above-mentioned method of simulating SPI interface based on GPIO interface, in step three, simulating SPI interface to receive data through delay unit includes the following steps: step P31: before data reception, the analog chip select signal CS interface level needs to be pulled down to a valid level; step P32: when the analog chip select signal CS is valid, a time interval of t6 is required before the falling edge signal of the analog clock signal SCLK; wherein, the time interval of t6 is implemented by calling the delay unit; step P33: the SPI interface of the analog clock signal SCLK is set to a low level, indicating that the reception of one bit of data can be started; step P34: after the falling edge of the clock, a time interval greater than t10 needs to be satisfied before the input signal can be transmitted, wherein, the time interval of t10 is implemented by calling the delay unit; step P35: based on The SPI interface of the analog input signal Din detects the high and low levels and records the input data; Step P36: After the SPI interface of the analog input signal Din receives one bit of data, a time interval greater than (t8-t10) is required to set the analog clock signal SCLK interface to a high level, wherein the (t8-t10) time interval is implemented by calling the delay unit; Step P37: The SPI interface of the analog clock signal SCLK is set to a high level to prepare for the transmission of the lower data; Step P38: When the SPI interface of the analog clock signal SCLK changes from a high level to a low level, a time interval greater than t7 is required to set the high level of the SPI interface of the analog clock signal SCLK to a low level, wherein the t7 time interval is implemented by calling the delay unit.

[0012] Compared with the prior art, the present invention has the following beneficial effects:

[0013] (1) The present invention realizes the configuration of four interfaces for simulating SPI communication, thereby eliminating the need to configure multiple SPI registers and reducing the complexity of the configuration;

[0014] (2) The present invention does not need to be limited to multiples of 1 byte by the SPI receiving and sending data of the main control chip, and the length of the received and sent data can be set according to the actual communication needs, thereby improving the flexibility of use;

[0015] (3) The present invention can flexibly configure the delay unit according to the timing requirements of the SPI communication protocol to achieve a suitable clock frequency;

[0016] (4) The present invention can break through the limitation of the number of SPI interfaces provided by the embedded microprocessor chip, and can configure the analog SPI interface according to the application requirements and the number of general pins of the microprocessor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0018] Figure 1 is a flow chart of a delay unit provided by an embodiment of the present invention;

[0019] Figure 2 It is a flow chart of simulating SPI interface sending data provided by an embodiment of the present invention;

[0020] Figure 3 is a data transmission timing diagram provided by an embodiment of the present invention;

[0021] Figure 4 It is a flow chart of simulating SPI interface receiving data provided by an embodiment of the present invention;

[0022] Figure 5 This is a data receiving timing diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that, in the absence of conflict, the embodiments of the present invention and the features described in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0024] The present embodiment provides a method for simulating an SPI interface based on a GPIO interface, the method comprising the following steps: step 1: selecting 4 GPIO interfaces in a microprocessor chip to simulate an SPI interface; step 2: simulating the SPI interface to send data through a delay unit; step 3: simulating the SPI interface to receive data through a delay unit.

[0025] Select 4 GPIO interfaces in the microprocessor chip to simulate the SPI interface: (1) one GPIO interface simulates the chip select signal CS; (2) one GPIO interface simulates the clock signal SCLK; (3) one GPIO interface simulates the output signal Dout; (4) one GPIO interface simulates the input signal Din.

[0026] The microprocessor chip acts as the communication mode of the master station. When idle, the SCLK clock is at a high level and the sampling time is an even edge. Therefore, the four selected analog GPIO interfaces are configured as follows in the program: (1) The analog chip select signal CS interface is configured as an ordinary GPIO interface and is set to data output mode; (2) The analog clock signal SCLK interface is configured as an ordinary GPIO interface and is set to data output mode; (3) The analog output signal Dout interface is configured as an ordinary GPIO interface and is set to data output mode; (4) The analog input signal Din interface is configured as an ordinary GPIO interface and is set to data input mode.

[0027] Elements that need to be configured for the analog SPI interface: (1) Set the length of each data sent and received. If the SPI interface of the DSP is used, the length of the sent and received data can only be bytes or multiples of bytes due to register restrictions. If the analog SPI interface is used, the length of the sent and received data can be flexibly set according to needs; (2) Initialize the analog chip select signal CS to a high level; (3) Initialize the analog clock signal SCLK to a high level, that is, the clock idle state is a high level.

[0028] Since SPI communication has high timing requirements, it is necessary to configure the analog clock frequency for communication according to the SPI protocol to be used. The delay unit is a functional unit used to adjust the analog clock frequency. The function of the delay unit is realized through the program algorithm. By changing the number of loops in the program, the delay unit duration is adjusted. The delay unit algorithm flow is as follows: Figure 1 .

[0029] 1) The assembly instruction set CP11 used to implement the P11 function is {cp11_1, cp11_2...cp11_n}, and the number of instruction cycles required to execute each instruction corresponding to the elements in the set CP11 is set CPF11={cpf11_1, cpf11_2...cpf11_n1};

[0030] The assembly instruction set CP12 used to implement the P12 function is {cp12_1, cp12_2...cp12_n}, and the number of instruction cycles required to execute each instruction corresponding to the elements in the set CP12 is set CPF12={cpf12_1, cpf12_2...cpf12_n2};

[0031] The assembly instruction set CP13 used to implement the P13 function is {cp13_1, cp13_2...cp13_n}, and the number of instruction cycles required to execute each instruction corresponding to the elements in the set CP13 is set CPF13={cpf13_1, cpf13_2...cpf13_n3};

[0032] The assembly instruction set CP14 used to implement the P14 function is {cp14_1, cp14_2...cp14_n}, and the number of instruction cycles required to execute each instruction corresponding to the elements in the set CP14 is set CPF14={cpf14_1, cpf14_2...cpf14_n4};

[0033] 2) The time required for each assembly language instruction cycle ct (Note: different chips have different corresponding instruction cycles); the number of cycles cyc_length required to implement the P13 function in the delay unit, and the execution delay unit is controlled by adjusting the number of cyc_length times;

[0034] 3) Execute the delay unit to obtain the delay:

[0035] t_delay=((cpf11_1+cpf11_2+……cpf11_n1)+((cpf12_1+cpf12_2+……cpf12_n2)+(cpf1 3_1+cpf13_2+……cpf13_n3))*cyc_length+(cpf11_1+cpf11_2+……cpf11_n4))*ct;……Formula 1

[0036] Simulate SPI interface to send data:

[0037] According to the SPI data transmission timing diagram ( Figure 3 ) and simulate SPI interface data transmission process ( Figure 2 ), the specific process is as follows:

[0038] Step P21: Based on Figure 3 , SPI data transmission timing diagram, before sending data, the analog chip select signal CS interface level needs to be pulled down to a valid level;

[0039] Step P22: When the analog chip select signal CS is valid and before the falling edge signal of the analog clock SCLK, the SPI data is sent according to the timing Figure 3 , a time interval of t1 is required, which can be implemented by calling the delay unit 22. Referring to formula 1, the time length used by the delay unit 22 is:

[0040] t_delay_t22=((cpf11_1+cpf11_2+……cpf11_n1)+((cpf12_1+cpf12_2+……cpf12_n2)+(cpf 13_1+cpf13_2+……cpf13_n3))*cyc_length22+(cpf11_1+cpf11_2+……cpf11_n4))*ct;……Formula 2

[0041] The parameters in formula 2: cpf11_1, cpf11_2…cpf11_n1; cpf12_1, cpf12_2…cpf12_n2; cp13_1, cp13_2…cp13_n3; cpf14_1, cpf14_2…cpf14_n4; ct; have the same meanings as in formula 1.

[0042] cyc_length22 is the number of cycles required to satisfy the t1 time interval, which can be calculated by t_delay_t22>t1 (Formula 3). cyc_length22 can be obtained by Formula 2 and Formula 3.

[0043] cyc_length22>((t1 / ct)-(cpf11_1+cpf11_2+……cpf11_n1)-(cpf11_1+cpf11_2+…… cpf11_n4)) / ((cpf12_1+cpf12_2+……cpf12_n2)+(cpf13_1+cpf13_2+……cpf13_n3))

[0044] Step P23: Set the analog clock signal SCLK interface to a low level, indicating that the transmission of one bit of data can be started;

[0045] Step P24: According to the SPI data transmission timing Figure 3 , after the falling edge of the clock, a time interval greater than t5 is required to transmit the output signal. This time interval can be implemented by calling the delay unit 24. Referring to formula 1, the time length used by the delay unit 24 is:

[0046] t_delay_t24=((cpf11_1+cpf11_2+……cpf11_n1)+((cpf12_1+cpf12_2+……cpf12_n2)+(cpf 13_1+cpf13_2+……cpf13_n3))*cyc_length24+(cpf11_1+cpf11_2+……cpf11_n4))*ct;……Formula 4

[0047] The parameters in formula 4: cpf11_1, cpf11_2…cpf11_n1; cpf12_1, cpf12_2…cpf12_n2; cp13_1, cp13_2…cp13_n3; cpf14_1, cpf14_2…cpf14_n4; ct; have the same meanings as those in formula 1.

[0048] cyc_length24 is the number of cycles required to satisfy the t5 time interval, which can be calculated by t_delay_t24>t5 (Formula 5). Cyc_length24 can be obtained by Formula 4 and Formula 5.

[0049] cyc_length24>((t5 / ct)-(cpf11_1+cpf11_2+……cpf11_n1)-(cpf11_1+cpf11_2+…… cpf11_n4)) / ((cpf12_1+cpf12_2+……cpf12_n2)+(cpf13_1+cpf13_2+……cpf13_n3)).

[0050] Step P25: setting the level of the analog output signal Dout interface according to the bit data to be sent;

[0051] Step P26: According to the SPI data transmission timing Figure 3 After the analog output signal Dout interface sends out a bit of data, a time interval greater than (t3-t5) is required to set the analog clock signal SCLK interface to a high level. This time interval can be implemented by calling the delay unit 26. Referring to formula 1, the time length used by the delay unit 26 is:

[0052] t_delay_t26=((cpf11_1+cpf11_2+……cpf11_n1)+((cpf12_1+cpf12_2+……cpf12_n2)+(cpf 13_1+cpf13_2+……cpf13_n3))*cyc_length26+(cpf11_1+cpf11_2+……cpf11_n4))*ct;……Formula 6

[0053] The parameters in Formula 6: cpf11_1, cpf11_2…cpf11_n1; cpf12_1, cpf12_2…cpf12_n2; cp13_1, cp13_2…cp13_n3; cpf14_1, cpf14_2…cpf14_n4; ct; have the same meanings as those in Formula 1.

[0054] cyc_length26 is the number of cycles required to satisfy the (t3-t5) time interval, which can be calculated by t_delay_t26>(t3-t5) (Formula 7). cyc_length26 can be calculated by Formula 6 and Formula 7:

[0055] cyc_length26>(((t3-t5) / ct)-(cpf11_1+cpf11_2+……cpf11_n1)-(cpf11_1+cpf11_2+ ……cpf11_n4)) / ((cpf12_1+cpf12_2+……cpf12_n2)+(cpf13_1+cpf13_2+……cpf13_n3)).

[0056] Step P27: Set the analog clock signal SCLK interface to a high level to prepare for transmitting the lower data;

[0057] Step P28: According to the SPI data transmission timing Figure 3 When the analog clock signal SCLK interface changes from a high level to a low level, a time interval greater than t2 is required to set the high level of the analog clock signal SCLK interface to a low level. This time interval can be implemented by calling the delay unit 28. Referring to formula 1, the time length used by the delay unit 28 is:

[0058] t_delay_t28=((cpf11_1+cpf11_2+……cpf11_n1)+((cpf12_1+cpf12_2+……cpf12_n2)+(cpf 13_1+cpf13_2+……cpf13_n3))*cyc_length28+(cpf11_1+cpf11_2+……cpf11_n4))*ct;……Formula 8

[0059] The parameters in formula 8: cpf11_1, cpf11_2…cpf11_n1; cpf12_1, cpf12_2…cpf12_n2; cp13_1, cp13_2…cp13_n3; cpf14_1, cpf14_2…cpf14_n4; ct; have the same meanings as those in formula 1.

[0060] cyc_length28 is the number of cycles required to satisfy the t2 time interval, which can be calculated by t_delay_t28>t2 (Formula 9). cyc_length28 can be calculated by Formula 8 and Formula 9:

[0061] cyc_length28>((t2 / ct)-(cpf11_1+cpf11_2+……cpf11_n1)-(cpf11_1+cpf11_2+…… cpf11_n4)) / ((cpf12_1+cpf12_2+……cpf12_n2)+(cpf13_1+cpf13_2+……cpf13_n3)).

[0062] Step P29: Determine whether the data has been sent completely. If so, go to step P210; otherwise, go to step P23.

[0063] Step P210: According to the SPI data transmission timing Figure 3 , once the data transmission ends, it is necessary to satisfy a time interval greater than t4 before pulling up the level of the analog chip select signal CS interface to an invalid level, indicating the end of this communication. Since a delay unit 28 is added before determining whether the data has been sent completely in the sending process, a time interval of t2 is obtained after executing the delay unit 28. When t2 > t4, the time interval requirement between the clock rising edge and the chip select rising edge can already be satisfied by executing the delay unit 28, and at this time, the delay unit 210 is not needed; when t2 < t4, the time interval requirement between the clock rising edge and the chip select rising edge cannot be satisfied by executing the delay unit 28, and at this time, the delay unit 210 is needed. The duration of the delay unit 210 is:

[0064] t_delay_t210 = ((cpf11_1 + cpf11_2 + …… cpf11_n1) + ((cpf12_1 + cpf12_2 + …… cpf12_n2) + (cpf13_1 + cpf13_2 + …… cpf13_n3)) * cyc_length210 + (cpf11_1 + cpf11_2 + …… cpf11_n4)) * ct; …… Formula 10

[0065] The parameters in Formula 10: cpf11_1, cpf11_2 …… cpf11_n1; cpf12_1, cpf12_2 …… cpf12_n2; cp13_1, cp13_2 …… cp13_n3; cpf14_1, cpf14_2 …… cpf14_n4; ct; have the same meanings as those referred to in Formula 1.

[0066] cyc_length210 is the number of cycles required to satisfy the (t4 - t2) time interval, which can be calculated by t_delay_t210 > (t4 - t2) (Formula 11). From Formula 10 and Formula 11, cyc_length210 can be obtained,

[0067] cyc_length210 > (((t4 - t2) / ct) - (cpf11_1 + cpf11_2 + …… cpf11_n1) - (cpf11_1 + cpf11_2 + …… cpf11_n4)) / ((cpf12_1 + cpf12_2 + …… cpf12_n2) + (cpf13_1 + cpf13_2 + …… cpf13_n3)).

[0068] P211: Set the analog chip select signal CS interface to a high level to indicate that the data transmission is completed.

[0069] Simulate SPI interface to receive data:

[0070] According to the SPI data receiving timing diagram ( Figure 5 ) and simulate SPI interface data receiving process ( Figure 4 ), the specific process is as follows:

[0071] Step P31: Based on Figure 5 , SPI data receiving timing diagram, before receiving data, the analog chip select signal CS interface level needs to be pulled down to a valid level;

[0072] Step P32: When the analog chip select signal CS is valid, before the analog clock SCLK falling edge signal, according to the SPI data transmission timing Figure 5 , a time interval of t6 is required, which can be implemented by calling the delay unit 32. Referring to formula 1, the time length used by the delay unit 32 is:

[0073] t_delay_t32=((cpf11_1+cpf11_2+……cpf11_n1)+((cpf12_1+cpf12_2+……cpf12_n2)+(cpf1 3_1+cpf13_2+……cpf13_n3))*cyc_length32+(cpf11_1+cpf11_2+……cpf11_n4))*ct;……Formula 12

[0074] The parameters in formula 2: cpf11_1, cpf11_2…cpf11_n1; cpf12_1, cpf12_2…cpf12_n2; cp13_1, cp13_2…cp13_n3; cpf14_1, cpf14_2…cpf14_n4; ct; have the same meanings as in formula 1.

[0075] cyc_length32 is the number of cycles required to satisfy the t6 time interval, which can be calculated by t_delay_t32>t6 (Formula 13). cyc_length32 can be calculated by Formula 12 and Formula 13,

[0076] cyc_length32>((t6 / ct)-(cpf11_1+cpf11_2+……cpf11_n1)-(cpf11_1+cpf11_2+…… cpf11_n4)) / ((cpf12_1+cpf12_2+……cpf12_n2)+(cpf13_1+cpf13_2+……cpf13_n3))

[0077] Step P33: setting the analog clock signal SCLK interface to a low level, indicating that the reception of one bit of data can be started;

[0078] Step P34: According to the SPI data receiving timing Figure 5 , after the falling edge of the clock, a time interval greater than t10 is required to transmit the input signal. This time interval can be implemented by calling the delay unit 34. Referring to formula 1, the time length used by the delay unit 34 is:

[0079] t_delay_t34=((cpf11_1+cpf11_2+……cpf11_n1)+((cpf12_1+cpf12_2+……cpf12_n2)+(cpf1 3_1+cpf13_2+……cpf13_n3))*cyc_length34+(cpf11_1+cpf11_2+……cpf11_n4))*ct;……Formula 14

[0080] The parameters in formula 14: cpf11_1, cpf11_2…cpf11_n1; cpf12_1, cpf12_2…cpf12_n2; cp13_1, cp13_2…cp13_n3; cpf14_1, cpf14_2…cpf14_n4; ct; have the same meanings as in formula 1.

[0081] cyc_length34 is the number of cycles required to satisfy the t10 time interval, which can be calculated by t_delay_t34>t10 (Formula 15). Cyc_length34 can be calculated by Formula 14 and Formula 15.

[0082] cyc_length34>((t10 / ct)-(cpf11_1+cpf11_2+……cpf11_n1)-(cpf11_1+cpf11_2+…… cpf11_n4)) / ((cpf12_1+cpf12_2+……cpf12_n2)+(cpf13_1+cpf13_2+……cpf13_n3)).

[0083] Step P35: Detecting the level of the analog input signal Din interface and recording the input data;

[0084] Step P36: According to the SPI data receiving timing Figure 5 After the analog input signal Din interface receives one bit of data, a time interval greater than (t8-t10) is required to set the analog clock signal SCLK interface to a high level. This time interval can be implemented by calling the delay unit 36. Referring to formula 1, the time length used by the delay unit 36 ​​is:

[0085] t_delay_t36=((cpf11_1+cpf11_2+……cpf11_n1)+((cpf12_1+cpf12_2+……cpf12_n2)+(cpf1 3_1+cpf13_2+……cpf13_n3))*cyc_length36+(cpf11_1+cpf11_2+……cpf11_n4))*ct;……Formula 16

[0086] The parameters in formula 16: cpf11_1, cpf11_2…cpf11_n1; cpf12_1, cpf12_2…cpf12_n2; cp13_1, cp13_2…cp13_n3; cpf14_1, cpf14_2…cpf14_n4; ct; have the same meanings as those in formula 1.

[0087] cyc_length36 is the number of cycles required to satisfy the (t8-t10) time interval, which can be calculated by t_delay_t36>(t8-t10) (Formula 17). From Formula 16 and Formula 17, cyc_length36 can be obtained, cyc_length36>(((t8-t10) / ct)-(cpf11_1+cpf11_2+…cpf11_n1)-(cpf11_1+cpf11_2+…cpf11_n4)) / ((cpf12_1+cpf12_2+…cpf12_n2)+(cpf13_1+cpf13_2+…cpf13_n3)).

[0088] Step P37: Set the analog clock signal SCLK interface to a high level to prepare for inputting lower-bit data;

[0089] Step P38: According to the SPI data transmission timing Figure 5 When the analog clock signal SCLK interface changes from a high level to a low level, a time interval greater than t7 is required to set the high level of the analog clock signal SCLK interface to a low level. This time interval can be implemented by calling the delay unit 38. Referring to formula 1, the time length used by the delay unit 38 is:

[0090] t_delay_t38=((cpf11_1+cpf11_2+……cpf11_n1)+((cpf12_1+cpf12_2+……cpf12_n2)+(cpf1 3_1+cpf13_2+……cpf13_n3))*cyc_length38+(cpf11_1+cpf11_2+……cpf11_n4))*ct;……Formula 18

[0091] The parameters in Formula 18: cpf11_1, cpf11_2... cpf11_n1; cpf12_1, cpf12_2... cpf12_n2; cp13_1, cp13_2... cp13_n3; cpf14_1, cpf14_2... cpf14_n4; ct; have the same meanings as those referred to in Formula 1.

[0092] cyc_length38 is the number of cycles required to satisfy the t7 time interval, which can be calculated by t_delay_t38 > t7 (Formula 19). cyc_length38 can be obtained from Formula 18 and Formula 19.

[0093] cyc_length38 > ((t7 / ct) - (cpf11_1 + cpf11_2 +... cpf11_n1) - (cpf11_1 + cpf11_2 +... cpf11_n4)) / ((cpf12_1 + cpf12_2 +... cpf12_n2) + (cpf13_1 + cpf13_2 +... cpf13_n3)).

[0094] Step P39: Determine whether the data reception is completed. If yes, go to Step P310; otherwise, go to Step P33.

[0095] Step P310: According to the SPI data sending timing Figure 5 , once the data reception ends, it needs to satisfy a time interval greater than t9 to pull up the level of the analog chip select signal CS interface to an invalid level, indicating the end of this communication. Since a delay unit 38 is added before determining whether the data is sent completely in the sending process, and the time interval of t7 is obtained after executing the delay unit 38. When t7 > t9, the time interval requirement between the clock rising edge and the chip select rising edge can already be satisfied by executing the delay unit 38, and at this time, the delay unit 310 is not needed; when t7 < t9, the time interval requirement between the clock rising edge and the chip select rising edge cannot be satisfied by executing the delay unit 38, and at this time, the delay unit 310 is needed. The duration of the delay unit 310 is:

[0096] t_delay_t310 = ((cpf11_1 + cpf11_2 +... cpf11_n1) + ((cpf12_1 + cpf12_2 +... cpf12_n2) + (cpf13_1 + cpf13_2 +... cpf13_n3)) * cyc_length310 + (cpf11_1 + cpf11_2 +... cpf11_n4)) * ct;... Formula 20

[0097] The parameters in formula 20: cpf11_1, cpf11_2…cpf11_n1; cpf12_1, cpf12_2…cpf12_n2; cp13_1, cp13_2…cp13_n3; cpf14_1, cpf14_2…cpf14_n4; ct; have the same meanings as in formula 1.

[0098] Cyc_length310 is the number of cycles required to satisfy the (t9-t7) time interval, which can be calculated by t_delay_t310>(t9-t7) (Formula 21). Cyc_length310 can be obtained by Formula 20 and Formula 21, cyc_length310>(((t9-t7) / ct)-(cpf11_1+cpf11_2+…cpf11_n1)-(cpf11_1+cpf11_2+…cpf11_n4)) / ((cpf12_1+cpf12_2+…cpf12_n2)+(cpf13_1+cpf13_2+…cpf13_n3)).

[0099] Step P311: Set the analog chip select signal CS interface to a high level to indicate that the data reception is complete.

[0100] The present invention realizes configuration of four interfaces of analog SPI communication, thereby eliminating the need to configure multiple SPI registers and reducing the complexity of configuration; the present invention is not limited to the fact that the main control chip SPI can only receive and send data in multiples of 1 byte, and the length of the received and sent data can be set according to actual communication requirements, thereby improving the flexibility of use; the present invention can flexibly configure the delay unit according to the timing requirements of the SPI communication protocol to achieve a suitable clock frequency; the present invention can break through the limitation on the number of SPI interfaces provided by the embedded microprocessor chip, and can configure the analog SPI interface according to application requirements and the number of general pins of the microprocessor chip.

[0101] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for simulating an SPI interface based on a GPIO interface, characterized in that: The method comprises the following steps: Step 1: Select 4 GPIO interfaces in the microprocessor chip to simulate the SPI interface; Step 2: Send data through the delay unit simulating the SPI interface; Step 3: Use the delay unit to simulate the SPI interface to receive data; In step 1, one GPIO interface simulates the SPI interface of the chip select signal CS; one GPIO interface simulates the SPI interface of the clock signal SCLK; one GPIO interface simulates the SPI interface of the output signal Dout; one GPIO interface simulates the SPI interface of the input signal Din; In step 1, the GPIO interface of the SPI interface for simulating the chip select signal CS is set to data output mode; the GPIO interface of the SPI interface for simulating the clock signal SCLK is set to data output mode; the GPIO interface of the SPI interface for simulating the output signal Dout is set to data output mode; the GPIO interface of the SPI interface for simulating the input signal Din is set to data input mode; Elements that need to be configured for the analog SPI interface: (1) Set the length of each data sent and received. If the SPI interface of the DSP is used, the length of the sent and received data can only be bytes or multiples of bytes due to register limitations. If the analog SPI interface is used, the length of the sent and received data can be flexibly set according to needs; (2) Initialize the analog chip select signal CS to a high level; (3) Initialize the analog clock signal SCLK to a high level, that is, the clock idle state is a high level; In step 2, sending data by simulating the SPI interface through the delay unit includes the following steps: Step P21: Pull down the SPI interface level of the analog chip select signal CS to a valid level; Step P22: after the analog chip select signal CS is valid, a time interval of t1 is required before the falling edge signal of the analog clock signal SCLK; wherein the time interval of t1 is implemented by calling a delay unit; Step P23: The SPI interface of the analog clock signal SCLK is set to a low level, indicating that the transmission of one bit of data can be started; Step P24: after the falling edge of the clock, a time interval greater than t5 is required to transmit the output signal, wherein the time interval t5 is implemented by calling a delay unit; Step P25: setting the SPI interface level of the analog output signal Dout according to the bit data to be sent; Step P26: After the SPI interface of the analog output signal Dout sends out one bit of data, the analog clock signal SCLK interface needs to be set to a high level only when a time interval greater than (t3-t5) is satisfied; wherein the time interval (t3-t5) is implemented by calling a delay unit, and t3 represents the falling edge period of the analog clock signal SCLK; Step P27: Set the SPI interface of the analog clock signal SCLK to a high level to prepare for transmitting the lower-bit data; Step P28: When the SPI interface of the analog clock signal SCLK changes from a high level to a low level, a time interval greater than t2 is required to set the high level of the SPI interface of the analog clock signal SCLK to a low level, wherein the t2 time interval is implemented by calling a delay unit, and t2 represents the rising edge period of the analog clock signal SCLK; In step 3, simulating the SPI interface to receive data through the delay unit includes the following steps: Step P31: Before receiving data, the analog chip select signal CS interface level needs to be pulled down to a valid level; Step P32: after the analog chip select signal CS is valid, a time interval of t6 is required before the falling edge signal of the analog clock signal SCLK; wherein the time interval of t6 is implemented by calling a delay unit; Step P33: setting the SPI interface of the analog clock signal SCLK to a low level, indicating that the reception of one bit of data can be started; Step P34: after the falling edge of the clock, a time interval greater than t10 is required to transmit the input signal, wherein the time interval t10 is implemented by calling a delay unit; Step P35: Detecting the level of the analog input signal Din through the SPI interface and recording the input data; Step P36: After the SPI interface of the analog input signal Din receives one bit of data, the analog clock signal SCLK interface needs to be set to a high level only when a time interval greater than (t8-t10) is satisfied, wherein the time interval (t8-t10) is implemented by calling a delay unit, and t8 represents the falling edge period of the analog clock signal SCLK; Step P37: Set the SPI interface of the analog clock signal SCLK to a high level to prepare for transmitting the lower data; Step P38: When the SPI interface of the analog clock signal SCLK changes from a high level to a low level, a time interval greater than t7 is required to set the high level of the SPI interface of the analog clock signal SCLK to a low level, wherein the t7 time interval is implemented by calling the delay unit, and t7 represents the rising edge period of the analog clock signal SCLK.

2. The method for simulating an SPI interface based on a GPIO interface according to claim 1, wherein: The delay unit is a functional unit used to adjust the frequency of the analog clock.

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