An oversampling asynchronous communication method based on FPGA logic resource delay
By implementing the oversampled asynchronous communication method on the FPGA, the problems of complexity and high cost of medium bandwidth asynchronous communication in the prior art are solved, and efficient signal transmission of bandwidth from 10Mbps to 100Mbps is achieved.
Patent Information
- Application Number
- CN202111196152.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-10-14
- Publication Date
- 2025-05-13
- Estimated Expiration
- 2041-10-14
AI Technical Summary
The existing asynchronous communication methods are complex and costly in medium bandwidth application scenarios, and it is difficult to meet the signal transmission requirements of bandwidth from 10Mbps to 100Mbps.
The oversampled asynchronous communication method based on FPGA logical resource delay is adopted. User data is stored, encoded, word bit conversion and clock insertion through the asynchronous transmission subsystem, and serial input data is received through the asynchronous reception subsystem, delay processing, sampling and bit clock extraction are performed to realize asynchronous serial communication.
It realizes efficient asynchronous serial communication in medium bandwidth application scenarios, which is suitable for signal transmission with bandwidth from 10Mbps to 100Mbps, reducing communication complexity and cost.
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Figure CN113934667B_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of power system communication, and in particular relates to an oversampling asynchronous communication method based on FPGA logic resource delay. Background Art
[0002] In the power system, various communication methods are required between systems, devices, and boards, such as Ethernet communication between systems or devices, PCIE communication between boards, USB communication between devices, low-speed RS232 or RS485 communication, etc. These communications are generally based on standard communication protocols. The bandwidth of Ethernet, PCIE, and USB communication is relatively high, ranging from hundreds of megahertz to tens of gigahertz. However, these communication methods are very complex when applied to hardware, requiring special physical layer chips and protocol stacks as well as corresponding drivers. RS232 or RS485 hardware is relatively simple and easy to design, but the bandwidth is only Kbps to 1-20Mbps, which is limited.
[0003] Therefore, there is a need for an asynchronous serial communication method that can be applied to application scenarios with few hardware devices, bandwidth ranging from 10Mbps to 100Mbps, and suitable for medium bandwidth without being very complex. Summary of the invention
[0004] The purpose of the present invention is to provide an oversampling asynchronous communication method based on FPGA logic resource delay, thereby solving the shortcomings of the existing asynchronous communication that is complicated and troublesome.
[0005] To achieve the above object, the present invention provides an oversampling asynchronous communication method based on FPGA logic resource delay, comprising the following steps:
[0006] Writing the user data to be sent into the asynchronous transmission subsystem in the oversampling asynchronous communication system according to the set timing, wherein the oversampling asynchronous communication system is an oversampling asynchronous communication system based on FPGA, and the asynchronous transmission subsystem stores the user data and determines whether the user data contains data, and outputs an idle code if there is no data; on the contrary, if there is data, the user data is encoded in a data frame format, word-bit conversion is performed on the encoded data, and clock insertion is performed on the data after word-bit conversion, and the data after clock insertion is output according to different output interface modes;
[0007] Serial input data is input into an asynchronous receiving subsystem in an oversampling asynchronous communication system through different input interfaces. The asynchronous receiving subsystem performs an OR operation on the serial input data for a specified product term to obtain a delayed signal, outputs a sampling value of the delayed signal through a register array, extracts a bit clock from the sampling value, converts the extracted serial data into a word data stream, and divides the data stream into data frames, thereby completing the reception of the serial input data.
[0008] Preferably, during the process of receiving data, the asynchronous receiving subsystem calculates the CRC in the received data in real time to determine whether there is an error in the data frame of the serial input data.
[0009] Preferably, the asynchronous sending subsystem stores the user data and sends out an empty signal, and determines whether the user data contains data through the empty signal.
[0010] Preferably, the asynchronous sending subsystem encodes the user data in a data frame format including the following steps:
[0011] Setting a sending rule of the data frame;
[0012] The frame header is sent in the first word clock cycle;
[0013] Reading the user data from the stored data in the second word clock cycle, first setting the initial level of the second word clock cycle to a high level, and then reading subsequent word clock cycles in sequence until all the user data are read;
[0014] Calculate the CRC value of all data in real time from reading the frame header to the last user data;
[0015] Send idle code after calculating the last CRC value;
[0016] The frame header, user data, CRC value, and idle code are combined in sequence to obtain encoded data.
[0017] Preferably, the asynchronous transmission subsystem performs word-bit conversion on the encoded data including the following steps:
[0018] The data frame value of each word clock cycle is read, and the data frame value of each word clock cycle is clock-shifted in sequence in a phase-high-to-low manner, and the data after word-bit conversion is output in sequence.
[0019] Preferably, the clock is inserted into the data after the clock is loaded into the word-bit conversion using a dual-phase output rule.
[0020] Preferably, the different output interfaces include: TTL, LVDS or optical fiber driver.
[0021] Preferably, the serial input data is subjected to an OR operation on a designated product term through a logic delay matrix to obtain a delayed signal.
[0022] Preferably, the bit clock extraction includes performing bit width testing and data recovery on the sampled values.
[0023] Preferably, the asynchronous transmission subsystem comprises a FIFO, an encoding module, a word-bit conversion module and a clock insertion module which are connected in sequence.
[0024] Preferably, the asynchronous receiving subsystem comprises a once-connected logic delay array, a sampling register array, a bit clock extraction array, a word extraction module and a receiving frame module.
[0025] Preferably, the asynchronous transmitting subsystem and the asynchronous receiving subsystem belong to the same oversampling asynchronous communication system.
[0026] Preferably, the asynchronous transmitting subsystem and the asynchronous receiving subsystem do not belong to the same oversampling asynchronous communication system.
[0027] Compared with the existing technology, the present invention has the following beneficial effects:
[0028] The oversampling asynchronous communication method based on FPGA logic resource delay provided by the present invention stores the user data to be sent through the asynchronous sending subsystem in the sampling asynchronous communication system, and determines whether the user data contains data. If there is no data, an idle code is output; on the contrary, if there is data, the user data is encoded in a data frame format, the encoded data is converted into word bits, and the clock is inserted into the data after the word bit conversion, and the data after the clock insertion is output to different interfaces according to different output interface modes. At the same time, the asynchronous receiving subsystem in the sampling asynchronous communication system can receive serial input data of different interfaces, complete the OR operation of the specified product term on the serial input data to obtain a delayed signal, output the sampled value of the delayed signal through the register array, extract the bit clock of the sampled value, convert the extracted serial data into a word data stream, and divide the data stream into data frames, so as to complete the reception of the serial input data, thereby realizing asynchronous serial communication, which is suitable for signal transmission with a bandwidth from 10Mbps to 100Mbps, and is very suitable for medium bandwidth and not very complex application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only one embodiment of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0030] Figure 1 It is a block diagram of an oversampling asynchronous communication system based on FPGA logic resource delay of the present invention;
[0031] Figure 2 is a schematic diagram of a data frame format according to one embodiment of the present invention;
[0032] Figure 3 is a diagram of sending bi-phase data according to one embodiment of the present invention;
[0033] Figure 4 is a schematic diagram of a logic delay array according to one embodiment of the present invention;
[0034] Figure 5 is a delay timing diagram of one embodiment of the present invention;
[0035] Figure 6 is a sampling position acquisition timing diagram of one embodiment of the present invention;
[0036] Figure 7 is a diagram of bit clock extraction in one embodiment of the present invention;
[0037] Figure 8 is a received data phase determination truth table of one embodiment of the present invention;
[0038] Fig. 9 is a phase timing diagram of receiving data in one embodiment of the present invention;
[0039] Fig.10 is a frame header search diagram of one embodiment of the present invention;
[0040] Fig.11 It is a timing diagram of receiving user data frames according to one embodiment of the present invention. DETAILED DESCRIPTION
[0041] The following is a clear and complete description of the technical solutions in the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0042] The oversampling asynchronous communication method based on FPGA logic resource delay provided by the present invention includes:
[0043] S1, writing the user data to be sent into the asynchronous transmission subsystem in the oversampling asynchronous communication system according to the set timing, wherein the oversampling asynchronous communication system is an asynchronous transmission subsystem based on FPGA, and the asynchronous transmission subsystem stores the user data and determines whether the user data contains data, and outputs an idle code if there is no data; otherwise, if there is data, the user data is encoded in a data frame format, word-bit conversion is performed on the encoded data, and clock insertion is performed on the data after word-bit conversion, and the data after clock insertion is output according to different output interface modes;
[0044] S2. The serial input data is input into the asynchronous receiving subsystem through different input interfaces. The asynchronous receiving subsystem performs an OR operation on the specified product terms on the serial input data to obtain a delayed signal, outputs a sampling value of the delayed signal through a register array, extracts the bit clock of the sampling value, converts the extracted serial data into a word data stream, and divides the data stream into data frames, thereby completing the reception of the serial input data.
[0045] The above-mentioned oversampling asynchronous communication method based on FPGA logic resource delay stores the user data to be sent through the asynchronous sending subsystem in the sampling asynchronous communication system, and determines whether the user data contains data. If there is no data, an idle code is output; on the contrary, if there is data, the user data is encoded in a data frame format, the encoded data is converted into word bits, and the clock is inserted into the data after the word bit conversion, and the data after the clock insertion is output to different interfaces according to different output interface modes. At the same time, the asynchronous receiving subsystem in the sampling asynchronous communication system can receive serial input data of different interfaces, complete the OR operation of the specified product term on the serial input data to obtain a delayed signal, output the sampled value of the delayed signal through the register array, extract the bit clock of the sampled value, convert the extracted serial data into a word data stream, and divide the data stream into data frames, so as to complete the reception of the serial input data, thereby realizing asynchronous serial communication, which is suitable for signal transmission with a bandwidth from 10Mbps to 100Mbps, and is very suitable for medium bandwidth and not very complex application scenarios.
[0046] In one of the embodiments, the asynchronous receiving subsystem calculates the CRC in the received data in real time during the data receiving process to determine whether there is an error in the data frame of the serial input data.
[0047] In one embodiment, the oversampling asynchronous communication system includes: different output interfaces, an asynchronous transmission subsystem, a PLL, an asynchronous reception subsystem, and different input interfaces connected in sequence.
[0048] The different output interfaces include: TTL, LVDS or optical fiber driver.
[0049] The asynchronous transmission subsystem includes a FIFO, an encoding module, a word-bit conversion module and a clock insertion module which are connected in sequence.
[0050] The PLL is a universal clock frequency multiplier, and the output clock can be set according to the required clock frequency. It can be a PLL inside the FPGA or an external PLL.
[0051] The asynchronous receiving subsystem includes a once-connected logic delay array, a sampling register array, a bit clock extraction array, a word extraction module and a receiving frame module.
[0052] The different input interfaces include: a TTL receiver, a LVDS receiver and a fiber optic receiver.
[0053] When the asynchronous transmitting subsystem and the asynchronous receiving subsystem are different boards in the same system, they can be paired with a TTL driver and a TTL receiver, or a LVDS driver and a LVDS receiver; when the asynchronous transmitting subsystem and the asynchronous receiving subsystem are two independent devices or systems, they can be paired with an LVDS driver and a LVDS receiver, or a fiber optic driver or a fiber optic receiver.
[0054] The above-mentioned oversampling asynchronous communication system uses fewer hardware devices and can reduce the cost of asynchronous communication.
[0055] In one of the embodiments, in step S1, the FIFO of the asynchronous sending subsystem stores the user data and sends out an empty signal, and determines whether the user data contains data through the empty signal.
[0056] Specifically, when the empty signal is at a high level, the data frame has no data, that is, the time sequence has no data; when the empty signal is at a low level, the data frame has data, that is, the time sequence has data.
[0057] In one embodiment, in step S1, the encoding module in the asynchronous transmission subsystem encodes the user data in a data frame format, including the following steps:
[0058] Setting the sending rule of the data frame; specifically, sending rule package: sending according to the word clock cycle, with 16 clock cycles between each byte (word);
[0059] The frame header is sent in the first word clock cycle;
[0060] Reading the user data from the stored data in the second word clock cycle, first setting the initial level of the second word clock cycle to a high level, and then reading subsequent word clock cycles in sequence until all the user data are read;
[0061] Calculate the CRC value of all data in real time from reading the frame header to the last user data;
[0062] Send idle code after calculating the last CRC value;
[0063] The frame header, user data, CRC value, and idle code are combined in sequence to obtain encoded data.
[0064] In one embodiment, in step S1, the word-to-bit conversion module in the asynchronous transmission subsystem performs word-to-bit conversion on the encoded data, including the following steps:
[0065] The data frame value of each word clock cycle is read, and the data frame value of each word clock cycle is clock-shifted in sequence in a phase-high-to-low manner, and the data after word-bit conversion is output in sequence.
[0066] In one embodiment, in step S1, the clock is inserted into the data after the clock is loaded into the word-bit conversion using a dual-phase output rule.
[0067] Specifically, the following steps are included:
[0068] When the data after word bit conversion is in high phase, the output data is the data after word bit conversion with a phase of positive 180 degrees, that is, the phase changes from low level to high level;
[0069] When the data after word bit conversion is in low phase, the output data is the data after word bit conversion with a phase of negative 180 degrees, that is, the phase changes from high level to low level;
[0070] Regardless of whether the data after word-free bit conversion is high or low, or normally high or normally low, there will always be data transitions on the data after the clock is inserted. The maximum frequency of the transition is two clocks, and the minimum frequency is one clock, that is, the clock on the sending side is loaded into the sending data.
[0071] In one embodiment, in step S2, the serial input data is subjected to an OR operation on a designated product term through a logic delay matrix to obtain a delayed signal.
[0072] Specifically, the logic delay array includes a plurality of lookup tables LUT of logic resources, and the lookup tables LUT of logic resources are connected in series one by one, and are composed of 32 groups of lookup table LUT groups in total, and each lookup table LUT group is composed of 2 independent lookup table LUTs adjacent to each other in physical positions. The lookup table LUT is the basic component unit of the internal logic resources of the FPGA, and can be used as any function generator with multiple inputs or one input and one output. Each group of lookup table LUT is configured as a direct output equal to input mode.
[0073] The physical placement method of the lookup table LUT inside the FPGA is that the first group of lookup tables must be placed closest to the serial input data, and each lookup table LUT position is placed using an absolute physical position constraint.
[0074] The delay of one LUT is 500ps, the delay of two LUTs as a group is 1ns, and the total delay of 32 LUTs is 32ns. Therefore, when the data time period of the serial input data is 20ns, the 32 LUTs can always find the corresponding sampling position.
[0075] In one of the embodiments, in step S2, the bit clock extraction includes performing a bit width test and data recovery on the sampled value.
[0076] The embodiment of the oversampling asynchronous communication method based on FPGA logic resource delay of the present invention is described in detail so that those skilled in the art can better understand the present invention:
[0077] In the oversampling asynchronous communication method based on FPGA logic resource delay and the oversampling asynchronous communication system: the bandwidth of sending serial data TX_SER_DRV is defined as TX_SER_DW, the unit is Mbps, and the sending clock frequency value of twice the clock TX_2X_CLK is equal to the value of TX_SER_DW, that is, TX_SER_DW is 100Mbps, then TX_2X_CLK is 100MHZ, so the frequency of TX_1X_CLK is half of TX_2X_CLK, that is, 50MHZ.
[0078] The bandwidth of the received serial data RX_SER_RCV is defined as RX_SER_DW, with a unit of 100Mbps. The receive clock RX_CLK is equal to the input data bandwidth, that is, 100MHZ.
[0079] like Figure 1 As shown, an oversampling asynchronous communication method based on FPGA logic resource delay specifically includes the following steps:
[0080] Step 100, the user writes the data to be sent into the FIFO according to a certain timing. When the written data signal TX_DVLD is at a high level, the timing data TX_DATA[15:0] data will be written into the transmit FIFO in the form of a user data frame with a fixed frame length of TX_LEN; and the FIFO outputs an empty signal TX_FIFO_EMPTY, which indicates whether there is data. If TX_FIFO_EMPTY is at a high level, there is no data, and if TX_FIFO_EMPTY is at a low level, there is data, which is used for subsequent modules to read out data; when TX_DVLD is at a low level, no data is written.
[0081] Step 110, the encoding module is used to send the user data according to a certain data frame format, as shown in the following example: Figure 2 As shown, a frame of data includes: frame header, user data, CRC field, and idle code. The frame header is defined as hexadecimal 0X0564, the CRC field is the CRC value calculated by the frame header and user data, the CRC field is 2 bytes, and the idle code is a constant value of 0XFFFF when no data is sent. The encoding module sends 16 bits at a time, that is, according to the word clock cycle, and the interval between each word is 16 TX_1X_CLK clock cycles (one clock cycle). Specifically, the following steps are included:
[0082] Step 111, when the encoding module obtains TX_FIFO_EMPTY as low, it means that there is user data to be sent. First, the encoding module sends the frame header 0X0564 in the first word clock cycle, indicating the beginning of a frame of data. The frame header word 0X0564 is output to TX_WORD_DOU, and the encoding module's TX_WORD_DVLD is set high;
[0083] Step 112, starting from the second word clock cycle, user data is read out from the transmit FIFO, the initial level TX_RD of the second word clock is first set to a high level, and then the remaining user data is read out in subsequent word clock cycles, with a total length of TX_LEN.
[0084] Step 113, starting from the frame header 0X0564 to the end of the last user data, calculate the CRC value of all data in real time, and output the CRC value to TX_WORD_DOU in the last word clock cycle.
[0085] Step 114, when the data output of a frame is completed, TX_WORD_DOU is set to 0XFFFF.
[0086] Step 115, sequentially combine the frame header, user data, CRC value, and idle code to obtain the encoded data TX_WORD_DOU.
[0087] Step 120, the word bit conversion module reads the encoded data TX_WORD_DOU value according to the TX_WORD_DLVD of the encoding module in each word clock cycle, and performs each TX_1X_CLK clock shift operation in sequence according to the high phase first and the lowest phase last method, and shifts the TX_WORD_DOU value in sequence according to the TX_1X_CLK clock shift and outputs it to TX_WORD2BIT_OUT.
[0088] Step 130, such as Figure 3 As shown, in the clock insertion module, TX_2X_CLK is twice the TX_1X_CLK clock, and the output data TX_SER_DRV of the clock insertion module is output in two phases according to the two-phase output rule. Specifically, the two-phase output rule includes: when TX_WORD2BIT_OUT is in a high phase, the phase of the output data TX_SER_DRV of the clock insertion module is positive 180 degrees, that is, from low to high; when TX_WORD2BIT_OUT is in a low phase, the phase of the output data TX_SER_DRV of the clock insertion module is negative 180 degrees, that is, from high to low. Therefore, no matter whether the TX_WORD2BIT_OUT data is high or low, or always high or low, there will always be data jumps on TX_SER_DRV, and the maximum frequency of the jump is TX_2X_CLK, and the minimum frequency is TX_1X_CLK, that is, the clock of the transmitting side is loaded into the transmitted data.
[0089] Step 140, the output data TX_SER_DRV of the clock insertion module is output to the TTL, LVDS or optical fiber driver, that is, the data transmission is completed.
[0090] Step 150, the serial data first enters the TTL, LVDS or fiber optic receiver, completes the conversion of the physical signal, and outputs the serial input data RX_SER_RCV signal, which enters the logic delay array.
[0091] Step 160, such as Figure 4As shown, the serial input data RX_SER_RCV signal enters the logic delay array, which is composed of a number of lookup tables LUT of logic resources. The lookup tables LUT of logic resources are connected in series one by one, and are composed of 32 groups of lookup table LUT groups in total. Each lookup table LUT group consists of 2 independent lookup table LUTs adjacent to each other in physical positions. The lookup table LUT is the basic component unit of the internal logic resources of the FPGA, and can be used as any function generator with multiple inputs or one input and one output. The serial input data RX_SER_RCV enters the first group of lookup tables, and the output signal RX_SER_DLY0 of the first group of lookup tables is connected to the second group of lookup tables in sequence, and the output signal RX_SER_DLY31 of the last group of lookup tables is connected in sequence, and the output signal RX_SER_DLY0--31 of each group of lookup tables is output to the sampling register array. Each group of lookup table LUT is configured to directly output equal to the input mode.
[0092] Step 161, the physical placement method of the lookup table LUT inside the FPGA is that the first group of lookup tables must be placed at the nearest position close to the RX_SER_RCV input signal, and each lookup table LUT position is placed in an absolute physical position constraint manner. The first LUT of the first group of lookup tables is placed at the position of LOC_X0Y0, and the second LUT of the first group of lookup tables is placed at LOC_X1Y0; the second group of lookup tables must be placed at the position of LOC_X0Y1, and the subsequent groups of lookup tables are placed in sequence, and the last group of lookup tables is placed at the position of LOC_X1Y31.
[0093] Step 162, such as Figure 5 As shown, generally, the delay of a lookup table LUT is 500ps, the delay of two lookup tables LUT as a group is 1ns, and the total delay of 32 groups of lookup tables LUT is 32ns; according to the method of step 161, the output delay of each group of lookup tables is RX_SER_DLY0 is 1ns, RX_SER_DLY1 is 2ns, and the last one RX_SER_DLY31 is 32ns; when the data time period of the input signal is 20ns, the 32 groups of lookup tables LUT can always find the corresponding sampling position, thereby obtaining the delayed signal RX_SER_DLY0--31.
[0094] Step 170, such as Figure 6 As shown, the signal RX_SER_DLY0--31 after delay through 32 groups of lookup tables enters the sampling register array, which includes 32 D flip-flops, which respectively sample the delayed signals obtained from the above 32 groups of lookup tables at the rising edge of the receiving clock RX_CLK, and output 32 sampling values RX_SER_Q0--31.
[0095] Assume that the phase of the input serial data RX_SER_RVC signal and RX_CLK is 0, that is, they jump at the same time. After the delay of step 160, the output of clock edge 2 is RX_SER_Q0--8 are all high level, and the other outputs RX_SER_Q10--31 are all low level. Therefore, the pulse width value is from the first high level (RX_SER_Q0) to the next low level (RX_SER_Q9). Since the delay value of each set of lookup tables is 1ns, the pulse width value of the signal after the delay is tested to be 10ns;
[0096] Step 180, 32 sample values RX_SER_Q0--31 enter the bit clock extraction module, such as Figure 7 As shown, the bit clock extraction module includes a bit width test module and a data recovery module. RX_SER_Q0--31 first enters the bit width test module. The width test module analyzes that the pulse width value from the first high level (RX_SER_Q0) to the next low level (RX_SER_Q9) is a pulse width value. Since the delay value of each set of lookup tables is 1ns, the pulse width value tested is 10ns; and the middle value from the first high level (RX_SER_Q0) to the next low level (RX_SER_Q9) is the stable point of sampling, that is, the stable point can meet the setup time and hold time requirements of sampling, so the stable value is RX_SER_Q5, and the stable value is output to the stable sampling signal RX_SER_QMUX through a multiplexer.
[0097] Step 181, after determining the stable sampling signal RX_SER_QMUX, the stable sampling signal is sent to the data recovery module. The data recovery module samples the RX_SER_QMUX signal for each RX_CLK clock, and combines the previous clock sampling value with the current clock sampling value to obtain a phase truth table, such as Figure 8 When the phase is positive 180 degrees, the data recovery module outputs the sampled signal RX_SER_SAMPLE_OUT after serial data recovery as logic high, and when the phase is negative 180 degrees, the output is logic low. If there is no change, it is maintained, and a data valid signal RX_SER_CLKEN is output every two RX_CLK clocks to indicate that the RX_SER_SAMPLE_OUT signal is valid, as shown in the figure. Fig. 9 shown.
[0098] Step 182, the sampled signal RX_SER_SAMPLE_OUT and the valid signal RX_SER_CLKEN after serial data recovery enter the word extraction module, which includes 16 D flip-flops. The input of the first D flip-flop is connected to RX_SER_SAMPLE_OUT, and the output of the first D flip-flop is connected to the input of the second D flip-flop. Subsequent D flip-flops are connected in sequence and shifted and output at each pulse of RX_SER_CLKEN to form a 16-bit shift register RX_SER_SHT[15:0]; each time the shift register receives a valid signal RX_SER_CLKEN, the counter RX_SER_CNT is increased by 1, the counter RX_SER_CNT is 4 bits, and the count value is from 0 to 15; at each valid signal RX_SER_CLKEN, the shift register R is judged. Whether X_SER_SHT[15:0] is equal to the frame header word 0X0564 in step 101, when the shift register RX_SER_SHT[15:0] is equal to the frame header 0X0564, the RX_SER_CNT value at the current moment is recorded and defined as RX_SER_CNT_HD; starting from obtaining the frame header 0X0564, every 16 valid signals RX_SER_CLKEN count cycles, when RX_SER_CNT in the counting cycle is equal to RX_SER_CNT_HD, the shift register RX_SER_SHT[15:0] outputs data RX_DATA_WORD[15:0], and when RX_SER_CNT is equal to RX_SER_CNT_HD, the output word data stream RX_DVLD_WORD is high inductance, and remains low at other times; That is, the word extraction module checks the frame header of the sampled signal RX_SER_SAMPLE_OUT after the serial data is restored in real time, accurately extracts the word segmentation in the bit stream data, and ensures that the bit data stream is converted into a word data stream, such as Fig.10 .
[0099] Step 183, as Fig.11As shown, the receiving framing module divides the word data stream into user frame data. When the word data stream RX_DVLD_WORD is high and the word data stream RX_DATA_WORD[15:0] is 0X0564, the output frame start signal RX_SOF is high. After the frame start signal RX_SOF starts, each word data stream RX_DLVD_WORD is incremented by 1 through the user data frame counter RX_DATA_CNT until the user data frame counter RX_DATA_CNT is equal to the total length TX_LEN of step 102, and the reception of the serial input data is completed. Starting from 0X0564, each word data stream RX_DATA_WORD is continuously output to the output data RX_DATA, and RX_DLVD is set high from the frame start signal RX_SOF until RX_DATA_CNT is equal to the total length TX_LEN, which is low. When RX_DATA_CNT is equal to the total length TX_LEN, the output frame end signal RX_EOF is high, indicating that a frame of data has ended, and the reception of the serial input data is completed.
[0100] During the entire data receiving process, the received data CRC is calculated in real time to confirm whether the user data is correct, and the RX_CRC value is output to indicate whether the user data frame has an error.
[0101] In summary, the present invention provides an oversampling asynchronous communication method based on FPGA logic resource delay, which can be transmitted with a simple oversampling asynchronous communication system, and is very easy to perform asynchronous communication between systems, devices, and boards.
[0102] What is disclosed above is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or modifications within the technical scope disclosed in the present invention, which should be covered within the protection scope of the present invention.
Claims
1. An oversampling asynchronous communication method based on FPGA logic resource delay, characterized in that: The following steps are involved: Writing the user data to be sent into the asynchronous transmission subsystem in the oversampling asynchronous communication system according to the set timing, wherein the oversampling asynchronous communication system is an oversampling asynchronous communication system based on FPGA, and the asynchronous transmission subsystem stores the user data and determines whether the user data contains data, and outputs an idle code if there is no data; On the contrary, if there is data, the user data is encoded in a data frame format, the encoded data is subjected to word-bit conversion, and clock insertion is performed on the data after word-bit conversion, and the data after clock insertion is output according to different output interface modes; The serial input data is input into an asynchronous receiving subsystem in an oversampling asynchronous communication system through different input interfaces, the asynchronous receiving subsystem performs an OR operation on the serial input data for a specified product term to obtain a delayed signal, outputs a sample value of the delayed signal through a register array, extracts a bit clock from the sample value, converts the extracted serial data into a word data stream, and divides the data stream into data frames, thereby completing the reception of the serial input data; The clock insertion adopts a dual-phase output rule to load the clock into the data after the word-bit conversion, including the following steps: When the data after word bit conversion is in high phase, the output data is the data after word bit conversion with a phase of positive 180 degrees, that is, the phase changes from low level to high level; When the data after word bit conversion is in low phase, the output data is the data after word bit conversion with a phase of negative 180 degrees, that is, the phase changes from high level to low level; No matter whether the data after word bit conversion is high or low, or always high or always low, there will always be data jumps on the data after clock insertion. The maximum frequency of jumps is two clocks, and the minimum frequency is one clock, that is, the clock of the sending side is loaded into the sending data; The asynchronous receiving subsystem calculates the CRC in the received data in real time during the data receiving process to determine whether there is an error in the data frame of the serial input data; The asynchronous transmission subsystem encodes the user data in a data frame format, comprising the following steps: Setting a sending rule of the data frame; The frame header is sent in the first word clock cycle; Reading the user data from the stored data in the second word clock cycle, first setting the initial level of the second word clock cycle to a high level, and then reading subsequent word clock cycles in sequence until all the user data are read; Calculate the CRC value of all data in real time from reading the frame header to the last user data; Send idle code after calculating the last CRC value; Combining the frame header, user data, CRC value, and idle code in sequence to obtain encoded data; The serial input data is subjected to an OR operation on a designated product term through a logic delay matrix to obtain a delayed signal.
2. The oversampling asynchronous communication method based on FPGA logic resource delay according to claim 1, characterized in that: The asynchronous sending subsystem stores the user data and sends out an empty signal, and determines whether the user data contains data through the empty signal.
3. The oversampling asynchronous communication method based on FPGA logic resource delay according to claim 1, characterized in that: The asynchronous transmission subsystem performs word-bit conversion on the encoded data, comprising the following steps: The data frame value of each word clock cycle is read, and the data frame value of each word clock cycle is clock-shifted in sequence in a phase-high-to-low manner, and the data after word-bit conversion is output in sequence.
4. The oversampling asynchronous communication method based on FPGA logic resource delay according to claim 1, characterized in that: The different output interfaces include: TTL, LVDS or optical fiber driver.
5. The oversampling asynchronous communication method based on FPGA logic resource delay according to claim 1, characterized in that: The bit clock extraction includes performing bit width testing and data recovery on the sampled values.
6. The oversampling asynchronous communication method based on FPGA logic resource delay according to claim 1, characterized in that: The asynchronous transmission subsystem includes a FIFO, an encoding module, a word-bit conversion module and a clock insertion module which are connected in sequence.
Citation Information
Patent Citations
IP core for achieving ASI interface function based on FPGA resources
CN112749119A