Mask synthesis using design directed biasing

Abstract

Aspects described herein relate to mask synthesis using design guided biasing. Based on a design of an integrated circuit, a target shape is obtained on an image surface to be manufactured using a mask. Rays are generated emanating from respective anchor points. The anchor points are on a boundary of the target shape or on a boundary of a mask shape of the mask. For each of the rays, a distance is defined between a first intersection of the respective ray with the boundary of the target shape and a second intersection of the respective ray with the boundary of the mask shape. An analysis is performed by one or more processors, wherein the analysis is configured to modify the distance based on an error between the target shape and a resulting shape simulated on the image surface caused by the mask shape.

Description

Technical Field

[0001] This disclosure relates to mask synthesis from integrated circuit designs, and more specifically, to mask synthesis using design-guided offsets. Background Technology

[0002] In recent years, with the increasing complexity of masks, the ability to synthesize and manufacture curved masks has improved, in contrast to traditional linear mask shapes. These curved mask shapes place new demands on the geometry processing algorithms within the mask synthesis process, as the mask optimization step requires the evolution of more complex shapes. Summary of the Invention

[0003] Some aspects of this disclosure relate to a method for circuit design. The method generally includes: based on an integrated circuit design, obtaining a target shape on an image surface to be manufactured using a mask; generating rays emanating from corresponding anchor points located on the boundary of the target shape or the boundary of a mask shape of the mask; for each ray, defining a distance between a first intersection point of the corresponding ray with the boundary of the target shape and a second intersection point of the corresponding ray with the boundary of the mask shape; modifying the distances by one or more processors based on an error between the target shape and the resulting shape simulated on the image surface by the mask shape; and generating a mask design for a mask to be used to manufacture the target shape on the image surface based on the modified distances.

[0004] Some aspects of this disclosure relate to an apparatus for circuit design. The apparatus generally includes a memory and one or more processors coupled to the memory. The memory and the one or more processors are configured to: based on an integrated circuit design, obtain a target shape on an image surface to be manufactured using a mask; generate rays emanating from corresponding anchor points located on the boundary of the target shape or the boundary of a mask shape of the mask; for each ray, define a distance between a first intersection point of the corresponding ray with the boundary of the target shape and a second intersection point of the corresponding ray with the boundary of the mask shape; and perform analysis by the one or more processors, the analysis being configured to modify the distances based on the error between the target shape and the resulting shape simulated on the image surface by the mask shape.

[0005] Some aspects of this disclosure relate to a non-transitory computer-readable medium including executable instructions that, when executed by one or more processors of the apparatus, cause the apparatus to:, based on an integrated circuit design, obtain a target shape on an image surface to be manufactured using a mask; generate rays emanating from corresponding anchor points located on the boundary of the target shape or the boundary of a mask shape of the mask; define, for each ray, a distance between a first intersection point of the corresponding ray with the boundary of the target shape and a second intersection point of the corresponding ray with the boundary of the mask shape; and perform an analysis by the one or more processors configured to modify the distances based on an error between the target shape and a resulting shape simulated on the image surface by the mask shape.

[0006] Other aspects include: an apparatus that is operable, configured, or otherwise suited to perform the methods described above and elsewhere herein; a non-transitory computer-readable medium having instructions that, when executed by one or more processors of the apparatus, cause the apparatus to perform the methods described above and elsewhere herein; a computer program product embodied on a computer-readable storage medium including code for performing the methods described above and elsewhere herein; and an apparatus having components for performing the methods described above and elsewhere herein. For example, the apparatus may include: a processing system, a device having a processing system, or a processing system cooperating over one or more networks.

[0007] For illustrative purposes, the following description and accompanying figures illustrate certain features. Attached Figure Description

[0008] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of the examples described herein. The drawings are intended to provide knowledge and understanding of the examples described herein and are not intended to limit the scope of this disclosure to those particular examples. Furthermore, the drawings are not necessarily drawn to scale.

[0009] Figure 1 This is a flowchart of a method for mask synthesis using design-guided offsets, based on some examples of this disclosure.

[0010] Figure 2 Examples of illustrations according to this disclosure are depicted. Figure 1 The layout of the mask synthesis method.

[0011] Figure 3 Customized, proprietary region boundaries are shown as some examples according to this disclosure.

[0012] Figure 4 Rays emanating from anchor points on a mask are shown in some examples according to this disclosure.

[0013] Figure 5 The present disclosure depicts some examples of layouts for illustrating negative distances for rays.

[0014] Figure 6 Examples of illustrations according to this disclosure are depicted. Figure 5 The layout of the mask shape formed after the degenerate part is removed.

[0015] Figure 7 The layout of aspects for illustrating obtaining a mask shape with Manhattan edges and / or straight edges is depicted according to some examples of this disclosure.

[0016] Figure 8 This illustrates the self-defined boundary of the area formed in the space between the design objective and another design objective.

[0017] Figure 9 Flowcharts depict various processes used during the design and manufacture of integrated circuits, according to some examples of this disclosure.

[0018] Figure 10 A diagram of an example computer system is depicted, in which the examples of this disclosure can be operated. Detailed Implementation

[0019] The aspects described herein relate to mask synthesis using design-guided offsets. This disclosure describes a method for tracking mask evolution that encapsulates a more typical optical proximity correction (OPC) technique, segmented from a given wafer design target / purpose offset. Optical proximity correction (OPC) is a lithographic enhancement technique used to compensate for image errors caused by diffraction or process effects. In some aspects, a data structure of rays emanating from anchor points (e.g., edges and corners of the design target) is used, and for each ray, the distance between the intersection of the ray with the boundary of the mask shape and the intersection of the ray with the boundary of the design target is tracked. Methods using these distances are introduced that have the benefit of a correspondence between the design target and mask positions without using the same edge orientation for the mask and design edges, thus allowing for a curved solution that yields better lithographic quality (QOR) results.

[0020] Various methods for curve mask evolution may involve using pixel-based approaches (such as level sets). These methods are computationally more intensive than the aspects disclosed herein and may suffer from inconsistencies related to shift variance. Other methods may include free-form point tracking methods for points on polygon edges. These methods are computationally difficult, have difficulty creating point intersections of illegal or undefined shapes, and may lose the connectivity between the mask and the design edges, a characteristic typically required for OPC operations.

[0021] Methods for typical OPC mask shape tracking are used across multiple mask synthesis applications, including but not limited to rule-based OPC, model-based OPC, rule-based retargeting, and model-based etch retargeting correction. Curved versions of these applications can be implemented using the methods described in this disclosure.

[0022] For rule-based OPC, this method constructs a set of geometric rules that determine modifications to the mask design. For example, geometric quantities such as pattern density, polygon side lengths, and distances from sub-parts of edges to corner vertices can be measured. The constructed rule table or function takes these various geometric quantities as input and outputs the amounts by which the design should be locally modified. Modifications can be specified by defining edge or sub-edge perturbations or other geometric manipulations in the normal direction of the polygon boundaries. These aspects can be used as algorithms to perform polygon operations to create rule-based curve mask polygons.

[0023] For model-based OPC, mask creation is similar to that of rule-based OPC, except that the method used to determine the amount of polygon manipulation is determined by model simulation feedback (such as wafer positioning errors or other wafer-level image signatures). Various aspects can be used as algorithms to manipulate a given input polygon to create a corrected mask polygon. Typically, model-based OPC will have an iterative process that can recalibrate the same polygon by taking into account further model-based feedback from previous iterations of polygon movement.

[0024] Rule-based redirection methods are similar to rule-based OPC, except that the output polygon shape is used as the input wafer target for subsequent lithography correction algorithms, such as OPC or Inverse Lithography (ILT). Therefore, the contents of the rule table or function can have different purposes, but the process of determining geometric measurements, assigning geometric changes to various parts of the design, and modifying the design is similar to rule-based OPC.

[0025] Similarly, etching models are often used to modify design targets to produce wafer targets for lithographic correction algorithms (e.g., OPC or ILT). Various embodiments can be used as algorithms to manipulate input design targets to produce wafer targets.

[0026] The various features are described below with reference to the accompanying drawings. It should be noted that these drawings may be drawn to scale or not, and throughout the drawings, elements with similar structures or functions are indicated by the same reference numerals. It should be noted that the drawings are intended only to facilitate the description of features. They are not intended as an exhaustive description of the claimed subject matter or as a limitation on the scope of the claimed subject matter. Furthermore, the illustrated examples do not need to possess all the aspects or advantages shown. Aspects or advantages described in conjunction with a particular example are not necessarily limited to that example and can be practiced in any other example, even if not so stated or so explicitly described. Additionally, the methods described herein may be described in a particular order of operation, but other methods according to other examples may be implemented in various other orders with more or fewer operations (e.g., including different serial or parallel performances of various operations).

[0027] Furthermore, this document uses various terms as used in the art. For example, as used in the art and as understood by one of ordinary skill in the art, “optimization,” “optimize,” and “optimizing” refer to a mathematical formulation of a problem to select some improvements (if available) of some identified characteristics within the structure of the implemented algorithm, without implying an absolute or global optimum of the characteristics (where the term is used more commonly). For example, in some cases where optimization can determine a minimum, the minimum may be a local minimum rather than a global minimum.

[0028] Figure 1 This is a flowchart of a method 100 for mask synthesis using design-guided offsets, based on some examples. Method 100 is described below in the various figures (especially...). Figure 2 The figures are described in illustrative terms within the context of the invention. These figures are provided by way of example only, and those skilled in the art will readily understand the application of method 100 in other examples. The various figures (especially...) Figure 2 The accompanying drawings may show some or less all of the components of certain types illustrated in the corresponding figures. This is to avoid obscuring the various aspects illustrated. Those skilled in the art will readily understand how the content illustrated and described throughout the implementation applies.

[0029] As described in further detail below, method 100 can be embodied by a set of one or more instructions stored on a non-transitory computer-readable medium, which may be one or more software modules. One or more processors of a computer system can be configured to read and execute the set of one or more instructions, causing the one or more processors to perform various operations or steps of method 100. Further details are provided below. In some examples, some operations or steps of method 100 can be embodied as a set of one or more instructions of one or more software modules, and other operations or steps of method 100 can be embodied as other sets of one or more instructions of one or more other software modules. In some examples, different software modules can be distributed and stored on different non-transitory computer-readable media on different computer systems for execution by corresponding one or more processors of the different computer systems.

[0030] refer to Figure 1 At position 102, an electronic representation of the integrated circuit design is obtained. For example, the electronic representation could be a .GDS file, etc. The integrated circuit design may include or indicate design target features (or design targets) that, during the fabrication of the integrated circuit on a semiconductor die (e.g., during the fabrication of a portion of the wafer), will be patterned in a photosensitive material (e.g., a photoresist) via a photolithography process. The design target can be used to form the mask used during the photolithography process. Figure 2 A polygon depicting a design objective 202 (e.g., a feature to be printed in a photosensitive material) as an example is shown.

[0031] refer to Figure 1 At position 104, the edges of each design target corresponding to the mask are segmented. (Reference) Figure 2 Segment 204 runs along the edge of design target 202 and represents a division of the design. Segmentation of one or more design targets can be a first step in an OPC solution, where the spacing dimensions of lithographic target points on the wafer and the mask roughness are specified. For simplicity, three segments 204 are shown, and many similar segments run along the edge of design target 202. The method used to determine segments 204 along the polygon edge for OPC is to use a rule-based or model-based function that collects feedback from geometric measurements or lithographic simulations, respectively, and determines where the endpoints of the segments along the design polygon edge should be placed to divide the design edge into a series of end-to-end segments. The input to this function is similar to the input described above for rule-based and model-based OPC methods.

[0032] Return to reference Figure 1At position 106, a ray emanating from the corresponding anchor point is generated. The anchor point can vary depending on the implementation. In the example implementing mask evolution, the anchor point can be along the edges and corners of design target 202. In the example implementing redirection, the anchor point can be along the edges, and if present, along the corners of the mask shape corresponding to the design target. In this redirection implementation, for example, the mask shape can be initialized corresponding to the design target by perturbing the edges of the design target laterally outward by a certain amount.

[0033] Figure 2 The anchor points are described in the context of the edges and corners along design target 202. The concepts described herein can be modified for application to redirection implementations. Figure 2 The diagram shows ray 206. Figure 2 Each ray 206 originates from an anchor point on the edge or convex corner formed by the edge of the design target 202. Figure 2 In some examples, one or more rays may emanate from anchor points (e.g., anchor point 290) at the concave corners of the polygon of the design target 202, which is inside the polygon. Rays 206 emanating from anchor points (e.g., anchor point 292) on the edges emanate in a direction perpendicular to the respective edges of the design target 202. In some examples, each segment 204 along the edge of the design target 202 has one or more rays 206 emanating from a corresponding anchor point on the corresponding segment 204.

[0034] In some examples, each corner (whether convex or concave) of the polygon of the design target 202 can be an anchor point and can have one or more rays 206 emanating from it. Figure 2 The illustration shows an example corner 208, and aspects of this corner 208 are described herein for illustrative purposes. The description provided for corner 208 also applies to other corners, whether convex or concave. An angle span 210 is located at corner 208 and is formed between corresponding directions 212, 214 extending from corner 208 and perpendicular to the two segments that meet to form corner 208. Rays 206 emanating from anchor points on corner 208 are emanating in corresponding directions that form equal angles 216 between each pair of adjacent rays 206 emanating from corner 208. An angle 218 is formed between the corresponding normal directions 212, 214 and the corresponding nearest ray 206 emanating from corner 208. In some examples, each angle 218 may be half or equal to angle 216.

[0035] The polygon orientation can be selected (e.g., the order of points in a counter-clockwise direction around the exterior of the polygon surrounding design target 202), thus determining whether a particular corner of design target 202 should have rays extending on the outside of the polygon (at convex corners) or on the inside of the polygon (at concave corners) by examining the normal direction of the edges that meet at the corners. A finite number of angles can be selected to create rays fanning out over the angular span.

[0036] refer to Figure 1 At point 108, a custom region boundary is generated. A custom region boundary is formed in design objective 202. In some aspects, such as those discussed in this paper… Figure 8 As described in more detail, one or more other proprietary region boundaries are formed in the space between a design objective and another design objective. Each proprietary region boundary may be a central axis transformation (MAT) of a design objective or the space between design objectives for which proprietary region boundaries are generated.

[0037] refer to Figure 2 A self-defined area boundary 220 is formed within design objective 20. The self-defined area boundary 220 (and any other self-defined area boundaries) is used to indicate which areas ray 206 is allowed to reach; for example, the self-defined area boundary 220 (and any other self-defined area boundaries) can serve as a constraint on the location of the extension of ray 206. In the illustrated example, ray 206 emanating from an anchor point on segment 204 extends to both the exterior and interior of the polygon of design objective 202, and ray 206 emanating from segment 204 extending into the interior of the polygon cannot cross the self-defined area boundary 220. In some examples, such as... Figure 8 As shown, the space between adjacent features can also have its own region boundaries that ray 206 cannot cross.

[0038] In some examples, for each corner of design target 202, the axis of the boundary of the design target's own region contacting the corresponding corner is used to determine the direction of a generalized ray extending outside the design target when the corresponding corner is convex, or the direction of a generalized ray extending inside the design target when the corresponding corner is concave. The generalized ray emanates from the corner along the axis of the boundary of the corner's own region. The generalized ray for a corresponding corner can be used as a corresponding ray for each ray emanating from the corresponding corner, which extends in a generalized direction opposite to those rays. This generalized ray can be used when any ray emanating from the corner degenerates, as described below. Reference Figure 2As an example for a convex corner, the axis 221 of the self-contained region boundary 220 contacts the corner 208, and a generalized ray (not explicitly shown) extends from inside the corner 208 to the design target 202 and along the axis 221. This generalized ray can be used as a corresponding generalized ray for each ray 206 shown within the corner span 210. For the purposes of the following description, although extending in generally opposite directions, the generalized ray can be considered as a part of each ray emanating from the respective corner.

[0039] Custom region boundaries can be user-defined and customized. In some examples, custom region boundaries can also be generated between OPC iterations from the MAT of the current mask shape generated by the stitching process (described later). As an example, Figure 3 A custom-owned region boundary 302 is shown at the center of the polygon deviating from the design target 202. This custom-owned region boundary 302 allows the mask to move beyond the center of the design polygon. Maintaining the topological connectivity of the custom-owned free region boundary 302 helps ensure that rays from multiple segments and corners do not intersect. Topological connectivity generally refers to graph connectivity between non-2nd-order nodes that meet at corresponding nodes, such as one edge, three edges, or more edges. It should be noted that the input design can be a previously corrected mask, in which case the topological connectivity of the original design can help construct the custom-owned region.

[0040] Return to reference Figure 1 At 110, for each ray, the distance is defined between the corresponding anchor point of the ray and the analysis point along the ray. The analysis point can vary based on the implementation. In some implementations, such as in mask evolution where the anchor point is on the edge of the design target, the analysis point can be the intersection of the mask boundary and the ray. In some implementations, such as in redirection where the anchor point is on the boundary of the mask, the analysis point can be the intersection of the edge of the design target and the ray. In these examples, the distance is defined between (i) the intersection of the mask boundary and the ray and (ii) the intersection of the edge of the design target and the ray. In any implementation, the mask shape can be initialized corresponding to the design target, for example, by perturbing the edge of the design target laterally outward by a certain amount.

[0041] continue Figure 2In the implementation illustrated, intersection 222 represents the corresponding intersection of mask shape 230 and ray 206. For each ray 206 originating from an edge or corner of design target 202, a distance (labeled d_i for the following description) that can be positive or negative is generated. The corresponding ray 206 emanates from the edge or corner of design target 202 to the intersection 222 on the corresponding ray 206, where positive distances are located outside design target 202 and negative distances are located inside design target 202. Example positive distance 224 and example negative distance 226 are illustrated. For rays emanating from convex corners, the negative distance d_i indicates ray degeneration, and the negative distance d_i is inside the design target and measured along the corresponding generalized ray. For rays emanating from concave corners, the positive distance d_i indicates ray degeneration, and the positive distance d_i is outside the design target and measured along the corresponding generalized ray. Those skilled in the art will readily understand the distances for the other rays 206.

[0042] Return to reference Figure 2 A mask shape 230 is formed by connecting the intersections 222 of adjacent rays 206. This is referred to as the stitched mask shape. The mask shape can be initialized to some shapes as described above, and various iterations of the analysis described herein can modify the mask shape.

[0043] although Figure 2 The illustration shows rays emanating from anchor points on the edges and corners of the design target, but as described, rays can also emanate from anchor points on the mask. Figure 4 The illustration shows (for example, corresponding to) Figure 2 The mask 230 shown is a stitched mask 406 and an initial mask 410. Figure 4 As shown, ray 404 originates from an anchor point (e.g., anchor point 408) on the initial mask 410. Intersection point 402 represents the corresponding intersection of the stitching mask 406 and ray 404. The stitching mask 406 is formed by connections between the intersection points 402 of adjacent rays 404.

[0044] refer to Figure 1 At 112, an analysis is performed, where the analysis is configured to perturb (e.g., modify) the mask shape based on distance and corresponding error. In some examples, the analysis (e.g., mask evolution) may involve using an iterative algorithm to compute the movement of intersection 222 or adjustments for each distance d_i along each ray 206. This analysis can be performed using mask perturbation or the gradient of the lithography cost function, which can obtain a quantity to be changed for any distance d_i to improve lithography QOR. In some aspects, a mask design is generated for a mask to be used to fabricate the target shape on the image surface, based on the modified distance.

[0045] Analysis may include obtaining an image profile based on the mask shape. The image profile can be obtained by simulating a photolithography process, where the image profile is the shape of a feature patterned in a photosensitive material using the mask shape from the photolithography process. For each ray, an error (denoted as e_i for the following description) is obtained, which is the distance between the target point associated with the ray and the intersection of the ray and the wafer image profile. Each target point can be associated with a ray and can be constructed independently of the ray. Target points can be placed to represent the boundaries of an ideal wafer profile that satisfies the specifications of the corresponding manufacturing process. Each ray can be associated with one or more target points, and / or each target point can be associated with one or more rays. For each ray, the sensitivity to changes in distance d_i (denoted as s_i for the following description) can be determined, where the sensitivity s_i is the ratio of the change in error e_i to the change in distance d_i. This sensitivity s_i can then be used to modify the distance d_i. Modifying the distance d_i perturbs the mask shape.

[0046] Figure 2 Image contour 250 and target points 252 that can be used in the OPC optimization algorithm are also shown. As illustrated, some targets in target 252 are on target shape 202, and some target points are offset from target shape 202. For example, some target points near the corners of target shape 202 can be offset because forming features with acute angles may be impossible (or at least difficult). Image contour 250 is the resulting feature or image simulated in a photosensitive material using mask shape 230. Figure 2 The constructed target points 252 are shown, and typically each target point 252 is associated with the ray 206 closest to the target point 252 and / or the ray 206 incident on the target point 252. The distance between the image contour 250 and the corresponding target point 252 associated with the corresponding ray 206 (e.g., example distance 254 is illustrated) is the error e_i (e.g., a signed error) for each target point. The error is negative if the distance is inside the design target 202, and positive if the distance is outside the design target 202. The sensitivity s_i can be assigned based on previous iterative feedback of the mask effect on the contour image or other numerical differentiation techniques, or set based on user knowledge or heuristics. The pseudocode for the example (where each ray has an associated target point) is as follows.

[0047] for each ray of index i

[0048] d_i=distance for ray of index i

[0049] e_i=error for target point of ray of index i

[0050] s_i=Δe_i / Δd_i=sensitivity of e_i to change in d_i

[0051] d_i+=e_i / s_i

[0052] There are also rule-based techniques that use geometric heuristics (such as local width, spacing, polygon density, etc.) to offset design edges to obtain non-simulation-based mask synthesis methods.

[0053] In some cases, there may be one or more rays 206 with a negative distance d_i, the magnitude of which is greater than the corresponding distance from the edge of the design feature 202 to the proprietary region boundary 220. In this case, the connected mask shape can be constructed to coincide with the proprietary region boundary 220 for those rays. Figure 5 An example is shown in which some rays in ray 206 (e.g., ray 206') have negative distances d_i (e.g., distance 502), such that the magnitude of the distance d_i is greater than or equal to the distance along ray 206 from the edge of the design target 202 to the boundary 220 of the self-owned region. Figure 5 As shown, mask 504 may have an edge 506 that partially overlaps with its own region boundary 220. Figure 6 The mask shapes 602 and 604 are shown after the degenerate portion along the self-region boundary 220 (e.g., edge 506 coinciding with the self-region boundary 220) has been removed. For example, the mask design can be generated by modifying the mask shapes such that the mask shapes are formed as multiple non-overlapping mask shapes (e.g., mask shapes 602 and 604) or that one mask shape is merged with another mask shape (e.g., mask shape 602 is merged with mask shape 604).

[0054] Similarly, in some cases, if the distance d_i of one or more rays 206 is equal to or greater than the distance along the corresponding ray 206 from the corresponding edge of the design target 202 to the spatial boundary of the different design targets, then two mask shapes can be merged into one mask shape.

[0055] In some examples, the connection between intersections 222 is a Manhattan line and / or a straight line or has other geometric directional constraints. For example... Figure 7As shown, a Manhattan mask 702 (partially shown) can be constructed. For a ray 206 emanating from the edge of the design target 202, a straight line segment 704 parallel to the corresponding edge of the design target 202 is used to form the mask 702. The segment 704 is placed at the corresponding intersection 222 of the ray 206 and has a length corresponding to the length of the edge segment 204 of the design target 202 from which the ray 206 emanates.

[0056] For a ray 206 emanating from a corner of design target 202, a segment 704 for ray 206 is parallel to the edge of design target 202, which is connected to form a corner (from which ray 206 emanates) and forms a minimum angle with the corresponding ray 206. For ray 206, which serves as the central axis of angular span 210, segment 704 can be parallel to any edge of design target 202 connected to form the corner. Segment 704 is placed at the corresponding intersection 222 of ray 206 and has a length determined by the distance d_i of ray 206. For example, the length of segment 704 can be proportional to the distance d_i. The larger the distance d_i, the larger the mask edge positioned near the corresponding ray 206 can be.

[0057] When adjacent segments 704 are parallel, they are connected at their adjacent ends by stitching segments 706 perpendicular to each other. When adjacent segments 704 (e.g., at corners) are perpendicular, they are extended until they intersect. The advantages of this ray-based approach compared to conventional OPC mask creation methods include a significantly increased range of mask shapes that can be created while maintaining a linear link between degrees of freedom (rays) and design objectives.

[0058] Those skilled in the art will readily understand the various data structures that can be implemented in the above process. For example, a classification of mask objects can be defined for polygons and / or edges of the mask pattern. A classification of segments 204 can be defined. A classification of rays 206 can be defined. The classification of rays may include anchor points, intersection points 222 and corresponding distances d_i (e.g., distances 224, 226), target points 242 and corresponding errors e_i (e.g., distance 254), etc. The above methods and / or algorithms can operate on instances of this classification and / or utilize instances of this classification. Different data structures and / or modified data structures can be used in different examples.

[0059] Figure 8The illustration depicts one or more self-owned region boundaries formed in the space between a design target and one or more other design targets. For example, as shown, a self-owned region 808 is formed between design targets 802, 804, and 806. Rays 810 emanate from design targets 802, 804, and 806 and terminate at the self-owned region 808. In other words, the self-owned region 808 provides the boundary between design targets 802, 804, and 806, at which rays 810 emanating from those design targets terminate.

[0060] Those skilled in the art will readily understand the various modifications to the logical and / or mathematical expressions of the examples described herein. Other examples take this modification into consideration.

[0061] Figure 9 The illustration shows an example of a set of processes 900 used during the design, verification, and fabrication of an integrated circuit on a semiconductor die to transform and verify design data and instructions representing the integrated circuit. Each of these processes can be constructed and implemented as multiple modules or operations. The term "EDA" stands for Electronic Design Automation. These processes begin at box 910, where a product idea is created using information provided by the designer. At box 912, the information is transformed to create an integrated circuit using a set of EDA processes. When the design is complete, it is taken offline at box 934, where the original drawing (e.g., geometric pattern) for the integrated circuit is sent to a manufacturing facility to create a mask set, which is then used to fabricate the integrated circuit. After offline, at box 936, the integrated circuit is fabricated on a semiconductor die, and at box 938, packaging and assembly processes are performed to produce the completed integrated circuit (often referred to as a "chip" or "integrated circuit chip") at box 940.

[0062] Specifications for circuits or electronic structures can range from low-level transistor material placement to high-level description languages. High-level representations can be used to design circuits and systems using hardware description languages ​​(HDLs) such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be translated into logic-level register-transfer level (RTL) descriptions, logic gate-level descriptions, placement-level descriptions, or mask-level descriptions. Each lower level of representation, as a more detailed description, adds more useful details to the design description, such as, for example, more details about the modules included in the description. Lower-level representations as more detailed descriptions can be computer-generated, derived from design libraries, or created by another design automation process. An example of a specification language used to specify the detailed language at lower levels is SPICE, which is used for detailed descriptions of circuits with many analog components. The description at each level of detail can be used by the corresponding tool for that layer (e.g., a formal verification tool). The design process can use... Figure 9 The sequence described herein. EAD products (or tools) can enable the described process.

[0063] During system design, at box 914, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics (such as power consumption, performance, area (physical and / or lines of code)) and cost reduction. At this stage, the design can be divided into different types of modules or components.

[0064] During logic design and functional verification, at box 916, modules or components in the circuit are specified in one or more description languages, and specifications are checked for functional accuracy. For example, components of the circuit can be verified to generate outputs that match the specification requirements of the circuit or system being designed. Functional verification can be performed using simulators and other programs, such as testbed generators, static HDL checkers, and formal verifiers. In some examples, a specific system of components, referred to as a simulator or prototype system, is used to accelerate functional verification.

[0065] During synthesis and design for testing, at box 918, the HDL code is converted into a netlist. In some examples, the netlist can be a graph structure, where the edges of the graph structure represent components of the circuit, and the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are layered fabrication products that EDA products can use to verify that the integrated circuit performs according to the specified design when it is manufactured. The netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the completed integrated circuit can be tested to verify that the integrated circuit meets specification requirements.

[0066] During netlist verification, at box 920, the netlist is checked for compliance with timing constraints and for correspondence with HDL code. During design planning, at box 922, the overall planar diagram of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0067] During layout or physical implementation, at box 924, physical placement (positioning of circuit components such as transistors or capacitors) and wiring (connection of circuit components through multiple conductors) occur, and cells can be selected from a library to enable specific logic functions. As used herein, the term "cell" can specify a collection of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (e.g., flip-flops or latches). As used herein, a circuit "box" can refer to two or more cells. Both cells and circuit boxes can be referred to as modules or components and can be enabled both as physical structures and in simulation. For selected cells, parameters (based on standard cells) are specified (e.g., size) and are accessible in a database for use in EDA products.

[0068] During analysis and extraction, at box 926, circuit functionality is verified at the layout level, allowing for refinement of the layout design. During physical verification, at box 928, the layout design is checked to ensure that manufacturing constraints are correct, such as Design Rule Check (DRC) constraints, electrical constraints, lithographic constraints, and circuit system functionality that matches the HDL design specification. During resolution enhancement, at box 930, the layout geometry is transformed to improve how the circuit design can be manufactured. For example, this can be performed in box 930. Figure 1 Method 100.

[0069] During the offline phase (after applying lithographic enhancement where appropriate), data is created for the production of the lithographic mask. During mask data preparation, at box 932, the offline data is used to generate the lithographic mask, which is used to produce the finished integrated circuit.

[0070] Computer systems (such as, Figure 10 The storage subsystem of the computer system 1000 can be used to store programs and data structures used by some or all of the EDA products described herein, and by products used for the development of units for libraries and for the physical and logical design of the use of libraries.

[0071] Figure 10An example of a computer system 1000 is illustrated, within which a set of instructions can be executed to cause the computer system to perform any or more of the methods discussed herein. In some implementations, the computer system may be connected (e.g., networked) to other machines or computer systems in a local area network (LAN), intranet, extranet, and / or the Internet. The computer system may operate as a server or client computer system in a client-server network environment, as a peer-to-peer computer system in a peer-to-peer (or distributed) network environment, or as a server or client computer system in a cloud computing infrastructure or environment.

[0072] A computer system can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specifies the actions the computer system should take. Furthermore, although a single computer system is illustrated, the term "computer system" should also be considered as any collection of computer systems that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more methods discussed herein.

[0073] Example computer system 1000 includes processing device 1002, main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM)), static memory 1006 (e.g., flash memory, static random access memory (SRAM)), etc.), and data storage device 1018, which communicate with each other via bus 1030. Main memory 1004 includes a non-transitory computer-readable medium or a non-transitory computer-readable medium. Main memory 1004 (e.g., a non-transitory readable medium) may store one or more sets of instructions 1026, which, when executed by processing device 1002, cause processing device 1002 to perform some, some, some, some, some, some operations ...

[0074] Processing device 1002 represents one or more processors, such as microprocessors, central processing units, etc. More specifically, processing device 1002 may be or include complex instruction set computing (CISC) microprocessors, reduced instruction set computing (RISC) microprocessors, very long instruction word (VLIW) microprocessors, processors implementing other instruction sets, or processor(s) implementing combinations of instruction sets. Processing device 1002 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1002 may be configured to execute instructions 1026 for performing some, steps, methods, and procedures described herein.

[0075] The computer system 1000 may also include a network interface device 1008 for communication via a network 1020. The computer system 1000 may also include a video display unit 1010 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1012 (e.g., a keyboard), a cursor control device 1014 (e.g., a mouse), a graphics processing unit 1022, a signal generation device 1016 (e.g., a speaker), a video processing unit 1028, and an audio processing unit 1032.

[0076] Data storage device 1018 may include machine-readable storage medium 1024 (e.g., non-transitory computer-readable medium) storing one or more sets of software or instructions 1026 embodying any one or more methods or functions described herein. Instructions 1026 may also reside wholly or at least partially within main memory 1004 and / or processing device 1002 during execution by computer system 1000, both of which also include machine-readable storage media.

[0077] In some implementations, instruction 1026 includes instructions for implementing the functions described above. Although machine-readable storage medium 1024 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be considered as a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that include one or more sets of stored instructions. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions for execution by a computer system and causing the computer system and processing device 1002 to perform any one or more of the methods described above. Therefore, the term "machine-readable storage medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0078] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the art to communicate the essence of their work to others skilled in the art. An algorithm can be a series of operations that lead to a desired result. These operations are those that require physical manipulation of physical quantities. These quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0079] However, it should be remembered that all these terms and similar terms are associated with appropriate physical quantities and are merely practical labels applied to those quantities. Unless otherwise clearly stated in this disclosure, it should be understood that throughout the description, certain terms refer to the actions and processes of computer systems or similar electronic computing devices that process and convert data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage devices.

[0080] This disclosure also relates to an apparatus for performing the operations described herein. The apparatus may be specifically constructed for its intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs, magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of medium suitable for storing electronic instructions, each storage medium being coupled to a computer system bus.

[0081] The algorithm and display presented herein are not substantially related to any particular computer or other device. Various other systems may be used in conjunction with the program taught herein, or it may be demonstrated that it is convenient to construct more specialized devices to perform the method. Furthermore, this disclosure is not described with reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using a variety of programming languages.

[0082] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media include any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media include machine-readable (e.g., computer-readable) storage media such as read-only memory (ROM), random access memory (RAM), disk storage media, optical storage media, flash memory devices, etc.

[0083] In the foregoing disclosure, implementations of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the implementations of the present disclosure as set forth in the following claims. Where elements are referred to in the singular tense in this disclosure, more than one element may be depicted in the figures, and similar elements may be labeled with similar numbers. Therefore, this disclosure and the accompanying drawings are to be considered illustrative rather than restrictive.

Claims

1. A method comprising: Based on integrated circuit design, a mask is used to obtain the target shape on the surface of the image to be manufactured; Generate rays emanating from corresponding anchor points, which are located on the boundary of the target shape or on the boundary of the mask shape of the mask; For each of the rays, the following distances are defined: The first intersection point of the corresponding ray with the boundary of the target shape; and The second intersection point of the corresponding ray with the boundary of the mask shape; The distance is modified by one or more processors based on the error between the target shape and the resulting shape simulated on the image surface caused by the mask shape; as well as Based on the modified distance, a mask design is generated for the mask to be used to create the target shape on the image surface.

2. The method of claim 1, further comprising generating an inherent region boundary in the target shape, wherein the ray does not extend beyond the inherent region boundary.

3. The method of claim 1, further comprising generating an inherent region boundary in the space between the target shape and one or more other target shapes, wherein the ray does not extend through the inherent region boundary.

4. The method of claim 3, wherein the self-owned region boundary is generated using a central axis transformation of the target shape.

5. The method of claim 4, wherein the proprietary region is user-defined.

6. The method of claim 3, wherein the mask shape includes an edge that partially overlaps with the self-owned region.

7. The method of claim 1, wherein generating the mask design includes modifying the mask shape such that the mask shape is formed as a plurality of non-overlapping mask shapes, or such that the mask shape is merged with another mask shape.

8. The method of claim 1, wherein one or more of the rays originate from a corner of the target shape or a corner of the mask shape.

9. The method of claim 8, wherein the one or more rays in the ray comprise a first ray, a second ray, and a third ray emanating from the corner, and wherein the angle between the first ray and the second ray is the same as the angle between the second ray and the third ray.

10. The method of claim 1, wherein the modification of the distance between the target shape and the resulting shape is based on a rule table.

11. The method of claim 1, further comprising determining a sensitivity, the sensitivity representing the ratio of the change in the error to the change in the distance, wherein the distance is modified based on the sensitivity.

12. The method of claim 1, wherein the masked shape comprises lines parallel to the edge of the target shape, each of the lines intersecting the second point of the masked shape through one of the rays.

13. The method of claim 12, wherein two of the lines are connected by another line perpendicular to the edge of the target shape.

14. An apparatus comprising: Memory; as well as One or more processors are coupled to the memory, and the memory and the one or more processors are configured to: Based on integrated circuit design, a mask is used to obtain the target shape on the surface of the image to be manufactured; Generate rays emanating from corresponding anchor points, which are located on the boundary of the target shape or on the boundary of the mask shape of the mask; For each of the rays, the following distances are defined: The first intersection point of the corresponding ray with the boundary of the target shape; and The second intersection point of the corresponding ray with the boundary of the mask shape; as well as An analysis is performed, which is configured to modify the distance based on the error between the target shape and the resulting shape simulated on the image surface caused by the mask shape.

15. The apparatus of claim 14, wherein the memory and the one or more processors are further configured to generate an inherent region boundary in the target shape, wherein the ray does not extend beyond the inherent region boundary.

16. The apparatus of claim 15, wherein the inherent region boundary is generated using a central axis transformation of the target shape.

17. The apparatus of claim 16, wherein the owned region is user-defined.

18. The apparatus of claim 15, wherein the mask shape includes an edge that partially overlaps with the self-owned region.

19. The apparatus of claim 14, wherein the memory and the one or more processors are further configured to generate an independent region boundary in a space disposed between the target shape and one or more other target shapes, wherein the ray does not extend through the independent region boundary.

20. A non-transitory computer-readable medium comprising executable instructions, which, when executed by one or more processors of a device, cause the device to: Based on integrated circuit design, a mask is used to obtain the target shape on the surface of the image to be manufactured; Generate rays emanating from corresponding anchor points, which are located on the boundary of the target shape or on the boundary of the mask shape of the mask; For each of the rays, the following distances are defined: The first intersection point of the corresponding ray with the boundary of the target shape; and The second intersection point of the corresponding ray with the boundary of the mask shape; as well as The analysis is performed by one or more processors and is configured to modify the distance based on the error between the target shape and the resulting shape simulated on the image surface caused by the mask shape.

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