A method for applying analog dynamic circuits to digital test tools

Abstract

The present invention is a processing method for applying an analog dynamic circuit to a digital test tool, comprising the following steps: (a) providing an analog dynamic circuit represented at the transistor level; (b) designing a plurality of corresponding equivalent models according to the operation of a plurality of transistors in the analog dynamic circuit; (c) performing a replacement operation to replace a plurality of dynamic logic elements in the analog dynamic circuit with the equivalent models and forming the analog dynamic circuit represented at the gate level; (d) importing the analog dynamic circuit represented at the gate level into a digital test tool to generate a test pattern; and (e) testing the analog dynamic circuit represented at the transistor level with the test pattern.

Description

Technical Field

[0001] The present invention is an application method of an integrated circuit testing tool, and particularly relates to a processing method for applying an analog dynamic circuit to a digital testing tool. Background Art

[0002] In integrated circuits, dynamic circuits have the advantages of higher speed, less area, and lower energy consumption. Therefore, dynamic circuits have been designed in central processing units (CPUs) and application-specific integrated circuits (ASICs). Compared with dynamic circuits, static circuits have better noise immunity, but static circuits have the disadvantages of larger area and slower speed.

[0003] The difference between a dynamic circuit and a static circuit is that a dynamic circuit uses a clock signal to operate, while a static circuit does not have a clock signal.

[0004] For example, a static circuit can be formed by various static logic elements, such as a NOT gate, an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, etc., to form a static combination logic circuit.

[0005] A dynamic circuit can be formed by various dynamic logic elements, such as a dynamic NOT gate (dynamic NOT), a dynamic AND gate (dynamic AND gate), a dynamic NAND gate (dynamic NAND gate), a dynamic OR gate (dynamic OR gate), a dynamic NOR gate (dynamic NOR gate), a dynamic XOR gate (dynamic XOR gate), etc., to form a dynamic combinational logic circuit.

[0006] In addition, in actual circuit design, static circuits are represented by higher-order gate levels, while dynamic circuits are represented by lower-order transistor levels. This is explained below.

[0007] Please refer to Figure 1A and Figure 1B, which shows the static circuit and dynamic circuit schematic diagram of a 1-bit Half-Adder. Figure 1A As shown, a static half adder 110 includes an XOR gate 112 and an AND gate 114. The two input terminals of the XOR gate 112 receive the first input signal A and the second input signal B respectively, and the output terminal of the XOR gate 112 generates a sum signal S. The two input terminals of the AND gate 114 receive the first input signal A and the second input signal B respectively, and the output terminal of the AND gate 114 generates a carry signal C.

[0008] The static half adder 110 can add the first signal A and the second signal B, and generate a sum signal S and a carry signal C. For example, when the first signal A and the second signal B are both "0", the sum signal S and the carry signal C are both "0". When the first signal A and the second signal B are "1, 0" or "0, 1", the sum signal S is "1", and the carry signal C is "0". When the first signal A and the second signal B are both "1", the sum signal S is "0", and the carry signal C is "1". Among them, "1" is a logic high level, and "0" is a logic low level.

[0009] Furthermore, if Figure 1B As shown, the dynamic half adder 120 includes a plurality of transistors a1-a8, b1-b6, and c1. Among them, the transistors a1-a8 and c1 are combined into a dynamic XOR gate. The transistors b1-b6 and c1 are combined into a dynamic AND gate. In addition, the clock signal CLK controls the transistors a1 and c1 in the dynamic XOR gate. The clock signal CLK controls the transistors b1 and c1 in the dynamic AND gate. In other words, the dynamic half adder 120 receives the clock signal CLK, the first signal A, and the second signal B to generate a sum signal S and a carry signal C.

[0010] When the clock signal CLK is at a logic low level (e.g., the ground voltage GND), it is a pre-charge phase, so that the sum signal S and the carry signal C are maintained at a logic low level. When the clock signal CLK is at a logic high level (e.g., the supply voltage Vdd), it is an evaluation phase. At this time, the dynamic half adder 120 can add the first signal A and the second signal B, and generate the sum signal S and the carry signal C. The detailed operation principle is not repeated here.

[0011] Basically, as the function of a circuit increases, the complexity of the circuit will also increase. For example, a 1-bit static full adder can be composed of two 1-bit static half adders and an OR gate. Obviously, the number of static logic elements in a 1-bit static full adder is greater and the connection relationship is more complex.

[0012] Similarly, a one-bit dynamic full adder will be composed of more transistors. Furthermore, the adder designed in the central processing unit (CPU) is at least a 32-bit adder, so it can be foreseen that the number of transistors in the 32-bit dynamic adder is more and the connection relationship is more complicated.

[0013] After the static circuit and dynamic circuit design are completed, test tools are needed to verify whether the circuit can operate normally. Automatic test pattern generation (ATPG) is a digital testing tool that can generate test patterns for digital circuits to test. In other words, ATPG is suitable for static circuits represented by gate levels.

[0014] When the static circuit design is completed, the static circuit can be imported into the ATPG system. This digital test tool can generate test patterns for the input endpoints, output endpoints, and all internal nodes of the static circuit. After that, the test pattern can be used to test the static circuit. When testing, the test pattern can be input into the static circuit, and based on whether the data generated by the nodes and output ends in the static circuit match the expected data, it is determined whether the static circuit can operate normally or whether a design error has occurred. In other words, the test pattern generated by ATPG has excellent test coverage for static circuits.

[0015] However, a dynamic circuit is an analog circuit. The operation of this analog dynamic circuit is to turn on or off the transistor according to the high or low level of the signal and drive the transistor of the next level. Therefore, the analog dynamic circuit includes multi-drive path, pull-up path, pull-down path, loop, etc.

[0016] Since dynamic circuits are represented at the transistor level, they are not suitable for digital test tools. In other words, since the nodes in the analog dynamic circuit are connected to various paths or loops, ATPG cannot generate test patterns for the internal nodes of the analog dynamic circuit. Therefore, when the analog dynamic circuit is introduced into the ATPG system, its test coverage will be very poor. Summary of the invention

[0017] The present invention proposes a processing method for applying an analog dynamic circuit to a digital test tool, comprising the following steps: (a) providing an analog dynamic circuit represented at a transistor level; (b) designing a plurality of corresponding equivalent models according to the operation of a plurality of transistors in the analog dynamic circuit; (c) performing a replacement operation to replace a plurality of dynamic logic elements in the analog dynamic circuit with the equivalent models, and forming the analog dynamic circuit represented at a gate level; (d) importing the analog dynamic circuit represented at a gate level into a digital test tool to generate a test pattern; and (e) testing the analog dynamic circuit represented at a transistor level with the test pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to better understand the above and other aspects of the present invention, preferred embodiments are described in detail below with reference to the accompanying drawings:

[0019] Figure 1A and Figure 1B The static circuit and dynamic circuit diagram of a one-bit half adder.

[0020] Figure 2 The figure is a flow chart of the processing method of the present invention.

[0021] Figure 3A and Figure 3B Dynamic XOR gate, dynamic AND gate and their equivalent models.

[0022] FIG. 4A to FIG. 4C Dynamic NAND gate, dynamic NOR gate, dynamic AND-NOR gate and their equivalent models.

[0023] The reference numerals are described as follows:

[0024] 110, 120: Half adder

[0025] 112: XOR gate

[0026] 114: AND gate

[0027] S202~S210: Step Flow DETAILED DESCRIPTION

[0028] Aiming at the problem that the existing analog dynamic circuit cannot be applied to digital test tools, the present invention proposes a processing method for applying the analog dynamic circuit to digital test tools.

[0029] In the processing method of the present invention, an equivalent model is provided to replace the dynamic logic elements in the analog dynamic circuit, so that the analog dynamic circuit can be represented at the gate level and introduced into a digital testing tool to generate a test pattern. Afterwards, when the analog dynamic circuit is tested, the test pattern is applied to the analog dynamic circuit to improve the test coverage.

[0030] Please refer to Figure 2 , which shows a flow chart of the processing method of the present invention. When the analog dynamic circuit design is completed, the processing method of the present invention can be started. First, an analog dynamic circuit represented by a transistor level is provided (step S202).

[0031] Next, the corresponding equivalent model is designed according to the operation of the transistor in the simulated dynamic circuit (step S204). Since transistors are used to form various dynamic logic elements in the simulated dynamic circuit, a corresponding equivalent model can be designed for each dynamic logic element. According to an embodiment of the present invention, the equivalent model is designed using a hardware description language (HDL). For example, the hardware description language Verilog is used to convert the function of the dynamic logic element into an equivalent model represented by the gate level.

[0032] Afterwards, a replacement operation is performed to replace the dynamic logic elements in the analog dynamic circuit with the equivalent model, and form an analog dynamic circuit represented by the gate level (step S206). In other words, after the replacement operation is completed, all dynamic logic elements in the analog dynamic circuit will be replaced by the corresponding equivalent model, so that the analog dynamic circuit becomes an analog dynamic circuit represented by the gate level (gate level).

[0033] Next, the analog dynamic circuit represented by the gate level is imported into the digital test tool to generate a test pattern (step S208). That is, the analog dynamic circuit represented by the gate level is imported into the ATPG system, and a test pattern is generated for the input terminals, output terminals and all internal nodes of the analog dynamic circuit.

[0034] After the test pattern is generated, the test pattern can be used to test the analog dynamic circuit represented by the transistor level (step S210). When testing, the test pattern can be input into the analog dynamic circuit represented by the transistor level, and the data generated by the nodes and output ends in the analog dynamic circuit represented by the transistor level can be judged whether it matches the expected data. If it matches, it is confirmed that the analog dynamic circuit can operate normally; if it does not match, it is judged that the analog dynamic circuit design is wrong.

[0035] In other words, by using the processing method of the present invention, the analog dynamic circuit represented by the transistor level can be converted into the analog dynamic circuit represented by the gate level. Therefore, the converted analog dynamic circuit can be smoothly introduced into the ATPG system, so that the test pattern generated by the ATPG system has good test coverage for the analog dynamic circuit.

[0036] The following uses a 1-bit Dynamic Half-Adder as an example to illustrate the processing method of the present invention. Figure 1B It can be seen that the dynamic half adder 120 is an analog dynamic circuit represented by transistor level. Furthermore, according to the operation of the analog dynamic circuit, transistors a1-a8 and c1 are combined into a dynamic XOR gate. In addition, transistors b1-b6 and c1 are combined into a dynamic AND gate.

[0037] like Figure 3A As shown, according to the function of the dynamic XOR gate, it is further converted into Verilog code as an equivalent model of the dynamic XOR gate. That is, the equivalent model of the dynamic XOR gate is:

[0038] / / equivalent model XOR

[0039] if CLK=0

[0040] S=1

[0041] if CLK=1

[0042] S=(not(A)and(B))or((A)and not(B))

[0043] like Figure 3BAs shown, according to the function of the dynamic AND gate, it is further converted into Verilog code as an equivalent model of the dynamic AND gate. That is, the equivalent model of the dynamic AND gate is:

[0044] / / equivalent model AND

[0045] if CLK=0

[0046] C=1

[0047] if CLK=1

[0048] C=(A and B)

[0049] When the equivalent model is completed, a replacement operation can be performed to replace the dynamic XOR gate and the dynamic AND gate in the 1-bit Dynamic Half-Adder with the equivalent model, and form a 1-bit Dynamic Half-Adder represented by the gate level.

[0050] Next, the 1-bit Dynamic Half-Adder represented by the gate level is imported into the ATPG system, and test patterns are generated for the input endpoints, output endpoints, and all internal nodes of the simulated dynamic circuit. After the test pattern is generated, the 1-bit Dynamic Half-Adder can be tested using the test pattern.

[0051] Of course, in addition to the dynamic XOR gate and dynamic AND gate mentioned above, it is also possible to design equivalent models of various dynamic logic elements and store them in the database. When simulating a dynamic circuit for replacement, the corresponding equivalent model can be directly selected from the database. FIG. 4A to FIG. 4C Briefly introduce the equivalent models of other dynamic logic elements.

[0052] like Figure 4A As shown, it is an equivalent model of a dynamic NAND gate. According to the function of the dynamic NAND gate, its equivalent model can be designed as:

[0053] / / equivalent model NAND

[0054] if CLK=0

[0055] OUT=1

[0056] if CLK=1

[0057] OUT=not(A and B)

[0058] like Figure 4B As shown, it is an equivalent model of a dynamic NOR gate. According to the function of the dynamic NOR gate, its equivalent model can be designed as:

[0059] / / equivalent model NOR

[0060] if CLK=0

[0061] OUT=1

[0062] if CLK=1

[0063] OUT=not(A or B)

[0064] like Figure 4C As shown, it is an equivalent model of a dynamic and-or-inverter (AOI). According to the function of the dynamic and-or-inverter (dynamic AOI), its equivalent model can be designed as follows:

[0065] / / equivalent model AOI

[0066] if CLK=0

[0067] OUT=1

[0068] if CLK=1

[0069] OUT = not(A and(B or C))

[0070] Of course, in addition to the equivalent models of the above-mentioned dynamic logic elements, technicians in this field can also design various equivalent models by themselves based on the technical features disclosed in the present invention, so that each equivalent model has a corresponding Verilog code and is stored in a database and can be used in the present invention.

[0071] From the above description, it can be seen that the present invention proposes a processing method for applying analog dynamic circuits to digital test tools. The present invention can convert analog dynamic circuits represented by transistor levels into analog dynamic circuits represented by gate levels, so that the converted analog dynamic circuits can be smoothly introduced into the ATPG system, so that the test patterns generated by the ATPG system have good test coverage for the analog dynamic circuits.

[0072] In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

Claims

1. A method for applying an analog dynamic circuit to a digital test tool, the method comprising the following steps: (a) providing a transistor-level representation of a simulated dynamic circuit; (b) designing corresponding equivalent models according to the operation of the plurality of transistors in the simulated dynamic circuit; (c) performing a replacement operation to replace a plurality of dynamic logic elements in the simulated dynamic circuit with the equivalent model, and forming a gate-level representation of the simulated dynamic circuit; (d) importing the gate-level representation of the analog dynamic circuit into a digital test tool to generate a test pattern; and (e) Testing the simulated dynamic circuit represented by the transistor level using the test pattern.

2. The processing method according to claim 1, wherein: The digital test tool is an automatic test pattern generation system.

3. The processing method according to claim 1, wherein: The equivalent model is stored in a database.

4. The processing method according to claim 1, further comprising: Each of the equivalent models is designed using a hardware description language.

5. The processing method according to claim 4, wherein: The hardware description language is a Verilog hardware description language.

6. The processing method according to claim 5, wherein: Each of the equivalent models has a corresponding Verilog code.

7. The processing method according to claim 1, further comprising: The test pattern is input into the analog dynamic circuit represented by the transistor level, and data generated by a plurality of nodes and at least one output terminal in the analog dynamic circuit represented by the transistor level are judged to be consistent with expected data.

8. The processing method according to claim 7, further comprising: When the data matches the expected data, it is confirmed that the simulated dynamic circuit operates normally; And, when the data does not match the expected data, it is determined that the simulated dynamic circuit design is wrong.

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