Solid state drive, electronic device and method of managing solid state drive

Abstract

Solid state drives, electronic devices, and methods of managing solid state drives are provided. The electronic device includes a power supply to provide first power and second power; first and second solid state drive (SSD) boards to receive the first power from the power supply, the first and second SSD boards each including two or more SSDs; and a substrate to receive the second power from the power supply, to power on or power off the first and second SSD boards independently of each other, and to access the SSDs of the SSD board that is in a powered on state among the first and second SSD boards. In response to a temperature of an SSD board that is in a powered off state increasing, at least one SSD of the SSD board that is in the powered off state can be powered on.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2020-0086230, titled “Solid State Drive, Electronic Device Including Solid State Drive, and Method of Managing Solid State Drive,” filed on July 13, 2020, in the Korean Intellectual Property Office, is hereby incorporated by reference in its entirety. Technical Field

[0003] The present invention relates to electronic devices, and more particularly, to a solid-state drive, an electronic device including the solid-state drive, and a method for managing the solid-state drive. Background Art

[0004] A solid-state drive (SSD) may include non-volatile memory. The SSD can store data in the non-volatile memory and provide data read from the non-volatile memory. Non-volatile memory may include flash memory, phase change memory, ferroelectric memory, magnetic memory, resistive memory, and the like. Summary of the Invention

[0005] An embodiment provides an electronic device comprising: a power supply configured to provide a first power and a second power; a first solid-state drive (SSD) backplane and a second SSD backplane, each configured to receive the first power from the power supply, the first solid-state drive (SSD) backplane and the second SSD backplane each including two or more SSDs; and a substrate configured to receive the second power from the power supply, power on or off the first SSD backplane and the second SSD backplane independently of each other, and access an SSD in a powered-on SSD backplane of the first or second SSD backplane. In response to an increase in the temperature of the powered-off SSD backplane, at least one SSD in the powered-off SSD backplane is powered on.

[0006] An embodiment is also directed to a method of managing a solid state drive (SSD), the method comprising: powering off the SSD; powering on the SSD in response to an increase in an ambient temperature of the SSD; and performing a hold recovery operation at the SSD.

[0007] An embodiment further provides a solid-state drive comprising: a nonvolatile memory device including a plurality of memory blocks, each of the memory blocks including a plurality of memory cells; and a controller including a temperature sensor and configured to perform a retention recovery operation on the plurality of memory blocks when a temperature sensed by the temperature sensor is greater than a critical value. Upon power-on, the controller may perform the retention recovery operation in response to a lack of communication initialization with an external host device, or after power-on, the controller may perform the retention recovery operation in response to a request from the external host device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become more apparent to those skilled in the art through example embodiments described in detail with reference to the accompanying drawings, in which:

[0009] Figure 1 An electronic device according to an example embodiment is shown.

[0010] Figure 2 An example is shown in which SSDs are installed in the first SSD baseboard, the second SSD baseboard, and the third SSD baseboard.

[0011] Figure 3 An SSD backplane according to a first example embodiment is shown.

[0012] Figure 4 A first example of a method of operating an electronic device according to an exemplary embodiment is shown.

[0013] Figure 5 A second example of a method of operating an electronic device according to an example embodiment is shown.

[0014] Figure 6 A third example of a method of operating an electronic device according to example embodiments is illustrated.

[0015] Figure 7 An SSD backplane according to a second example embodiment is shown.

[0016] Figure 8 An SSD backplane according to a third example embodiment is shown.

[0017] Figure 9 A fourth example of a method of operating an electronic device according to an exemplary embodiment is illustrated.

[0018] Figure 10 A fifth example of the operating method of the electronic device according to example embodiments is illustrated.

[0019] Figure 11 A sixth example of the operating method of the electronic device according to example embodiments is illustrated.

[0020] Figure 12 A seventh example of the operating method of the electronic device according to example embodiments is illustrated.

[0021] Figure 13 Examples of program / erase cycles and adjusted threshold values ​​are shown as examples of wear information.

[0022] Figure 14 An eighth example of the operating method of the electronic device according to example embodiments is illustrated.

[0023] Figure 15 An SSD backplane according to a fourth example embodiment is shown.

[0024] Figure 16 An SSD according to an example embodiment is shown. DETAILED DESCRIPTION

[0025] Figure 1 An electronic device 100 according to an example embodiment is shown.

[0026] Reference Figure 1 , the electronic device 100 may be, for example, a server. The electronic device 100 may include a power supply 110 and a power receiver 120. The power supply 110 may generate power PWR from external power and may provide the generated power PWR to the power receiver 120. The power PWR may be provided in the form of two or more different voltages.

[0027] The power receiver 120 may receive power PWR from the power source 110 and may operate based on the power PWR. The power receiver 120 may include a baseboard 130, a first solid state drive (SSD) backplane 140, a second SSD backplane 150, a third SSD backplane 160, a cooling control board 170, a cooler 180, and a sensor 190.

[0028] The base board 130 may include a first central processing unit (CPU) 131, a second CPU 132, a first memory 133 and a second memory 134 connected to the first CPU 131, a third memory 135 and a fourth memory 136 connected to the second CPU 132, and a baseboard management controller (BMC) 137. The base board 130 may provide power PWR received from the power supply 110 to the first CPU 131, the second CPU 132, the first memory 133, the second memory 134, the third memory 135, and the fourth memory 136.

[0029] The first CPU 131 can use the first memory 133 and the second memory 134 as working memory. The second CPU 132 can use the third memory 135 and the fourth memory 136 as working memory. The first CPU 131 and the second CPU 132 can execute an operating system and various applications. The first CPU 131 and the second CPU 132 can control the components of the power receiver 120. For example, the first CPU 131 and the second CPU 132 can control the components of the power receiver 120 based on PCIe.

[0030] The first CPU 131 and the second CPU 132 can access the first SSD backplane 140, the second SSD backplane 150, and the third SSD backplane 160. For example, the first CPU 131 and the second CPU 132 can access the first SSD backplane 140, the second SSD backplane 150, and the third SSD backplane 160 based on NVMe. The first memory 133, the second memory 134, the third memory 135, and the fourth memory 136 may include DIMM memories installed in DIMM slots.

[0031] The BMC 137 may be a separate system from the operating systems of the first CPU 131 and the second CPU 132. The BMC 137 may collect information from components of the electronic device 100 and may access these components. The BMC 137 may be based on a separate communication interface (e.g., PCIe) that is separate from the communication interfaces of the first CPU 131 and the second CPU 132. For example, the BMC 137 may be based on the Intelligent Platform Management Interface (IPMI). The communication interface of the BMC 137 may communicate with the communication interfaces of the first CPU 131 and the second CPU 132.

[0032] The first SSD backplane 140 can receive power PWR from the power supply 110, exchange signals SIG with the baseboard 130, and receive power signals PS from the baseboard 130. The first SSD backplane 140 can exchange signals SIG with the first CPU 131, the second CPU 132, or the BMC 137 of the baseboard 130, and receive power signals PS therefrom. A plurality of SSDs can be mounted in the first SSD backplane 140. This may mean that the first SSD backplane 140 includes a plurality of SSDs.

[0033] The first CPU 131 and the second CPU 132 of the baseboard 130 can access (e.g., write, read, and erase) the SSDs of the first SSD backplane 140 through the signal SIG. The BMC 137 of the baseboard 130 can monitor the first SSD backplane 140 through the signal SIG and can access and control the first SSD backplane 140. The first CPU 131, the second CPU 132, or the BMC 137 of the baseboard 130 can power on or off the first SSD backplane 140 by using the power signal PS.

[0034] The structures and operations of the second and third SSD backplanes 150 and 160 may be the same as those of the first SSD backplane 140. Therefore, additional description will be omitted to avoid redundancy.

[0035] The base plate 130 can independently power on or off the first SSD backplane 140, the second SSD backplane 150, and the third SSD backplane 160. For example, the services supported by the first SSD backplane 140, the second SSD backplane 150, and the third SSD backplane 160 can be different. When the electronic device 100 does not provide a specific service, the SSD backplane corresponding to the specific service can be powered off, and the remaining SSD backplanes can be powered on.

[0036] For example, the usage frequency of services supported by the first, second, and third SSD backplanes 140, 150, and 160 may be different for each time zone. In a time zone where the usage frequency of services supported by the first, second, and third SSD backplanes 140, 150, and 160 is low, at least one of the first, second, and third SSD backplanes 140, 150, and 160 may be powered off.

[0037] The cooling control board 170 may receive power PWR from the power supply 110. The cooling control board 170 may control the cooler 180 under the control of the baseboard 130. For example, the cooling control board 170 may control the cooler 180 under the control of the first CPU 131, the second CPU 132, or the BMC 137 of the baseboard 130. The cooling control board 170 may control the activation and deactivation of the operation of the cooler 180 and the intensity of cooling (e.g., fan speed RPM).

[0038] The cooler 180 can receive power PWR from the power supply 110. The cooler 180 can perform cooling under the control of the cooling control board 170, so that the temperature of the electronic device 100 is reduced. The cooler 180 may include a fan, but the embodiment is not limited thereto. The cooler 180 is not limited to the case where the cooler 180 is centrally arranged in one location. For example, the cooler 180 can be distributed and arranged in two or more locations. A portion of the cooler 180 can be attached to the chassis of the electronic device 100 and can inject external air into the electronic device 100. The remaining coolers 180 can be arranged at specific components and can be fully responsible for the cooling of specific components.

[0039] The sensor (SENS) 190 may receive power PWR from the power supply 110. The sensor 190 may be provided adjacent to components of the electronic device 100. The sensor 190 may collect various information under the control of the substrate 130 and may provide the collected information to the substrate 130.

[0040] For example, the sensor 190 may collect information under the control of the BMC 137 of the baseboard 130 and may provide the collected information to the BMC 137. The sensor 190 may provide the collected information to the BMC 137 through a sensor data repository (SDR) of the IPMI. For example, different record IDs may be assigned to the sensor 190. The sensor 190 may provide information to the BMC 137 based on the different record IDs. The sensor 190 may include various sensors such as a temperature sensor, a humidity sensor, and a vibration sensor.

[0041] Although Figure 1 , an example in which a specific number of CPUs and a specific number of memories are mounted in the substrate 130 is shown, but the number of CPUs and the number of memories are not limited thereto. Figure 1 A specific number of SSD backplanes is shown in FIG, but the number of SSD backplanes is not limited thereto. Figure 1 , the number of coolers is shown to be up to a certain number, but the number of coolers and coolers is not limited thereto. Figure 1 A specific number of sensors is shown in FIG, but the types of sensors and the number of sensors are not limited thereto.

[0042] Figure 2 140, the second SSD base plate 150, and the third SSD base plate 160. Figure 1 and Figure 2In order to reduce the size of the electronic device 100, the SSD can be closely mounted in each of the first SSD base plate 140, the second SSD base plate 150, and the third SSD base plate 160. In addition, in order to reduce the size of the electronic device 100, the first SSD base plate 140, the second SSD base plate 150, and the third SSD base plate 160 can be in close contact with each other.

[0043] When one of the first SSD backplane 140, the second SSD backplane 150, and the third SSD backplane 160 is powered off, the remaining SSD backplanes can be powered on. Due to heat generated by the powered-on SSD backplane, the temperature of the powered-off SSD backplane may increase. Due to heat convected by the cooler 180, the temperature of the powered-off SSD backplane may also increase.

[0044] When the temperature of the SSD backplane in the power-off state increases, the increased temperature accelerates the reduction in retention of the SSD installed in the power-off SSD backplane. The reduction in retention can be recovered by a retention recovery operation. However, when the SSD backplane is in the power-off state, the retention recovery operation is not performed. Therefore, due to the reduction in retention, data loss may occur in the SSD installed in the SSD backplane in the power-off state. In this way, the electronic device 100 according to the example embodiment can power on at least one SSD installed in the SSD backplane in the power-off state in response to the increase in the temperature of the power-off SSD backplane. The powered-on SSD can perform a retention recovery operation to recover the reduction in retention. Therefore, data loss due to the reduction in retention accelerated by the high temperature when the SSD backplane is in the power-off state can be prevented.

[0045] Figure 3 An SSD backplane 200 according to a first example embodiment is shown.

[0046] The SSD backplane 200 may correspond to Figure 1 The first SSD backplane 140, the second SSD backplane 150 and the third SSD backplane 160. Figure 1 and Figure 3 The SSD backplane 200 may include first to fourth SSD slots 211, 212, 213, and 214. However, the number of slots is not limited. A corresponding SSD may be installed in each of the first SSD slot 211, the second SSD slot 212, the third SSD slot 213, and the fourth SSD slot 214. The SSD may exchange signals SIG with the substrate 130 via signal lines.

[0047] The SSD base plate 200 may include first to fourth bi-metals 221, 222, 223 and 224 corresponding to the first to fourth SSD slots 211, 212, 213 and 214, respectively, and may include first to fourth regulators 231, 232, 233 and 234 corresponding to the first to fourth SSD slots 211, 212, 213 and 214, respectively.

[0048] Each of the first bimetal 221, the second bimetal 222, the third bimetal 223, and the fourth bimetal 224 can include two separate materials (or metals) bonded together and having different coefficients of thermal expansion. In response to an increase in temperature, the material with the larger coefficient of thermal expansion can expand more than the material with the smaller coefficient of thermal expansion. Therefore, each of the first bimetal 221, the second bimetal 222, the third bimetal 223, and the fourth bimetal 224 can bend toward the material with the smaller coefficient of thermal expansion when heated. Conversely, in response to a decrease in temperature, the material with the larger coefficient of thermal expansion can contract more than the material with the smaller coefficient of thermal expansion. Therefore, each of the first bimetal 221, the second bimetal 222, the third bimetal 223, and the fourth bimetal 224 can bend toward the material with the larger coefficient of thermal expansion when cooled.

[0049] The first bimetal 221, the second bimetal 222, the third bimetal 223 and the fourth bimetal 224 can be respectively arranged adjacent to the first SSD slot 211, the second SSD slot 212, the third SSD slot 213 and the fourth SSD slot 214, so that the first bimetal 221, the second bimetal 222, the third bimetal 223 and the fourth bimetal 224 can bend in response to the temperature of the first SSD slot 211, the second SSD slot 212, the third SSD slot 213 and the fourth SSD slot 214.

[0050] The first bimetal 221, the second bimetal 222, the third bimetal 223, and the fourth bimetal 224 can receive voltages from the first regulator 231, the second regulator 232, the third regulator 233, and the fourth regulator 234, respectively. In response to an increase in temperature, the first bimetal 221, the second bimetal 222, the third bimetal 223, and the fourth bimetal 224 can bend to connect to the terminals of the first regulator 231, the second regulator 232, the third regulator 233, and the fourth regulator 234 (or, to be spaced apart from or disconnected from the terminals of the first regulator 231, the second regulator 232, the third regulator 233, and the fourth regulator 234 (for example, the contacts can be normally open or normally closed, and appropriate logic can be implemented accordingly)). Therefore, the first bimetal 221, the second bimetal 222, the third bimetal 223, and the fourth bimetal 224 may return (or may not return) the voltage received from the first regulator 231, the second regulator 232, the third regulator 233, and the fourth regulator 234 to the first regulator 231, the second regulator 232, the third regulator 233, and the fourth regulator 234. Conversely, in response to a decrease in temperature, the first bimetal 221, the second bimetal 222, the third bimetal 223, and the fourth bimetal 224 may bend to be spaced apart from (or attached to) the terminals of the first regulator 231, the second regulator 232, the third regulator 233, and the fourth regulator 234. Therefore, the first bimetal 221, the second bimetal 222, the third bimetal 223 and the fourth bimetal 224 can not return (or can return) the voltage received from the first regulator 231, the second regulator 232, the third regulator 233 and the fourth regulator 234 to the first regulator 231, the second regulator 232, the third regulator 233 and the fourth regulator 234.

[0051] The SSD backplane 200 may be powered on or off in response to a power signal PS from the substrate 130. When the SSD backplane 200 is powered on, the first regulator 231, the second regulator 232, the third regulator 233, and the fourth regulator 234 may supply power to the SSDs in the first SSD slot 211, the second SSD slot 212, the third SSD slot 213, and the fourth SSD slot 214. When the SSD backplane 200 is powered off, the first regulator 231, the second regulator 232, the third regulator 233, and the fourth regulator 234 may prevent power from being supplied to the SSDs in the first SSD slot 211, the second SSD slot 212, the third SSD slot 213, and the fourth SSD slot 214.

[0052] When the SSD backplane 200 is powered off, the first regulator 231, the second regulator 232, the third regulator 233, and the fourth regulator 234 can monitor whether a voltage is delivered from the first bimetal 221, the second bimetal 222, the third bimetal 223, and the fourth bimetal 224. When no voltage (or a voltage) is delivered, the first regulator 231, the second regulator 232, the third regulator 233, and the fourth regulator 234 can maintain a power interruption. When a voltage (or no voltage) is delivered, the first regulator 231, the second regulator 232, the third regulator 233, and the fourth regulator 234 can supply power to the SSDs of the first SSD slot 211, the second SSD slot 212, the third SSD slot 213, and the fourth SSD slot 214.

[0053] Each of the first regulator 231, the second regulator 232, the third regulator 233, and the fourth regulator 234 can include a capacitor "C" that stores power. When the ambient temperature is sufficiently high, i.e., a voltage is delivered (or no voltage is delivered) from one of the first bimetal 221, the second bimetal 222, the third bimetal 223, and the fourth bimetal 224, the corresponding regulator can supply power to the corresponding SSD. In the case where no voltage is delivered (or a voltage is delivered) from one bimetal due to a decrease in the ambient temperature before the completion of the hold recovery operation of the corresponding SSD, the corresponding regulator can prevent power supply to the corresponding SSD. In this case, the corresponding SSD can complete the hold recovery operation by using the power stored in the capacitor "C". For example, the capacitor "C" can be connected with an output terminal of the output power PWR of the corresponding regulator.

[0054] In an example embodiment, the first regulator 231, the second regulator 232, the third regulator 233, and the fourth regulator 234 can prevent or supply power in response to a common power signal PS. In another embodiment, the first regulator 231, the second regulator 232, the third regulator 233, and the fourth regulator 234 can independently prevent or supply power in response to different power signals PS, respectively.

[0055] The first regulator 231, the second regulator 232, the third regulator 233, and the fourth regulator 234 can be powered on or off in response to a power signal PS from the first CPU 131, the second CPU 132, or the BMC 137 of the substrate 130. The first regulator 231, the second regulator 232, the third regulator 233, and the fourth regulator 234 can be integrated into one regulator.

[0056] In example embodiments, the first, second, third, and fourth regulators 231 , 232 , 233 , and 234 may be replaced with power switches that operate in response to the power signal PS and voltages from the first, second, third, and fourth bimetals 221 , 222 , 223 , and 224 .

[0057] Figure 4 A first example of an operating method of the electronic device 100 according to an exemplary embodiment is shown. Figure 4 2 shows an operating method for an SSD installed in one SSD slot (eg, the first SSD slot 211 ).

[0058] Reference Figure 1 、 Figure 3 and Figure 4 In operation S110, the substrate 130 may request the SSD backplane (eg, 140) to power off through a power signal PS. The power signal PS may be transmitted based on one of various communication interfaces such as PCIe, NVMe, and IPMI.

[0059] In operation S120, the first SSD backplane 140 may block power supply to the SSD to shut down the power supply. While the SSD is powered off, in operation S130, a regulator (e.g., the first regulator 231) may supply voltage to the first bimetal 221 disposed adjacent to the first SSD slot 211 and determine whether voltage is transmitted from the first bimetal 221.

[0060] When the first bimetal 221 does not transmit voltage (or the second bimetal 221 transmits voltage) and the bimetal signal is deactivated, the first regulator 231 may maintain power interruption. When the first bimetal 221 transmits voltage (or no voltage) and the bimetal signal is activated, operation S140 is performed. In operation S140, the first regulator 231 may supply power to the SSD in the first SSD slot 211 to power on.

[0061] In operation S150, in response to the SSD being powered on, the SSD may perform communication initialization with the substrate 130. Communication initialization may include the following initializations for communication of the signal SIG between the substrate 130 and the SSD: timing adjustment, terminal resistance adjustment, and signal strength adjustment. Prior to or in parallel with communication initialization, the SSD may perform internal initialization. Internal initialization may include initialization of internal operations of the SSD: loading firmware and setting internal voltage levels.

[0062] In operation S160, the powered-on SSD may perform a retention recovery operation as a background operation. For example, the retention recovery operation may include a detection operation for detecting the retained data by reading the data and a recovery operation for rewriting the retained data to another location. The SSD may schedule the retention recovery operation according to an internal algorithm and execute the retention recovery operation according to the schedule.

[0063] Can be executed in parallel for each SSD belonging to the powered-off SSD backplane Figure 4 The operation shown. When the temperature drops while performing background operations, power can be blocked. In this case, each SSD can perform a hold-and-recovery operation using the power charged in capacitor "C." While maintaining high temperature and continuous power supply, the SSD can perform a hold-and-recovery operation two or more times based on an internal given algorithm.

[0064] In an example embodiment, each SSD may include a temperature sensor, and each SSD may schedule a retention recovery operation according to an internal given algorithm based on the temperature sensed by the temperature sensor, and may perform the retention recovery operation according to the schedule.

[0065] Figure 5 A second example of an operating method of the electronic device 100 according to an exemplary embodiment is shown.

[0066] Reference Figure 1 、 Figure 3 and Figure 5 , with Figure 4 Operations S210 , S220 , S230 , and S240 are performed in the same manner as operations S110 , S120 , S130 , and S140 . Therefore, additional description will be omitted to avoid redundancy.

[0067] After the regulator (e.g., the first regulator 231) powers on the SSD installed in the first SSD slot 211, the baseboard 130 may not perform communication initialization with the SSD. In example embodiments, even if the SSD (or SSD backplane) powered off by the baseboard 130 requests communication initialization, or a communication initialization process is performed, the baseboard 130 may ignore the request or process for communication initialization.

[0068] In operation S250, in response to the lack of communication initialization, the SSD may perform a retention recovery operation. In response to the lack of communication initialization, the SSD may recognize that power is temporarily turned on due to a temperature increase. After powering on, the SSD may immediately perform the retention recovery operation and may quickly detect a decrease in retention, thereby quickly preventing data loss caused by the decrease in retention.

[0069] In another example embodiment, even if communication initialization is not performed, each SSD may schedule a retention recovery operation as a background operation according to an internal given algorithm and may perform the scheduled retention recovery operation.

[0070] Figure 6 A third example of an operating method of the electronic device 100 according to an exemplary embodiment is shown.

[0071] Reference Figure 1 、 Figure 3 and Figure 6 , with Figure 4 Operations S310 , S320 , S330 , S340 , and S350 are performed in the same manner as operations S110 , S120 , S130 , S140 , and S150 . Therefore, additional description will be omitted to avoid redundancy.

[0072] In response to the communication initialization in operation S350, the first CPU 131, the second CPU 132, or the BMC 137 of the baseboard 130 may recognize that the SSD installed in the SSD slot (e.g., the first SSD slot 211) is powered on. In response to the SSD of the powered-off SSD backplane (e.g., the first SSD backplane 140) being powered on, the baseboard 130 may recognize that the SSD is powered on due to a temperature increase.

[0073] In operation S360, the substrate 130 may request the powered SSD to perform a retention recovery operation. The substrate 130 may request the powered SSD to perform a retention recovery operation through a signal SIG. In operation S370, the powered SSD may perform a retention recovery operation in response to the request from the substrate 130.

[0074] In the above description, the substrate 130 recognizes a temperature increase through communication initialization (operation S350). However, the manner in which the substrate 130 recognizes a temperature increase is not limited. For example, in response to the bimetal signal being activated (operation S330), the regulator (e.g., the first regulator 231) may notify the substrate 130 of the temperature increase via a separate signal line. The separate signal line may be based on one of various communication interfaces such as PCIe, NVMe, and IPMI.

[0075] When the substrate 130 transmits the retention recovery request in operation S360, the substrate 130 may transmit additional information to the powered SSD. For example, the substrate 130 may provide the powered SSD with environmental information (such as temperature information) and additional information that affects the retention of the powered SSD. The powered SSD may perform a retention recovery operation based on the information from the substrate 130.

[0076] In an example embodiment, when the temperature increase is identified, the substrate 130 can enable the cooling control board 170 to intensify cooling of the cooler 180 in operation S395. In an example embodiment, a reference temperature for intensifying cooling can be different from a reference temperature for powering on the SSD. The reference temperature for cooling and the reference temperature for powering on can be implemented differently by respectively providing a bimetal corresponding to the reference temperature for cooling and a bimetal corresponding to the reference temperature for powering on. The reference temperature for cooling can be lower or higher than the reference temperature for powering on.

[0077] Figure 7 An SSD backplane 300 according to a second example embodiment is illustrated.

[0078] The SSD backplane 300 can correspond to Figure 1 the first, second, and third SSD backplanes 140, 150, and 160 of FIG. 1. Referring to Figure 1 and Figure 7 , the SSD backplane 300 can include first to fourth SSD slots 311, 312, 313, and 314. SSDs installed in the first to fourth SSD slots 311, 312, 313, and 314 can exchange a signal SIG with the substrate 130 through a signal line.

[0079] In contrast to Figure 3 , one bimetal 321 or 322 can be disposed adjacent to two SSD slots 311 and 312, or 313 and 314. Also, one regulator 331 or 332 can supply power PWR to two SSD slots 311 and 312, or 313 and 314, can supply a voltage to one bimetal 321 or 322, and can determine whether a voltage is received from one bimetal 321 or 322.

[0080] Accordingly, when the temperature increases in a state in which the SSD backplane 300 is in a powered-off state, two or more SSDs can be powered on together. Each of the powered-on SSDs can perform a hold recovery operation. Thereafter, when the temperature decreases again, two or more SSDs can be powered off together. When a hold recovery operation of at least one of the two or more SSDs is not completed, the at least one SSD can continue the hold recovery operation by using power stored in a capacitor "C".

[0081] Figure 8 An SSD backplane 400 according to a third example embodiment is illustrated. The SSD backplane 400 can correspond to Figure 1 the first, second, and third SSD backplanes 140, 150, and 160 of FIG. 1.

[0082] Referring to Figure 1 and Figure 8 The SSD backplane 400 may include first to fourth SSD slots 411, 412, 413, and 414. However, the number of slots is not limited. An SSD may be installed in each of the first SSD slot 411, the second SSD slot 412, the third SSD slot 413, and the fourth SSD slot 414. The SSD may exchange signals SIG with the substrate 130 via signal lines.

[0083] The SSD backplane 400 may include first to fourth sensors 421, 422, 423, and 424 corresponding to the first to fourth SSD slots 411, 412, 413, and 414, respectively, and may include first to fourth regulators 431, 432, 433, and 434 corresponding to the first to fourth SSD slots 411, 412, 413, and 414, respectively. The first sensor 421, the second sensor 422, the third sensor 423, and the fourth sensor 424 may be temperature sensors. Each of the first sensor 421, the second sensor 422, the third sensor 423, and the fourth sensor 424 may periodically sense the ambient temperature and may transmit information about the sensed temperature to the base plate 130.

[0084] For example, each of the first sensor 421, the second sensor 422, the third sensor 423, and the fourth sensor 424 may transmit temperature information to the BMC 137 of the baseboard 130 based on the communication interface of the IPMI. The temperature information may be transmitted to the BMC 137 through the sensor data repository (SDR) field of the IPMI message. In an example embodiment, the first sensor 421, the second sensor 422, the third sensor 423, and the fourth sensor 424 may be Figure 1 Among the sensors 190 , a sensor is provided on the SSD baseboard 400 .

[0085] The SSD backplane 400 can be powered on or off in response to a power signal PS from the substrate 130. When the SSD backplane 400 is powered on, the first regulator 431, the second regulator 432, the third regulator 433, and the fourth regulator 434 can supply power to the SSDs in the first SSD slot 411, the second SSD slot 412, the third SSD slot 413, and the fourth SSD slot 414. When the SSD backplane 400 is powered off, the first regulator 431, the second regulator 432, the third regulator 433, and the fourth regulator 434 can prevent power from being supplied to the SSDs in the first SSD slot 411, the second SSD slot 412, the third SSD slot 413, and the fourth SSD slot 414.

[0086] The BMC 137 can monitor whether the temperature of the SSD is greater than a critical value based on the temperature information transmitted from the first sensor 421, the second sensor 422, the third sensor 423, and the fourth sensor 424. When the temperature of the SSD is equal to or less than the critical value, the SSDs of the powered-off SSD backplane 400 can remain powered-off. When the temperature of a specific SSD is greater than the critical value, the first CPU 131, the second CPU 132, or the BMC 137 of the baseboard 130 can control the corresponding regulator via the corresponding power signal PS to supply power to the specific SSD.

[0087] Each of the first regulator 431, the second regulator 432, the third regulator 433, and the fourth regulator 434 may include a capacitor "C" to store power. When the ambient temperature is higher than a critical value, the corresponding regulator may supply power to the corresponding SSD. If the ambient temperature decreases before the maintenance recovery operation of the corresponding SSD is completed, the corresponding regulator may prevent power from being supplied to the corresponding SSD. In this case, the corresponding SSD can complete the maintenance recovery operation by using the power stored in the capacitor "C". Therefore, the capacitor "C" may be connected to the output terminal of the output power PWR of the corresponding regulator.

[0088] In example embodiments, the first regulator 431 , the second regulator 432 , the third regulator 433 , and the fourth regulator 434 may be replaced with power switches that operate in response to the power signal PS.

[0089] Figure 9 A fourth example of a method of operating the electronic device 100 according to an exemplary embodiment is shown. In an exemplary embodiment, Figure 9 An operating method for an SSD installed in one SSD slot (eg, the first SSD slot 411 ) is shown.

[0090] Reference Figure 1 、 Figure 8 and Figure 9 In operation S410, the base plate 130 may request the SSD backplane (eg, the first SSD backplane 140) to be powered off through a power signal PS. The power signal PS may be transmitted based on one of various communication interfaces such as PCIe, NVMe, and IPMI.

[0091] In operation S420, the first SSD backplane 140 may block power supply to the SSD to shut down the SSD. While the SSD is powered off, in operation S430, a sensor (e.g., first sensor 421) mounted in the SSD backplane 400 may periodically transmit temperature information to the BMC 137 of the baseboard 130. The BMC 137 may receive the temperature information and record the received temperature information.

[0092] In operation S440 , the first CPU 131 , the second CPU 132 , or the BMC 137 of the base 130 may determine whether the temperature of the SSD is greater than a critical value. When the temperature of the SSD is not greater than the critical value, the base 130 may not perform separate control on the SSD baseplate 400 .

[0093] When the temperature of the SSD is greater than the critical value, in operation S450, the base plate 130 may request power on of the SSD in the SSD backplane 400. The power on request may be transmitted using the power signal PS. In operation S460, the first regulator 431 may supply power to the SSD in the first SSD slot 411 to power on.

[0094] In operation S470, in response to the SSD being powered on, the SSD may perform communication initialization with the substrate 130. Before, after, or in parallel with the communication initialization, the SSD may perform internal initialization.

[0095] In operation S480, the powered-on SSD may perform a retention recovery operation as a background operation. For example, the retention recovery operation may include a detection operation for detecting the retained data by reading the data and a recovery operation for rewriting the retained data to another location. The SSD may schedule the retention recovery operation based on an internal algorithm and may perform the retention recovery operation according to the schedule.

[0096] Can be executed in parallel for each SSD belonging to the powered-off SSD backplane Figure 9 When the temperature drops while performing background operations, power can be blocked. In this case, each SSD can perform a hold recovery operation using the power stored in capacitor "C." While power is continuously supplied due to the high temperature being maintained, the SSD can perform a hold recovery operation two or more times based on an internal algorithm.

[0097] In an example embodiment, each SSD may include a temperature sensor, and each SSD may schedule a retention recovery operation according to an internal given algorithm based on the temperature sensed by the temperature sensor, and may perform the retention recovery operation according to the schedule.

[0098] In an example embodiment, upon detecting a temperature increase, the base plate 130 may enable the cooling control board 170 to enhance cooling of the cooler 180 in operation S495. In an example embodiment, the reference temperature for enhancing cooling may be different from the reference temperature for powering on the SSD. The base plate 130 may compare the temperature of the SSD with two different critical values ​​so that the reference temperature for cooling and the reference temperature for powering on are achieved differently. The reference temperature for cooling may be lower or higher than the reference temperature for powering on.

[0099] Figure 10 A fifth example of an operating method of the electronic device 100 according to an exemplary embodiment is shown. Figure 1 、 Figure 8 and Figure 10 , operations S510, S520, S530, S540, S550, S560, and S595 may be performed with Figure 9 Operations S410, S420, S430, S440, S450, S460, and S495 are identically performed. Therefore, additional description will be omitted to avoid repetition.

[0100] The base board 130 may not perform communication initialization with the SSD after the regulator (e.g., the first regulator 431) powers off the SSD installed in the first SSD slot 211. In example embodiments, even if communication initialization is requested by the SSD that is powered off due to temperature increase, or when a process for communication initialization is performed, the base board 130 may ignore the request or process for communication initialization.

[0101] In operation S570, in response to the lack of communication initialization, the SSD may perform a retention recovery operation. Due to the lack of communication initialization, the SSD may recognize that power was temporarily turned on due to a temperature increase. Upon powering on, the SSD may immediately perform a retention recovery operation and quickly detect a decrease in retention, thereby quickly preventing data loss caused by the decrease in retention.

[0102] In another example embodiment, even if communication initialization is not performed, each SSD may schedule a retention recovery operation as a background operation according to an internal given algorithm and may perform the scheduled retention recovery operation.

[0103] Figure 11 A sixth example of an operating method of the electronic device 100 according to an exemplary embodiment is shown. Figure 1 、 Figure 8 and Figure 11 , operations S610, S620, S630, S640, S650, S660, S670, and S695 may be performed with Figure 9 Operations S410, S420, S430, S440, S450, S460, S470, and S495 are identically performed. Therefore, additional description will be omitted to avoid redundancy.

[0104] In operation S680, the substrate 130 may request the powered SSD to perform a retention recovery operation. The substrate 130 may request the powered SSD to perform a retention recovery operation through a signal SIG. In operation S690, the powered SSD may perform a retention recovery operation in response to the request from the substrate 130.

[0105] When the substrate 130 transmits the retention recovery request in operation S680, the substrate 130 may transmit additional information to the powered SSD. For example, the substrate 130 may provide the powered SSD with environmental information (such as temperature information) and additional information that affects the retention of the powered SSD. The powered SSD may perform a retention recovery operation based on the information from the substrate 130.

[0106] Figure 12 FIG. 7 shows a seventh example of an operating method of the electronic device 100 according to an exemplary embodiment. Figure 1 、 Figure 8 and Figure 12 , operation S710, operation S720, operation S730, operation S750, operation S760, operation S770, operation S780 and operation S795 can be Figure 9 Operations S410, S420, S430, S450, S460, S470, S480, and S495 are identically performed. Therefore, additional description will be omitted to avoid redundancy.

[0107] Before powering off the SSD backplane 400, the first CPU 131, the second CPU 132, or the BMC 137 of the baseboard 130 may request wear information from the SSD in operation S701. In operation S702, the SSD may transmit the wear information to the baseboard 130. Thereafter, the baseboard 130 may request power off in operation S710.

[0108] Wear information may indicate wear of the SSD due to operations such as programming and erasing. As wear progresses, the SSD's retention characteristics may degrade. Before powering off the SSD, substrate 130 may collect the SSD's wear information and adjust a critical value based on the wear information. Subsequently, if it is determined in operation S740 that the temperature is greater than the adjusted critical value, substrate 130 may request the SSD to be powered on (operation S750).

[0109] In an example embodiment, the wear information may include SMART (Self-Monitoring Analysis and Reporting Technology) information of the SSD. The wear information may be collected based on IPMI. Specifically, the wear information may be collected by using the SDR field of the IPMI message.

[0110] In an example embodiment, the configuration of collecting wear information in operations S701 and S702 and the configuration of using the adjusted critical value in operation S740 may also be applied to Figure 10 and Figure 11 Example of .

[0111] Figure 13 An example of program / erase (PE) cycles and adjusted threshold values ​​is shown as an example of wear information. Figure 1 and Figure 13 When the number of PE cycles is equal to or less than 0.1K, the critical value may be 80; when the number of PE cycles exceeds 0.1K and is equal to or less than 1K, the critical value may be 70; when the number of PE cycles exceeds 1K and is equal to or less than 3K, the critical value may be 60; when the number of PE cycles exceeds 3K and is equal to or less than 5K, the critical value may be 50; when the number of PE cycles exceeds 5K and is equal to or less than 7K, the critical value may be 40; when the number of PE cycles exceeds 7K and is less than or equal to 10K, the critical value may be 30. As the number of PE cycles increases, the wear degree of the SSD may increase and the critical value may decrease.

[0112] The substrate 130 according to example embodiments may further compare the temperature with a cautious value less than a critical value. When the number of PE cycles is equal to or less than 0.1K, the cautious value may be 70; when the number of PE cycles exceeds 0.1K and is equal to or less than 1K, the cautious value may be 60; when the number of PE cycles exceeds 1K and is equal to or less than 3K, the cautious value may be 50; when the number of PE cycles exceeds 3K and is equal to or less than 5K, the cautious value may be 40; when the number of PE cycles exceeds 5K and is equal to or less than 7K, the cautious value may be 30; and when the number of PE cycles exceeds 7K and is equal to or less than 10K, the cautious value may be 20.

[0113] In an example embodiment, when the temperature of the SSD is equal to or less than a critical value, and when the temperature of the SSD is greater than a caution value for an amount of time exceeding a given period of time, the base plate 130 may power on the SSD to instruct a retention recovery operation of the SSD (or request the SSD to perform a retention recovery operation). Therefore, a decrease in the retention of the SSD that occurs when the temperature of the SSD is equal to or less than the critical value but the SSD is left unattended for a long time at a temperature close to the critical value can be detected, and data loss due to the decrease in retention can be prevented.

[0114] Figure 14 An eighth example of the operating method of the electronic device 100 according to an exemplary embodiment is shown.

[0115] Reference Figure 1 、 Figure 8 and Figure 14 In operation S810 , the substrate 130 may receive temperature information from the first sensor 421 adjacent to one SSD slot (eg, the first SSD slot 411 ) of the SSD base plate 400 .

[0116] In operation S820, the substrate 130 may determine whether the temperature of the SSD is within a cautious value range. For example, the substrate 130 may determine whether the temperature of the SSD is equal to or less than a critical value and greater than a cautious value. If the temperature of the SSD is within the cautious value range, in operation S830, the substrate 130 may increase the SSD count.

[0117] In operation S840, the substrate 130 may determine whether the SSD count is greater than a threshold value. If the SSD count is not greater than the threshold value, the substrate 130 may not perform separate control on the SSD. If the SSD count is greater than the threshold value, the substrate 130 may request power on of the SSD in operation S850. In operation S860, the substrate 130 may reset the SSD count.

[0118] Operation S850 may correspond to Figure 9 Operation S450, Figure 10 Operation S550, Figure 11 Operation S650 and Figure 12 Operation S750 can be performed after operation S850. Figure 9 Operations after operation S452, Figure 10 Operations after operation S550, Figure 11 Operations after operation S650 or Figure 12 Operations after operation S750.

[0119] If it is determined in operation S820 that the temperature of the SSD is not within the cautious value range, the substrate 130 may determine whether the temperature of the SSD is within the critical value range in operation S870. For example, the substrate 130 may determine whether the temperature of the SSD is greater than the critical value. If the temperature is greater than the critical value, operation S850 may be performed.

[0120] When the temperature is not greater than the critical value, the substrate 130 may not perform separate control on the SSD. When the temperature is greater than the critical value, in operation S850, the substrate 130 may request power on of the SSD. In operation S860, the substrate 130 may reset the count of the SSD.

[0121] Whenever temperature information is received from a sensor (eg, the first sensor 421) corresponding to one SSD slot (eg, the first SSD slot 411) of the SSD backplane 400, the Figure 14In another embodiment, the first sensor 421 can transmit temperature information to the substrate 130 based on the first time period. The substrate 130 can perform a temperature measurement based on the second time period by using the most recently transferred temperature. Figure 14 The second time period may be longer than the first time period.

[0122] Figure 15 The SSD backplane 500 according to the fourth exemplary embodiment is shown. The SSD backplane 500 may correspond to Figure 1 The first SSD backplane 140, the second SSD backplane 150 and the third SSD backplane 160 are shown.

[0123] Reference Figure 1 and Figure 15 , the SSD base plate 500 may include first to fourth SSD slots 511, 512, 513, and 514. The SSDs installed in the first to fourth SSD slots 511, 512, 513, and 514 may exchange signals SIG with the substrate 130 through signal lines.

[0124] and Figure 8 In contrast, one sensor 521 or 522 may be provided adjacent to two SSD slots 511 and 512, or 513 and 514. In addition, one regulator 531 or 532 may provide power PWR to two SSD slots 511 and 512, or 513 and 514.

[0125] Therefore, when the temperature rises while the SSD backplane 500 is powered off, two or more SSDs can be powered on together. Each powered-on SSD can perform a hold-and-recovery operation. Thereafter, when the temperature drops again, the two or more SSDs can be powered off together. If the hold-and-recovery operation of at least one of the two or more SSDs is not completed, the at least one SSD can continue the hold-and-recovery operation by using the power stored in capacitor "C."

[0126] Figure 16 An SSD 600 is shown according to an example embodiment.

[0127] Reference Figure 16 , the SSD 600 may include a non-volatile memory device 610, a memory controller 620, and a buffer memory 630. The non-volatile memory device 610 may include a plurality of memory cells. Each of the plurality of memory cells may store two or more bits. For example, the non-volatile memory device 610 may include at least one of various non-volatile memory devices, such as a flash memory device, a phase change memory device, a ferroelectric memory device, a magnetic memory device, and a resistive memory device.

[0128] The storage controller 620 can receive various requests for writing data into or reading data from the nonvolatile storage device 610 from the electronic device 100. The storage controller 620 can store (or buffer) user data for communication with the electronic device 100 in the buffer memory 630, and can store metadata for managing the SSD 600 in the buffer memory 630.

[0129] The storage controller 620 can access the nonvolatile storage device 610 through the first channel CH1 and the second channel CH2. For example, the storage controller 620 can transmit a command and an address to the nonvolatile storage device 610 through the first channel CH1. The storage controller 620 can exchange data with the nonvolatile storage device 610 through the first channel CH1.

[0130] The storage controller 620 can transmit a first control signal to the nonvolatile storage device 610 through the second channel CH2. The storage controller 620 can receive a second control signal from the nonvolatile storage device 610 through the second channel CH2.

[0131] In an example embodiment, the storage controller 620 can be configured to control two or more nonvolatile storage devices. The storage controller 620 can provide a different first channel and a different second channel for each of the two or more nonvolatile storage devices.

[0132] In another example embodiment, the storage controller 620 can share one first channel with respect to two or more nonvolatile storage devices. The storage controller 620 can share a portion of the second channel CH2 with respect to the two or more nonvolatile storage devices, and can individually provide the remaining portion.

[0133] The buffer memory 630 can include a random access memory. For example, the buffer memory 630 can include at least one of a dynamic random access memory, a phase change random access memory, a ferroelectric random access memory, a magnetic random access memory, or a resistive random access memory.

[0134] The memory controller 620 can include a bus 621, a host interface 622, an internal buffer 623, a processor 624, a buffer controller 626, a storage manager 627, and an error correction code (ECC) block 628.

[0135] The bus 621 can provide a communication channel between components in the storage controller 620. The host interface 622 can receive various requests from the electronic device 100, and can parse the received requests. The host interface 622 can store the parsed requests to the internal buffer 623.

[0136] The host interface 622 can send various responses to the electronic device 100. The host interface 622 can exchange signals with the electronic device 100 according to a given communication protocol. The internal buffer 623 may include a random access memory. For example, the internal buffer 623 may include a static random access memory or a dynamic random access memory.

[0137] The processor 624 may drive an operating system or firmware for driving the storage controller 620. The processor 624 may read the parsed request stored in the internal buffer 623 and may generate a command and address for controlling the nonvolatile memory device 610. The processor 624 may pass the generated command and address to the storage manager 627.

[0138] The processor 624 may store various meta information for managing the SSD 600 in the internal buffer 623. The processor 624 may access the buffer memory 630 through the buffer controller 626. The processor 624 may control the buffer controller 626 and the storage manager 627 so that user data stored in the buffer memory 630 is transmitted to the nonvolatile memory device 610.

[0139] The processor 624 may control the host interface 622 and the buffer controller 626 so that the data stored in the buffer memory 630 is transmitted to the electronic device 100. The processor 624 may control the buffer controller 626 and the storage manager 627 so that the data received from the nonvolatile memory device 610 is stored in the buffer memory 630. The processor 624 may control the host interface 622 and the buffer controller 626 so that the data received from the electronic device 100 is stored in the buffer memory 630.

[0140] The processor 624 may include a retention controller (RC) 625. The retention controller 625 may control a retention recovery operation. The retention recovery operation may include a detection read and a recycle. The retention controller 625 may perform a detection read to detect whether the retention of data written to the non-volatile memory device 610 has been reduced. For example, the retention controller 625 may schedule a detection read according to an internal given algorithm and may execute the scheduled detection read.

[0141] In an example embodiment, the retention controller 625 may schedule a detection read based on temperature information obtained by the sensor 629, management information of the non-volatile memory device 610 including wear information included in metadata, and environmental information that can be transmitted from the electronic device 100. When a decrease in retention is detected during the detection read, the retention controller 625 may schedule a reclamation associated with the corresponding data. The reclamation may include a regular read to read the corresponding data and a regular write to write the read data to any other storage space. The detection read may be performed in a manner different from a regular read.

[0142] During power-on, the hold controller 625 can detect whether the electronic device 100 has been powered on due to a temperature increase. For example, when communication initialization is not being performed, the hold controller 625 can recognize that power-on has been performed due to a temperature increase. In this case, the hold controller 625 can immediately perform a detection read for a hold recovery operation. In another embodiment, the hold controller 625 can perform a detection read for a hold recovery operation in response to a hold recovery request received from the electronic device 100.

[0143] Under the control of the processor 624, the buffer controller 626 may write data into the buffer memory 630 or may read data from the buffer memory 630. The memory manager 627 may communicate with the nonvolatile memory device 610 through the first channel CH1 and the second channel CH2 under the control of the processor 624.

[0144] The error correction code block 628 may perform error correction encoding on data to be transmitted to the nonvolatile memory device 610 by using the error correction code ECC. The error correction code block 628 may perform error correction decoding on data received from the nonvolatile memory device 610 by using the error correction code ECC.

[0145] In example embodiments, the SSD 600 may not include the buffer memory 630 and the buffer controller 626. When the buffer memory 630 and the buffer controller 626 are not included in the SSD 600, the above-described functions of the buffer memory 630 and the buffer controller 626 may be performed by the internal buffer 623.

[0146] In the above embodiments, components are described using the terms "first," "second," "third," etc. However, the terms "first," "second," "third," etc. may be used to distinguish and identify components from one another. For example, the terms "first," "second," "third," etc. do not refer to any form of order or numerical meaning.

[0147] In the above embodiments, components are described using blocks. These blocks can be implemented using various hardware devices (such as integrated circuits, application-specific ICs (ASICs), field programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs)), firmware driven in hardware devices, software (such as applications), or a combination of hardware devices and software. In addition, these blocks may include circuits implemented using semiconductor elements in integrated circuits or circuits registered as intellectual property (IP).

[0148] To summarize and review, the property of data stored in nonvolatile memory is called "retention." Flash memory can store data in the form of threshold voltage, while phase-change memory, ferroelectric memory, magnetic memory, and resistive memory can store data in the form of resistance. Retention is maintained when the threshold voltage or resistance value remains within a predetermined range during write operations. Retention degrades when the threshold voltage or resistance value exceeds the expected range over time.

[0149] The SSD can detect a decrease in retention and perform a retention recovery operation to restore the decreased retention. This allows the SSD to prevent data stored in the non-volatile memory from being lost due to the decrease in retention. However, if the SSD is left unpowered, the retention recovery operation will not be performed. This could result in data stored in the non-volatile memory being lost due to the decrease in retention.

[0150] According to an exemplary embodiment, a solid-state drive in a high-temperature state (in which the reduction of retention is accelerated) can be powered on, and the powered-on solid-state drive can perform a retention recovery operation. Therefore, a solid-state drive that prevents data loss due to a reduction in retention, an electronic device including the solid-state drive, and a method for managing the solid-state drive are provided.

[0151] As described above, embodiments can provide a solid-state drive that avoids loss of retention due to external temperature, an electronic device including the solid-state drive, and a method for managing the solid-state drive. Embodiments can also provide a solid-state drive that prevents data loss due to decreased retention when left alone in a power-off state, an electronic device including the solid-state drive, and a method for managing the solid-state drive.

[0152] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, it will be apparent to those skilled in the art at the time of filing this application that features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically noted. Therefore, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. An electronic device comprising: a power supply configured to provide a first power and a second power; a first SSD backplane and a second SSD backplane, wherein the first SSD backplane and the second SSD backplane are configured to receive the first power from the power supply, and each of the first SSD backplane and the second SSD backplane includes two or more SSDs; as well as a baseboard configured to receive the second power from the power supply, power on or off the first SSD backplane and the second SSD backplane independently of each other, and access an SSD of the powered-on SSD backplane of the first SSD backplane and the second SSD backplane; In response to a temperature increase of the SSD baseboard in the power-off state among the first SSD baseboard and the second SSD baseboard, at least one SSD of the SSD baseboard in the power-off state is powered on.

2. The electronic device according to claim 1, wherein: The first SSD base plate and the second SSD base plate both include bimetal, and The temperature increase is detected based on the bimetal.

3. The electronic device according to claim 1, wherein The first SSD backplane and the second SSD backplane both include: a bimetal disposed adjacent to the SSD and configured to activate a signal in response to the temperature increase; and a regulator configured to receive the first power from the power supply and power on or off the SSD under the control of the substrate, The regulator changes the power-off state of the SSD adjacent to the bimetal to the power-on state in response to the bimetal activating the signal.

4. The electronic device according to claim 1, wherein The at least one SSD that is powered on performs a hold recovery operation as a background operation.

5. The electronic device according to claim 1, wherein The at least one SSD that is powered on performs a retention recovery operation in response to a lack of communication initialization with the substrate.

6. The electronic device according to claim 5, wherein: The substrate transmits a hold recovery request to the at least one powered-on SSD, and The at least one SSD that is powered on performs the preservation recovery operation in response to the preservation recovery request. 7 . The electronic device of claim 1 , further comprising a cooler, wherein the substrate increases cooling of the cooler in response to the temperature increase.

8. The electronic device according to claim 7, wherein: The temperature used to power on the at least one SSD and the temperature used to increase the cooling are different.

9. The electronic device according to claim 1, wherein: The first SSD backplane and the second SSD backplane each include a temperature sensor configured to transmit temperature information to the substrate, and The temperature increase is detected based on the temperature information.

10. The electronic device according to claim 1, wherein The first SSD backplane and the second SSD backplane both include: a temperature sensor disposed adjacent to the SSD and configured to transmit temperature information of the temperature increase to the substrate; and a regulator configured to receive the first power from the power supply and power on or off the SSD under the control of the substrate, When the temperature information indicates that the temperature is greater than a critical value, the substrate controls the regulator to power on the SSD adjacent to the temperature sensor.

11. The electronic device according to claim 10, wherein: The substrate adjusts the critical value based on a number of program / erase cycles of a specific SSD of the SSD backplane in a powered-off state.

12. The electronic device according to claim 11, wherein As the number of program / erase cycles for the particular SSD increases, the substrate decreases the threshold value.

13. The electronic device according to claim 11, wherein The substrate collects the program / erase cycle count of the specific SSD when the SSD backplane including the specific SSD is powered off.

14. The electronic device according to claim 11, wherein The baseboard includes a baseboard management controller configured to collect the program / erase cycle count and the temperature information of the specific SSD through a management interface.

15. The electronic device according to claim 10, wherein The substrate enables the regulator to power on the SSD adjacent to the temperature sensor when the temperature is greater than a cautionary temperature value for a time greater than a threshold time, the cautionary temperature value being less than the critical value.

16. The electronic device according to claim 15, wherein The substrate is configured as follows: When the temperature is greater than the caution temperature value, incrementing a count; and When the count is greater than a threshold, the SSD adjacent to the temperature sensor is powered on.

17. The electronic device according to claim 16, wherein: The substrate resets the count when the SSD adjacent to the temperature sensor is powered on.

18. A method for managing a solid state drive (SSD), the method comprising: Powering off the SSD; In response to an increase in the ambient temperature of the SSD, powering on the SSD; as well as A persist recovery operation is performed at the SSD.

19. The method according to claim 18, further comprising: Cooling is increased in response to an increase in the ambient temperature of the SSD.

20. A solid state drive comprising: A nonvolatile memory device, the nonvolatile memory device comprising a plurality of memory blocks, each of the memory blocks comprising a plurality of memory cells; as well as a controller including a temperature sensor and configured to perform a retention recovery operation on the plurality of memory blocks when a temperature sensed by the temperature sensor is greater than a critical value, wherein, upon power-on, the controller performs the hold-recovery operation in response to no communication initialization with an external host device, or Wherein, after power-on, the controller performs the hold recovery operation in response to a request of the external host device.

Images