Storage System and Method for Balancing Four-Level Unit Encoding

Abstract

Provided are a storage system and method for balanced quad-level cell (QLC) encoding with tolerance for internal data load (IDL) reads. In one instance, an MLC fine programming method uses balanced 3-4-4-4 encoding, where data is encoded by assigning a unique binary sequence to each state. IDL reads are supported by using the unique 3-4-4-4 encoding that provides at least a three-state gap between MLC states, while using the same ECC redundancy per page. This reduces the write buffer by supporting IDL reads and also provides a balanced bit error rate (BER) due to the balanced mapping.

Description

BACKGROUND OF THE INVENTION

[0001] When writing data to a non-volatile memory having a multi-level cell (MLC) configuration, this process is typically achieved by storing each of the multiple bits of a cell in a random access memory (RAM) in a memory controller for all cells in a full word line in the memory, and then performing a multi-stage programming process for injecting charge into each multi-bit cell to achieve the desired programmed state of the cell. Generally, multi-stage programming involves an initial programming portion (i.e., the "Foggy" programming step) of programming the states with a widened voltage distribution, and a subsequent final programming (i.e., the "Fine" programming step) of all states with a tight voltage distribution. As part of this multi-step programming process, and for each of the multiple programming steps, the memory in the controller can store copies of all data bits to be programmed in the cells and process error correction code (ECC) bits of the data. In cases where the data programmed in the Foggy programming step can be read from the memory array without error or this data can be reliably decoded within the memory die to support subsequent Fine programming steps, the Foggy data does not need to be temporarily stored in the memory controller before the Fine step, and the size of the memory buffer within the memory controller can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1A is a block diagram of a non-volatile storage system of an embodiment.

[0003] Figure 1B is a block diagram showing a storage module of an embodiment.

[0004] Figure 1C is a block diagram showing a hierarchical storage system of an embodiment.

[0005] Figure 2A is a block diagram showing components of a controller of a non-volatile storage system shown in Figure 1A in accordance with an embodiment.

[0006] Figure 2B is a block diagram showing components of a non-volatile storage system shown in Figure 1A in accordance with an embodiment.

[0007] Figure 3 is a chart and graph showing a 3-4-4-4 encoding of an embodiment.

[0008] Figure 4 is a flowchart of a method of an embodiment.

[0009] Figure 5 is a flowchart of another method of an embodiment.

[0010] Figure 6 It is a graph of a method of an embodiment for assisting a read operation using an encoding scheme. Detailed Description

[0011] Now turning to the drawings, a storage system suitable for implementing aspects of these embodiments is shown in Figures 1A to 1C . Figure 1A It is a block diagram showing a non-volatile storage system 100 (sometimes referred to herein as a storage device or simply as a device) according to an embodiment of the subject matter described herein. Referring to Figure 1A , the non-volatile storage system 100 includes a controller 102 and non-volatile memory, and the non-volatile memory may be composed of one or more non-volatile memory dies 104. As used herein, the term "die" refers to a collection of non-volatile memory cells formed on a single semiconductor substrate and associated circuitry for managing the physical operations of those non-volatile memory cells. The controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to the non-volatile memory die 104.

[0012] The controller 102 (which may be a non-volatile memory controller such as a flash memory, resistive random access memory (ReRAM), phase change memory (PCM), or magnetoresistive random access memory (MRAM) controller) may take the form of processing circuitry, a microprocessor, or a processor and a computer-readable medium storing computer-readable program code (such as firmware) that can be executed by, for example, a (micro)processor, logic gates, switches, application-specific integrated circuit (ASIC), programmable logic controller, and embedded microcontroller. The controller 102 may be configured with hardware and / or firmware to perform the various functions described below and shown in the flowcharts. Also, some components shown to be within the controller may also be stored outside the controller and other components may be used. Additionally, the phrase "operably communicates with" may mean communicates directly with or communicates indirectly (wired or wireless) with via one or more components that may or may not be shown or described herein.

[0013] As used herein, a non-volatile memory controller is a device that manages data stored on non-volatile memory and communicates with a host such as a computer or an electronic device. The non-volatile memory controller may have various functionalities in addition to the specific functionalities described herein. For example, the non-volatile memory controller may format the non-volatile memory to ensure proper operation of the memory, map out bad non-volatile memory cells, and allocate spare cells to replace future failing cells. A portion of the spare cells may be used to store firmware to operate the non-volatile memory controller and implement other features. In operation, when the host needs to read data from or write data to the non-volatile memory, the host may communicate with the non-volatile memory controller. If the host provides a logical address to read / write data, the non-volatile memory controller may convert the logical address received from the host into a physical address in the non-volatile memory. (Alternatively, the host may provide a physical address). The non-volatile memory controller may also perform various memory management functions such as, but not limited to, wear leveling (distributing writes to avoid wearing out a particular memory block that would otherwise be repeatedly written to) and garbage collection (after a block is full, moving only the valid data pages to a new block so that the full block can be erased and reused). Also, the structure of the "component" recited in the claims may include some or all of the structure of the controller described herein, the structure being programmed or fabricated to cause the controller to operate to perform the recited function.

[0014] The non-volatile memory die 104 may include any suitable non-volatile memory medium, including resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), phase change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells may take the form of solid-state (e.g., flash) memory cells and may be once-programmable, few-times-programmable, or many-times-programmable. The memory cells may also be single-level cells (SLCs), multi-level cells (MLCs), three-level cells (TLCs), or other memory cell level technologies known today or developed in the future. Also, the memory cells may be fabricated in two dimensions or three dimensions.

[0015] The interface between the controller 102 and the non-volatile memory die 104 may be any suitable flash interface, such as Toggle Mode 200, 400, or 800. In one embodiment, the storage system 100 may be a card-based system, such as a Secure Digital (SD) or Micro Secure Digital (Micro SD) card. In an alternative embodiment, the storage system 100 may be part of an embedded storage system.

[0016] Although in Figure 1AIn the example shown, the non-volatile storage system 100 (sometimes referred to herein as a storage module) includes a single channel between the controller 102 and the non-volatile memory die 104, but the subject matter described herein is not limited to having a single memory channel. For example, in some storage system architectures (such as Figure 1B and Figure 1C the storage system architectures shown), depending on the controller capabilities, there may be 2, 4, 8, or more memory channels between the controller and the memory devices. In any of the embodiments described herein, even if a single channel is shown in the figures, there may be more than a single channel between the controller and the memory die.

[0017] Figure 1B FIG. shows a storage module 200 that includes a plurality of non-volatile storage systems 100. As such, the storage module 200 may include a storage controller 202 that interfaces with a host and with the storage system 204, which includes a plurality of non-volatile storage systems 100. The interface between the storage controller 202 and the non-volatile storage system 100 may be a bus interface, such as a Serial Advanced Technology Attachment (SATA), a Peripheral Component Interconnect Express (PCIe) interface, or a Double Data Rate (DDR) interface. In one embodiment, the storage module 200 may be a Solid State Drive (SSD) or a Non-Volatile Dual In-line Memory Module (NVDIMM), such as those found in a server PC or a portable computing device (such as a laptop computer and a tablet computer).

[0018] Figure 1C FIG. is a block diagram showing a hierarchical storage system. The hierarchical storage system 250 includes a plurality of storage controllers 202, each of which controls a corresponding storage system 204. The host system 252 may access the memory within the storage system via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Express (NVMe) interface or an Ethernet Fibre Channel (FCoE) interface. In one embodiment, Figure 1C the system shown in FIG. may be a rack-mounted mass storage system that can be accessed by multiple host computers, such as those found in a data center or other locations that require mass storage devices.

[0019] Figure 2Ais a block diagram that more particularly illustrates the components of the controller 102. The controller 102 includes a front-end module 108 that interfaces with a host, a back-end module 110 that interfaces with one or more non-volatile memory dies 104, and various other modules that perform the functions that will be described in detail now. The modules can take the form of, for example, an encapsulated functional hardware unit designed to be used with other components, a portion of program code (such as software or firmware) executable by a (micro)processor or processing circuitry that typically performs a specific function of the related functions, or a self-contained hardware or software component that interfaces with a larger system. The controller 102 may sometimes be referred to herein as a NAND controller or a flash controller, but it should be understood that the controller 102 can be used with any suitable memory technology, and some examples of memory technologies are provided below.

[0020] Referring again to the modules of the controller 102, the buffer manager / bus controller 114 manages the buffers in the random access memory (RAM) 116 and controls the internal bus arbitration of the controller 102. The read-only memory (ROM) 118 stores the system boot code. Although shown as being separately located from the controller 102 in Figure 2A , in other embodiments, one or both of the RAM 116 and the ROM 118 may be located within the controller. In still other embodiments, portions of the RAM and the ROM may be located within and outside of the controller 102.

[0021] The front-end module 108 includes a host interface 120 that provides an electrical interface to a host or a next-level storage controller and a physical layer interface (PHY) 122. The choice of the type of the host interface 120 may depend on the type of the memory being used. Examples of the host interface 120 include but are not limited to SATA, SATA Express, Serial Attached Small Computer System Interface (SAS), Fibre Channel, Universal Serial Bus (USB), PCIe, and NVMe. The host interface 120 generally facilitates the transfer of data, control signals, and timing signals.

[0022] The backend module 110 includes an Error Correction Code (ECC) engine 124 that encodes data bytes received from a host and decodes and corrects errors in data bytes read from the non-volatile memory. A command sequencer 126 generates command sequences to be transmitted to the non-volatile memory die 104, such as programming and erase command sequences. An independent Redundant Array of Independent Drives (RAID) module 128 manages the generation of RAID parity and the recovery of failed data. The RAID parity can be used as an additional level of integrity protection for writing data to the memory device 104. In some cases, the RAID module 128 can be part of the ECC engine 124. A memory interface 130 provides the command sequences to the non-volatile memory die 104 and receives status information from the non-volatile memory die 104. In one embodiment, the memory interface 130 can be a Double Data Rate (DDR) interface, such as a toggle mode 200, 400, or 800 interface. A flash control layer 132 controls the overall operation of the backend module 110.

[0023] The storage system 100 also includes other discrete components 140, such as an external electrical interface, external RAM, resistors, capacitors, or other components that can interface with the controller 102. In an alternative embodiment, one or more of the physical layer interface 122, the RAID module 128, the media management layer 138, and the buffer management / bus controller 114 are optional components that are not necessarily in the controller 102.

[0024] Figure 2B is a block diagram that more particularly illustrates the components of the non-volatile memory die 104. The non-volatile memory die 104 includes a peripheral circuit 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells for storing data. The non-volatile memory cells can be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells in a two-dimensional and / or three-dimensional configuration. The non-volatile memory die 104 further includes a data cache 156 that caches data. The peripheral circuit 141 includes a state machine 152 that provides status information to the controller 102.

[0025] Returning again to Figure 2A, a flash control layer 132 (which will be referred to herein as a flash translation layer (FTL) or more generally as a "media management layer" when the memory may not be flash memory) handles flash errors and interfaces with the host. Specifically, the FTL, which can be an algorithm in firmware, is responsible for internal memory management and translates writes from the host into writes to the memory 104. Because the memory 104 may have limited durability, can only be written in multi-page form, and / or may not be written to unless the memory 104 is erased as a block, an FTL may be required. The FTL is aware of these potential limitations of the memory 104, which may not be visible to the host. Thus, the FTL attempts to translate writes from the host into writes in the memory 104.

[0026] The FTL can include a logical-to-physical address (L2P) mapping (sometimes referred to herein as a table or data structure) and an allocated cache memory. In this way, the FTL translates a logical block address ("LBA") from the host into a physical address in the memory 104. The FTL can include other features such as, but not limited to, power failure recovery (to enable recovery of the FTL's data structures in the event of a sudden power loss) and wear leveling (to make the wear on the storage blocks more even to prevent some blocks from wearing out excessively, which would lead to a greater probability of failure).

[0027] As mentioned above, when writing data to a non-volatile memory having a multi-level cell (MLC) configuration, this process is typically achieved by: storing each of the multiple bits of a cell in a random access memory (RAM) in a memory controller for all cells in a complete word line in the memory, and then performing a multi-stage programming process for injecting charge into each multi-bit cell to achieve the desired programmed state of the cell. Generally, the multi-stage programming involves an initial programming portion (i.e., the "fuzzy" programming step) of the states using a widened voltage distribution, and a subsequent final programming (i.e., the "fine" programming step) of all states using a tight voltage distribution. As part of this multi-step programming process, and for each of the multiple programming steps, the memory in the controller can store a copy of all the data bits to be programmed in the cell and process the error correction code (ECC) bits of the data. In the case where the data programmed in the fuzzy programming step can be read from the memory array without error or this data can be reliably decoded within the memory die to support the subsequent fine programming step, the fuzzy data does not need to be temporarily stored in the memory controller before the fine step, and the size of the memory buffer within the memory controller can be reduced. The fuzzy-fine programming scheme is well known for programming multi-level cell memories.

[0028] When error-free internal soft reads (i.e., internal data load (IDL) reads) within a memory die are not possible, soft data needs to be temporarily stored in a write buffer within the memory controller for reuse during the fine stage. The size of the memory write buffer required to implement soft-fine programming grows with the increase in the number of memory planes and strings, which is a general trend as memories progress from generation to generation in order to reduce memory costs. For example, a memory with 6 strings x 4 planes x 4 pages per 16KB may require a write buffer of approximately 1.5MB per memory die, which significantly increases the controller cost. Therefore, there is a great need for a scheme that allows reliable soft reads (IDL reads) within a memory die.

[0029] One such scheme is the MLC fine programming scheme, where two pages are programmed during the soft stage ("MLC" programming), and two pages are added during the fine stage. Such MLC fine programming significantly reduces the required write buffer to approximately 128KB to 256KB per die. Such a programming scheme requires tolerance for MLC internal data load (IDL) reads. IDL reads are used to read back memory cells after programming the first page / first few pages but before programming the second page / last few pages. This read can store the first page into a set of data latches on the memory chip and can load the first data page into the data latches without transferring data from the chip to the data latches.

[0030] However, not every state encoding can provide such tolerance. For example, Figure 6 the balanced 3-4-4-4 encoding shown above for QLC does not provide such tolerance. Unbalanced encodings such as 2-3-5-5 or 1-2-6-6 can provide tolerance for IDL reads but may result in unbalanced BER and tR for each page, which is undesirable. Therefore, in order to balance the BER and tR between pages, a state encoding with several balanced transitions per page (i.e., 3-4-4-4 encoding) may be required.

[0031] However, since QLC fuzzy-fine programming requires a large write buffer, MLC fine programming can be considered. Since MLC fine programming relies on the ability to perform IDL reads of MLC pages, it requires a much smaller write buffer, thus eliminating the need to store it in the controller write buffer. This can reduce the required write buffer size for QLC from 1536 KB to 128 KB to 256 KB. The problem is that almost all balanced 3-4-4-4 mappings are not well-suited for MLC fine programming because they do not provide enough tolerance for IDL reads. Unbalanced mappings such as 2-3-5-5 and 1-2-6-6 coding can provide a large tolerance for IDL reads, but result in an unbalanced bit error rate (BER) per page. Having an unbalanced BER per page means that more ECC redundancy is needed to achieve the same reliability (since ECC needs to handle the worst page). This in turn reduces the memory cost efficiency because more overhead needs to be allocated for ECC.

[0032] The following embodiments provide alternative 3-4-4-4 codings that provide high tolerance for MLC IDL reads. Generally, these embodiments disclose a method of MLC fine programming using balanced 3-4-4-4 coding, in which data is encoded by assigning a unique binary sequence per state. IDL reads (i.e., internal reads of MLC data) are supported by using a unique 3-4-4-4 coding that provides at least a three-state gap between MLC states, while using the same ECC redundancy per page. This reduces the write buffer by supporting IDL reads and also provides a balanced bit error rate (BER) due to the balanced mapping.

[0033] The following paragraphs explain the impact of state coding on the expected BER and the sensitivity of the BER to state positioning jitter, thus providing the motivation for using balanced state coding.

[0034] Regarding the impact of state coding on the BER, in one embodiment, the ECC codeword is contained within the logical page ("non-interleaved coding"). This means that we are controlled by the worst page within the word line. Therefore, it is necessary to balance the BER between different pages. Using unbalanced state coding requires adjusting the verification level so as to non-uniformly position the state distribution in a way that will result in an equal BER being triggered for all logical pages. This is not without cost, as unbalanced coding has two drawbacks. First, due to the non-uniform spacing of the states, the BER increases for a given voltage window and state width. Second, the sensitivity to any "jitter" in the distribution position increases. Since the memory operates under variable operating conditions (e.g., P / E, DR, Xtemp, interference, etc.), we cannot ensure perfect positioning of the states under all conditions. Due to the above points, using 3-4-4-4 balanced state coding is highly desirable.

[0035] In one embodiment, a new 3-4-4-4 state encoding is provided to overcome these problems. This encoding provides a higher tolerance for IDL reads of MLC pages, which enables MLC fine programming. As Figure 3 shown, the MLC stage will program the programming states S0, S3, S6, and S10, which will provide at least a three-state tolerance for IDL reads.

[0036] Figure 4 is a flowchart 1200 of a method of an embodiment. As Figure 4 shown, a QLC 3-4-4-4 Gray code is provided (action 1210). In this code, the first two pages (without loss of generality) initiate MLC Gray encoding with a tolerance of at least a two-state difference (action 1210). Subsequently, the first two pages (lower and middle) are programmed as MLC (action 1220). Then, the MLC programming stage is read (verified) on the chip (without error correction) (action 1230). Then, the upper and top pages are programmed to initiate QLC distribution (action 1240).

[0037] Regarding handling unexpected graceful shutdown (UGSD), in the case of a write abort (WA) due to power loss, the storage system can program the data in the four latches into the SLC memory (using capacitor energy). During power-on, the data will be restored by reading the SLC pages (which contain the states of the latches during WA) and the QLC pages of the write abort. For each cell, the latch state will indicate whether the cell has been verified / blocked, in which case its QLC data is valid, or whether it has not been verified, in which case its SLC data is the valid data.

[0038] Alternatively, XOR (across L pages of all strings) and XOR (across M pages of all strings) can be stored into the SLC. In this instance, every X QLC pages program two SLC pages once, where X is the number of strings within the memory die. In the case of power loss during MLC stage programming, the two XOR pages are flushed into the SLC. After power-on, the lower and middle pages can be restored from the XOR pages and other successfully programmed pages. In the case of power loss during the fine stage, the top and upper pages can be flushed into the SLC. After power-on, the lower and middle pages can be restored from the XOR pages and other successfully programmed pages. The top and upper pages can be restored from the flushed SLC pages.

[0039] Figure 5 is a flowchart 1300 of another method of an embodiment. As Figure 5As shown, the first two MLC pages (lower and middle) are programmed, and their XOR is temporarily stored (action 1310). Then, the MLC programming stage is read (verified) on the memory die using the temporary XOR page and decoded (action 1320). Then, the QLC upper page and the top page are programmed (action 1230).

[0040] Figure 6 is a graph showing this embodiment that uses a conventional 3-4-4-4 state encoding with XOR(L,M) (which does not provide tolerance for IDL reads) to assist IDL reads. In this embodiment, the conventional 3-4-4-4 mapping is used to support MLC fine by storing XOR(L,M) in the controller write buffer during the fine stage for IDL reads and transferring this XOR page to the NAND. Using the XOR(L,M) page, we can perform IDL reads with sufficient tolerance. If the XOR bit is 0, then the programmed MLC state is (0 or 4), and if the XOR bit is 1, then the programmed MLC state is (2 or 12). Thus, we can perform an IDL read by issuing two senses, one sense between 0 and 4 and another sense between 2 and 12, and select the relevant result based on the XOR bit. The write buffer for each die of this scheme can be 64KB * 1 string * 2 pages + 64KB * X strings * 1 page (XOR) = (X + 2) * 64KB.

[0041] Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include: volatile memory devices such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices; non-volatile memory devices such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”); and other semiconductor elements capable of storing information. Each type of memory device can have a different configuration. For example, flash memory devices can be configured in a NAND or NOR configuration.

[0042] Memory devices can be formed from passive and / or active elements in any combination. By way of non-limiting examples, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistive switching memory elements such as anti-fuses, phase change materials, etc., and optionally include steering elements such as diodes, etc. Additionally, by way of non-limiting examples, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements having charge storage regions such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0043] Multiple memory elements can be configured such that they are connected in series or such that each element can be accessed individually. By way of non-limiting examples, flash memory devices in a NAND configuration (NAND memories) typically contain memory elements connected in series. A NAND memory array can be configured such that the array consists of multiple memory strings, where a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements can be configured such that each element can be accessed individually, such as in a NOR memory array. NAND and NOR memory configurations are examples, and the memory elements can be configured in other ways.

[0044] Semiconductor memory elements located within and / or above a substrate can be configured in two-dimensional or three-dimensional forms, such as two-dimensional memory structures or three-dimensional memory structures.

[0045] In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Generally, in a two-dimensional memory structure, the memory elements are arranged in a plane that extends substantially parallel to the main surface of the substrate that supports the memory elements (e.g., in the x-z direction plane). The substrate can be a wafer of a layer on or in which the memory elements are formed, or can be a carrier substrate attached to the memory elements after the memory elements are formed. By way of non-limiting examples, the substrate can include a semiconductor such as silicon.

[0046] The memory elements can be arranged in an ordered array such as multiple rows and / or columns in a single memory device level. However, the memory elements can be arranged in a non-regular or non-orthogonal configuration. Each memory element can have two or more electrodes or contact lines, such as bit lines and word lines.

[0047] A three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y, and z directions, where the y direction is substantially perpendicular to the main surface of the substrate, and the x and z directions are substantially parallel to the main surface of the substrate).

[0048] As a non-limiting example, a three-dimensional memory structure can be vertically arranged as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending generally perpendicular to the major surface of the substrate (i.e., in the y direction)), where each column has multiple memory elements in each column. The columns can be arranged in a two-dimensional configuration (e.g., in the x-z plane), thereby resulting in a three-dimensional arrangement of memory elements having elements on multiple vertically stacked memory planes. Other configurations of memory elements in a three-dimensional form can also constitute a three-dimensional memory array.

[0049] By way of non-limiting example, in a three-dimensional NAND memory array, the memory elements can be coupled together to form NAND strings within a single horizontal (e.g., x-z) memory device level. Alternatively, the memory elements can be coupled together to form vertical NAND strings that traverse multiple horizontal memory device levels. Other three-dimensional configurations can be envisioned, where some NAND strings contain memory elements in a single memory level, while other strings contain memory elements spanning multiple memory levels. The three-dimensional memory array can also be designed in a NOR configuration and in a ReRAM configuration.

[0050] Generally, in a monolithic three-dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three-dimensional memory array can also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate can comprise a semiconductor such as silicon. In a monolithic three-dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device level of the array. However, the layers of adjacent memory device levels of the monolithic three-dimensional memory array can be shared, or there can be intervening layers between the memory device levels.

[0051] Moreover, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrates can be thinned or removed from the memory device levels before stacking, but since the memory device levels are initially formed above separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Additionally, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0052] Associated circuitry is typically required to operate and communicate with the memory elements. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory elements to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read and write operations may be located on a separate controller chip and / or on the same substrate as the memory elements.

[0053] Those skilled in the art will recognize that the present invention is not limited to the two-dimensional and three-dimensional structures described, but encompasses all relevant memory structures as described herein and as understood by those skilled in the art within the spirit and scope of the present invention.

[0054] It is to be understood that the foregoing detailed description is to be regarded as illustrative of selected forms that the invention may take, and not as limiting of the invention. Only the appended claims (including all equivalents) are intended to define the scope of the claimed invention. Finally, it should be noted that any aspect of any of the embodiments described herein may be used alone or in combination with each other.

Claims

1. A storage system, comprising: A memory; And A controller configured to: Apply a four-level cell (QLC) 3-4-4-4 Gray code to lower and intermediate data pages, thereby inducing a multi-level cell Gray coding with a tolerance of at least two state differences; Program the lower and intermediate data pages in the memory using a multi-level cell programming operation; Read the programming of the lower and intermediate data pages in the memory; And Program upper and top data pages in the memory using the read lower and intermediate pages to induce a four-level cell (QLC) distribution.

2. The storage system according to claim 1, wherein the read data is retrieved without using error correction.

3. The storage system according to claim 1, wherein the lower and intermediate pages are read from the memory array without retrieving them in a write buffer in the controller.

4. The storage system according to claim 1, wherein the memory comprises a three-dimensional memory.

5. The storage system according to claim 1, wherein the storage system is configured to be embedded in a host.

6. The storage system according to claim 1, wherein the storage system is configured to be removably connected to a host.

7. A method in a storage system comprising a memory and a controller, comprising: Programming lower and intermediate data pages in the memory using a multi-level cell programming operation; Generating an exclusive OR of the lower and intermediate data pages in the memory; Storing the exclusive OR of the lower and intermediate data pages in the storage system; Reading the programming of the lower and intermediate data pages in the memory; Decoding the lower and intermediate data pages using the exclusive OR of the lower and intermediate data pages; and Programming upper and top data pages in the memory.

8. The method according to claim 7, wherein the exclusive OR of the lower and intermediate data pages is stored in a temporary location in the storage system.

9. The method according to claim 7, wherein the read data is retrieved without using error correction.

10. The method according to claim 7, wherein the lower and intermediate pages are read from the memory array without retrieving them in a write buffer in the controller.

11. The method according to claim 7, wherein the memory comprises a three-dimensional memory.

12. The method according to claim 7, wherein the storage system is configured to be embedded in a host.

13. The method according to claim 7, wherein the storage system is configured to be removably connected to a host.

14. A storage system, comprising: A memory; Means for applying a four-level cell (QLC) 3-4-4-4 Gray code to lower and intermediate data pages thereby inducing a multi-level cell Gray coding with a tolerance of at least two state differences; Means for programming the lower and intermediate data pages in the memory using a multi-level cell programming operation; Means for reading the programming of the lower and intermediate data pages in the memory; And Components for programming upper and top data pages in the memory to induce a four-level cell (QLC) distribution.

15. The storage system according to claim 14, wherein read data is retrieved without using error correction.

16. The storage system according to claim 14, wherein the lower and middle pages are read from the memory array without retrieving them in a write buffer in the controller.

17. The storage system according to claim 14, wherein the memory includes a three-dimensional memory.

18. The storage system according to claim 14, wherein the storage system is configured to be embedded in a host.

19. The storage system according to claim 14, wherein the storage system is configured to be removably connected to a host.

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