Display substrate, manufacturing method thereof and display device

Abstract

The present disclosure provides a display substrate, a preparation method thereof and a display device, and belongs to the technical field of display. The present disclosure can solve the problem of uneven light emission of the existing display panel. The present disclosure provides a preparation method of a display substrate, which comprises: providing a substrate, sequentially forming a first induction film and a first metal film on the substrate; under the induction of the first induction film, the crystal grains in the first metal film grow from a first size to a second size to form a first metal layer; the first size is larger than the second size; and the first metal layer and the first induction film are patterned to form a pattern comprising a signal line.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0002] An organic light emitting diode (OLED) display panel has many advantages such as self-illumination, low driving voltage, high luminous efficiency, short response time, high definition and contrast, wide viewing angle, wide temperature range of use, and full-color display in a large area, and is considered as the most potential display panel in the industry. The OLED display panel belongs to a self-illumination type display panel, and an OLED light emitting device thereon usually includes a pixel electrode used as an anode, a common electrode used as a cathode, and organic functional layers arranged between the pixel electrode and the common electrode, which emit light when a current passes through.

[0003] However, in the application of a large-size display panel, due to the increase of the size of the display panel, the length of the gate line wire connected to the sub-pixel including the OLED light emitting device is lengthened. Since the gate line itself has a certain resistance, the lengthening of the gate line wire leads to the increase of the resistance of the gate line, which causes the delay of the scanning signal on the gate line, and further leads to the insufficient opening time of the thin film transistor (TFT) in the sub-pixel, and the poor display effect of the display panel. SUMMARY

[0004] The present disclosure aims to at least solve one of the technical problems in the prior art, and provide a display substrate, a preparation method thereof and a display device.

[0005] In a first aspect, the present disclosure provides a preparation method of a display substrate, which includes: providing a substrate substrate; sequentially forming a first induced film and a first metal film on the substrate substrate; under the induction of the first induced film, the crystal grains in the first metal film grow from a first size to a second size to form a first metal layer; the first size is smaller than the second size; and the first metal layer and the first induced film are patterned to form a pattern including a signal line.

[0006] The step of sequentially forming the first induced film and the first metal film on the substrate substrate includes: sequentially forming the first induced film and the first metal film at a temperature of 20-260°C.

[0007] The thickness of the first induced film is 100-500 angstroms.

[0008] The material of the first induced film at least includes any one of W, Nb, Ti, Ta, MoW, MoCu, MoAl, MoNi, MoNb, MoTi, MoAlTi and MoNiTi.

[0009] The signal line includes a gate line, a data line, a reset signal line, a switching electrode line and a power supply line.

[0010] When the signal line is the gate line, the preparation method of the display substrate further includes forming a pixel driving circuit on the substrate; the step of forming the pixel driving circuit includes forming a plurality of thin film transistors and a storage capacitor; the step of forming the thin film transistor and the storage capacitor includes:

[0011] The first metal layer and the first induced film are patterned to form a pattern including a control electrode of the thin film transistor and a first plate of the storage capacitor; the gate line, the control electrode of the thin film transistor and the first plate of the storage capacitor are formed in one patterning process; wherein the gate electrode of the thin film transistor and the first plate of the storage capacitor are formed in one patterning process with the gate line.

[0012] The step of forming the second plate of the storage capacitor includes sequentially forming a second induced film and a second metal film on the substrate; under the induction of the induced film, the crystal grains in the second metal film grow from the first size to the second size to form a second metal layer.

[0013] The second metal layer and the second induced film are patterned to form a pattern including the second plate of the storage capacitor.

[0014] The thin film transistor includes a low-temperature polysilicon thin film transistor and / or a metal oxide thin film transistor.

[0015] In a second aspect, the present disclosure provides a display substrate, which includes a substrate and a plurality of signal lines arranged on the substrate; the signal lines include a first sub-signal line and a second sub-signal line arranged in a direction away from the substrate; the material of the first sub-signal line can make the crystal grains in the first metal film grow from a first size to a second size to form the material of the second sub-signal line; wherein the first size is smaller than the second size.

[0016] The material of the first metal film at least includes Mo.

[0017] The material of the first sub-signal line comprises at least one of W, Nb, Ti, Ta, MoW, MoCu, MoAl, MoNi, MoNb, MoTi, MoAlTi and MoNiTi.

[0018] The signal line comprises a gate line, and the display substrate further comprises a pixel driving circuit disposed on the substrate and electrically connected to the gate line; the pixel driving circuit comprises a plurality of thin film transistors and a storage capacitor; the gate line, the control electrode of the thin film transistor and the first electrode plate of the storage capacitor are disposed in the same layer, and the control electrode of the thin film transistor comprises a first sub-gate electrode and a second sub-gate electrode disposed in the same layer; the first electrode plate of the storage capacitor comprises a first sub-electrode plate and a second sub-electrode plate disposed in the same layer; the first sub-gate electrode and the first sub-electrode plate are made of the same material as the first sub-signal line and disposed in the same layer; and the second sub-gate electrode and the second sub-electrode plate are made of the same material as the second sub-signal line and disposed in the same layer.

[0019] The display substrate further comprises a light-emitting device disposed on the side of the pixel driving circuit away from the substrate; the light-emitting device is electrically connected to the pixel driving circuit; and the light-emitting device comprises an organic light-emitting diode.

[0020] In a third aspect, the present disclosure provides a display device comprising the display substrate. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a schematic diagram of an existing display substrate;

[0022] Figure 2 is another schematic diagram of an existing display substrate;

[0023] Figure 3a is a schematic diagram of a grain structure with a first size according to an embodiment of the present disclosure;

[0024] Figure 3b is a schematic diagram of a grain structure with a second size according to an embodiment of the present disclosure;

[0025] Figure 3c is another schematic diagram of a grain structure with a second size according to an embodiment of the present disclosure;

[0026] Figure 3d is another schematic diagram of a grain structure with a second size according to an embodiment of the present disclosure;

[0027] Figure 4 is a cross-sectional schematic diagram of a display substrate according to an embodiment of the present disclosure;

[0028] Figure 5FIG. 2 is a cross-sectional view of another display substrate according to an embodiment of the present disclosure;

[0029] Figure 6 FIG. 3 is a schematic diagram of a pixel driving circuit of a 2T1C structure according to an embodiment of the present disclosure;

[0030] Figure 7 FIG. 4 is a schematic diagram of a pixel driving circuit of a 7T1C structure according to an embodiment of the present disclosure;

[0031] Figure 8 FIG. 5 is a flowchart of a manufacturing process of a display substrate according to an embodiment of the present disclosure;

[0032] Figure 9 FIG. 6 is a flowchart of a manufacturing process of a pixel driving circuit according to an embodiment of the present disclosure;

[0033] Figure 10 FIG. 7 is another flowchart of a manufacturing process of a pixel driving circuit according to an embodiment of the present disclosure;

[0034] Figure 11 FIG. 8 is a cross-sectional view of a signal line according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] In order to enable persons skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure will be further described in detail below with reference to the drawings and specific embodiments.

[0036] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by a person skilled in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are merely used to distinguish different constituent parts. Similarly, the terms "one", "a", or "the" and similar terms do not denote a quantity restriction, but mean that there is at least one. The terms "include", "comprise", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms do not mean a physical or mechanical connection, but can include an electrical connection, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like merely represent relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships can also change accordingly.

[0037] The transistors used in the exemplary embodiments and embodiments of this disclosure can be thin-film transistors (TFTs), field-effect transistors (FETs), or other switching devices with the same characteristics. Thin-film transistors (TFTs) can include oxide semiconductor thin-film transistors (TFTs), amorphous silicon thin-film transistors (TFTs), or polycrystalline silicon thin-film transistors (TFTs), etc. Each transistor includes a first electrode, a second electrode, and a control electrode; wherein the control electrode serves as the gate of the transistor, one of the first electrode and the second electrode serves as the source of the transistor, and the other serves as the drain of the transistor; and the source and drain of the transistor can be structurally symmetrical, so their physical structures can be indistinguishable. In the embodiments of this disclosure, to distinguish the transistors, except for the gate serving as the control electrode, the first electrode is directly described as the source and the second electrode as the drain.

[0038] Furthermore, transistors can be classified into N-type and P-type based on their characteristics. In the following exemplary embodiments and embodiments of this disclosure, when an N-type transistor is used, the first electrode is the source of the N-type transistor, the second electrode is the drain of the N-type transistor, and the transistor is turned on when the gate input is high. The opposite is true for P-type transistors. It is conceivable that using a P-type transistor is something that those skilled in the art can easily conceive of without inventive effort, and therefore it is also within the protection scope of the embodiments of this disclosure.

[0039] like Figure 1 As shown, Figure 1 This is a schematic diagram of a display substrate 1 according to an embodiment of the present disclosure; as shown Figure 1 As shown, the display substrate 1 includes a plurality of pixel units 10 arranged in an array along a first direction and a second direction; wherein the first direction and the second direction intersect, one of which can be a row direction and the other a column direction. In this embodiment, the first direction is described as a row direction and the second direction as a column direction. In this embodiment, the plurality of pixel units 10 may include, but is not limited to, red pixel units 10, green pixel units 10, blue pixel units 10, etc.

[0040] Specific examples Figure 2 As shown, the exemplary display substrate 1 further includes a gate driving circuit 200 disposed in the peripheral area and gate lines 2 arranged along a first direction on the display substrate 1. The gate driving circuit 200 includes M cascaded shift registers, which are electrically connected to pixel units 10 disposed on the display substrate 1 via the gate lines 2 arranged along the first direction. The shift registers in the gate driving circuit 200 output control signals to the pixel units 10 located in the same row through the gate lines 2, controlling the pixel units 10 located in the same row to emit light.

[0041] The inventors find that when the size of the display substrate 1 is large, the length of the gate line 2 on the display substrate 1 will also be long. Since the gate line 2 itself has resistance, as the length of the wire increases, the resistance of the gate line 2 becomes larger and larger, resulting in a delay in the electrical signal received by the pixel unit 10 at the edge of the display substrate 1, insufficient opening time of the thin film transistor connected to the gate line 2 in the pixel unit 10, uneven brightness of the light emitting device in the pixel unit 10, and poor display effect of the display substrate 1.

[0042] In view of the problems existing in the prior art, the inventors have made some improvements to the prior art.

[0043] In a first aspect, as shown in Figures 1 to 11 The present disclosure provides a preparation method of a display substrate 1, which comprises: providing a substrate 11, sequentially forming a first induced film 12 and a first metal film on the substrate 11, growing the crystal grains in the first metal film from a first size to a second size under the induction of the first induced film 12 to form a first metal layer 13, the first size being smaller than the second size, patterning the first metal layer 13 and the first induced film 12 to form a pattern comprising a signal line 4.

[0044] In an embodiment of the present disclosure, as shown in Figures 1 to 5 The substrate 11 is provided for arranging the basic structure of the display substrate 1 of the present disclosure thereon. Specifically, the substrate 11 can be a flexible substrate 11, for example, comprising a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer stacked on a glass carrier. The first induced film 12 is formed on the substrate 11 by plasma sputtering. After the formation of the first induced film 12, the sputtering is continuously performed to form the first metal film without breaking the vacuum. Since the first metal film is continuously formed on the first induced film 12 after the formation of the first induced film 12, the crystal grains in the first metal film grow from a first size to a second size to form a first metal layer 13. The second size is larger than the first size. The first metal layer 13 and the first induced film 12 are patterned by a one-time patterning process to form a signal line 4 having a laminated structure as shown in Figure 11

[0045] ​In the embodiment, the first metal thin film is formed continuously after the first induced thin film 12 is formed without breaking the vacuum. Compared with the film layer structure of the first metal thin film formed in the prior art, the first induced thin film 12 has fewer defects, so that the crystal grains in the first metal layer 13 can be induced to grow into larger-sized crystal grains. Therefore, the crystal grains in the first metal thin film grow from the first size to the second size under the induction of the first induced thin film 12, and the crystal grains with the second size are continuously deposited to form the first metal layer 13. In the embodiment of the present disclosure, as shown in Figure 3a , the first size can be about 15-20 nm, for example, the size of some crystal grains with the first size is 15 nm; as shown in Figure 3a , the second size can be about 50-100 nm, for example, the size of some crystal grains with the second size is 100 nm. Since the signal line 4 is formed by the first induced thin film 12 and the first metal layer 13 through the patterning process and has the stack structure as shown in Figure 11 , the size of the crystal grains in the first metal layer 13 is the second size, so the size of the crystal grains in the signal line 4 is significantly increased. Since the size of the crystal grains in the signal line 4 is increased, the number of grain boundaries in the crystal structure of the signal line 4 is reduced, the resistance of the signal line 4 is reduced, the delay of the electrical signal on the signal line 4 is shortened, and the display effect of the display substrate 1 is improved.

[0046] In some embodiments, the signal line 4 of the present disclosure includes the gate line 2, the data line, the reset signal line, the switching electrode line, and the power supply line. Since the resistance of the signal line 4 arranged in the first direction on the display substrate 1 in the embodiment of the present disclosure is large, the gate line 2, the data line, the switching electrode line, and the like arranged on the display substrate 1 in the embodiment of the present disclosure can significantly reduce the resistance of the gate line 2, the data line, the switching electrode line, and the like arranged on the display substrate 1 of the present disclosure, shorten the signal delay of the gate line 2, the data line, and the switching electrode line, and improve the display effect of the display substrate 1.

[0047] In the embodiment, the signal line 4 of the present disclosure is taken as the gate line 2 for illustration. Since the gate line 2 of the large-size display substrate 1 is long, the resistance of the gate line 2 is large, which leads to large delay of the control signal on the gate line 2, insufficient opening time of the thin film transistor in the pixel circuit connected to the gate line 2, and poor display effect. Therefore, the sheet resistance of the gate line 2 prepared by the preparation method of the present disclosure is significantly reduced. In the embodiment of the present disclosure, the sheet resistance of the gate line 2 prepared by the preparation method is 0.2-0.3 Ω / □, which greatly reduces the delay of the control signal on the gate line 2, makes the brightness of each light emitting device more uniform, and improves the display effect of the display substrate 1.

[0048] In some embodiments, the step of sequentially forming a first induction film 12 and a first metal film on a substrate 11 includes: sequentially forming the first induction film 12 and the first metal film at a temperature of 20°C-260°C. Since the higher the film formation temperature of the first induction film 12 and the first metal film, the larger the grains in the formed first metal film, the fewer the grain boundaries in the formed gate line 2 due to the larger grain size, resulting in lower resistance of the gate line 2. For example: Figure 3a The grain structure shown, with a first metal thin film thickness of 3000 Å, results in a first-size grain in gate line 2 formed at room temperature, and a sheet resistance of 0.42 Ω / □ for gate line 2; Figure 3b The grain structure shown, when the thickness of the first inducing film 12 is 100 Å and the thickness of the first metal film is 3000 Å, results in a grain size of the second dimension in the gate line 2 formed at 200°C. The sheet resistance of the gate line 2 is 0.22 Ω / □, representing a reduction of approximately 50%. In the embodiments of this disclosure, the film formation temperature of the first inducing film 12 and the first metal film is 50°C. Because the delay of the control signal on the gate line 2 is lower, the brightness of each light-emitting device is more uniform, improving the display effect of the display substrate 1.

[0049] In some embodiments, the thickness of the first induced thin film 12 is approximately 100 Å to 500 Å. Because a larger thickness of the first induced thin film 12 results in larger grain sizes in the induced first metal thin film, fewer grain boundaries in the formed gate line 2, and lower resistance of the gate line 2 itself. For example: Figure 3c The grain structure shown, under film formation conditions of 50°C, when the thickness of the first induced film 12 is 300 Å and the thickness of the first metal film is 3000 Å, results in a grain size of the second dimension, a sheet resistance of 0.24 Ω / □ for the gate line 2, and a reduction in sheet resistance of approximately 40%. In this embodiment, when the thickness of the first induced film 12 is greater than 300 Å, the effect of increasing the thickness of the first induced film 12 on the grain size in the first metal film is weakened. Figure 3d As shown, when the thickness of the first inducing film 12 is 500 Å and the thickness of the first metal film is 3000 Å, the grain size formed in the first metal film is basically the same as that when the thickness of the first inducing film 12 is 300 Å. Therefore, the preferred thickness of the first inducing film 12 is 200 Å-300 Å. Because the lower the delay of the control signal on the gate line 2, the more uniform the brightness of each light-emitting device, thus improving the display effect of the display substrate 1.

[0050] In some embodiments, the material of the first inducing thin film 12 at least includes any one of W, Nb, Ti, Ta, MoW, MoCu, MoAl, MoNi, MoNb, MoTi, MoAlTi and MoNiTi. The first inducing thin film 12 composed of the above-mentioned metal or alloy material has less defects on the first inducing thin film 12 compared with the film layer structure used for forming the first metal thin film in the prior art, and thus can induce the grain growth in the first metal layer 13 to be larger in size. Therefore, the grains in the first metal thin film grow from the first size to the second size under the induction of the first inducing thin film 12, the grains with the second size continuously deposit to form the first metal layer 13, and the gate line 2 formed by the patterning process of the first metal layer 13 and the first inducing thin film 12 has the grain size changed to the second size, so that the number of grain boundaries in the gate line 2 structure is less, the resistance of the gate line 2 is lower, and the resistance on the gate line 2 is smaller. This makes the brightness of each light emitting device more uniform, and improves the display effect of the display substrate 1. In the embodiments of the present disclosure, when the material of the first inducing thin film 12 is a single metal, the material of the first inducing thin film 12 can be W; when the material of the first inducing thin film 12 is an alloy, the material of the first inducing thin film 12 can be MoAlTi. Of course, the above two examples do not constitute a limitation on the protection scope of the embodiments of the present disclosure.

[0051] Specifically, as shown in FIG. 1, the preparation method of the display substrate 1 of the embodiments of the present disclosure is as follows: Figure 8

[0052] S1, forming the substrate 11. The specific steps of forming the above-mentioned substrate 11 are as follows:

[0053] ​The substrate 11 disclosed herein can be a flexible substrate 11. The steps of forming the flexible substrate 11 include forming a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass substrate. The first flexible material layer and the second flexible material layer are made of materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first inorganic material layer and the second inorganic material layer are made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the water and oxygen resistance of the substrate 11. The first inorganic material layer and the second inorganic material layer are also referred to as barrier layers. The semiconductor layer is made of amorphous silicon (a-Si). In some exemplary embodiments, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, the preparation process includes: firstly, coating a layer of polyimide on a glass substrate, curing it into a film to form a first flexible (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it into a film to form a second flexible (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the preparation of the substrate 11.

[0054] S2. Fabricate a pixel driving circuit layer 3 on the substrate 11.

[0055] The pixel driving structure layer includes multiple pixel driving circuits 3, each pixel driving circuit 3 including multiple thin-film transistors and at least one storage capacitor 32, such as a 2T1C, 3T1C, or 7T1C design. In some embodiments, the thin-film transistors include low-temperature polycrystalline silicon thin-film transistors and / or metal-oxide thin-film transistors. In the embodiments of this disclosure, all thin-film transistors can be low-temperature polycrystalline silicon thin-film transistors. This embodiment has a high aperture ratio for the display substrate 1, allowing it to be used in high-resolution display devices. In the embodiments of this disclosure, the thin-film transistors can also be: the switching thin-film transistors connected to the gate line 2 in the pixel circuit are metal-oxide thin-film transistors, while the remaining thin-film transistors are low-temperature polycrystalline silicon thin-film transistors. This embodiment results in lower power consumption for the display substrate 1.

[0056] Specifically, Figure 9 This is a flowchart illustrating the fabrication process of the pixel driving circuit 3 of this disclosure. In the embodiments of this disclosure, when all the thin-film transistors in the pixel driving circuit 3 are low-temperature polycrystalline silicon thin-film transistors, the description will be based on a 2T1C structure for the pixel driving circuit 3. Figure 6As shown in the pixel driving circuit 3, the first transistor 31 is a driving transistor, the second transistor 33 is a switching transistor, and the storage capacitor 32 is connected in parallel with the gate-source of the first transistor 31. In the embodiment of the present disclosure, Figure 4 As a partial view of the driving circuit, the embodiment of the present disclosure takes the first transistor 31 and the storage capacitor 32 as examples for illustration. The steps of forming the pixel driving circuit 3 are as follows:

[0057] S21, forming the first insulating layer 16 and the first active layer 17.

[0058] The first insulating film and the first active layer 17 film are sequentially deposited on the substrate 11, the first active layer film is patterned by a patterning process, the first insulating layer 16 covering the entire substrate 11 is formed, and the active layer pattern is arranged on the first insulating layer 16, and the active layer pattern at least includes the first active layer 17. In this embodiment, since the switching transistor is a low-temperature polysilicon thin film transistor, the material of the first active layer 17 is low-temperature polysilicon.

[0059] S22, forming the gate of the switching transistor and the first plate 321 of the storage capacitor 32.

[0060] In this embodiment, since the signal line 4 in the embodiment of the present disclosure is the gate line 2, the control electrode of the thin film transistor and the first plate 321 of the storage capacitor 32 are formed in one patterning process with the gate line 2. Specifically, the second insulating film, the first induction film 12 and the first metal film are sequentially deposited, the second insulating film is processed by a patterning process to form the second insulating layer 18 covering the first active layer 17 pattern, and the first induction film 12 and the first metal film are processed by one patterning process to form the first gate metal layer pattern arranged on the second insulating layer 18, and the first gate metal layer pattern at least includes the gate of the first transistor 31 and the first plate 321 of the storage capacitor 32.

[0061] In this embodiment, the gate of the first transistor 31 and the first plate 321 of the storage capacitor 32 are formed by the same patterning process as the gate line 2. Therefore, the material and the grain structure of the gate of the first transistor 31 and the first plate 321 of the storage capacitor 32 are the same as the gate line 2, that is, the grains in the gate of the first transistor 31 and the first plate 321 of the storage capacitor 32 grow from the first size to the second size under the action of the first induced thin film 12. Since the gate of the first transistor 31 and the first plate 321 of the storage capacitor 32 have the grain size changed to the second size, the fewer the number of grain boundaries in the structure of the gate of the first transistor 31 and the first plate 321 of the storage capacitor 32, the lower the resistance of the gate of the first transistor 31 and the first plate 321 of the storage capacitor 32, and the smaller the resistance on the gate of the first transistor 31 and the first plate 321 of the storage capacitor 32. Further reduce the delay of the control signal transmitted on the gate line 2, so that the brightness of each light emitting device is more uniform, and the display effect of the display substrate 1 is improved.

[0062] S23, forming a third insulating layer 19 and a second plate 322 of the storage capacitor 32.

[0063] The third insulating thin film, the second induced thin film 14 and the second metal thin film are sequentially deposited on the substrate substrate 11, the third insulating thin film is patterned by a patterning process to form a third insulating layer 19 covering the entire substrate substrate 11, and the second induced thin film 14 and the second metal thin film are processed by a one-time patterning process to form a pattern including the second plate 322 of the storage capacitor 32 disposed on the third insulating layer 19, and the projections of the first plate 321 and the second plate 322 of the storage capacitor 32 on the substrate substrate 11 at least partially overlap.

[0064] In this embodiment, the second induced thin film 14 has the same material thickness as the first induced thin film 12, and the second metal thin film has the same material thickness as the first metal thin film. The external environment when the second metal thin film and the second induced thin film 14 are subjected to the patterning process is the same as the external environment when the first metal thin film and the first induced thin film 12 are subjected to the patterning process, that is, at least two of them have the same temperature, which is 50℃. Therefore, the material and the grain structure of the second plate 322 of the storage capacitor 32 are the same as the gate line 2, that is, the grains in the second plate 322 of the storage capacitor 32 grow from the first size to the second size under the action of the second induced thin film 14. Since the gate of the driving transistor and the first plate 321 of the storage capacitor 32 have the grain size changed to the second size, the fewer the number of grain boundaries in the structure of the second plate 322 of the storage capacitor 32, the lower the resistance of the second plate 322 of the storage capacitor 32, and the smaller the resistance on the second plate 322 of the storage capacitor 32. Further reduce the delay of the control signal transmitted on the gate line 2, so that the brightness of each light emitting device is more uniform, and the display effect of the display substrate 1 is improved.

[0065] S24, Form the fourth insulating layer 20.

[0066] A fourth insulating film is deposited, and the fourth insulating film is patterned by a patterning process to form a pattern of the fourth insulating layer 20 covering the second electrode plate 322 of the storage capacitor 32. At least two first vias are formed on the fourth insulating layer 20. The fourth insulating layer 20, the third insulating layer 19 and the second insulating layer 18 in the two first vias are etched away to expose the surface of the first active layer 17.

[0067] S25, forming the source and drain electrodes of the first transistor 31.

[0068] A third metal thin film is deposited and patterned using a patterning process to form a third metal layer 22 on the fourth insulating layer 20, including source and drain metal layer patterns. The source and drain metal layers include at least the source and drain patterns of the first transistor 31. The source and drain of the first transistor 31 are connected to the first active layer 17 through a first via.

[0069] This completes the fabrication of the pixel driving circuit 3.

[0070] Specifically, Figure 10 This is a flowchart illustrating the fabrication process of an embodiment of this disclosure. In an embodiment of this disclosure, when the switching transistor in the pixel driving circuit 3 is a metal-oxide-slim thin-film transistor and the remaining transistors are low-temperature polycrystalline silicon thin-film transistors, such as... Figure 7 As shown, this embodiment of the present disclosure uses a 7T1C structure for the pixel driving circuit 3 as an example for explanation. In this type of pixel driving circuit 3, as... Figure 5 As shown, in this embodiment, transistor T3 is a metal-oxide-slim transistor with a dual-gate structure, and the other transistors are low-temperature polycrystalline silicon thin-film transistors. In this embodiment, transistor T3 is used as the first transistor 31, and transistor T7 is used as the second transistor 33 for illustration. Figure 5 This is a partial screenshot of the pixel driving circuit 3. This embodiment of the disclosure will be described using the formation of the first transistor 31 and the second transistor 33 as an example. The steps for forming the pixel driving circuit 3 are as follows:

[0071] S31, forming a first insulating layer 16 and a first active layer 17.

[0072] A first insulating film and a first active layer 17 are sequentially deposited on a substrate 11. The first active layer is patterned using a patterning process to form a first insulating layer 16 covering the entire substrate 11, and an active layer pattern disposed on the first insulating layer 16. The active layer pattern includes at least the first active layer 17. In this embodiment, since the second transistor 33 is a low-temperature polycrystalline silicon thin-film transistor, the material of the first active layer 17 is low-temperature polycrystalline silicon.

[0073] In some embodiments, the step of step S31 can further include:

[0074] S310, forming a first light shielding layer 23 before forming the first insulating film.

[0075] Specifically, a first light shielding film is deposited on the substrate 11, and the first light shielding film is patterned by a patterning process to form a light shielding layer pattern disposed on the substrate 11, the light shielding layer pattern at least including the first light shielding layer 23. In this embodiment, the first light shielding layer 23 and the first active layer 17 at least partially overlap in projection on the substrate 11. In this way, the first active layer 17 is shielded from light to prevent light from affecting the electrical properties of the thin film transistor.

[0076] S32, forming a gate of the second transistor 33 and a first gate 24 of the first transistor 31.

[0077] In this embodiment, since the signal line 4 is the gate line 2 in the embodiments of the present disclosure, the above-mentioned gate of the second transistor 33 and the first gate 24 of the first transistor 31 are formed in one patterning process. Specifically, a second insulating film, a first induced film 12 and a first metal film are sequentially deposited, the second insulating film is processed by a patterning process to form a second insulating layer 18 covering the first active layer 17 pattern, and the first induced film 12 and the first metal film are processed by one patterning process to form a first gate metal layer pattern disposed on the second insulating layer 18, the first gate metal layer pattern at least including the first gate 24 of the first transistor 31 and the gate of the second transistor 33.

[0078] In this embodiment, since the gate of the second transistor 33 and the first gate 24 of the first transistor 31 are formed by one patterning process. Therefore, the material and grain structure of the gate of the thin film transistor are the same as the gate line 2, i.e. the grains in the gate of the second transistor 33 and the first gate 24 of the first transistor 31 grow from the first size to the second size under the action of the first induced film 12. Since the gate of the second transistor 33 and the first gate 24 of the first transistor 31 have the second size of the grains, the number of grain boundaries in the structure of the gate of the second transistor 33 and the first gate 24 of the first transistor 31 is reduced, and the resistance of the gate of the second transistor 33 and the first gate 24 of the first transistor 31 is reduced. Further reduce the delay of the control signal transmitted on the gate line 2, so that the brightness of each light emitting device is more uniform, and the display effect of the display substrate 1 is improved.

[0079] Similarly, the materials, forming conditions and forming steps of the first metal film and the first induced film 12 have been described in the above-mentioned step of forming the gate line 2, and will not be described again.

[0080] S33, forming a fifth insulating layer and a second active layer.

[0081] The fifth insulating film and the second active layer film are sequentially deposited on the substrate 11, the second active layer film is patterned by a patterning process, and the fifth insulating layer covering the entire substrate 11 and the active layer pattern arranged on the fifth insulating layer are formed. The active layer pattern at least includes the second active layer. In this embodiment, since the second transistor 33 is a metal oxide thin film transistor, the material of the second active layer is IGZO (indium gallium zinc oxide).

[0082] S34, forming a third insulating layer 19 and a second gate 27 of the second transistor 33.

[0083] Subsequently, the third insulating film, the fourth inducing film and the fourth metal film are sequentially deposited, the third insulating film is processed by a patterning process to form the third insulating layer 19 covering the second active layer pattern, and the second inducing film 14 and the second metal film are processed by a one-time patterning process to form the second gate metal layer pattern arranged on the fourth insulating layer 20. The second gate metal layer pattern at least includes the second gate 27 of the second transistor 33.

[0084] In this embodiment, the material thickness of the fourth inducing film is the same as that of the first inducing film 12, and the material thickness of the fourth metal film is the same as that of the first metal film. The external environment when the fourth metal film and the fourth inducing film are subjected to the patterning process is the same as that when the first metal film and the first inducing film 12 are subjected to the patterning process, that is, at least the temperature is the same, both being 50°C. Therefore, the material and the grain structure of the second gate 27 of the second transistor 33 are the same as those of the gate line 2, that is, the grains in the second gate 27 of the second transistor 33 grow from the first size to the second size under the action of the fourth inducing film. Since the grain size of the second gate 27 of the second transistor 33 becomes the second size, the number of grain boundaries in the structure of the second gate 27 of the second transistor 33 decreases, and the resistance of the second gate 27 of the second transistor 33 becomes smaller. The delay of the control signal transmitted on the gate line 2 is further reduced, the brightness of each light emitting device is more uniform, and the display effect of the display substrate 1 is improved.

[0085] S35, forming a fourth insulating layer 20.

[0086] Depositing a fourth insulating film, patterning the fourth insulating film by a patterning process to form a fourth insulating layer 20 pattern covering the second gate metal layer, the fourth insulating layer 20 being provided with at least two first vias and two second vias, the fifth insulating layer, the fourth insulating layer 20, the third insulating layer 19 and the second insulating layer 18 in the two first vias being etched away to expose the surface of the first active layer 17, the fifth insulating layer and the fourth insulating layer 20 in the two second vias being etched away.

[0087] S36, source and drain electrodes of the first transistor 31 and the second transistor 33.

[0088] Depositing a third metal film, patterning the third metal film by a patterning process to form a source and drain metal layer pattern on the fourth insulating layer 20, the source and drain metal layer including at least the source and drain of the first transistor 31 and the second transistor 33. The source and drain of the first transistor 31 are connected to the first active layer 17 through the first vias respectively, and the source and drain of the second transistor 33 are connected to the second active layer through the second vias respectively.

[0089] In some exemplary embodiments, the first insulating layer 16, the second insulating layer 18, the third insulating layer 19, the fourth insulating layer 20 and the fifth insulating layer are any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), which can be a single layer, multiple layers or a composite layer. The first insulating layer 16 and the fifth insulating layer are referred to as buffer layers for improving the water and oxygen resistance of the substrate 11; the second insulating layer 18 and the third insulating layer 19 are referred to as gate insulator (GI) layers; and the fourth insulating layer 20 is referred to as an interlayer dielectric (ILD) layer. The third metal film is made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0090] S37, forming a transfer electrode layer and a sixth insulating layer 32 on the substrate 11 formed with the above pattern.

[0091] Specifically, a sixth insulating film, a third inducing film and a fifth metal film are deposited on the substrate 11 with the aforementioned pattern, the sixth insulating film is processed by a patterning process to form a sixth insulating layer 32 covering the third metal layer 22, and the third inducing film and the fifth metal film are processed by a one-time patterning process to form a transfer electrode layer pattern disposed on the sixth insulating layer 32, the transfer electrode layer at least including a transfer electrode 28, the transfer electrode 28 being electrically connected to the drain of the first transistor 31 through a third via hole on the sixth insulating layer 32.

[0092] In this embodiment, the third inducing film has the same material thickness as the first inducing film 12, and the fifth metal film has the same material thickness as the first metal film. The external environment during the patterning process of the fifth metal film and the third inducing film is the same as the external environment during the patterning process of the first metal film and the first inducing film 12, i.e., at least the temperature is the same, both being 50°C. Therefore, the material and the grain structure of the transfer electrode 28 are the same as those of the gate line 2, i.e., the grains in the transfer electrode 28 grow from the first size to the second size under the action of the third inducing film. Since the grain size of the transfer electrode 28 becomes the second size, the number of grain boundaries in the transfer electrode 28 decreases, and the resistance of the transfer electrode 28 decreases. Since the transfer electrode 28 electrically connects the light emitting device and the driving transistor, the driving current of the light emitting device has a smaller delay and a larger current, so that the light emitted by each sub-pixel is more uniform, and the display effect is better.

[0093] At this point, the manufacturing of the pixel driving circuit 3 is completed.

[0094] S3, forming a planar layer 30 on the substrate 11 with the aforementioned pattern.

[0095] Specifically, a planar film of an organic material is coated on the substrate 11 with the aforementioned pattern to form a planar (PLN, Planarization) layer covering the entire substrate 11, and a plurality of fourth via holes are formed on the planar layer 30 in the display area by a mask, exposure and development process. The plurality of fourth via holes are used to electrically connect the light emitting device and the thin film transistor.

[0096] S4, forming a first electrode 5 pattern on the substrate 11 with the aforementioned pattern. In some examples, the first electrode 5 is a reflective anode.

[0097] In some example embodiments, a conductive film is deposited on the substrate 11 with the aforementioned pattern, and the conductive film is patterned by a patterning process to form the first electrode 5 pattern. The first electrode 5 is electrically connected to the driving transistor through the transfer electrode 28 or the via hole.

[0098] S5, forming a pixel definition (PDL) layer pattern on the substrate 11 on which the aforementioned pattern is formed.

[0099] Specifically, a pixel definition film is coated on the substrate 11 on which the aforementioned pattern is formed, and a pixel definition layer 31 pattern is formed through a mask, exposure, and development process. As shown in FIG. 3, the pixel definition layer 31 of the display region includes a plurality of sub-pixel definition portions, and a plurality of pixel definition layer 31 openings are formed between adjacent sub-pixel definition portions. The pixel definition layer 31 in the plurality of pixel definition layer 31 openings is developed away, and the partial surfaces of the first electrodes 5 of the sub-pixels are respectively exposed. Figures 4 to 5

[0100] S6, sequentially forming an organic functional layer and a second electrode 7 on the substrate 11 on which the aforementioned pattern is formed. In some examples, the second electrode 7 is a transparent cathode. The light-emitting device can emit light from the side away from the substrate 11 through the transparent cathode, achieving top emission. In some example embodiments, the organic functional layer of the light-emitting element includes a light-emitting layer 6.

[0101] In an embodiment of the present disclosure, the light-emitting layer 6 is formed on the substrate 11 on which the aforementioned pattern is formed by evaporation. The light-emitting layer 6 is formed in the sub-pixel region, achieving connection of the light-emitting layer 6 with the anode. The cathode is formed on the pixel definition layer 31 and connected with the organic functional layer.

[0102] In some example embodiments, the cathode can adopt any one or more of magnesium (Mg), silver (Ag), and aluminum (Al), or an alloy made of any one or more of the above-mentioned metals, or a transparent conductive material, for example, indium tin oxide (ITO), or a multilayer composite structure of a metal and a transparent conductive material.

[0103] S7, forming an encapsulation layer on the substrate 11 on which the aforementioned pattern is formed.

[0104] In some example embodiments, the encapsulation layer is formed on the substrate 11 on which the aforementioned pattern is formed. The encapsulation layer can include a first encapsulation layer 91, a second encapsulation layer 92, and a third encapsulation layer 93 stacked. The first encapsulation layer 91 adopts an inorganic material and covers the cathode in the display region. The second encapsulation layer 92 adopts an organic material. The third encapsulation layer 93 adopts an inorganic material and covers the first encapsulation layer 91 and the second encapsulation layer 92. However, the present embodiment is not limited thereto. In some examples, the encapsulation layer can adopt a five-layer structure of inorganic / organic / inorganic / organic / inorganic.

[0105] The preparation of the display substrate 1 is completed so far.

[0106] ​The display substrate 1 formed by the manufacturing method of the embodiments of the present disclosure has low sheet resistance of the signal line 4, the gate of the thin film transistor and the plate of the storage capacitor 32, and in a large-size display substrate 1, the luminance of each sub-pixel is more uniform, and the display effect is good.

[0107] In a second aspect, the embodiments of the present disclosure also provide a display substrate 1, comprising: a substrate 11, and a plurality of signal lines 4 disposed on the substrate 11, the signal line 4 comprising a first sub-signal line 41 and a second sub-signal line 42 disposed in a direction away from the substrate in sequence, the material of the first sub-signal line 41 being capable of growing the crystal grains in the first metal thin film from a first size to a second size to form the material of the second sub-signal line 42. Wherein the first size is smaller than the second size.

[0108] The cross-sectional view of the display substrate 1 in the embodiments of the present disclosure is shown in Figures 4 to 5 The signal line 4 on the display substrate 1 is used to transmit the driving signal output by the driving circuit to the pixel unit 10 on the display substrate 1. When the signal line 4 is disposed as shown in Figure 10 The material of the first sub-signal line 41 is capable of growing the crystal grains in the second sub-signal line 42 formed by the first size to the second size. In the embodiments of the present disclosure, the first size can be about 15-20 nm, for example, as shown in Figure 3a The size of the part of the crystal grains with the first size is 15 nm; the second size can be about 50-100 nm, for example, as shown in Figure 3b The size of the part of the crystal grains with the second size is 100 nm. Since the crystal grains in the second sub-signal line 42 are significantly larger, the number of grain boundaries in the second sub-signal line 42 is reduced, and the resistance of the second sub-signal line 42 is significantly reduced. Therefore, the loss of the driving signal output by the driving circuit in the transmission to the pixel unit 10 on the display substrate 1 is reduced, the thin film transistor in the driving circuit connected to the signal line 4 has sufficient opening time, the brightness of the light emitting device in each pixel unit 10 is more uniform, and the display effect of the display substrate 1 is better.

[0109] In some embodiments, the material of the first metal thin film at least includes Mo. Since the crystal grains in the first metal thin film form the second sub-signal line 42, the material of the second sub-signal line 42 can also be Mo. In the embodiments of the present disclosure, the material of the first metal thin film includes but is not limited to Mo-based materials. In this way, the signal line 4 formed by Mo-based metal has good high-temperature resistance and is more compatible with existing processes, reducing the design cost of the display substrate 1. At the same time, the signal line 4 formed by Mo-based metal can be better applied to high-resolution display substrates 1.

[0110] In some embodiments, the material of the first sub-signal line 41 includes at least one of: W, Nb, Ti, Ta, MoW, MoCu, MoAl, MoNi, MoNb, MoTi, MoAlTi, and MoNiTi. In this way, since the defects in the first sub-signal line 41 composed of the above materials are fewer than those in the film structure used to form the second sub-signal line 42 in the prior art, the grains in the second sub-signal line 42 can be induced to grow to a larger size. Therefore, the first sub-signal line 41 composed of at least one of the above materials can cause the grains in the formed second sub-signal line 42 to have a second size, thereby reducing the number of grain boundaries in the second sub-signal line 42 and significantly reducing the resistance of the signal line 4 including the second sub-signal line 42. This reduces the loss in the transmission of the driving signal output from the gate driving circuit 200 to the pixel unit 10 on the display substrate 1, ensuring sufficient turn-on time for the thin-film transistors in the driving circuit connected to the signal line 4, resulting in more uniform brightness of the light-emitting devices in each pixel unit 10 and a better display effect on the display substrate 1.

[0111] In some embodiments, such as Figures 4 to 5 As shown, signal line 4 includes gate line 2, and display substrate 1 also includes: pixel driving circuit 3 disposed on the substrate 11. Pixel driving circuit 3 is electrically connected to gate line 2. Pixel driving circuit 3 includes multiple thin-film transistors and storage capacitor 32. Gate line 2, control electrode of thin-film transistor, and first electrode plate 321 of storage capacitor 32 are disposed on the same layer. The gate of thin-film transistor includes a first sub-gate and a second sub-gate disposed in a stacked manner. The first electrode plate 321 of storage capacitor 32 includes a first sub-electrode and a second sub-electrode disposed in a stacked manner. The first sub-gate and the first sub-electrode are made of the same material as the first sub-signal line 41 and are disposed on the same layer. The second sub-gate and the second sub-electrode are made of the same material as the second sub-signal line 42 and are disposed on the same layer.

[0112] In the embodiment, the pixel driving circuit 3 includes a plurality of thin film transistors and at least one storage capacitor 32, for example, a 2T1C, 3T1C or 7T1C design. In the embodiment of the present disclosure, the 2T1C structure is described, in which the transistor in the pixel driving circuit 3 whose control electrode is electrically connected to the gate line 2 is the first transistor 31, and the transistor whose source electrode is connected to the first transistor 31 is the second transistor 33. In this case, the first transistor 31 is used to control the switching of the pixel driving circuit 3. Since the transistor in the embodiment of the present disclosure is taken as an N-type transistor, when the gate electrode of the first transistor 31 receives a high-level control signal on the gate line 2, the first transistor 31 is turned on to write the data signal on the data line into the pixel driving circuit 3, so the first transistor 31 is a switching transistor in the pixel driving circuit 3. After the second transistor 33 receives the data signal, it is turned on to write the enable signal into the light-emitting device to drive the light-emitting device to emit light, so the second transistor 33 is a driving transistor in the pixel driving circuit 3. The pixel driving circuit 3 further includes the storage capacitor 32, which is connected in parallel with the gate electrode and the source electrode of the second transistor 33, and is used to prevent the voltage of the gate electrode of the second transistor 33 from drifting.

[0113] Figure 4 The figure shows a cross-sectional view of an embodiment of the present disclosure, in which the thin film transistor shown in the figure is the second transistor 33, and the signal line 4 includes at least the gate line 2, the data line and the power line. Since the gate electrode, the gate electrode of the second transistor 33 and the first plate 321 of the storage capacitor 32 are arranged in the same layer, they can be formed by one patterning process, so the first sub-gate electrode and the second sub-gate electrode arranged in the gate electrode of the second transistor 33 are completely the same as the first sub-signal line 41 and the second sub-signal line 42 in terms of formation condition, material and thickness, and the first sub-plate and the second sub-plate arranged in the first plate 321 of the storage capacitor 32 are completely the same as the first sub-signal line 41 and the second sub-signal line 42 in terms of formation condition, material and thickness. Therefore, the grain size in the control electrode of the second transistor 33 and the first plate 321 of the storage capacitor 32 is the second size, so the number of grain boundaries in the control electrode of the second transistor 33 and the first plate 321 of the storage capacitor 32 is reduced, and the resistance of the control electrode of the second transistor 33 and the first plate 321 of the storage capacitor 32 is significantly reduced. Therefore, the loss of the driving signal output by the driving circuit when transmitted to the pixel unit 10 on the display substrate 1 is reduced, so the thin film transistor in the driving circuit connected to the signal line 4 has sufficient on-time, the brightness of the light-emitting device in each pixel unit 10 is more uniform, and the display effect of the display substrate 1 is better.

[0114] In some embodiments, the thin film transistors in the display substrate 1 can also be: the switching thin film transistors connected with the gate lines 2 in the pixel circuit are metal oxide thin film transistors, and the rest of the thin film transistors are low-temperature polysilicon thin film transistors. The display substrate 1 in this embodiment has lower power consumption. Specifically, as shown in FIG. 6, Figure 4 Figure 4 FIG. 7 is a schematic cross-sectional view of the display substrate 1 in the embodiment of the present disclosure. It includes a substrate 11, a pixel driving circuit 3 disposed on the substrate 11, a plurality of signal lines 4, and a light emitting device. In the embodiment of the present disclosure, the signal lines 4 at least include data lines, gate lines 2, a switching electrode 28, and a power supply line. The pixel driving circuit 3 disposed on the substrate 11 is electrically connected with at least the gate lines 2, and the pixel driving circuit 3 is electrically connected with the light emitting device through the switching electrode 28. Since the switching electrode 28 is part of the signal lines 4, it is composed of part of the first sub-signal lines 41 and part of the second sub-signal lines 42, so the resistance of the switching electrode 28 is significantly reduced, the delay of the driving current of the light emitting device is reduced, the driving current is increased, the luminance of the light emitting device in each pixel unit 10 is more uniform, and the display effect of the display substrate 1 is better.

[0115] In some embodiments, the display substrate 1 further includes the pixel driving circuit 3 disposed on the substrate 11 and the light emitting device located on the side of the pixel driving circuit 3 away from the substrate 11. The light emitting device is electrically connected with the pixel driving circuit 3, and the light emitting device includes an organic light emitting diode. In the embodiment of the present disclosure, the organic light emitting diode at least includes a reflective anode, a light emitting layer 6, and a transparent cathode. In this way, the light emitting of the pixel unit 10 is realized, and since the light emitting device is an organic light emitting diode, the display substrate 1 has the advantages of being lighter, brighter, lower in power consumption, and faster in corresponding speed.

[0116] In a third aspect, the embodiment of the present disclosure also provides a display device including any of the display substrates provided by the embodiment of the present disclosure. The display device can be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function.

[0117] It can be understood that the above embodiments are only exemplary embodiments adopted to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the present disclosure.​

Claims

1. A method for preparing a display substrate, characterized in that, include: Provide a substrate; The process of sequentially forming a first induced thin film and a first metal thin film on the substrate includes: first forming a first induced thin film on the substrate by plasma sputtering, and then continuously sputtering to form a first metal thin film after the first induced thin film is formed without breaking the vacuum. Under the induction action of the first induced film, the grains in the first metal film grow from a first size to a second size to form a first metal layer; The first dimension is smaller than the second dimension; The first metal layer and the first induction film are patterned to form a pattern including signal lines.

2. The preparation method according to claim 1, characterized in that, The step of sequentially forming the first induced thin film and the first metal thin film on the substrate includes: The first induced thin film and the first metal thin film are formed sequentially at a temperature of 20℃-260℃.

3. The preparation method according to claim 1, characterized in that, The thickness of the first induced film is 100 Å-500 Å.

4. The preparation method according to any one of claims 1-3, characterized in that, The material of the first induced film includes at least one of the following: W, Nb, Ti, Ta, MoW, MoCu, MoAl, MoNi, MoNb, MoTi, MoAlTi, and MoNiTi.

5. The preparation method according to any one of claims 1-3, characterized in that, The signal lines include: gate lines, data lines, reset signal lines, adapter electrode lines, and power lines.

6. The preparation method according to claim 5, characterized in that, When the signal line includes a gate line, the method for fabricating the display substrate further includes: forming a pixel driving circuit on the substrate; the step of forming the pixel driving circuit includes forming a plurality of thin-film transistors and a storage capacitor; the step of forming the thin-film transistors and the storage capacitor includes: The first metal layer and the first inductive thin film are patterned to form a pattern including the control electrode of the thin film transistor and the first electrode of the storage capacitor; the gate line, the control electrode of the thin film transistor and the first electrode of the storage capacitor are formed in a single patterning process; wherein the gate of the thin film transistor and the first electrode of the storage capacitor are formed together with the gate line in a single patterning process.

7. The preparation method according to claim 6, characterized in that, The steps for forming the second plate of the storage capacitor include: A second induced thin film and a second metal thin film are sequentially formed on the substrate. Under the induction effect of the induced thin film, the grains in the second metal thin film grow from the first size to the second size to form a second metal layer; The second metal layer and the second induction film are patterned to form a pattern including the second electrode plate of the storage capacitor.

8. The preparation method according to claim 6, characterized in that, The thin-film transistors include low-temperature polycrystalline silicon thin-film transistors and / or metal oxide thin-film transistors.

9. A display substrate, characterized in that, include: A substrate and multiple signal lines disposed on the substrate; the signal lines include a first sub-signal line and a second sub-signal line stacked sequentially along the direction away from the substrate, wherein, when forming the signal lines, the first sub-signal line is first formed on the substrate by plasma sputtering, and after the first sub-signal line is formed, the second sub-signal line is continuously sputtered without breaking the vacuum. The material of the first sub-signal line is such that the grains in the first metal thin film grow from a first size to a second size to form the material of the second sub-signal line; wherein the first size is smaller than the second size.

10. The display substrate according to claim 9, characterized in that, The material of the first metal thin film includes at least Mo.

11. The display substrate according to claim 10, characterized in that, The material of the first sub-signal line includes at least one of the following: W, Nb, Ti, Ta, MoW, MoCu, MoAl, MoNi, MoNb, MoTi, MoAlTi, and MoNiTi.

12. The display substrate according to claim 10 or 11, characterized in that, The signal line includes a gate line, and the display substrate further includes a pixel driving circuit disposed on the substrate, the pixel driving circuit being electrically connected to the gate line; the pixel driving circuit includes a plurality of thin-film transistors and a storage capacitor; the gate line, the control electrode of the thin-film transistor, and the first electrode plate of the storage capacitor are disposed in the same layer, and the control electrode of the thin-film transistor includes a first sub-gate and a second sub-gate disposed in a stacked manner; the first electrode plate of the storage capacitor includes a first sub-plate and a second sub-plate disposed in a stacked manner; the first sub-gate and the first sub-plate are made of the same material as the first sub-signal line and are disposed in the same layer; the second sub-gate and the second sub-plate are made of the same material as the second sub-signal line and are disposed in the same layer.

13. The display substrate according to claim 12, characterized in that, It also includes a light-emitting device disposed on the side of the pixel driving circuit facing away from the substrate; the light-emitting device is electrically connected to the pixel driving circuit; the light-emitting device includes an organic light-emitting diode.

14. A display device, characterized in that, The display substrate includes any one of claims 9-13.

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