Display substrate, preparation method thereof and display device

Abstract

A display substrate comprises a substrate, a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer and a second conductive layer. The first conductive layer comprises at least one shielding electrode. The semiconductor layer comprises an active layer of at least one transistor. The second conductive layer comprises a control electrode and a first electrode of the transistor, and a first connecting electrode. The second insulating layer is provided with at least one first via hole and at least one second via hole. The control electrode and the first electrode of the transistor are electrically connected. The first electrode of the transistor is electrically connected to the shielding electrode and a first connecting area of the active layer through the first via hole, and the first connecting electrode is electrically connected to a second connecting area of the active layer through the second via hole.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate, a method for preparing the same, and a display device.

[0005] On one hand, this disclosure provides a display substrate, including: a substrate, a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, and a second conductive layer disposed on the substrate. The first conductive layer includes at least one shielding electrode. The semiconductor layer includes an active layer of at least one transistor. The second conductive layer includes a control electrode and a first electrode of the transistor, and a first connection electrode. The second insulating layer has at least one first via and at least one second via. The control electrode and the first electrode of the transistor are electrically connected, the first electrode of the transistor is electrically connected to the shielding electrode and a first connection region of the active layer through the first via, and the first connection electrode is electrically connected to a second connection region of the active layer through the second via.

[0006] In some exemplary embodiments, the display substrate further includes a third conductive layer located on the side of the second conductive layer away from the substrate. The third conductive layer includes a second electrode of the transistor; the second electrode of the transistor is electrically connected to the first connection electrode.

[0007] In some exemplary embodiments, the display substrate further includes a third insulating layer located between the second conductive layer and the third conductive layer; the third insulating layer has at least one third via. The second electrode of the transistor is electrically connected to the first connection electrode through the third via.

[0008] In some exemplary embodiments, the orthographic projection of the second electrode of the transistor onto the substrate covers the orthographic projection of the first connection electrode onto the substrate.

[0009] In some exemplary embodiments, the third conductive layer further includes a second connection electrode; the third insulating layer also has a fourth via. The second connection electrode is electrically connected to the first electrode of the transistor through the fourth via.

[0010] In some exemplary embodiments, the orthographic projections of the fourth via and the second connection electrode onto the substrate do not overlap with the orthographic projections of the active layer of the transistor onto the substrate.

[0011] In some exemplary embodiments, the second conductive layer further includes a third connecting electrode; the third insulating layer also has a fifth via. The second electrode of the transistor is also electrically connected to the third connecting electrode through the fifth via.

[0012] In some exemplary embodiments, the orthographic projection of the shielding electrode onto the substrate covers the orthographic projection of the control electrode, the first electrode, and the active layer of the transistor onto the substrate.

[0013] In some exemplary embodiments, the control electrode and the first electrode of the transistor are integrally formed.

[0014] In some exemplary embodiments, the integral structure of the control electrode and the first electrode of the transistor is U-shaped when projected onto the substrate.

[0015] On the other hand, embodiments of this disclosure provide a display device including a display substrate as described above.

[0016] On the other hand, this disclosure provides a method for fabricating a display substrate, comprising: forming a first conductive layer on a substrate, the first conductive layer including at least one shielding electrode; forming a first insulating layer on the side of the first conductive layer away from the substrate; forming a semiconductor layer on the side of the first insulating layer away from the substrate, the semiconductor layer including an active layer of at least one transistor; forming a second insulating layer on the side of the semiconductor layer away from the substrate, the second insulating layer having at least one first via and at least one second via; forming a second conductive layer on the side of the second insulating layer away from the substrate, the second conductive layer including a control electrode and a first electrode of the transistor, and a first connection electrode. The first electrode of the transistor is electrically connected to the shielding electrode and a first connection region of the active layer through the first via, and the first connection electrode is electrically connected to a second connection region of the active layer through the second via.

[0017] In some exemplary embodiments, forming a second insulating layer on the side of the semiconductor layer away from the substrate includes: depositing a second insulating film on the semiconductor layer; coating photoresist on the second insulating film; patterning the photoresist using a halftone mask process; retaining the photoresist in a first region; thinning the photoresist in a second region; removing all the photoresist in a third region; removing the second insulating film in the third region; removing the photoresist in the second region; thinning the photoresist in the first region; removing the first insulating layer in the third region; removing the second insulating film in the second region; and removing the photoresist in the first region. In the second region, the second conductive layer overlaps with the orthographic projection of the semiconductor layer onto the substrate; in the third region, the second conductive layer is in direct contact with both the semiconductor layer and the first conductive layer.

[0018] In some exemplary embodiments, the fabrication method further includes forming a third insulating layer and a third conductive layer on the side of the second conductive layer away from the substrate. The third insulating layer has at least one third via; the third conductive layer includes the second electrode of the transistor; the second electrode of the transistor is electrically connected to the first connection electrode through the third via.

[0019] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0021] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0022] Figure 2 This is a schematic diagram of the electrostatic discharge unit in the peripheral area of ​​at least one embodiment of the present disclosure;

[0023] Figure 3A This is a partial top view of a display substrate according to at least one embodiment of the present disclosure;

[0024] Figure 3B for Figure 3A A partial cross-sectional view along the Q-Q' direction;

[0025] Figure 4A This is a partial top view of a display substrate after the formation of the first conductive layer, according to at least one embodiment of the present disclosure;

[0026] Figure 4B for Figure 4A A partial cross-sectional view along the Q-Q' direction;

[0027] Figure 5A This is a partial top view of a display substrate after the semiconductor layer has been formed, according to at least one embodiment of the present disclosure;

[0028] Figure 5B for Figure 5A A partial cross-sectional view along the Q-Q' direction;

[0029] Figure 6A This is a partial top view of a display substrate after the formation of the second insulating layer, according to at least one embodiment of the present disclosure;

[0030] Figure 6B for Figure 6A A partial cross-sectional view along the Q-Q' direction;

[0031] Figure 7 This is a schematic diagram illustrating the preparation process of the second insulating layer according to at least one embodiment of the present disclosure;

[0032] Figure 8A This is a partial top view of a display substrate after the formation of the second conductive layer, according to at least one embodiment of the present disclosure;

[0033] Figure 8B for Figure 8A A partial cross-sectional view along the Q-Q' direction;

[0034] Figure 9A This is a partial top view of a display substrate after the formation of the third insulating layer, according to at least one embodiment of the present disclosure;

[0035] Figure 9B for Figure 9A A partial cross-sectional view along the Q-Q' direction;

[0036] Figure 10 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0037] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be changed to one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0038] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0039] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements, not to limit the quantity. The term “multiple” in this disclosure refers to two or more quantities.

[0040] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0041] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Electrical connection" includes situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the term "component having some electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0042] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0043] In this disclosure, to distinguish the two electrodes of a transistor other than the gate electrode, one electrode is referred to as the first electrode and the other as the second electrode. The first electrode can be either the source electrode or the drain electrode, and the second electrode can be either the drain electrode or the source electrode. Furthermore, the gate electrode of the transistor is referred to as the control electrode. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0044] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0045] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0046] In this disclosure, "about" or "approximately" means without strictly defining the limits, allowing for the possibility of errors in the process and measurement.

[0047] OLED display substrates include thin-film transistors (TFTs). A TFT typically includes an active layer, a gate, a source, and a drain. Perpendicular to the display substrate, the substrate typically includes a substrate, a light-shielding layer, a buffer layer, an active layer, a gate insulating (GI) layer, a gate layer, an interlayer insulating layer (ILD), and source / drain metal layers. However, in some larger display substrates (e.g., 95 inches), due to limitations in fabrication equipment and processes, the thickness of the interlayer insulating layer in the display area (e.g., approximately 9000 angstroms) is greater than that in the surrounding areas (e.g., approximately 8000 angstroms). Furthermore, during the etching process of the interlayer insulating layer, the etching rate in the surrounding areas is faster, easily leading to over-etching. This damages the active layer and buffer layer during the etching of the interlayer insulating layer in the surrounding areas, causing short circuits between the source / drain metal layers and the light-shielding layer, thus affecting the display effect. For example, if the clock signal of the gate drive circuit in the peripheral area is over-electrostatically discharged, it will cause the clock signal line to short-circuit, resulting in the gate drive circuit becoming uncontrollable and causing abnormalities in the display.

[0048] This disclosure provides a display substrate, including: a substrate, a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, and a second conductive layer disposed on the substrate. The first conductive layer includes at least one shielding electrode. The semiconductor layer includes an active layer of at least one transistor. The second conductive layer includes a control electrode and a first electrode of the transistor, and a first connection electrode. The second insulating layer has at least one first via and at least one second via. The control electrode and the first electrode of the transistor are electrically connected. The first electrode of the transistor is electrically connected to the shielding electrode and a first connection region of the active layer through the first via. The first connection electrode is electrically connected to a second connection region of the active layer through the second via. In some examples, the first insulating layer may also be referred to as a buffer layer, and the second insulating layer may also be referred to as a gate insulating layer.

[0049] The display substrate provided in this embodiment achieves electrical connection between the second conductive layer and the first conductive layer and the semiconductor layer by forming a first via and a second via in the second insulating layer. The conductive layer formed subsequently can achieve electrical connection with the semiconductor layer by being electrically connected with the second conductive layer, thereby avoiding the situation of short circuit caused by over-etching of the insulating layer in subsequent processes, thereby improving the yield of the display substrate and ensuring the display effect.

[0050] In some exemplary embodiments, the display substrate may further include a third conductive layer located on the side of the second conductive layer away from the substrate. The third conductive layer may include the second electrode of a transistor. The second electrode of the transistor is electrically connected to the first connection electrode. In this example, the third conductive layer can be electrically connected to the semiconductor layer via the second conductive layer.

[0051] In some exemplary embodiments, the display substrate may further include a third insulating layer located between the second conductive layer and the third conductive layer. The third insulating layer has at least one third via. The second electrode of the transistor can be electrically connected to the first connection electrode through the third via. In some examples, the third insulating layer may also be referred to as an interlayer insulating layer. In this example, the third insulating layer may have vias exposing the second conductive layer, thereby achieving electrical connection between the second and third conductive layers. This can prevent short circuits between the third and first conductive layers caused by over-etching of the third insulating layer, thereby improving the yield of the display substrate.

[0052] In some exemplary embodiments, the orthographic projection of the second electrode of the transistor onto the substrate may overlap with the orthographic projection of the first connection electrode onto the substrate. However, this embodiment is not limited to this. For example, the orthographic projection of the second electrode of the transistor onto the substrate and the orthographic projection of the first connection electrode onto the substrate may partially overlap.

[0053] In some exemplary embodiments, the third conductive layer may further include a second connection electrode. The third insulating layer also has a fourth via. The second connection electrode is electrically connected to the first electrode of the transistor through the fourth via. In some examples, the orthographic projections of the fourth via and the second connection electrode onto the substrate may not overlap with the orthographic projection of the active layer of the transistor onto the substrate. However, this embodiment is not limited to this.

[0054] In some exemplary embodiments, the second conductive layer may further include a third connection electrode. The third insulating layer also has a fifth via. The second electrode of the transistor may also be electrically connected to the third connection electrode through the fifth via. In this example, the second electrode of the transistor may be electrically connected to both the first and third connection electrodes.

[0055] In some exemplary embodiments, the orthographic projection of the shielding electrode onto the substrate can cover the orthographic projection of the transistor's control electrode, first electrode, and active layer onto the substrate. In this example, the shielding electrode can prevent light from affecting the active layer of the transistor.

[0056] The following examples illustrate the solution of this embodiment.

[0057] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as Figure 1 As shown, the display substrate may include: a display area AA and a peripheral area BB located around the display area AA. The peripheral area BB surrounds the display area AA. In some examples, the display substrate may have a generally rectangular shape. However, this embodiment is not limited to this. In some examples, the display substrate may be a closed polygon including linear edges, a circle or ellipse including curved edges, or a semicircle or semi-ellipse including linear edges and curved edges, etc. In some examples, when the display substrate has linear edges, at least some corners of the display substrate may be curved. When the display substrate has a rectangular shape, the portion where adjacent linear edges intersect each other may be replaced by a curve with a predetermined curvature. The curvature can be set according to the position of the curve. For example, the curvature can be changed according to the starting position of the curve, the length of the curve, etc.

[0058] In some exemplary implementations, such as Figure 1As shown, the display area AA includes at least: multiple sub-pixels PX, multiple gate lines G, and multiple data lines D. The multiple gate lines G extend along a first direction X and are arranged sequentially along a second direction Y; the multiple data lines D extend along the second direction Y and are arranged sequentially along the first direction X. The orthographic projections of the multiple gate lines G and the multiple data lines D on the substrate intersect to form multiple sub-pixel regions, each sub-pixel region containing one sub-pixel PX. The multiple data lines D are electrically connected to the multiple sub-pixels PX and are configured to provide data signals to the multiple sub-pixels PX. The multiple gate lines G are electrically connected to the multiple sub-pixels PX and are configured to provide gate control signals (e.g., scan signals) to the multiple sub-pixels PX. However, this embodiment is not limited in this respect.

[0059] In some exemplary embodiments, a pixel unit may include three sub-pixels, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, namely a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. In some examples, the shape of the sub-pixels may be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the three sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited to this.

[0060] In some exemplary embodiments, the peripheral area BB may be provided with a gate driving circuit (e.g., a scan driving circuit and a light-emitting driving circuit), a timing controller, and a data driver. The timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver; the timing controller can provide clock signals, start signals, etc., of specifications suitable for the scan driving circuit to the scan driving circuit; the timing controller can provide clock signals, start signals, etc., of specifications suitable for the light-emitting driving circuit to the light-emitting driving circuit. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to multiple data lines. For example, the data driver can sample grayscale values ​​using a clock signal and apply data signals corresponding to the grayscale values ​​to multiple data lines on a sub-pixel row basis. The scan driving circuit can use clock signals, start signals, etc., received from the timing controller to generate scan signals to be provided to multiple scan lines. For example, the scan driving circuit can sequentially provide scan signals with on-level pulses to the scan lines. The light-emitting driving circuit can use clock signals, start signals, etc., received from the timing controller to generate light-emitting control signals to be provided to multiple light-emitting control lines.

[0061] In some exemplary embodiments, the peripheral area BB may be provided with multiple drive control lines, which are configured to provide drive control signals to the gate drive circuit. For example, the multiple drive control lines may include at least one clock signal line, a power supply line, and a start signal line. In some examples, the drive control lines may achieve electrostatic discharge by connecting to an electrostatic discharge unit located in the peripheral area BB to avoid affecting the display effect.

[0062] Figure 2 This is a schematic diagram of an electrostatic discharge unit according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as Figure 2 The illustration uses an electrostatic discharge unit connected by a clock signal line CLK, a first power supply line GVDD, and a start signal line STV as an example. Each of the clock signal line CLK, the first power supply line GVDD, and the start signal line STV is electrically connected to a second power supply line VGL via an electrostatic discharge unit. The first power supply line GVDD can be configured to continuously provide a high-level signal. The second power supply line VGL can be configured to continuously provide a low-level signal. However, this embodiment is not limited to this.

[0063] In some exemplary embodiments, each electrostatic discharge unit may include an electrostatic discharge transistor. For example... Figure 2 As shown, an electrostatic discharge unit electrically connected to the clock signal line CLK may include an electrostatic discharge transistor T1. The control terminal and first terminal of electrostatic discharge transistor T1 are both electrically connected to the clock signal line CLK, and the second terminal of electrostatic discharge transistor T1 is electrically connected to the second power supply line VGL. An electrostatic discharge unit electrically connected to the first power supply line GVDD may include an electrostatic discharge transistor T2. The control terminal and first terminal of electrostatic discharge transistor T2 are both electrically connected to the first power supply line GVDD, and the second terminal of electrostatic discharge transistor T2 is electrically connected to the second power supply line VGL. An electrostatic discharge unit electrically connected to the start signal line STV may include an electrostatic discharge transistor T3. The control terminal and first terminal of electrostatic discharge transistor T3 are both electrically connected to the start signal line STV, and the second terminal of electrostatic discharge transistor T3 is electrically connected to the second power supply line VGL. However, this embodiment is not limited in this respect.

[0064] Figure 3A This is a partial top view of a display substrate according to at least one embodiment of the present disclosure. Figure 3B for Figure 3A A partial cross-sectional view along the Q-Q' direction is shown. In this example, the structure of a thin-film transistor (e.g., an electrostatic discharge transistor T1) in the peripheral region of the display substrate is described as an example.

[0065] In some exemplary implementations, such as Figure 3BAs shown, in a direction perpendicular to the display substrate, the display substrate may include: a substrate 10, a first conductive layer, a first insulating layer 11, a semiconductor layer, a second insulating layer 12, a second conductive layer, a third insulating layer 13, and a third conductive layer sequentially disposed on the substrate 10. The first conductive layer may include: a shielding electrode 21. The semiconductor layer may include: active layers 221 and 222 of an electrostatic discharge transistor. The second conductive layer may include: a control electrode 231 and a first electrode 232 of the electrostatic discharge transistor, a first connection electrode 233, and a third connection electrode 234. The third conductive layer may include: a second electrode 242 of the electrostatic discharge transistor and a second connection electrode 241. Taking the electrostatic discharge transistor T1 as an example, the first electrode 232 of the electrostatic discharge transistor T1 can be electrically connected to the clock signal line CLK through the second connection electrode 241, and the second electrode 242 of the electrostatic discharge transistor T1 can be electrically connected to the second power line VGL through the third connection electrode 234. For example, the second connection electrode 241 may be integrated with the clock signal line CLK, and the third connection electrode 234 may be integrated with the second power line VGL. However, this embodiment is not limited in this respect.

[0066] In some exemplary implementations, such as Figure 3A As shown, in a direction parallel to the display substrate, the orthogonal projection of the shielding electrode 21 onto the substrate 10 can cover the orthogonal projections of the active layers 221 and 222 of the electrostatic discharge transistor, the first electrode 232, and the control electrode 231 onto the substrate 10, and can also cover the orthogonal projection of the first connecting electrode 233 onto the substrate 10. In this example, the first conductive layer can serve as a light-shielding layer to protect the active layer of the electrostatic discharge transistor.

[0067] In some exemplary implementations, such as Figure 3A and Figure 3B As shown, the control electrode 231 and the first electrode 232 of the electrostatic discharge transistor can be an integral structure and are electrically connected to the shielding electrode 21 and the first connection regions of the active layers 221 and 222 of the electrostatic discharge transistor. The second electrode 242 of the electrostatic discharge transistor is electrically connected to the second connection regions of the active layers 221 and 222 of the electrostatic discharge transistor through the first connection electrode 233. The first connection region and the second connection region of the active layer 221 are located on opposite sides of the channel region, and the first connection region and the second connection region of the active layer 222 are located on opposite sides of the channel region.

[0068] The following reference Figures 3A to 9BThe fabrication process of the display substrate is illustrated by way of example. The "patterning process" described in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metallic, inorganic, or transparent conductive materials; and for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; and etching can be performed using any one or more of dry and wet etching. This disclosure does not limit the methods used. The phrase "A and B are arranged in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of A includes the orthographic projection of B" or "the orthographic projection of B is within the orthographic projection range of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0069] In some exemplary embodiments, the fabrication process of the display substrate may include the following operations.

[0070] (1) Provide a substrate.

[0071] In some exemplary embodiments, the substrate 10 can be a rigid substrate, such as a glass substrate. However, this embodiment is not limited to this. In some examples, the substrate can be a flexible substrate. For example, the substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer soft films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers.

[0072] (2) A first conductive layer is formed on the substrate.

[0073] In some exemplary embodiments, a first conductive thin film is deposited on a substrate 10, and the first conductive thin film is patterned using a patterning process to form a first conductive layer, such as... Figure 4A and Figure 4B As shown. The first conductive layer may include a shielding electrode 21. The orthographic projection of the shielding electrode 21 onto the substrate 10 may be rectangular. In this example, the first conductive layer serves as a light-shielding layer for the electrostatic discharge transistor. However, this embodiment is not limited to this.

[0074] (3) Form a semiconductor layer on the substrate.

[0075] In some exemplary embodiments, a first insulating film and a semiconductor film are sequentially deposited on the substrate 10 forming the aforementioned structure to form a first insulating layer 11 covering the first conductive layer, and the semiconductor layer film is patterned using a patterning process to form a semiconductor layer, such as... Figure 5A and Figure 5B As shown. In some examples, the semiconductor layer includes at least the active layers 221 and 222 of the electrostatic discharge transistor. The orthographic projections of the active layers 221 and 222 onto the substrate 10 can both be rectangular. The orthographic projection of the shielding electrode 21 onto the substrate 10 can cover the orthographic projections of the active layers 221 and 222 of the electrostatic discharge transistor onto the substrate 10.

[0076] In some examples, the semiconductor thin film can be made of semiconductor materials such as metal oxide semiconductors, amorphous silicon, or polycrystalline silicon. For example, the semiconductor thin film can be made of metal oxide semiconductors such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), or gallium zinc oxide (GZO). However, this embodiment is not limited to this.

[0077] (4) A second insulating layer is formed on the substrate.

[0078] In some exemplary embodiments, a second insulating film is deposited on the substrate 10 where the aforementioned structure is formed to form a second insulating layer 12, such as... Figure 6A and Figure 6B As shown, the second insulating layer 12 has a plurality of first vias H1 and a plurality of second vias H2. The second insulating layer 12 within the second via H2 is removed, exposing the surface of the semiconductor layer. In a portion of the first via H1, the second insulating layer 12 is removed, exposing the surface of the semiconductor layer; in another portion, both the second insulating layer 12 and the first insulating layer 11 are removed, exposing the surface of the first conductive layer. In some examples, the orthographic projections of the first vias H1 and the second vias H2 onto the substrate 10 can be circular or elliptical. However, this embodiment is not limited to this. For example, the orthographic projections of the first vias H1 and the second vias H2 onto the substrate 10 can be rectangular or polygonal.

[0079] In some exemplary implementations, such as Figure 7As shown, the second insulating layer 12 can be prepared by: depositing a second insulating film 12a on the side of the semiconductor layer away from the substrate 10; coating photoresist 31 on the second insulating film 12a; and patterning the photoresist 31 using a halftone mask process. The photoresist 31 is retained in a first region I, thinned in a second region II, and completely removed in a third region III. In the second region II, the second conductive layer overlaps with the semiconductor layer; in the third region III, the second conductive layer is in direct contact with both the semiconductor layer and the first conductive layer, i.e., the third region III can be the overlapping area between the second conductive layer and the semiconductor layer and the first conductive layer. The second insulating film 12a in the third region III is removed using a dry etching process. Subsequently, the photoresist 31 in the first region I and the second region II is irradiated with ultraviolet light of a certain intensity to thin the photoresist 31 in the first region I and completely remove the photoresist 31 in the second region II. A dry etching process is then used to etch and remove the second insulating film 12a in the second region II and the first insulating layer 11 in the third region III. Afterward, the photoresist 31 in the first region I is removed to form the second insulating layer 12. The second insulating layer 12 has a first via H1 and a second via H2.

[0080] (5) Form a second conductive layer on the substrate.

[0081] In some exemplary embodiments, a second conductive thin film is deposited on the substrate 10 forming the aforementioned structure, and the second conductive thin film is patterned using a patterning process to form a second conductive layer, such as... Figure 8A and Figure 8B As shown. In some examples, the second conductive layer may include: a control electrode 231, a first electrode 232, a first connection electrode 233, and a third connection electrode 234 of an electrostatic discharge transistor. The orthographic projections of the control electrode 231, the first electrode 232, and the first connection electrode 233 of the electrostatic discharge transistor onto the substrate 10 may lie within the orthographic projection of the shielding electrode 21 onto the substrate 10. The control electrode 231 and the first electrode 232 of the electrostatic discharge transistor may be an integral structure, and the orthographic projection of this integral structure onto the substrate 10 may be U-shaped. However, this embodiment is not limited to this.

[0082] In some exemplary embodiments, after the second conductive layer is formed, the second insulating layer 12 can be etched to remove the second insulating layer 12 not covered by the second conductive layer, and the exposed semiconductor layer can be made conductive. In some examples, for semiconductor layers using IGZO material, the semiconductor layer can be made conductive by plasma treatment. For example, the semiconductor layer can be made conductive by increasing the concentration of hydrogen in the active layer or decreasing the concentration of oxygen in the active layer. For example, the gas forming the plasma can include hydrogen-containing gases such as hydrogen (H2), ammonia (NH3), and silane (SiH4). These gases are ionized during plasma treatment to form hydrogen ions that enter the active layer, thereby increasing the concentration of hydrogen in the active layer and improving the conductivity of the active layer.

[0083] In some examples, active layers 221 and 222 are formed by conductor-conducting the semiconductor layer to create a first connection region and a second connection region, with a channel region spaced between the first connection region and the second connection region.

[0084] In some exemplary implementations, such as Figure 8A and Figure 8B As shown, the first electrode 232 of the electrostatic discharge transistor can be electrically connected to the shielding electrode 21 through multiple first vias H1 (e.g., four first vias), and also electrically connected to the first connection regions of the active layers 221 and 222. The control electrode 231 of the electrostatic discharge transistor is electrically connected to the shielding electrode 21 through the first vias H1, forming a dual-gate transistor structure. The orthographic projection of the control electrode 231 of the electrostatic discharge transistor onto the substrate 10 overlaps with the orthographic projection of the communication regions of the active layers 221 and 222 onto the substrate 10. The first connection electrode 233 can be electrically connected to the second connection regions of the active layers 221 and 222 through multiple second vias H2 (e.g., four second vias). The third connection electrode 234 can be located on one side of the shielding electrode 21.

[0085] (6) A third insulating layer is formed on the substrate.

[0086] In some exemplary embodiments, a third insulating film is deposited on the substrate 10 forming the aforementioned structure, and the third insulating film is patterned using a patterning process to form a third insulating layer 13, such as... Figure 9A and Figure 9B As shown. The third insulating layer 13 has a third via H3, a fourth via H4, and a fifth via H5. The third insulating layer 13 within the third via H3, the fourth via H4, and the fifth via H5 is removed, exposing the surface of the second conductive layer.

[0087] (7) Form a third conductive layer on the substrate.

[0088] In some exemplary embodiments, a third conductive film is deposited on the substrate 10 forming the aforementioned structure, and the third conductive film is patterned using a patterning process to form a third conductive layer, such as... Figure 3A and Figure 3B As shown. In some examples, the third conductive layer includes at least: a second electrode 242 of an electrostatic discharge transistor and a second connection electrode 241. The second electrode 242 of the electrostatic discharge transistor can be electrically connected to the first connection electrode 233 through two third vias H3, and can also be electrically connected to the third connection electrode 234 through a fifth via H5. The orthographic projection of the second electrode 242 of the electrostatic discharge transistor onto the substrate 10 can cover the orthographic projection of the first connection electrode 233 onto the substrate 10. The second connection electrode 241 can be electrically connected to the first electrode 232 of the electrostatic discharge transistor through a fourth via H4. The orthographic projections of the second connection electrode 241 and the fourth via H4 onto the substrate 10 do not overlap with the orthographic projections of the active layers 221 and 222 onto the substrate 10.

[0089] In some exemplary embodiments, the first, second, and third conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the aforementioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. For example, the second conductive layer can be made of copper, the third conductive layer can be made of copper, and the thickness can be approximately 7000 angstroms to 9000 angstroms. However, this embodiment is not limited in this respect.

[0090] In some exemplary embodiments, the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single-layer, multi-layer, or composite layers. For example, the material of the second insulating layer 12 and the third insulating layer 13 may be SiO2. However, this embodiment is not limited in this respect.

[0091] In some exemplary embodiments, after fabricating the third conductive layer, a fourth insulating layer (or passivation layer) covering the third conductive layer can also be formed. A color filter layer, a planarization layer, and a light-emitting device can also be fabricated in the display area. In some examples, the light-emitting element of a sub-pixel can include: an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The pixel definition layer has a pixel opening exposing the anode, and the organic light-emitting layer is formed within the pixel opening. The organic light-emitting layer of the light-emitting element is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of the corresponding color under the drive of the anode and cathode. An encapsulation layer can be disposed on the side of the cathode away from the substrate. The encapsulation layer can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting element.

[0092] The structure and fabrication process of the display substrate in this exemplary embodiment are merely illustrative. In some exemplary embodiments, the structure can be modified and patterning processes can be added or reduced as needed.

[0093] The display substrate provided in this exemplary embodiment achieves electrical connection between the third conductive layer and the semiconductor layer by forming a first via and a second via in the second insulating layer and electrically connecting them through the second conductive layer and the third conductive layer. This avoids short circuits between the third conductive layer and the first conductive layer caused by over-etching the third insulating layer. Furthermore, by using a halftone mask process to form the first via in the second insulating layer, the second conductive layer can overlap with the first conductive layer, and the overlap between the second conductive layer and the third conductive layer eliminates the need for deep vias in the third insulating layer. This simplifies the process, reduces costs, and improves the yield rate of the display substrate.

[0094] At least one embodiment of this disclosure also provides a method for fabricating a display substrate, comprising: forming a first conductive layer on a substrate, the first conductive layer including at least one shielding electrode; forming a first insulating layer on the side of the first conductive layer away from the substrate; forming a semiconductor layer on the side of the first insulating layer away from the substrate, the semiconductor layer including an active layer of at least one transistor; forming a second insulating layer on the side of the semiconductor layer away from the substrate, the second insulating layer having at least one first via and at least one second via; forming a second conductive layer on the side of the second insulating layer away from the substrate, the second conductive layer including a control electrode and a first electrode of the transistor, and a first connection electrode. The first electrode of the transistor is electrically connected to the shielding electrode and a first connection region of the active layer through the first via, and the first connection electrode is electrically connected to a second connection region of the active layer through the second via.

[0095] In some exemplary embodiments, forming a second insulating layer on the side of the semiconductor layer away from the substrate may include: depositing a second insulating film on the semiconductor layer; coating the second insulating film with photoresist; patterning the photoresist using a halftone mask process; retaining the photoresist in a first region; thinning the photoresist in a second region; removing all the photoresist in a third region; removing the second insulating film in the third region; removing the photoresist in the second region; thinning the photoresist in the first region; removing the first insulating layer in the third region; removing the second insulating film in the second region; and removing the photoresist in the first region. In the second region, the second conductive layer overlaps with the semiconductor layer in its orthographic projection onto the substrate; in the third region, the second conductive layer is in direct contact with both the semiconductor layer and the first conductive layer.

[0096] In some exemplary embodiments, the above-described fabrication method may further include: forming a third insulating layer and a third conductive layer on the side of the second conductive layer away from the substrate. The third insulating layer has at least one third via. The third conductive layer includes a second electrode of a transistor. The second electrode of the transistor is electrically connected to a first connection electrode through the third via.

[0097] The method for preparing the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0098] Figure 10 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 10 As shown, this embodiment provides a display device 91, including a display substrate 910. The display substrate 910 can be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 can be any product or component with display function, such as an OLED display device, a watch, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator. However, this embodiment is not limited to this.

[0099] The accompanying drawings in this disclosure only illustrate the structures involved in this disclosure; other structures can be referred to with common design. Unless otherwise specified, the embodiments and features described in these embodiments can be combined to obtain new embodiments. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this disclosure without departing from the spirit and scope of this disclosure, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate, characterized in that, include: The display area and the surrounding area located outside the display area; The surrounding area is provided with a gate drive circuit, an electrostatic discharge unit, and multiple drive control lines. The multiple drive control lines are configured to provide drive control signals to the gate drive circuit. The drive control lines are connected to the electrostatic discharge unit, which includes an electrostatic discharge transistor. The display substrate includes: a substrate, a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, and a second conductive layer disposed on the substrate; The first conductive layer includes: at least one shielding electrode; The semiconductor layer includes: an active layer of at least one transistor; The second conductive layer includes: a control electrode and a first electrode of the transistor, and a first connection electrode; the transistor is an electrostatic discharge transistor; The second insulating layer has at least one first via and at least one second via; The control electrode and the first electrode of the transistor are electrically connected, and the control electrode and the first electrode of the transistor are integral structures; the first electrode of the transistor is electrically connected to the shielding electrode and the first connection area of ​​the active layer through the first via, and the first connection electrode is electrically connected to the second connection area of ​​the active layer through the second via.

2. The display substrate according to claim 1, characterized in that, The display substrate further includes a third conductive layer located on the side of the second conductive layer away from the substrate. The third conductive layer includes: the second electrode of the transistor; the second electrode of the transistor is electrically connected to the first connecting electrode.

3. The display substrate according to claim 2, characterized in that, The display substrate further includes: a third insulating layer located between the second conductive layer and the third conductive layer; the third insulating layer has at least one third via; The second electrode of the transistor is electrically connected to the first connecting electrode through the third via.

4. The display substrate according to claim 2 or 3, characterized in that, The projection of the second electrode of the transistor onto the substrate covers the projection of the first connecting electrode onto the substrate.

5. The display substrate according to claim 3, characterized in that, The third conductive layer further includes: a second connecting electrode; the third insulating layer also has a fourth through hole; The second connection electrode is electrically connected to the first electrode of the transistor through the fourth via.

6. The display substrate according to claim 5, characterized in that, The orthographic projections of the fourth via and the second connecting electrode onto the substrate do not overlap with the orthographic projections of the active layer of the transistor onto the substrate.

7. The display substrate according to claim 3, characterized in that, The second conductive layer further includes: a third connecting electrode; the third insulating layer also has a fifth via. The second electrode of the transistor is also electrically connected to the third connecting electrode through the fifth via.

8. The display substrate according to claim 1, characterized in that, The projection of the shielding electrode onto the substrate covers the projection of the control electrode, the first electrode, and the active layer of the transistor onto the substrate.

9. The display substrate according to claim 1, characterized in that, The integrated structure of the control electrode and the first electrode of the transistor is U-shaped when projected onto the substrate.

10. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 9.

11. A method for preparing a display substrate, characterized in that, The display substrate includes a display area and a peripheral area surrounding the display area; the peripheral area is provided with a gate driving circuit, an electrostatic discharge unit, and multiple driving control lines, the multiple driving control lines being configured to provide driving control signals to the gate driving circuit, the driving control lines being connected to the electrostatic discharge unit, and the electrostatic discharge unit including an electrostatic discharge transistor; the fabrication method includes: A first conductive layer is formed on a substrate, the first conductive layer including at least one shielding electrode; A first insulating layer is formed on the side of the first conductive layer away from the substrate. A semiconductor layer is formed on the side of the first insulating layer away from the substrate, the semiconductor layer including an active layer of at least one transistor; the transistor is an electrostatic discharge transistor. A second insulating layer is formed on the side of the semiconductor layer away from the substrate, and the second insulating layer has at least one first via and at least one second via. A second conductive layer is formed on the side of the second insulating layer away from the substrate. The second conductive layer includes the control electrode and the first electrode of the transistor, as well as a first connection electrode. The control electrode and the first electrode of the transistor are integrally formed. The first electrode of the transistor is electrically connected to the shielding electrode and the first connection region of the active layer through the first via, and the first connection electrode is electrically connected to the second connection region of the active layer through the second via.

12. The preparation method according to claim 11, characterized in that, The formation of a second insulating layer on the side of the semiconductor layer away from the substrate includes: A second insulating film is deposited on the semiconductor layer, and photoresist is coated on the second insulating film; The photoresist is patterned using a halftone mask process. The photoresist is retained in a first region, thinned in a second region, and completely removed in a third region. In the second region, the second conductive layer and the semiconductor layer overlap in their orthogonal projections onto the substrate. In the third region, the second conductive layer is in direct contact with both the semiconductor layer and the first conductive layer. Remove the second insulating film from the third region; Remove the photoresist in the second region and thin the photoresist in the first region; Remove the first insulating layer in the third region and remove the second insulating film in the second region; Remove the photoresist from the first region.

13. The preparation method according to claim 11, characterized in that, The preparation method further includes: forming a third insulating layer and a third conductive layer on the side of the second conductive layer away from the substrate; The third insulating layer has at least one third via; the third conductive layer includes the second electrode of the transistor; the second electrode of the transistor is electrically connected to the first connecting electrode through the third via.

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