Power amplifier circuit

Abstract

Provided is a power amplifier circuit that suppresses gain when operating in a low output operation mode while suppressing changes in input impedance. The power amplifier circuit includes: a first transistor having a first terminal to which a first signal is input; a second transistor having a first terminal to which the first signal is input; a first resistor having one end to which a first bias current is supplied and the other end connected to the first terminal of the first transistor; a second resistor having one end to which a second bias current is supplied and the other end connected to the first terminal of the second transistor; and a third resistor having one end connected to the one end of the first resistor and the other end connected to the one end of the second resistor.

Description

TECHNICAL FIELD

[0001] The present application relates to a power amplification circuit. BACKGROUND

[0002] In a mobile communication device exemplified by a portable telephone device, a power amplification circuit is used in order to amplify the power of a signal transmitted to a base station. In such a power amplification circuit, in order to improve power added efficiency (PAE), the gain is sometimes switched according to the output level.

[0003] In the technology described in Patent Document 1, in the case of a high output operation mode, a first bias circuit that outputs a first bias current is electrically connected between the base of a first transistor and a second transistor and a first resistance. Further, in the case of a low output operation mode, a second bias circuit that outputs a second bias current is electrically connected between the base of the second transistor and a second resistance. Moreover, in the technology described in Patent Document 1, in the case of operating in the low output operation mode, the second bias current is supplied to the base of the second transistor via the second resistance, and is also supplied to the base of the first transistor via the second resistance and the first resistance. Thereby, in the technology described in Patent Document 1, in the case of the low output operation mode, the first transistor is set to a state of not being completely cut off, whereby the variation in input impedance can be suppressed.

[0004] PRIOR ART DOCUMENTS

[0005] PATENT DOCUMENT

[0006] Patent Document 1: Japanese Patent Application Publication No. 2016-208305

[0007] In the technology described in Patent Document 1, in the case of operating in the low output operation mode, the bias current supplied to the base of the first transistor is made somewhat larger, and the operating point of the first transistor is made somewhat higher. Therefore, the gain of the first transistor is made somewhat higher. Thereby, in the case of the low output operation mode, the gain of the power amplification circuit is made somewhat higher. However, in the case of the low output operation mode, there is a demand to further reduce the gain of the power amplification circuit. SUMMARY

[0008] PROBLEMS TO BE SOLVED BY THE INVENTION

[0009] The present application has been achieved in view of the above, and aims to suppress the gain in the case of operating in the low output operation mode, while suppressing the variation in input impedance.

[0010] MEANS FOR SOLVING THE PROBLEMS

[0011] The power amplification circuit of one aspect of the present application includes one or more first transistors to which a first signal is input at a first terminal, one or more second transistors to which the first signal is input at a first terminal and which are electrically connected to second terminals of the one or more first transistors, one or more first resistors to which a first bias current is supplied at one end and which are electrically connected to the first terminals of the one or more first transistors at the other end, one or more second resistors to which a second bias current is supplied at one end and which are electrically connected to the first terminals of the one or more second transistors at the other end, and a third resistor electrically connected at one end to one end of the one or more first resistors and at the other end to one end of the one or more second resistors.

[0012] Effects of the Invention

[0013] According to the present application, it is possible to suppress the gain in the case where the power amplification circuit operates in the low output operation mode while suppressing the variation of the input impedance. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 FIG. 1 is a diagram showing the structure of a transmission unit of a power amplification circuit including a first comparative example.

[0015] Figure 2 FIG. 2 is a diagram showing the structure of the power amplification circuit of the first comparative example.

[0016] Figure 3 FIG. 3 is a diagram showing the structure of a power amplification circuit of a second comparative example.

[0017] Figure 4 FIG. 4 is a diagram showing the operation of the power amplification circuit of the second comparative example.

[0018] Figure 5 FIG. 5 is a diagram showing the operation of the power amplification circuit of the second comparative example.

[0019] Figure 6 FIG. 6 is a diagram showing the structure of a power amplification circuit of a first embodiment.

[0020] Figure 7 FIG. 7 is a diagram showing the operation of the power amplification circuit of the first embodiment.

[0021] Figure 8 FIG. 8 is a diagram showing the operation of the power amplification circuit of the first embodiment.

[0022] Figure 9 FIG. 9 is a diagram showing a simulation circuit of the power amplification circuit of the first embodiment.

[0023] Figure 10 FIG. 10 is a diagram showing the circuit simulation results of the power amplification circuit of the first comparative example.

[0024] Figure 11 is a graph showing a circuit simulation result of the power amplification circuit of the 1st comparative example.

[0025] Figure 12 is a graph showing a circuit simulation result of the power amplification circuit of the 1st comparative example.

[0026] Figure 13 is a graph showing a circuit simulation result of the power amplification circuit of the 1st embodiment.

[0027] Figure 14 is a graph showing a circuit simulation result of the power amplification circuit of the 1st embodiment.

[0028] Figure 15 is a graph showing a circuit simulation result of the power amplification circuit of the 1st embodiment.

[0029] Figure 16 is a graph showing a circuit simulation result of the 1st embodiment and the 2nd comparative example.

[0030] Figure 17 is a graph showing a circuit simulation result of the 1st embodiment and the 2nd comparative example.

[0031] Figure 18 is a graph showing a circuit simulation result of the 1st embodiment and the 2nd comparative example.

[0032] Figure 19 is a graph showing a circuit simulation result of the 1st embodiment and the 2nd comparative example.

[0033] Figure 20 is a graph showing a circuit simulation result of the 1st embodiment and the 2nd comparative example.

[0034] Figure 21 is a graph showing a circuit simulation result of the 1st embodiment and the 2nd comparative example.

[0035] Figure 22 is a graph showing a circuit simulation result of the 1st embodiment and the 2nd comparative example.

[0036] Figure 23 is a graph showing a structure of the power amplification circuit of the 2nd embodiment.

[0037] Figure 24 is a graph showing a structure of the power amplification circuit of the 3rd embodiment.

[0038] Explanation of Reference Numerals

[0039] 1, 120, 300 power amplification circuit

[0040] 100 transmission unit

[0041] 110 modulation circuit;

[0042] 130 front-end circuit;

[0043] 140 antenna;

[0044] 200, 210 bias circuit;

[0045] 220 bias control circuit;

[0046] C1, C2, C3, C4, C5, C11 capacitor;

[0047] L1 choke coil;

[0048] Q1, Q2, Q3, Q4, Q5 transistor;

[0049] R1, R2, R3, R4, R5, R11 current-limiting resistor;

[0050] R21 coupling resistor. DETAILED DESCRIPTION

[0051] Hereinafter, the embodiments of the power amplification circuit of the present application will be described in detail based on the drawings. In addition, the present application is not limited by the present embodiments. Each embodiment is an example, and it is self-evident that a part of the structure shown in different embodiments can be replaced or combined. Descriptions about matters common to the first embodiment will be omitted after the second embodiment, and only the different points will be described. In particular, the same effects brought about by the same structures will not be mentioned in each embodiment in turn.

[0052] <First Embodiment and Comparative Example>

[0053] Hereinafter, the first embodiment will be described, but in order to make the first embodiment easy to understand, the comparative example will be described first.

[0054] (First Comparative Example)

[0055] Figure 1 is a diagram showing the structure of a transmission unit of a power amplification circuit including the first comparative example. The transmission unit 100 is used for transmitting various signals such as voice, data, and the like to a base station, for example, in a mobile communication device such as a portable telephone. In addition, the mobile communication device is also provided with a reception unit for receiving signals from the base station, but the description thereof will be omitted here.

[0056] As shown in Figure 1 , the transmission unit 100 includes a modulation circuit 110, a power amplification circuit 120, a front-end circuit 130, and an antenna 140.

[0057] The modulation circuit 110 modulates an input signal based on a modulation scheme of HSUPA (High Speed Uplink Packet Access), LTE (Long Term Evolution), 5G, or the like, and generates a high-frequency signal of a radio frequency (RF) used for wireless transmission. The high-frequency signal can be exemplified by several hundred MHz to several tens of GHz, for example, but the present disclosure is not limited thereto.

[0058] The power amplification circuit 120 amplifies the power of the high-frequency input signal RFin output from the modulation circuit 110 to a level required for transmission to a base station and outputs a high-frequency output signal RFout.

[0059] The power amplification circuit 120 operates in an operation mode corresponding to the operation mode control voltage Vmode. The operation mode includes a first operation mode (high output operation mode) and a second operation mode (low output operation mode) in which the gain is relatively low compared to the first operation mode.

[0060] The front-end circuit 130 performs filtering of the high-frequency output signal RFout, switching of a reception signal received from a base station, and the like. The high-frequency output signal RFout output from the front-end circuit 130 is transmitted to a base station via the antenna 140.

[0061] Figure 2 is a diagram showing the structure of the power amplification circuit of the first comparative example. The power amplification circuit 120 includes transistors Q1 to Q5, capacitors C1 to C5 and C11, ballast resistors R1 to R5, a choke coil L1, bias circuits 200 and 210, and a bias control circuit 220.

[0062] The transistors Q1 to Q5 are transistors for amplification, which can be exemplified by a heterojunction bipolar transistor (HBT), for example, but the present disclosure is not limited thereto. Each of the transistors Q1 to Q5 can be exemplified by one unit transistor (finger) of a multi-finger transistor, for example, but the present disclosure is not limited thereto. In other words, the transistors Q1 to Q5 can be exemplified by constituting a multi-finger transistor, but the present disclosure is not limited thereto.

[0063] In the present disclosure, each transistor is provided as a bipolar transistor, but the present disclosure is not limited thereto. The transistor can also be a field effect transistor (FET), for example. The transistor can also be a multi-finger transistor in which a plurality of unit transistors are electrically connected in parallel. The so-called unit transistor refers to the smallest structure constituting the transistor.

[0064] The base or gate of each transistor corresponds to the "first terminal" of the present disclosure. The collector or drain of each transistor corresponds to the "second terminal" of the present disclosure. The emitter or source of each transistor corresponds to the "third terminal" of the present disclosure.

[0065] The transistors Q1 to Q5 are electrically connected in parallel, forming an amplification circuit. The emitters of the transistors Q1 to Q5 are electrically connected to a reference potential. The reference potential can exemplify a ground potential, but the present disclosure is not limited thereto. At the bases of the transistors Q1 to Q5, high-frequency input signals RFin are respectively input via capacitors C1 to C5 as DC cut capacitors. Further, the collectors of the transistors Q1 to Q5 are electrically connected to a power supply potential Vcc via an inductor L1. The transistors Q1 to Q5 output high-frequency output signals RFout from the collectors via a capacitor C11. In addition, at the power supply potential Vcc, either a variable voltage based on a DC-DC converter or a voltage based on an envelope of a modulation signal can be supplied.

[0066] The ballast resistor R1 is supplied with a portion of the bias current Ibiasl (ideally 4 / 1 of the bias current Ibiasl) at one end and is electrically connected to the base of the transistor Q1 at the other end. The ballast resistor R2 is supplied with a portion of the bias current Ibiasl (ideally 4 / 1 of the bias current Ibiasl) at one end and is electrically connected to the base of the transistor Q2 at the other end. The ballast resistor R3 is supplied with a portion of the bias current Ibiasl (ideally 4 / 1 of the bias current Ibiasl) at one end and is electrically connected to the base of the transistor Q3 at the other end. The ballast resistor R4 is supplied with a portion of the bias current Ibiasl (ideally 4 / 1 of the bias current Ibiasl) at one end and is electrically connected to the base of the transistor Q4 at the other end. The ballast resistor R5 is supplied with the bias current Ibias2 at one end and is electrically connected to the base of the transistor Q5 at the other end.

[0067] The bias circuit 200 generates the bias current Ibiasl based on the bias control voltage and the current Vbiasl. The bias circuit 200 includes a transistor Q31. The transistor Q31 can exemplify a heterojunction bipolar transistor (HBT), but the present disclosure is not limited thereto. The transistor Q31 is supplied with the bias control voltage and the current Vbiasl at the base via a resistor R31, is electrically connected to the power supply potential Vcc at the collector, and is electrically connected to one end of the ballast resistors R1 to R4 at the emitter. In other words, the transistor Q31 and the ballast resistors R1 to R4 are emitter-follower-connected, but the present disclosure is not limited thereto.

[0068] The bias circuit 210 generates a bias current Ibias2 based on a bias control voltage and a current Vbias2. The bias circuit 210 includes a transistor Q32. The transistor Q32 can be exemplified as a heterojunction bipolar transistor (HBT), but the present disclosure is not limited thereto. The transistor Q32 is supplied with the bias control voltage and the current Vbias2 at a base via a resistor R32, and a collector is electrically connected to a power supply potential Vcc, and an emitter is electrically connected to one end of the ballast resistor R5. In other words, the transistor Q32 and the ballast resistor R5 are connected in an emitter follower connection.

[0069] The bias control circuit 220 controls the bias control voltage and the currents Vbias1 and Vbias2 based on the operation mode control voltage Vmode. Specifically, the bias control circuit 220 controls the bias control voltage and the current Vbias1 to a high level and controls the bias control voltage and the current Vbias2 to a low level in a case where the operation mode control voltage Vmode indicates the first operation mode. Further, the bias control circuit 220 controls the bias control voltage and the current Vbias1 to a low level and controls the bias control voltage and the current Vbias2 to a high level in a case where the operation mode control voltage Vmode indicates the second operation mode. In addition, the high level is a voltage higher than a threshold voltage at which the transistors Q31 and Q32 included in the bias circuits 200 and 210 become in an on state, and the low level is a voltage lower than the threshold voltage.

[0070] In the power amplification circuit 120, in a case of the first operation mode, no current is supplied to the base of the transistor Q5, and the transistor Q5 becomes in a completely off state. In other words, the four transistors Q1 to Q4 become in an on state, and the one transistor Q5 becomes in a completely off state. Further, in the power amplification circuit 120, in a case of the second operation mode, no current is supplied to the bases of the transistors Q1 to Q4, and the transistors Q1 to Q4 become in a completely off state. In other words, the four transistors Q1 to Q4 become in a completely off state, and the one transistor Q5 becomes in an on state.

[0071] As such, in the power amplification circuit 120, the number of transistors in an on state is different between a case of the first operation mode (four) and a case of the second operation mode (one). Therefore, the input impedance of the power amplification circuit 120 is greatly different between a case of the first operation mode and a case of the second operation mode. Thereby, the state of impedance matching between the power amplification circuit 120 and the circuit of the previous stage is broken, and thus, the high-frequency input signal RFin is reflected due to the mismatch, the high-frequency input signal RFin does not enter the power amplification circuit 120, and the output level decreases.

[0072] (Second Comparative Example)

[0073] Figure 3 Fig. 2 is a diagram showing the structure of the power amplification circuit of the second comparative example.

[0074] As for the structural elements of the power amplification circuit 300 of the second comparative example that are the same as those of the power amplification circuit 120 of the first comparative example, the same reference numerals are assigned and the explanation is omitted.

[0075] The power amplification circuit 300 includes transistors Q1 to Q4. The transistors Q1 to Q4 are electrically connected in parallel, forming an amplification circuit.

[0076] The power amplification circuit 300 includes a ballast resistor R11. The ballast resistor R11 is supplied with a bias current Ibias2 at one end and is electrically connected to the base of the transistor Q4 at the other end.

[0077] The emitter of the transistor Q31 is electrically connected to one end of the ballast resistors R1 to R4.

[0078] The emitter of the transistor Q32 is electrically connected to one end of the ballast resistor R11.

[0079] Figure 4 and Figure 5 Fig. 4 is a diagram explaining the operation of the power amplification circuit of the second comparative example. In detail, Figure 4 Fig. 5 is a diagram explaining the operation in the case of the first operation mode of the power amplification circuit 300. Figure 5 Fig. 6 is a diagram explaining the operation in the case of the second operation mode of the power amplification circuit 300.

[0080] Referring to Figure 4 , the bias control circuit 220 controls the bias control voltage and current Vbiasl to be high level and the bias control voltage and current Vbias2 to be low level in the case of the first operation mode. As a result, the transistor Q31 in the bias circuit 200 becomes in the on state and the transistor Q32 in the bias circuit 210 becomes in the off state. Therefore, the bias current Ibiasl is output from the bias circuit 200 as shown by an arrow 310. In addition, the bias current Ibias2 is not output from the bias circuit 210.

[0081] As shown by an arrow 310, a part of the bias current Ibiasl (ideally, 4 / 1 of the bias current Ibiasl) is supplied to the base of the transistor Ql via the ballast resistor Rl. Similarly, a part of the bias current Ibiasl (ideally, 4 / 1 of the bias current Ibiasl) is supplied to the base of the transistor Q2 via the ballast resistor R2. Similarly, a part of the bias current Ibiasl (ideally, 4 / 1 of the bias current Ibiasl) is supplied to the base of the transistor Q3 via the ballast resistor R3. Similarly, a part of the bias current Ibiasl (ideally, 4 / 1 of the bias current Ibiasl) is supplied to the base of the transistor Q4 via the ballast resistor R4.

[0082] Thus, the transistors Ql to Q4 become the on state. Therefore, the high frequency input signal RFin is amplified by the transistors Ql to Q4.

[0083] Referring to Figure 5 , the bias control circuit 220 controls the bias control voltage and current Vbiasl to be low level and the bias control voltage and current Vbias2 to be high level in the case of the 2nd operation mode. Thus, the transistor Q31 in the bias circuit 200 becomes the off state and the transistor Q32 in the bias circuit 210 becomes the on state. Therefore, the bias current Ibias2 is outputted from the bias circuit 210 as shown by an arrow 311. In addition, the bias current Ibiasl is not outputted from the bias circuit 200.

[0084] As shown by an arrow 311, a part of the bias current Ibias2 is supplied to the base of the transistor Q4 via the ballast resistor Rl l.

[0085] Thus, the transistor Q4 becomes the on state. Therefore, the high frequency input signal RFin is amplified by the transistor Q4.

[0086] Furthermore, as shown by an arrow 312, the remaining current Ibias2a of the bias current Ibias2 flows to the ballast resistors R1 to R3 via the ballast resistor R4. A part of the current Ibias2a (ideally, 3 / 1 of the current Ibias2a) is supplied to the base of the transistor Ql via the ballast resistor R4 and Rl. Likewise, a part of the current Ibias2a (ideally, 3 / 1 of the current Ibias2a) is supplied to the base of the transistor Q2 via the ballast resistor R4 and R2. Likewise, a part of the current Ibias2a (ideally, 3 / 1 of the current Ibias2a) is supplied to the base of the transistor Q3 via the ballast resistor R4 and R3. However, the current value of the current supplied to the bases of the transistors Ql to Q3 is smaller than the current value of the current supplied to the base of the transistor Q4. Therefore, the emitter current value per unit emitter area of the transistors Ql to Q3 becomes smaller than that of the transistor Q4, although the transistors Ql to Q3 do not become a completely off state. Therefore, the gain of the transistors Ql to Q3 becomes lower than that of the transistor Q4. Figure 4 The first operation mode described above is different from the second operation mode described above.

[0087] As described with reference to Figure 4 and Figure 5 In the power amplification circuit 300, in the case of the first operation mode, the transistors Ql to Q4 become an on state by supplying the bias current Ibiasl to the bases of the transistors Ql to Q4. Furthermore, in the power amplification circuit 300, in the case of the second operation mode, the transistor Q4 becomes an on state by supplying most of the bias current Ibias2 to the base of the transistor Q4. However, the remaining part of the bias current Ibias2 is also supplied to the bases of the transistors Ql to Q3 via the ballast resistor R4, and the transistors Ql to Q3 become a non-completely off state.

[0088] The power amplification circuit 300 is capable of varying the gain by switching between the first operation mode and the second operation mode.

[0089] Furthermore, in the power amplification circuit 300, in the case of the second operation mode, the transistors Ql to Q3 become a non-completely off state. In other words, in the power amplification circuit 300, the number of transistors that become an on state is the same in the case of the first operation mode and in the case of the second operation mode. Thus, the power amplification circuit 300 is capable of suppressing variation of the input impedance as compared with the power amplification circuit 120.

[0090] (One aspect of the problem)

[0091] The resistance values of the ballast resistors R1 to R4 and R11 can be exemplified as 100 Ω to 200 Ω. The resistance values of the ballast resistors R1 to R4 and R11 are restricted by the chip layout, and thus cannot be set larger than this. Therefore, in the case of the 2nd operation mode, Figure 5 The current indicated by the arrow 312 becomes somewhat larger, and the operation points of the transistors Q1 to Q3 become somewhat higher. Therefore, the gains of the transistors Q1 to Q3 become somewhat higher. Thus, the gain of the power amplification circuit 300 becomes somewhat higher in the case of the 2nd operation mode. However, in the case of the 2nd operation mode, there is a demand to make the gain of the power amplification circuit 300 lower.

[0092] (1st Embodiment)

[0093] Figure 6 is a view showing the structure of the power amplification circuit of the 1st embodiment.

[0094] For the structural elements of the power amplification circuit 1 of the 1st embodiment that are the same as those of the power amplification circuit 120 of the 1st comparative example or the power amplification circuit 300 of the 2nd comparative example, the same reference numerals are attached, and the explanation is omitted.

[0095] The power amplification circuit 1 differs from the power amplification circuit 120 of the 1st comparative example in that it further includes the coupling resistor R21.

[0096] In the 1st embodiment, the transistors Q1 to Q4 correspond to the “one or more 1st transistors” of the present disclosure. The transistor Q5 corresponds to the “one or more 2nd transistors” of the present disclosure. The ballast resistors R1 to R4 correspond to the “one or more 1st resistors” of the present disclosure. The ballast resistor R5 corresponds to the “one or more 2nd resistors” of the present disclosure. The coupling resistor R21 corresponds to the “3rd resistor” of the present disclosure. The bias current Ibias1 corresponds to the “1st bias current” of the present disclosure. The bias current Ibias2 corresponds to the “2nd bias current” of the present disclosure. The high-frequency input signal RFin corresponds to the “1st signal” of the present disclosure. The high-frequency output signal RFout corresponds to the “2nd signal” of the present disclosure.

[0097] One end of the coupling resistor R21 is electrically connected to one end of the ballast resistors R1 to R4. The other end of the coupling resistor R21 is electrically connected to one end of the ballast resistor R5. The resistance value of the coupling resistor R21 is not restricted by the chip layout, and thus can be set larger than the resistance values of the ballast resistors R1 to R5 (for example, 100 Ω to 200 Ω). The resistance value of the coupling resistor R21 can be exemplified as 1 kΩ to 1.5 kΩ, but the present disclosure is not limited thereto.

[0098] Figure 7 andFigure 8 is a view explaining the operation of the power amplification circuit of the first embodiment. In detail, Figure 7 is a view explaining the operation in the case of the first operation mode of the power amplification circuit 1. Figure 8 is a view explaining the operation in the case of the second operation mode of the power amplification circuit 1.

[0099] Referring to Figure 7 , the bias control circuit 220 controls the bias control voltage and current Vbiasl to be high level and controls the bias control voltage and current Vbias2 to be low level in the case of the first operation mode. Thereby, the transistor Q31 in the bias circuit 200 becomes the on state and the transistor Q32 in the bias circuit 210 becomes the off state. Therefore, the bias current Ibiasl is output from the bias circuit 200 as indicated by an arrow 10. In addition, the bias current Ibias2 is not output from the bias circuit 210.

[0100] Most of the bias current Ibiasl is supplied to the base of the transistors Ql to Q4 via the ballast resistors Rl to R4, respectively, as indicated by an arrow 10.

[0101] Thereby, the transistors Ql to Q4 become the on state. Therefore, the high frequency input signal RFin is amplified by the transistors Ql to Q4.

[0102] In addition, the rest of the bias current Ibiasl, Ibiasla, is supplied to the base of the transistor Q5 via the coupling resistor R21 and the ballast resistor R5, as indicated by an arrow 11. However, the resistance values of the ballast resistors Rl to R5 are 100 Ω to 200 Ω, and in comparison, the resistance value of the coupling resistor R21 is 1 kΩ to 1.5 kΩ. Therefore, the current value of the current Ibiasla is very small. In other words, the current value of the current supplied to the base of the transistor Q5 is very small compared to the current values of the currents supplied to the bases of the transistors Ql to Q4, respectively. Therefore, the transistor Q5 does not become the complete off state, but the emitter current value per unit emitter area of the transistor Q5 is very small compared to the transistors Ql to Q4.

[0103] Referring to Figure 8 , the bias control circuit 220 controls the bias control voltage and current Vbiasl to be low level and controls the bias control voltage and current Vbias2 to be high level in the case of the second operation mode. Thereby, the transistor Q31 in the bias circuit 200 becomes the off state and the transistor Q32 in the bias circuit 210 becomes the on state. Therefore, the bias current Ibias2 is output from the bias circuit 210 as indicated by an arrow 12. In addition, the bias current Ibiasl is not output from the bias circuit 200.

[0104] Most of the bias current Ibias2 is supplied to the base of the transistor Q5 via the ballast resistor R5 as indicated by an arrow 12.

[0105] Thus, the transistor Q5 becomes in an on state. Therefore, the high frequency input signal RFin is amplified by the transistor Q5.

[0106] Furthermore, the remaining current Ibias2b of the bias current Ibias2 flows to the ballast resistors R1 to R4 via the coupling resistor R21 as indicated by an arrow 13. A part of the current Ibias2b (ideally, 4 / 1 of the current Ibias2b) is supplied to the base of the transistor Ql via the coupling resistor R21 and the ballast resistor Rl. Likewise, a part of the current Ibias2b (ideally, 4 / 1 of the current Ibias2b) is supplied to the base of the transistor Q2 via the coupling resistor R21 and the ballast resistor R2. Likewise, a part of the current Ibias2b (ideally, 4 / 1 of the current Ibias2b) is supplied to the base of the transistor Q3 via the coupling resistor R21 and the ballast resistor R3. Likewise, a part of the current Ibias2b (ideally, 4 / 1 of the current Ibias2b) is supplied to the base of the transistor Q4 via the coupling resistor R21 and the ballast resistor R4.

[0107] However, the resistance values of the ballast resistors Rl to R5 are 100 Ω to 200 Ω, and in contrast to this, the resistance value of the coupling resistor R21 is 1 kΩ to 1.5 kΩ. Therefore, the current value of the current flowing through the coupling resistor R21 is very small. That is, the current value of the current Ibias2b is very small compared to the current Ibias2a (refer to the first operation mode described in the power amplifier circuit 120). Figure 5 Therefore, the current values of the currents supplied to the bases of the transistors Ql to Q4 are very small compared to the current value of the current supplied to the base of the transistor Q5. Therefore, the emitter current values per unit emitter area of the transistors Ql to Q4 are very small compared to the transistor Q5. Therefore, the gains of the transistors Ql to Q4 are very small compared to the case of the first operation mode described in the power amplifier circuit 120. Figure 7

[0108] The power amplifier circuit 1 is capable of changing the gain by switching between the first operation mode and the second operation mode. Moreover, in the power amplifier circuit 1, in the case of the second operation mode, the transistors Ql to Q4 are in a state of not being completely cut off. Therefore, the power amplifier circuit 1 is capable of suppressing the change in input impedance compared to the power amplifier circuit 120.

[0109] ​Further, in the power amplification circuit 1, in the case of the 2nd operation mode, the operation points of the transistors Q1 to Q4 are lower than those of the power amplification circuit 300. Therefore, in the power amplification circuit 1, in the case of the 2nd operation mode, the gains of the transistors Q1 to Q4 are lower than those of the power amplification circuit 300. Thus, the power amplification circuit 1 can suppress the gain in the case of the 2nd operation mode, compared with the power amplification circuit 300.

[0110] (Comparison between the 1st embodiment and the 1st comparative example)

[0111] The power amplification circuit 1 of the 1st embodiment and the power amplification circuit 120 of the 1st comparative example are compared by circuit simulation.

[0112] Figure 9 is a graph showing a simulation circuit of the power amplification circuit of the 1st embodiment. As shown in Figure 9 , a matching circuit 400 is arranged in the front stage of the power amplification circuit 1. Further, the impedance when the rear stage is observed from the input of the matching circuit 400 is set as Zin1. In addition, the input impedance when the rear stage is observed from the input of the power amplification circuit 1 is set as Zin2. The simulation circuit of the power amplification circuit 120 of the 1st comparative example is also the same as Figure 9 .

[0113] Figure 10 to Figure 12 is a graph showing the result of the circuit simulation of the power amplification circuit of the 1st comparative example.

[0114] Figure 10 is a Smith chart of the impedance Zin1 of the power amplification circuit 120. Figure 10 The waveform 500 in shows the impedance Zin1 of the power amplification circuit 120 in the case of the 1st operation mode at the frequencies of 1 GHz (gigahertz) to 8.5 GHz. The partial waveform 500a, which is a part of the waveform 500, shows the impedance Zin1 of the power amplification circuit 120 at the frequencies of 2.5 GHz to 2.7 GHz. Figure 10 The waveform 501 in shows the impedance Zin1 of the power amplification circuit 120 in the case of the 2nd operation mode at the frequencies of 1 GHz to 8.5 GHz. The partial waveform 501a, which is a part of the waveform 501, shows the impedance Zin1 of the power amplification circuit 120 at the frequencies of 2.5 GHz to 2.7 GHz.

[0115] Figure 11 is a graph showing the Voltage Standing Wave Ratio (V.S.W.R) of the power amplification circuit 120. In Figure 11 , the horizontal axis is the frequency (GHz), and the vertical axis is the V.S.W.R.

[0116] Figure 11 The waveform 502 in FIG. 5B shows the V.S.W.R of the power amplification circuit 120 at the frequencies 2.40 GHz to 2.80 GHz in the case of the 1st operation mode. The partial waveform 502a, which is a part of the waveform 502, shows the V.S.W.R of the power amplification circuit 120 at the frequencies 2.50 GHz to 2.70 GHz. Figure 11 The waveform 503 in FIG. 5B shows the V.S.W.R of the power amplification circuit 120 at the frequencies 2.40 GHz to 2.80 GHz in the case of the 2nd operation mode. The partial waveform 503a, which is a part of the waveform 503, shows the V.S.W.R of the power amplification circuit 120 at the frequencies 2.50 GHz to 2.70 GHz.

[0117] Figure 12 The Smith chart in FIG. 5C is the input impedance Zin2 of the power amplification circuit 120. Figure 12 The waveform 504 in FIG. 5D shows the input impedance Zin2 of the power amplification circuit 120 at the frequencies 1 GHz to 8.5 GHz in the case of the 1st operation mode. The partial waveform 504a, which is a part of the waveform 504, shows the input impedance Zin2 of the power amplification circuit 120 at the frequencies 2.5 GHz to 2.7 GHz. Figure 12 The waveform 505 in FIG. 5D shows the input impedance Zin2 of the power amplification circuit 120 at the frequencies 1 GHz to 8.5 GHz in the case of the 2nd operation mode. The partial waveform 505a, which is a part of the waveform 505, shows the input impedance Zin2 of the power amplification circuit 120 at the frequencies 2.5 GHz to 2.7 GHz.

[0118] Figure 13 to Figure 15 The chart in FIG. 6 is a circuit simulation result showing the power amplification circuit of the 1st embodiment.

[0119] Figure 13 The Smith chart in FIG. 7 is the input impedance Zin1 of the power amplification circuit 1. Figure 13 The waveform 506 in FIG. 7 shows the input impedance Zin1 of the power amplification circuit 1 at the frequencies 1 GHz to 8.5 GHz in the case of the 1st operation mode. The partial waveform 506a, which is a part of the waveform 506, shows the input impedance Zin1 of the power amplification circuit 1 at the frequencies 2.5 GHz to 2.7 GHz. Figure 13 The waveform 507 in FIG. 7 shows the input impedance Zin1 of the power amplification circuit 1 at the frequencies 1 GHz to 8.5 GHz in the case of the 2nd operation mode. The partial waveform 507a, which is a part of the waveform 507, shows the input impedance Zin1 of the power amplification circuit 1 at the frequencies 2.5 GHz to 2.7 GHz.

[0120] Figure 14 The chart in FIG. 8 is a chart showing the V.S.W.R of the power amplification circuit 1. In Figure 14In FIG. 12, the horizontal axis is frequency (GHz), and the vertical axis is V.S.W.R.

[0121] Figure 14 The waveform 508 in FIG. 11 shows the V.S.W.R. of the power amplification circuit 1 at frequencies 2.40 GHz to 2.80 GHz in the case of the 1st operation mode. The partial waveform 508a, which is a part of the waveform 508, shows the V.S.W.R. of the power amplification circuit 1 at frequencies 2.50 GHz to 2.70 GHz. Figure 14 The waveform 509 in FIG. 11 shows the V.S.W.R. of the power amplification circuit 1 at frequencies 2.40 GHz to 2.80 GHz in the case of the 2nd operation mode. The partial waveform 509a, which is a part of the waveform 509, shows the V.S.W.R. of the power amplification circuit 1 at frequencies 2.50 GHz to 2.70 GHz.

[0122] Figure 15 The Smith chart in FIG. 10 is the input impedance Zin2 of the power amplification circuit 1. Figure 15 The waveform 510 in FIG. 10 shows the input impedance Zin2 of the power amplification circuit 1 at frequencies 1 GHz to 8.5 GHz in the case of the 1st operation mode. The partial waveform 510a, which is a part of the waveform 510, shows the input impedance Zin2 of the power amplification circuit 1 at frequencies 2.5 GHz to 2.7 GHz. Figure 15 The waveform 511 in FIG. 10 shows the input impedance Zin2 of the power amplification circuit 1 at frequencies 1 GHz to 8.5 GHz in the case of the 2nd operation mode. The partial waveform 511a, which is a part of the waveform 511, shows the input impedance Zin2 of the power amplification circuit 1 at frequencies 2.5 GHz to 2.7 GHz.

[0123] The waveforms 510 and 511 are compared with each other in a frequency range of frequencies 2.50 GHz to 2.70 GHz. Figure 12 The waveforms 510 and 511 are compared with each other in a frequency range of frequencies 2.50 GHz to 2.70 GHz. Figure 15 The partial waveform 510a (Zin2 in the case of the 1st operation mode) and the partial waveform 511a (Zin2 in the case of the 2nd operation mode) of FIG. 10 are compared with each other. Figure 15 The interval between the partial waveform 510a (Zin2 in the case of the 1st operation mode) and the partial waveform 511a (Zin2 in the case of the 2nd operation mode) of FIG. 10 is narrower than the interval between the partial waveform 504a (Zin2 in the case of the 1st operation mode) and the partial waveform 505a (Zin2 in the case of the 2nd operation mode) of FIG. 9. That is, the amount of change in the input impedance Zin2 of the power amplification circuit 1 between the operation modes is smaller than the amount of change in the input impedance Zin2 of the power amplification circuit 120 between the operation modes. Figure 12 The interval between the partial waveform 510a (Zin2 in the case of the 1st operation mode) and the partial waveform 511a (Zin2 in the case of the 2nd operation mode) of FIG. 10 is narrower than the interval between the partial waveform 504a (Zin2 in the case of the 1st operation mode) and the partial waveform 505a (Zin2 in the case of the 2nd operation mode) of FIG. 9. That is, the amount of change in the input impedance Zin2 of the power amplification circuit 1 between the operation modes is smaller than the amount of change in the input impedance Zin2 of the power amplification circuit 120 between the operation modes.

[0124] The waveforms 510 and 511 are compared with each other in a frequency range of frequencies 2.50 GHz to 2.70 GHz. Figure 10 The waveforms 510 and 511 are compared with each other in a frequency range of frequencies 2.50 GHz to 2.70 GHz. Figure 13 The waveforms 510 and 511 are compared with each other in a frequency range of frequencies 2.50 GHz to 2.70 GHz. Figure 13the interval of the partial waveform 506a (Zinl in the case of the 1st operation mode) and the partial waveform 507a (Zinl in the case of the 2nd operation mode) is narrower than Figure 10 the interval of the partial waveform 500a (Zinl in the case of the 1st operation mode) and the partial waveform 501a (Zinl in the case of the 2nd operation mode) is narrower. That is, the amount of change in the impedance Zinl of the power amplification circuit 1 between the operation modes is smaller than the amount of change in the impedance Zinl of the power amplification circuit 120 between the operation modes. The reason for this is as described above, because the amount of change in the input impedance Zin2 of the power amplification circuit 1 between the operation modes is smaller than the amount of change in the input impedance Zin2 of the power amplification circuit 120 between the operation modes.

[0125] The power amplification circuit 1 of the 1st embodiment and the power amplification circuit 300 of the 2nd comparative example were compared by circuit simulation. Figure 11 and Figure 14 were compared. Figure 14 the V.S.W.R in the case of the 1st operation mode of the power amplification circuit 1 represented by the partial waveform 508a is substantially the same as Figure 11 the V.S.W.R in the case of the 1st operation mode of the power amplification circuit 120 represented by the partial waveform 502a. In other words, the standing wave in the case of the 1st operation mode of the power amplification circuit 1 is substantially the same as the standing wave in the case of the 1st operation mode of the power amplification circuit 120.

[0126] Figure 14 the V.S.W.R in the case of the 2nd operation mode of the power amplification circuit 1 represented by the partial waveform 509a is smaller than Figure 11 the V.S.W.R in the case of the 2nd operation mode of the power amplification circuit 120 represented by the partial waveform 503a. In other words, the standing wave in the case of the 2nd operation mode of the power amplification circuit 1 is smaller than the standing wave in the case of the 2nd operation mode of the power amplification circuit 120.

[0127] As described above, the power amplification circuit 1 can suppress the amount of change in the input impedance between the operation modes compared to the power amplification circuit 120. Furthermore, the power amplification circuit 1 can suppress the standing wave in the case of the 2nd operation mode compared to the power amplification circuit 120. Due to this, the power amplification circuit 1 can suppress the decrease in efficiency and the like in the case of the 2nd operation mode compared to the power amplification circuit 120.

[0128] (Comparison between the 1st embodiment and the 2nd comparative example)

[0129] The power amplification circuit 1 of the 1st embodiment and the power amplification circuit 300 of the 2nd comparative example were compared by circuit simulation.

[0130] Figure 16 to Figure 20is a graph showing the results of circuit simulation of the first embodiment and the second comparative example.

[0131] Figure 16 is a graph showing the gain of the entire power amplification circuit 1 and 300 in the case of the second operation mode. In Figure 16 , the horizontal axis is the output power (dBm) and the vertical axis is the gain (dB).

[0132] In Figure 16 , the waveform 521 shows the gain of the power amplification circuit 1 at 2.50 GHz. The waveform 522 shows the gain of the power amplification circuit 1 at 2.60 GHz. The waveform 523 shows the gain of the power amplification circuit 1 at 2.70 GHz. The waveform 524 shows the gain of the power amplification circuit 300 at 2.50 GHz. The waveform 525 shows the gain of the power amplification circuit 300 at 2.60 GHz. The waveform 526 shows the gain of the power amplification circuit 300 at 2.70 GHz.

[0133] If the waveform 521 and the waveform 524 are compared, the gain of the power amplification circuit 1 at 2.50 GHz is lower than the gain of the power amplification circuit 300 at 2.50 GHz. If the waveform 522 and the waveform 525 are compared, the gain of the power amplification circuit 1 at 2.60 GHz is lower than the gain of the power amplification circuit 300 at 2.60 GHz. If the waveform 523 and the waveform 526 are compared, the gain of the power amplification circuit 1 at 2.70 GHz is lower than the gain of the power amplification circuit 300 at 2.70 GHz.

[0134] Therefore, the power amplification circuit 1 can suppress the gain in the second operation mode compared to the power amplification circuit 300.

[0135] Figure 17 is a graph showing the consumption current of the entire power amplification circuit 1 and 300 in the case of the second operation mode. In Figure 17 , the horizontal axis is the output power (dBm) and the vertical axis is the consumption current (A (ampere)).

[0136] In Figure 17 , the waveform 527 is the consumption current of the power amplification circuit 1 at 2.50 GHz. The waveform 528 is the consumption current of the power amplification circuit 1 at 2.60 GHz. The waveform 529 is the consumption current of the power amplification circuit 1 at 2.70 GHz. The waveform 530 of the consumption current of the power amplification circuit 300 at 2.50 GHz substantially overlaps the waveform 527. The waveform 531 of the consumption current of the power amplification circuit 300 at 2.60 GHz substantially overlaps the waveform 528. The waveform 532 of the consumption current of the power amplification circuit 300 at 2.70 GHz substantially overlaps the waveform 529.

[0137] Therefore, the consumed current in the case of the second operation mode of the power amplification circuit 1 is substantially the same as the consumed current in the case of the second operation mode of the power amplification circuit 300.

[0138] Figure 18 is a graph showing the power added efficiency (PAE) of each of the power amplification circuits 1 and 300 in the case of the second operation mode. In Figure 18 , the horizontal axis is the output power (dBm) and the vertical axis is the PAE (% (percent)). Figure 19 is a partial enlarged view of Figure 18 .

[0139] In Figure 18 and Figure 19 , the waveform 533 is the PAE of the power amplification circuit 1 at 2.50 GHz. The waveform 534 is the PAE of the power amplification circuit 1 at 2.60 GHz. The waveform 535 is the PAE of the power amplification circuit 1 at 2.70 GHz. In Figure 19 , the waveform 536 is the PAE of the power amplification circuit 300 at 2.50 GHz. The waveform 537 is the PAE of the power amplification circuit 300 at 2.60 GHz. The waveform 538 is the PAE of the power amplification circuit 300 at 2.70 GHz.

[0140] The waveform 533 and the waveform 536 substantially overlap. The waveform 534 and the waveform 537 substantially overlap. The waveform 535 and the waveform 538 substantially overlap.

[0141] Therefore, the PAE in the case of the second operation mode of the power amplification circuit 1 is substantially the same as the PAE in the case of the second operation mode of the power amplification circuit 300.

[0142] Figure 20 is a graph showing the V.S.W.R of each of the power amplification circuits 1 and 300 in the case of the second operation mode. In Figure 20 , the horizontal axis is the frequency (GHz) and the vertical axis is the V.S.W.R.

[0143] Figure 20 The waveform 539 in Figure 20Waveform 540 in FIG. 5B shows the V.S.W.R of the power amplification circuit 300 in the case of the 2nd operation mode at the frequency of 2.40 GHz to 2.80 GHz. Partial waveform 540a, which is a part of the waveform 540, shows the V.S.W.R of the power amplification circuit 300 at the frequency of 2.50 GHz to 2.70 GHz.

[0144] The V.S.W.R of the power amplification circuit 1 in the case of the 2nd operation mode, which is shown by the partial waveform 539a, is smaller than the V.S.W.R of the power amplification circuit 300 in the case of the 2nd operation mode, which is shown by the partial waveform 540a. In other words, the standing wave in the case of the 2nd operation mode of the power amplification circuit 1 is smaller than the standing wave in the case of the 2nd operation mode of the power amplification circuit 300.

[0145] As explained above, the power amplification circuit 1 can suppress the gain in the case of the 2nd operation mode while maintaining the input characteristics substantially equivalent to the power amplification circuit 300.

[0146] (Relationship between coupling resistance and ballast resistance)

[0147] Referring again to Figure 8 , if the resistance value of the coupling resistance R21 of the power amplification circuit 1 is too small compared to the resistance values of the ballast resistances R1 to R5, the current shown by the arrow 13 becomes large. Therefore, the operating points of the transistors Q1 to Q4 become high, and the gains of the transistors Q1 to Q4 become high. On the other hand, if the resistance value of the coupling resistance R21 is too large compared to the resistance values of the ballast resistances R1 to R5, the current shown by the arrow 13 hardly flows. Therefore, the transistors Q1 to Q4 become in the off state, and the amount of change in the input impedance of the power amplification circuit 1 between the operation modes becomes large.

[0148] Therefore, it can be considered that there is a preferable range of ratio between the resistance value of the coupling resistance R21 and the resistance values of the ballast resistances R1 to R5.

[0149] Figure 21 and Figure 22 are graphs showing the results of circuit simulation of the 1st embodiment and the 2nd comparative example.

[0150] Figure 21 is a graph showing the overall gain of each of the power amplification circuits 1 and 300 in the case of the 2nd operation mode. In Figure 21 , the horizontal axis is the frequency (GHz), and the vertical axis is the gain (dB).

[0151] The waveform 541 shows the gain of the power amplification circuit 1 from 2.40 GHz to 2.80 GHz in the case where the resistance value of the coupling resistor R21 is set to 2.5 times the resistance values of the ballast resistors R1 to R5. The partial waveform 541a, which is a part of the waveform 541, shows the gain of the power amplification circuit 1 from 2.50 GHz to 2.70 GHz.

[0152] The waveform 542 shows the gain of the power amplification circuit 1 from 2.40 GHz to 2.80 GHz in the case where the resistance value of the coupling resistor R21 is set to 2.5 times the resistance values of the ballast resistors R1 to R5. The partial waveform 542a, which is a part of the waveform 541, shows the gain of the power amplification circuit 1 from 2.50 GHz to 2.70 GHz.

[0153] The waveform 543 shows the gain of the power amplification circuit 1 from 2.40 GHz to 2.80 GHz in the case where the resistance value of the coupling resistor R21 is set to 5 times the resistance values of the ballast resistors R1 to R5. The partial waveform 543a, which is a part of the waveform 541, shows the gain of the power amplification circuit 1 from 2.50 GHz to 2.70 GHz.

[0154] The waveform 544 shows the gain of the power amplification circuit 1 from 2.40 GHz to 2.80 GHz in the case where the resistance value of the coupling resistor R21 is set to 7.5 times the resistance values of the ballast resistors R1 to R5. The partial waveform 544a, which is a part of the waveform 541, shows the gain of the power amplification circuit 1 from 2.50 GHz to 2.70 GHz.

[0155] The waveform 545 shows the gain of the power amplification circuit 1 from 2.40 GHz to 2.80 GHz in the case where the resistance value of the coupling resistor R21 is set to 10 times the resistance values of the ballast resistors R1 to R5. The partial waveform 545a, which is a part of the waveform 541, shows the gain of the power amplification circuit 1 from 2.50 GHz to 2.70 GHz.

[0156] As shown in the partial waveform 542a, in the case where the resistance value of the coupling resistor R21 is set to 2.5 times the resistance values of the ballast resistors R1 to R5, the gain in the second operation mode of the power amplification circuit 1 becomes substantially the same as the gain in the second operation mode of the power amplification circuit 300. Also, as shown in the partial waveforms 543a to 545a, the greater the resistance value of the coupling resistor R21, the more the gain in the second operation mode of the power amplification circuit 1 decreases.

[0157] Therefore, from the viewpoint of suppressing the gain in the second operation mode of the power amplification circuit 1, it is preferable that the resistance value of the coupling resistor R21 be set to 2.5 times or more the resistance values of the ballast resistors R1 to R5.

[0158] Figure 22 is a graph showing the V.S.W.R of each of the power amplification circuit 1 and 300 in the case of the 2nd operation mode. In Figure 22 , the horizontal axis is the frequency (GHz) and the vertical axis is the V.S.W.R.

[0159] The waveform 546 shows the V.S.W.R of the power amplification circuit 300 from 2.40 GHz to 2.80 GHz. The partial waveform 546a, which is a part of the waveform 546, shows the V.S.W.R from 2.50 GHz to 2.70 GHz.

[0160] The waveform 547 shows the V.S.W.R of the power amplification circuit 1 from 2.40 GHz to 2.80 GHz in the case where the resistance value of the coupling resistance R21 is set to 10 times the resistance value of the ballast resistances R1 to R5. The partial waveform 547a, which is a part of the waveform 547, shows the V.S.W.R of the power amplification circuit 1 from 2.50 GHz to 2.70 GHz.

[0161] The waveform 548 shows the V.S.W.R of the power amplification circuit 1 from 2.40 GHz to 2.80 GHz in the case where the resistance value of the coupling resistance R21 is set to 7.5 times the resistance value of the ballast resistances R1 to R5. The partial waveform 548a, which is a part of the waveform 548, shows the V.S.W.R of the power amplification circuit 1 from 2.50 GHz to 2.70 GHz.

[0162] The waveform 549 shows the V.S.W.R of the power amplification circuit 1 from 2.40 GHz to 2.80 GHz in the case where the resistance value of the coupling resistance R21 is set to 5 times the resistance value of the ballast resistances R1 to R5. The partial waveform 549a, which is a part of the waveform 549, shows the V.S.W.R of the power amplification circuit 1 from 2.50 GHz to 2.70 GHz.

[0163] The waveform 550 shows the V.S.W.R of the power amplification circuit 1 from 2.40 GHz to 2.80 GHz in the case where the resistance value of the coupling resistance R21 is set to 2.5 times the resistance value of the ballast resistances R1 to R5. The partial waveform 550a, which is a part of the waveform 550, shows the V.S.W.R of the power amplification circuit 1 from 2.50 GHz to 2.70 GHz.

[0164] As shown in partial waveform 547a, in a case where the resistance value of the coupling resistor R21 is set to 10 times the resistance values of the ballast resistors R1 to R5, the V.S.W.R at 2.50 GHz in the case of the second operation mode of the power amplification circuit 1 is approximately the same as the V.S.W.R at 2.50 GHz in the case of the second operation mode of the power amplification circuit 300. Also, as shown in partial waveforms 548a to 550a, the more the resistance value of the coupling resistor R21 is reduced, the more the V.S.W.R in the case of the second operation mode of the power amplification circuit 1 is reduced.

[0165] Therefore, from the viewpoint of suppressing the V.S.W.R in the second operation mode of the power amplification circuit 1, it is preferable that the resistance value of the coupling resistor R21 be set to 10 times or less the resistance values of the ballast resistors R1 to R5.

[0166] In view of the above, the resistance value of the coupling resistor R21 is preferably set to 2.5 times or more and 10 times or less the resistance values of the ballast resistors R1 to R5.

[0167] (SUMMARY)

[0168] In the power amplification circuit 1, in the case of the second operation mode, most of the bias current Ibias2 is supplied to the base of the transistor Q5 via the ballast resistor R5, and the remaining portion of the bias current Ibias2 is supplied to the bases of the transistors Q1 to Q4 via the coupling resistor R21. Thereby, in the power amplification circuit 1, in the case of the second operation mode, the transistors Q1 to Q4 become a state of non-fully cut-off. In other words, in the power amplification circuit 1, the number of transistors that become an on state is the same in the case of the first operation mode and in the case of the second operation mode. Therefore, the power amplification circuit 1 can suppress the amount of change in input impedance between the operation modes, as compared with the power amplification circuit 120.

[0169] Further, in the power amplification circuit 1, in the case of the second operation mode, the operation points of the transistors Q1 to Q4 become lower as compared with the power amplification circuit 300. Therefore, in the power amplification circuit 1, in the case of the second operation mode, the gains of the transistors Q1 to Q4 become lower as compared with the power amplification circuit 300. Thereby, the power amplification circuit 1 can suppress the gain in the case of the second operation mode, as compared with the power amplification circuit 300.

[0170] Further, the resistance value of the coupling resistor R21 is preferably set to 2.5 times or more and 10 times or less the resistance values of the ballast resistors R1 to R5, from the viewpoint of suppressing the gain in the second operation mode of the power amplification circuit 1 and from the viewpoint of suppressing the V.S.W.R in the second operation mode of the power amplification circuit 1.

[0171] Also, in the power amplification circuit 1, the number of amplification transistors is set to five, the transistors Q1 to Q5, but the present disclosure is not limited to this. The number of amplification transistors can be four or less, and can also be six or more. Also, in the first embodiment, the number of amplification transistors in the case of the first operation mode is set to four, the transistors Q1 to Q4, but the present disclosure is not limited to this. The number of amplification transistors in the case of the first operation mode can be three or less, and can also be five or more. Also, the number of amplification transistors in the case of the second operation mode can be set to one, the transistor Q5, but the present disclosure is not limited to this. The number of amplification transistors in the case of the second operation mode can be two or more. However, since the gain in the case of the second operation mode is lower than the gain in the case of the first operation mode, the number of amplification transistors in the case of the second operation mode can be less than the number of amplification transistors in the case of the first operation mode.

[0172] The power amplification circuit 1 can also be used for a multistage amplification circuit in which a plurality of power amplification circuits are connected in multiple stages. In this case, the power amplification circuit 1 can be used as an amplification circuit of the first stage (a driver stage or a primary stage) of the multistage amplification circuit, can be used as an amplification circuit of the last stage (a power stage or a final stage) of the multistage amplification circuit, and can be used as an amplification circuit of an intermediate stage.

[0173] In the case where the power amplification circuit 1 is used as a driver stage or a primary stage amplification circuit, the amplitude of the high-frequency input signal RFin is small, and thus the characteristics of the high-frequency output signal RFout are easily affected by changes in the input impedance of the power amplification circuit 1. However, since the input impedance of the power amplification circuit 1 changes little between operation modes, the characteristics of the high-frequency output signal RFout are less affected.

[0174] In the case where the power amplification circuit 1 is used as a power stage or a final stage amplification circuit, the output level of the high-frequency output signal RFout is easily adjusted by the gain of the power amplification circuit 1.

[0175] <Second Embodiment>

[0176] Figure 23 is a view showing the structure of the power amplification circuit of the second embodiment.

[0177] The power amplification circuit 1A differs from the power amplification circuit 1 (refer to Figure 6 ) of the first embodiment in that a resistor R41 for an attenuator is electrically connected between the base of the transistor Q5 and the capacitor C5.

[0178] The resistor R41 corresponds to the “one or more fourth resistors” of the present disclosure.

[0179] In the power amplification circuit 1A, the high-frequency input signal RFin input to the base of the transistor Q5 is attenuated by the resistor R41. Therefore, the power amplification circuit 1A can further suppress the gain in the case of the 2nd operation mode.

[0180] In addition, in the power amplification circuit 120 of the 1st comparative example (refer to Figure 2 ) since the amount of change in the input impedance between the operation modes becomes larger, it is not possible to provide the resistor R41 between the base of the transistor Q5 and the capacitor C5. On the other hand, the power amplification circuit 1A suppresses the amount of change in the input impedance between the operation modes by having the coupling resistor R21. Therefore, the power amplification circuit 1A can provide the resistor R41 between the base of the transistor Q5 and the capacitor C5.

[0181] <3rd Embodiment>

[0182] Figure 24 is a view showing the structure of the power amplification circuit of the 3rd embodiment.

[0183] The power amplification circuit 1B is different from the power amplification circuit 1 of the 1st embodiment (refer to Figure 6 ) in the position at which the coupling resistor R21 is connected.

[0184] In the 3rd embodiment, the transistors Q1 to Q3 correspond to "one or more 1st transistors" of the present disclosure. The transistors Q4 and Q5 correspond to "one or more 2nd transistors" of the present disclosure. The ballast resistors R1 to R3 correspond to "one or more 1st resistors" of the present disclosure. The ballast resistors R4 and R5 correspond to "one or more 2nd resistors" of the present disclosure.

[0185] One end of the coupling resistor R21 is electrically connected to one end of the ballast resistors R1 to R3. The other end of the coupling resistor R21 is electrically connected to one end of the ballast resistors R4 and R5.

[0186] In the case of the 1st operation mode, most of the bias current Ibias1 is supplied to the bases of the transistors Q1 to Q3 via the ballast resistors R1 to R3, respectively.

[0187] By this, the transistors Q1 to Q3 become in the on state. Therefore, the high-frequency input signal RFin is amplified by the transistors Q1 to Q3.

[0188] Further, the remaining portion of the bias current Ibiasl (ideally, 2 / 3 of the remaining portion of the bias current Ibiasl) is supplied to the base of the transistor Ql via the coupling resistor R21 and the ballast resistor Rl. Similarly, the remaining portion of the bias current Ibiasl (ideally, 2 / 3 of the remaining portion of the bias current Ibiasl) is supplied to the base of the transistor Q2 via the coupling resistor R21 and the ballast resistor R2. Similarly, the remaining portion of the bias current Ibiasl (ideally, 2 / 3 of the remaining portion of the bias current Ibiasl) is supplied to the base of the transistor Q3 via the coupling resistor R21 and the ballast resistor R3.

[0189] In the case of the 2nd operation mode, the majority of the bias current Ibias2 is supplied to the bases of the transistors Q4 and Q5 via the ballast resistors R4 and R5.

[0190] Thereby, the transistors Q4 and Q5 become in the on state. Therefore, the high-frequency input signal RFin is amplified by the transistors Q4 and Q5.

[0191] Further, the remaining portion of the bias current Ibias2 (ideally, 3 / 4 of the remaining portion of the bias current Ibias2) is supplied to the base of the transistor Ql via the coupling resistor R21 and the ballast resistor Rl. Similarly, the remaining portion of the bias current Ibias2 (ideally, 3 / 4 of the remaining portion of the bias current Ibias2) is supplied to the base of the transistor Q2 via the coupling resistor R21 and the ballast resistor R2. Similarly, the remaining portion of the bias current Ibias2 (ideally, 3 / 4 of the remaining portion of the bias current Ibias2) is supplied to the base of the transistor Q3 via the coupling resistor R21 and the ballast resistor R3.

[0192] Further, the remaining portion of the bias current Ibias2 (ideally, 3 / 4 of the remaining portion of the bias current Ibias2) is supplied to the base of the transistor Ql via the coupling resistor R21 and the ballast resistor Rl. Similarly, the remaining portion of the bias current Ibias2 (ideally, 3 / 4 of the remaining portion of the bias current Ibias2) is supplied to the base of the transistor Q2 via the coupling resistor R21 and the ballast resistor R2. Similarly, the remaining portion of the bias current Ibias2 (ideally, 3 / 4 of the remaining portion of the bias current Ibias2) is supplied to the base of the transistor Q3 via the coupling resistor R21 and the ballast resistor R3.

[0193] The power amplification circuit 1B can adjust the number of amplification transistors in the first operation mode and the number of amplification transistors in the second operation mode by changing the position at which the coupling resistor R21 is connected. Thus, the power amplification circuit 1B can adjust the gain in the first operation mode and the gain in the second operation mode.

[0194] In addition, the third embodiment and the second embodiment can be combined. That is, a resistor for an attenuator can be provided between the base of the transistor Q4 of the power amplification circuit 1B and the capacitor C4, and a resistor for an attenuator can also be provided between the base of the transistor Q5 and the capacitor C5. Thus, the power amplification circuit 1B can suppress the gain in the second operation mode.

[0195] In addition, the above-described embodiments are used to facilitate understanding of the present application, and are not used to limit the interpretation of the present application. The present application can be changed / modified without departing from the spirit thereof, and equivalents thereof are also included in the present application.

Claims

1. A power amplification circuit comprising: one or more first transistors to which a first signal is input at a first terminal; one or more second transistors to which the first signal is input at a first terminal and to which a second terminal of the one or more first transistors is electrically connected; one or more first resistors to which a first bias current is supplied at one end and to which a first terminal of the one or more first transistors is electrically connected at the other end, respectively; one or more second resistors to which a second bias current is supplied at one end and to which a first terminal of the one or more second transistors is electrically connected at the other end, respectively; and a third resistor to which one end of the one or more first resistors is electrically connected and to which one end of the one or more second resistors is electrically connected.

2. A power amplification circuit comprising: one or more first transistors to which a first signal is input at a first terminal; one or more second transistors to which the first signal is input at a first terminal and to which a second terminal of the one or more first transistors is electrically connected; one or more first resistors to which a first bias current is supplied at one end and to which a first terminal of the one or more first transistors is electrically connected at the other end, respectively; one or more second resistors to which a second bias current is supplied at one end and to which a first terminal of the one or more second transistors is electrically connected at the other end, respectively; and a third resistor to which one end of the one or more first resistors is electrically connected and to which one end of the one or more second resistors is electrically connected, wherein in a first operation mode, a part of the first bias current is supplied to the first terminal of the one or more first transistors via the one or more first resistors, and the remaining part of the first bias current is supplied to the first terminal of the one or more second transistors via the third resistor and the one or more second resistors, in a second operation mode in which the gain is relatively lower than in the first operation mode, a part of the second bias current is supplied to the first terminal of the one or more second transistors via the one or more second resistors, and the remaining part of the second bias current is supplied to the first terminal of the one or more first transistors via the third resistor and the one or more first resistors, and a second signal in which the first signal is amplified is output from the second terminal of the one or more first transistors and the one or more second transistors.

3. The power amplification circuit according to claim 1 or 2, further comprising one or more fourth resistors to which the first signal is input at one end and to which a first terminal of the one or more second transistors is electrically connected at the other end, respectively.

4. The power amplification circuit according to claim 1 or 2, wherein a resistance value of the third resistor is more than 2.5 times and less than 10 times a resistance value of the one or more first resistors and the one or more second resistors.

5. The power amplification circuit according to claim 1 or 2, wherein the power amplification circuit is a driver stage amplification circuit of a multi-stage amplification circuit. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 6. The power amplification circuit according to claim 1 or 2, wherein the power amplification circuit is a power stage amplification circuit of a multi-stage amplification circuit.

7. The power amplification circuit according to claim 1 or 2, wherein the one or more first transistors and the one or more second transistors are each a bipolar transistor.

8. The power amplification circuit according to claim 1 or 2, wherein further comprising: a first bias circuit in emitter follower connection with the one or more first resistors, which supplies the first bias current to one end of the one or more first resistors in the case of a first operation mode; and a second bias circuit in emitter follower connection with the one or more second resistors, which supplies the second bias current to one end of the one or more second resistors in the case of a second operation mode.

9. The power amplification circuit according to claim 1 or 2, wherein the one or more first transistors and the one or more second transistors are each a field effect transistor.

10. The power amplification circuit according to claim 1 or 2, wherein the one or more first resistors and the one or more second resistors are each a resistor having a resistance of 1 kΩ or more and 10 kΩ or less.

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