Systems and Methods for SOC Power-On Sequencing

Abstract

Apparatus and associated methods relate to an integrated power-on reset system (PORS) at the system-on-chip (SoC) level. In an illustrative example, an integrated circuit (215) may include a first power domain (300a) and a second power domain (300b). A level shifter circuit (300c) may be coupled to convert data from the first power domain to the second power domain. A PORS (270) including voltage detection circuits (410, 470a, 470b), glitch filter circuits (415, 475a, 475b), and logic gates (420a, 420b) may be configured to generate isolation signals (310, 320) between the first power domain (300a) and the second power domain (300b). The level shifter circuit (300c) may be enabled in response to the generated isolation signals. By using the isolation signals, multiple power domains on the IC (215) may be comprehensively managed during power-on to avoid unstable operation.

Description

Technical Field

[0001] Various embodiments generally relate to integrated circuit devices, and more particularly, to devices including a power management circuit that can manage multiple power supplies provided to a system-on-chip (SoC) during power-on. Background Art

[0002] A programmable integrated circuit (IC) refers to an IC that includes programmable circuitry. An example of a programmable IC is a field-programmable gate array (FPGA). The FPGA is characterized by including programmable circuit blocks. Examples of programmable circuit blocks include, but are not limited to, input / output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), digital signal processing blocks (DSPs), processors, clock managers, and delay lock loops (DLLs).

[0003] By loading configuration data (sometimes referred to as a configuration bitstream) into the device, a circuit design can be physically implemented in the programmable circuitry of the programmable IC. The configuration data can be loaded into internal configuration storage units of the device. The collective state of the individual configuration storage units determines the functionality of the programmable IC. For example, once the configuration data is loaded, the specific operations performed by the various programmable circuit blocks and the connectivity between the programmable circuit blocks of the programmable IC are determined by the collective state of the configuration storage units. Summary of the Invention

[0004] Apparatuses and associated methods relate to an integrated power-on reset system (PORS) at the system-on-chip (SoC) level. In an illustrative example, an integrated circuit can include a first power domain and a second power domain. A level-shifting circuit can be coupled to convert data from the first power domain to the second power domain. The PORS includes a voltage detection circuit, a glitch filter circuit, and logic gates, and the PORS can be configured to generate an isolation signal between the first power domain and the second power domain. The level-shifting circuit is enabled in response to the generated isolation signal. By using the isolation signal, comprehensive management of multiple power domains on the IC can be performed during power-on to avoid unstable operation.

[0005] Various embodiments can achieve one or more advantages. For example, during power - on, a power supply with different ramp rates can be controlled, which can significantly reduce or eliminate contention current on the chip and / or noise coupling between different power domains. In some embodiments, chip damage during power - on caused by multiple voltage cross - domain deficiencies and large current surges can be significantly reduced or eliminated. In some embodiments, an isolation signal can reach a High - Availability Seamless Redundancy protocol (HSR) before a Programmable Logic (PL) obtains a Power - on Reset (POR) signal. When an unexpected POR / reset event occurs, IO glitches can be prevented by delaying the POR signal relative to the isolation signal. In some embodiments, the isolation signal between the PL and the on - chip network (NoC) block power supply may be delayed (e.g., 100 ns) due to PL power - off, which can significantly reduce the noise coupled to the NoC block. Some embodiments can provide power - aware support for a POR voltage detection model for Register Transfer Level (RTL) verification enhancement. Some embodiments can reduce the total power - on time, and some embodiments can improve the performance of the PL structure through on - chip voltage generation. Some embodiments can also provide a PMC deep - sleep mode to reduce system - level power consumption. In some embodiments, after knowing that all PL power supplies (Vccint, Vccint_ram, Vccaux) start from a System Monitor (SYSMON) / Analog Mixer Signal (AMS) during normal mode, a firmware (FM) - dependent skip_por_cnt that skips a 26 - ms counter can be used to generate a por_pl_b signal to minimize the total power - on time. Some embodiments can provide a smooth boundary scan chain across multiple power domains.

[0006] In one exemplary aspect, an integrated circuit (IC) includes a first region powered by a first power domain and a second region powered by a second power domain. A first level - shifting circuit is coupled to convert first data from the first power domain to the second power domain, and a second level - shifting circuit is coupled to convert second data from the second power domain to the first power domain. The IC also includes a Power - on Reset System (PORS). The PORS includes a voltage - detection circuit for detecting the voltages of the first power domain and the second power domain. A control circuit is coupled to the first level - shifting circuit and the second level - shifting circuit and is configured to generate a first isolation signal for controlling the first level - shifting circuit and a second isolation signal for controlling the second level - shifting circuit in response to the detected voltages of the first power domain and the second power domain.

[0007] In some embodiments, the PORS may further include a glitch filter circuit coupled to a voltage detection circuit to indicate a voltage change in the second power domain. When the voltage change in the second power domain exceeds a predetermined time period, the control circuit may be configured to disable the second level shifter circuit after a first predetermined delay after disabling the first level shifter circuit. In some embodiments, the control circuit may further be configured to release a power-on reset signal to reset the second power domain after a second predetermined delay after disabling the second level shifter circuit.

[0008] In some embodiments, the control circuit may be configured to release a power-on reset signal to reset the second power domain after a second predetermined delay after disabling the second level shifter circuit. The second region may be provided in a portion of the IC that does not overlap with the first region. The first region may include a platform management controller (PMC) configured to act as a main power supply and provide power management for the IC. The second region may include programmable logic (PL) blocks. The second region may include a processor system (PS). In some embodiments, the integrated circuit may further include a third region powered by a third power domain. A third level shifter circuit may be coupled to convert third data from the second power domain to the third power domain, and a fourth level shifter circuit may be coupled to convert fourth data from the third power domain to the second power domain. The voltage detection circuit may also be used to detect the voltages of the first power domain, the second power domain, and the third power domain. The control circuit may also be coupled to the third level shifter circuit and the fourth level shifter circuit and configured to generate a third isolation signal for controlling the third level shifter circuit and a fourth isolation signal for controlling the fourth level shifter circuit in response to the detected voltages of the first power domain, the second power domain, and the third power domain. In some embodiments, the third region may include a data processing engine (DPE) array.

[0009] In another exemplary aspect, a method includes powering a first region by a first power domain and powering a second region by a second power domain. A first level shifter circuit is coupled to transfer first data from the first power domain to the second power domain, and a second level shifter circuit is coupled to transfer second data from the second power domain to the first power domain. The method further includes detecting the voltages of the first power domain and the second power domain and generating a first isolation signal for controlling the first level shifter circuit and a second isolation signal for controlling the second level shifter circuit in response to the detected voltages of the first power domain and the second power domain.

[0010] In some embodiments, when the voltage of the second power domain changes over a predetermined period of time, the method may include using a first isolation signal to disable a first level shifter circuit, a first predetermined delay after disabling the first level shifter circuit, using a second isolation signal to disable a second level shifter circuit, and a second predetermined delay after disabling the second level shifter circuit, and releasing a power-on reset signal to reset the second power domain.

[0011] In some embodiments, a second region is disposed in a portion of the IC that does not overlap with the first region. The first region may include a platform management controller (PMC) that is configured to act as a main power supply and provide power management for the IC. In some embodiments, the second region may include a processor system. In some embodiments, the second region may include an extended performance I / O block (XPIO). The second region may include a programmable logic (PL) block.

[0012] In some embodiments, the method may further include (1) powering a third region by a third power domain, a third level shifter circuit being coupled to transfer third data from the second power domain to the third power domain, and a fourth level shifter circuit being coupled to transfer fourth data from the third power domain to the second power domain, (2) detecting the voltages of the first power domain, the second power domain, and the third power domain, and (3) generating a third isolation signal for controlling the third level shifter circuit and a fourth isolation signal for controlling the fourth level shifter circuit in response to the detected voltages of the first power domain, the second power domain, and the third power domain.

[0013] In some embodiments, when the voltage of the third power domain changes over a predetermined period of time, the method may further include (4) using the third isolation signal to disable the third level shifter circuit, (5) a third predetermined delay after disabling the third level shifter circuit, using the fourth isolation signal to disable the fourth level shifter circuit, and, (6) a fourth predetermined delay after disabling the fourth level shifter circuit, and releasing a power-on reset signal to reset the third power domain. In some embodiments, the third region may include a data processing engine (DPE) array.

[0014] Details of various embodiments are set forth in the accompanying drawings and the following description. Other features and advantages are apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Exemplary programmable integrated circuits on which the disclosed circuits and processes may be implemented are described;

[0016] Figure 2 Exemplary integrated circuits having a power-on reset system (PORS) at the system-on-chip (SoC) level are described;

[0017] Figure 3A Describes an exemplary schematic diagram of different power domains on an IC;

[0018] Figure 3B Describes an exemplary interface architecture between the interconnect block power domain and the XPIO power domain of programmable logic (PL);

[0019] Figure 4 Describes an exemplary architecture of a power-on reset system on an IC;

[0020] Figure 5 Describes a data sheet related to exemplary isolation signals generated by PORS;

[0021] Figure 6 Describes a flowchart of an exemplary method for coordinating power conversion between IC power domains;

[0022] Like reference symbols in the figures indicate like elements. Detailed Description

[0023] For ease of understanding, this document is organized as follows. First, with reference to Figure 1 briefly introduced an exemplary platform (e.g., FPGA) for comprehensively managing signal isolation across power domains under power-on transient conditions. Second, with reference to Figures 2 - 4 , this document then turns to describe how an exemplary power-on reset system (PORS) can be used to generate isolation signals between different power domains. Then, with reference to Figure 5 , this document discloses exemplary isolation signals generated by the power-on reset system (PORS). Finally, with reference to Figure 6 , this document discloses an exemplary method for coordinating power conversion between the power domains of an IC. By using the power-on reset system (PORS), multiple powers of a system-on-chip (SoC) can be managed during power-on, thereby significantly reducing or eliminating contention current on the chip.

[0024] Figure 1 Depicts an exemplary programmable integrated circuit (IC) on which the disclosed circuits and processes can be implemented. The programmable IC 100 includes FPGA logic. The programmable IC 100 can be implemented with various programmable resources and can be referred to as a system-on-chip (SoC). Various examples of FPGA logic can include several different types of programmable logic blocks in an array.

[0025] For example Figure 1Shown is a programmable IC 100, which includes a large number of different programmable tile blocks. The programmable tile blocks include multi-gigabit transceivers (MGTs) 101, configurable logic blocks (CLBs) 102, block random access memories (BRAMs) 103, input / output blocks (IOBs) 104, configuration and clock logic (CONFIG / CLOCKS) 105, digital signal processing blocks (DSPs) 106, dedicated input / output blocks (I / Os) 107 (e.g., clock ports), and other programmable logic 108 (e.g., digital clock managers, analog-to-digital converters, system monitoring logic). The programmable IC 100 includes a dedicated processor block (PROC) 110. The programmable IC 100 may include internal and external reconfiguration ports (not shown).

[0026] In various examples, a serializer / deserializer can be implemented by using the MGT 101. The MGT 101 may include various data serializers and deserializers. The data serializer may include various multiplexer implementations. The data deserializer may include a demultiplexer implementation.

[0027] In some examples of FPGA logic, each programmable tile block includes a programmable interconnect element (INT) 111, which has standard connections 124 to and from corresponding interconnect elements in each adjacent tile block. Thus, the programmable interconnect elements together implement the programmable interconnect structure for the shown FPGA logic. The programmable interconnect element INT 111 includes intra-connections 120 to and from programmable logic elements in the same tile block, as shown in the example including Figure 1 In the example shown. The programmable interconnect element INT 111 includes inter-INT interconnects 122 to and from the programmable interconnect element INT 111 in the same tile block, as shown in Figure 1 In the example shown.

[0028] For example, the CLB 102 may include configurable logic elements (CLE) 112, which may be programmed to implement user logic together with a single programmable interconnect element INT 111. The BRAM 103 may include BRAM logic elements (BRL) 113 and one or more programmable interconnect elements. In some examples, the number of interconnect elements included in a cell block may depend on the height of the cell block. In the illustrated embodiment, the BRAM cell block has the same height as five CLBs, but may also be other numbers (e.g., four). The DSP cell block 106 may include DSP logic elements (DSPL) 114 and one or more programmable interconnect elements. For example, the IOB 104 may include two instances of input / output logic elements (IOL) 115 and one instance of a programmable interconnect element INT 111. For example, the actual I / O pads connected to the I / O logic element 115 may be fabricated using a metal that is stacked above the various logic blocks shown and may not be limited to the area of the input / output logic element 115.

[0029] In the illustrated implementation, the columnar region near the die center ( Figure 1 shown shaded in ) is used for configuration, clock, and other control logic. The horizontal region 109 extending from the columns distributes clock and configuration signals across the width of the programmable IC 100. Note that the references to "columnar" and "horizontal" regions are with respect to viewing the figure in the longitudinal direction.

[0030] Using Figure 1 Some programmable ICs with the illustrated architecture may include other logic blocks that disrupt the regular columnar structure that makes up the programmable IC. The other logic blocks may be programmable blocks and / or dedicated logic. For example, Figure 1 the illustrated processor block PROC 110 spans several columns of CLBs 102 and BRAMs 103.

[0031] Figure 1 An example of a programmable IC architecture is shown. The number of logic blocks in a column, the relative widths of the columns, the number and order of the columns, the types of logic blocks included in a column, the relative sizes of the logic blocks, and the interconnect / logic implementation are provided only as examples. For example, in an actual programmable IC, more than one adjacent column of CLBs 102 may be included wherever the CLB 102 appears to facilitate the efficient implementation of user logic.

[0032] Programmable logic (PL) and a processor system (PS) can be integrated on a single chip to have comprehensive functionality. For example, a single chip can be implemented in communication systems, medical devices, and the vision field. A single chip can have multiple power domains. For example, different ramp rates of any / all power supplies may result in coupled noise and contention current. A power-on reset system (PORS) can be used during power-on to manage signal transmission between different power domains, where the different power domains are operably powered by multiple power supplies of a single chip.

[0033] Figure 2 An exemplary integrated circuit having a power-on reset system (PORS) at the system-on-chip (SoC) level is described. In the example described, communication system 200 includes base station 205. Base station 205 can be used to transmit and receive analog signals from mobile phone 210. Base station 205 includes integrated circuit (IC) 215 for data communication between base station 205 and mobile phone 210. IC 215 can also be used for data processing by using separate circuits powered by multiple power domains respectively. In various embodiments, for example, the multiple power domains can be powered by separate, independent voltage regulators. For example, various embodiments can be separate domains powered by a common regulator through independent circuit paths and can have separate inductive filtering or capacitive filtering.

[0034] In the example described, IC 215 is implemented as a device of the system-on-chip (SoC) type. Generally speaking, an SoC refers to an IC that includes two or more subsystems capable of interacting with each other. As an example, an SoC can include a processor that executes program code and one or more other circuits. The other circuits can be implemented as hardwired circuits, programmable circuits, other subsystems, and / or any combination thereof. These circuits can cooperate with each other and / or with the processor. In the example described, the SoC includes a data processing engine (DPE) array 220. DPE array 220 can include one or more DPEs. For example, a DPE can include a math engine (ME).

[0035] For illustrative purposes, IC 215 includes programmable logic (PL) 230. PL 230 is a circuit that can be programmed to perform a specific function. As an example, PL 230 can be implemented as a field programmable gate array (FPGA) circuit. PL 230 can include an array of programmable circuit blocks. Examples of programmable circuit blocks within PL 230 include, but are not limited to, interconnect blocks 231, PL interface blocks 232, configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), digital signal processing blocks (DSPs), clock managers, and / or delay locked loops (DLLs). In Figure 2In the example, PL 230 is shown as two separate parts. In another example, PL 230 can be implemented as a unified region of a programmable circuit. In yet another example, PL 230 can be implemented as more than two different programmable circuit regions. The specific organization of PL 230 is not intended as a limitation. In some embodiments, PL 230 can include some programmable circuit blocks. Each programmable circuit block within PL 230 can include programmable interconnect circuitry (e.g., interconnect block 231) and programmable logic circuitry. The programmable interconnect circuitry can include a large number of interconnect lines of different lengths interconnected by programmable interconnect points (PIPs). The interconnect lines are configured (e.g., on a per-line basis) to provide per-bit connectivity (e.g., where each line conveys one bit of information). The programmable logic circuitry implements user-designed logic using programmable elements, which can include, for example, lookup tables, registers, arithmetic logic, and so on. The programmable interconnect (e.g., interconnect block 231) and the programmable logic circuitry can be programmed by loading configuration data into internal configuration storage units that define how the programmable elements are configured and operate.

[0036] In some embodiments, multiple power supplies may be required to power different PL resources in IC 215. Different resources can operate at different voltage levels to improve performance or signal strength while maintaining enhanced immunity to noise and parasitic effects. For example, interconnect block 231 can operate in V ccint power domain. Thus, the PL interface 232 can be used to interface between different voltage domains. Refer to Figure 3B for a more detailed description of an example of the PL interface architecture.

[0037] IC 215 also includes a processor system (PS) 235 implemented as hardwired circuitry that is fabricated as part of IC 215. PS 235 can be implemented as, or include, any one of a variety of different processor types. For example, PS 235 can be implemented as a single processor, such as a single-core capable of executing program code. In another example, PS 235 can be implemented as a multi-core processor. In yet another example, PS 235 can include one or more cores, modules, coprocessors, interfaces, and / or other resources. PS 235 can be implemented using any one of a variety of different types of architectures. Example architectures that can be used to implement PS 235 include, but are not limited to, the ARM processor architecture, the x86 processor architecture, the RISC architecture, the GPU architecture, the mobile processor architecture, the DSP architecture, and other suitable architectures capable of executing computer-readable instructions or program code. In some embodiments, PS 235 can have a low power domain (LPD) and a full power domain (FPD).

[0038] IC 215 also includes subsystems, such as a network-on-chip (NoC) 225, and / or any hardwired circuit blocks 240, 245, 250, 255, and / or 260. Through the NoC 225, one or more DPEs in the DPE array 220 can communicate with the PS and / or the hardwired circuit blocks 255 and 260. For example, in some embodiments, the hardwired circuit blocks 255 and 260 may include I / O (e.g., extended performance I / O (XPIO) 256) or a memory controller (MC). In some embodiments, one or more DPEs in the DPE array 220 can communicate with the hardwired circuit blocks 240, 245, 250 via a system-on-chip (SoC) interface block and the PL 230. In some embodiments, the SoC interface block may be directly coupled to one or more subsystems of the IC 215. For example, the SoC interface block may be directly coupled to the PS 235 and / or other hardwired circuit blocks. In a particular embodiment, the hardwired circuit blocks 240-260 may be considered examples of an ASIC.

[0039] In the described example, the PS 235 also includes a platform management controller (PMC) 265. The PMC 265 is designed to be the main power source responsible for power management (e.g., power-on / power-off, reset, isolation, IRO clock). In some embodiments, the PMC 265 itself may be a power domain that must be started and is available to start the IC 215 and all other functions on the IC 215. Other power domains may be designed as subordinate power domains to the PMC power domain. For example, the power supply of the PL 230 (e.g., the power domain of the interconnect block 231) is designed as a subset of the PMC 265 power supply. In some embodiments, for example, the PL 230 may operate at a different reference voltage and a different clock speed from the DPE array 220 and / or the PS 235.

[0040] The PMC 265 also includes a power-on reset system (PORS) 270. The PORS 270 is configured to generate multiple isolation signals across power domains. The PORS 270 is also configured to generate a power-on reset (POR) signal and power status signals for different power supplies after detecting all power supplies. The power status signals for different power supplies may indicate the stability of different power domains (e.g., the PL power domain, the PMC power domain). Refer to Figure 3A Examples of the PORS for controlling the sequencing between power domains in an IC during ramp-up and / or ramp-down are described in more detail.

[0041] Although in the described example, the PORS 270 is arranged in the PMC 265, in various embodiments, the PORS 270 may be implemented in different places (e.g., in the programmable logic PL).

[0042] In some embodiments, PORS 270 can be implemented as a hard block fixed circuit. For example, an application specific integrated circuit (ASIC) can provide PROS 270 for generating isolation signals and POR signals.

[0043] In some embodiments, some or all of the functions of PORS 270 can be implemented in a processor (e.g., PS 235) that is configured to execute a set of instructions stored in a data memory to control the generation of isolation signals and / or POR signals. The processor (e.g., PS 235) and the data memory can be arranged on the same integrated circuit 215 as PL 230. In some embodiments, the processor (e.g., PS 235) and the data memory can be implemented in a programmable logic block (e.g., PL 230) of a system on a chip (SoC) or in a hard circuit block by using fixed circuits of the SoC.

[0044] Figure 3A An exemplary schematic diagram of different power domains on an IC is depicted. Different functional blocks on IC 215 can operate at different voltages, and thus, IC 215 can include several power domains. For example, PS 235 can include a low power domain (LPD) and / or a full power domain (FPD), NoC 225 can have different power domains, and the DPE array 220 can have another different power domain. In the example described, PMC 265 itself is a power domain and must be powered on and available to power on IC 215 and all other functions on IC 215.

[0045] In the described example, the IC 215 includes a first power domain 300a (powered by a first voltage) and a second power domain 300b (powered by a second voltage). The first power domain 300a and the second power domain 300b can power one or more functional blocks. For example, in some embodiments, the DPE array 220 can be powered by the first power domain 300a. In some embodiments, the PS 235 can be powered by the first power domain 300a. In some embodiments, the PL 230 can be powered by the first power domain 300a. In some embodiments, the XPIO 256 can be powered by the first power domain 300a. In some embodiments, the NoC 225 can be powered by the second power domain 300b. In some embodiments, the DPE array 220 can be powered by the second power domain 300b. The IC 215 also includes an interface circuit 300c, (e.g., the PL interface 232), for interfacing between the PMC power domain 300 and the first power domain 300a. In the described example, the interface circuit 300c, (e.g., the PL interface 232), is also used for interfacing between the first power domain 300a and the second power domain 300b. In some embodiments, other interface circuits can be used for interfacing between the first power domain 300a and the second power domain 300b. In some embodiments, the IC 215 can include multiple interface blocks for interfacing between corresponding different power domains. For example, Figure 2 the DPE array 220 in Figure 2 can include a first interface block for communicating with the NoC 225 and a second interface block for communicating with the interconnect block 231. In other examples, the IC 215 can include many different power domains (e.g., more than five power domains).

[0046] To control the sequencing between different power domains, the PORS 270 can receive the power states (e.g., voltages) of different power domains and process them to generate isolation signals for application to the interface block, and / or generate power-reset signals to reset one or more different power domains. For example, the PORS 270 receives the power state 301 (e.g., voltage) of the PMC power domain 300 and the first power state 302 of the first power domain 300a. The received power states can be processed by the PORS 270 to generate an isolation signal 304a. The isolation signal 304a can enable or disable the interface circuit 300c to initiate data transfer between the two power domains 300, 300a. The interface circuit 300c can include multiple level-shifting circuits that can be disabled or enabled by the isolation signal 304a to convert data from the PMC power domain 300 to the first power domain 300a or convert data from the first power domain 300a to the PMC power domain 300. For example, when the isolation signal is at a high level (e.g., digital 1), the interface circuit 300c between the PMC power domain 300 and the first power domain 300a can be enabled. When the isolation signal is at a low level (e.g., digital 0), the interface circuit 300c between the two power domains 300, 300a can be disabled. By controlling the delay between different isolation signals, the power-on and / or power-off sequence of different power domains can be controlled. Thus, the contention current and / or noise coupling between different power domains can be advantageously reduced. In the example described herein, the PORS 270 also receives the power state 301 (e.g., voltage) of the PMC power domain 300, the first power state 302 of the first power domain 300a, and the second power state 303 of the second power domain 300b. The received power states can be processed by the PORS 270 to generate an isolation signal 304b. The isolation signal 304b can enable or disable the interface circuit 300c to initiate data transfer between the two power domains 300a, 300b. For example, when the isolation signal is at a high level (e.g., digital 1), the interface circuit 300c between the two power domains 300a, 300b can be enabled. When the isolation signal is at a low level (e.g., digital 0), the interface circuit 300c between the two power domains 300a, 300b can be disabled. By controlling the delay between different isolation signals, the power-on and / or power-off sequence of different power domains can be controlled. Thus, the contention current and / or noise coupling between different power domains can be advantageously reduced. An example of the PORS architecture will be described in more detail with reference to Figure 4 be described in more detail.

[0047] Figure 3B An exemplary interface architecture between an interconnect block power domain and an XPIO power domain in a programmable logic (PL) is described. More specifically, in the example described, the PL interface 232 is capable of operating between two different power domains (e.g., V ccint domain and V ccint_socinterface between domains). In this case, the PL interface 232 is capable of providing the operating voltage V of the interconnect block 231 ccint and the operating voltage V of other circuits in the IC 215 (e.g., NoC 225 and / or XPIO 256) ccint_soc interface for conversion between. For example, other circuits may include a NoC, a math engine (ME), functional blocks in a low power domain (LPD), and / or functional blocks in a full power domain (FPD). In the example described herein, the PL interface 232 includes a first level shifter 305 configured to convert signals from the SoC power domain (e.g., the power domain of the NoC and XPIO) to the PL power domain and allow compatibility between the SoC power domain and the PL power supply. The first level shifter 305 is controlled by the isolation signal iso_soc_pl_b 310. For example, the first level shifter 305 can be enabled or disabled based on whether the isolation signal iso_soc_pl_b 310 is a digital 1 or a digital 0.

[0048] The PL interface 232 includes a second level shifter 315 configured to convert signals from the PL power domain to the SoC power domain and allow compatibility between the PL power domain and the SoC power domain. The second level shifter 315 is controlled by the isolation signal iso_pl_soc_b 320. The isolation signals iso_soc_pl_b 310 and iso_pl_soc_b 320 can be used as gate signals in the level shifters 305 / 315 across the PL power domain and the SoC power domain on the chip. The isolation signals can be generated by the PORS 270. Refer to Figure 4 for a more detailed description of an example of the PORS. In some embodiments, the connection between the PL interface 232 and the PL 230 is programmable (e.g., configurable) in width. For example, the connection between the PL interface 232 and the PL 230 can be configured to be 32 bits, 64 bits, or 128 bits wide. In the example described herein, the PORS 270 also generates a POR signal por_pl_b to reset the V ccint domain having a voltage change (e.g., glitch) of not less than, for example, 40 ns ccint domain. The PORS 270 also generates a POR signal por_int_b to reset the interconnect block 231. In some embodiments, the POR signal por_int_b can be generated later than the POR signal por_pl_b (e.g., about 3 us) to allow sufficient time for the data in the interconnect block 231 to be received by other functional blocks.

[0049] Figure 4Depicts an exemplary architecture of a power-on reset system on an IC. In the described example, PORS 270 includes a first circuit 405 configured to generate power-on reset signals (e.g., generate a first power-on reset signal por_int_b for the interconnect block in PL 230, a second power-on reset signal por_pl_pmc_b for the PL-related logic present in PMC 265, and a third power-on reset signal por_pl_b for PL 230).

[0050] The first circuit 405 includes a first voltage detection circuit 410. The first voltage detection circuit 410 includes power-on detectors that detect the power supplies of PL 230, PS 235, and PMC 265. In the described example, the first voltage detection circuit 410 detects the core supply voltage V of PL (e.g., interconnect block 231) ccint , the supply voltage V of block BRAM cc_ram , the auxiliary supply voltage V of the PL auxiliary logic ccaux , the core supply voltage V of PMC 265 ccint_pmc , and the auxiliary supply voltage V of the PMC auxiliary logic ccaux_pmc . Then, the detected voltages are filtered by a first glitch filter circuit 415 to filter out any power-off power glitches, such as those approximately 40 ns or shorter. Then, the filtered voltages are processed by a first logic circuit 420a to generate the power-on reset signals por_int_b, por_pl_pmc_b, and por_pl_b. The POR signal por_int_b can be used to reset the interconnect block 231, and the POR signal por_pl_b can be used to reset the entire V ccint domain.

[0051] In the described example, the first logic circuit 420a includes a first logic AND circuit 425. All of the filtered voltages are received by the first logic AND circuit 425 to produce a first AND signal POR_1. The first AND signal POR_1 is delayed by 26 ms or 1 us. A selection circuit (e.g., a dual-input multiplexer) 430 is used to receive the 26 ms delay signal and the 1 us delay signal. A selection signal skip_por_cnt is used to output either the 26 ms delay signal or the 1 us delay signal. The user can select between the two delay signals by using the selection signal skip_por_cnt. Then, the output signal is delayed by 2 ms to produce a first intermediate signal por_pl_pmc_b_src. The 2 ms delay can help V gg to stabilize, V ggIt can be the power supply voltage regulated by the configuration storage unit of the interconnect block 231. The first intermediate signal por_pl_pmc_b_src and the hardware-related signal pl_ipor_b are received by the dual-input AND gate 435 to generate the por_pl_pmc_b_buf_int signal. The hardware-related signal pl_ipor_b is a function of the external signal Ext_por_b and an external test signal (e.g., Joint Test Action Group (JTAG) mode). The signal pl_ipor_b can be gated through boundary scan, and the boundary scan chain can span multiple power domains. In some embodiments, the isolation control of multiple power domains can be software-controlled, and the PL and SoC power domains can be coupled to the por_pl_b signal. The por_ipor_b signal can control the por_pl_b signal to meet JTAG requirements.

[0052] Then the por_pl_pmc_b_buf_int signal is processed to generate the power-on reset signals por_int_b, por_pl_pmc_b, and por_pl_b. More specifically, the por_pl_pmc_b_buf_int signal is received by the first buffer 440. The first buffered por_pl_pmc_b_buf_int signal is delayed by 3 us during a power ramp-down. The first buffered por_pl_pmc_b_buf_int signal and the 3 us-delayed por_pl_pmc_b_src signal are received by the first dual-input OR gate 445 to generate the first power-on reset signal por_int_b. The por_pl_pmc_b_buf_int signal is received by the second buffer 450. For example, the second buffered por_pl_pmc_b_buf_int signal is delayed by approximately 200 ns during a power ramp-down. The second buffered por_pl_pmc_b_buf_int signal and the 200 ns-delayed por_pl_pmc_b_buf_int signal are received by the second dual-input OR gate 455 to generate the second power-on reset signal por_pl_pmc_b. The second power-on reset signal por_pl_pmc_b is an internal POR signal used in the PMC power domain 300. Then the second power-on reset signal por_pl_pmc_b is buffered by the third buffer 460 to generate the third power-on reset signal por_pl_b. The third power-on reset signal por_pl_b is an internal POR that is released after all internal PMC and PL detectors trip and the interconnect and configuration storage unit are ready for configuration. The third power-on reset signal por_pl_b can also ensure that the internal regulated power supply (V gg ) is in a rising and stable state.

[0053] The first power-on reset signal por_int_b is a delayed version of por_pl_b and can be used to avoid interconnect contention during power-off.

[0054] The second power-on reset signal por_pl_pmc_b can have the same function as the third power-on reset signal por_pl_b.

[0055] In the example described, PORS 270 also includes a second circuit 465 configured to generate an isolation signal for the PL interface 232. The second circuit 465 includes a second voltage detection circuit 470a. The second voltage detection circuit 470a detects the core supply voltage V of the PMC ccint_pmc and the auxiliary supply voltage V of the PMC auxiliary logic ccaux_pmc . Then the second detected voltage is filtered by the second glitch filter circuit 475a. The filtered second voltage is then processed by the second dual-input AND gate 480a to generate the second AND signal POR_2. The second AND signal POR_2 is received by the V ccaux_pmc level shifter 485a to generate a second intermediate signal init_pmc_aux_lvish_aux_n. Then, the second AND signal POR_2 and the external power-on reset signal Ext_por_b are received by the third dual-input AND gate 480b to generate the third AND signal pmc_raw_por_n. The third AND signal pmc_raw_por_n can be used as the main power-on reset signal for the entire IC 215. The external power-on reset signal Ext_por_b is released by the user to confirm whether the PMC power ramps up. User confirmation may be required before releasing the actual internal POR signal. In some embodiments, the first AND signal POR_1 and the second AND signal POR_2 can be monitored by a watchdog circuit. When the first voltage detection circuit 410 and / or the second voltage detection circuit 470a fails, the watchdog circuit can detect the failure and force the first AND signal POR_1 and the second AND signal POR_2 externally to bypass the first voltage detection circuit 410 and / or the second voltage detection circuit 470a to ensure the generation of the isolation signal. The first AND signal POR_1 and the second AND signal POR_2 can be used as a fail-safe option.

[0056] The second circuit 465 also includes a third voltage detection circuit 470b. The third voltage detection circuit 470b detects the power status of all power domains in the IC 215 except the PMC power domain 300. In the example described, the third voltage detection circuit 470b detects the core supply voltage V of the NoC 225 or XPIO 256 ccint_soc , the low power domain V of the PS 235 cc_psintlp , the full power domain V of the PS 235 cc_psintfp , the core supply voltage V of the PL 230 ccint, the internal core supply voltage V of the block BRAM ccint_ram and the auxiliary supply voltage V of the PL auxiliary logic ccaux . For example, the third voltage detection circuit 470b can also detect the power supply state of the DPE array 220. In the depicted example, the voltage detected by the third voltage detection circuit 470b is filtered by the third glitch filter circuit 475b. All the filtered third detection voltages are output as power supply state signals. The filtered third detection voltages, the third AND signal pmc_raw_por_n, the first control signal ctrl_iso_pmc_pl, the second control signal ctrl_iso_pl_soc, and the first intermediate signal por_pl_pmc_b_src are processed by the second logic circuit 420b to generate isolation signals between different power domains. The first control signal ctrl_iso_pmc_pl and the second control signal ctrl_iso_pl_soc can be stored in on-chip control registers. For example, the first control signal ctrl_iso_pmc_pl can be a register-based control signal to release or isolate signals from the PMC power domain (V ccint_pmc ) to the PL power domain (V ccint ). For example, when the control signal ctrl_iso_pmc_pl is at a high level (e.g., digital 1), signals from the PMC power domain (V ccint_pmc ) to the PL power domain (V ccint ) can be isolated. When the control signal ctrl_iso_pmc_pl is at a low level (e.g., digital 0), signals from the PMC power domain (V ccint_pmc ) to the PL power domain (V ccint ) can be released. The second control signal ctrl_iso_pl_soc can also be a register-based control signal to release or isolate signals from the PL power domain (V ccint ) to the NoC / XPIO power domain (V ccint_soc ). Various control signals ctrl_iso_* can be similarly generated for various power domain crossings not shown in Figure 4 but listed in Figure 5 .

[0057] In the described example, the filtered V ccint , the third AND signal pmc_raw_por_n, and the inverted first control signal ctrl_iso_pmc_pl are received by a three-input AND gate 480c to generate a fourth AND signal. The fourth AND signal is the isolation signal iso_pl_pmc_b. The isolation signal iso_pl_pmc_b can be used to enable the level shifter for converting data from the PL 230 to the PMC 265. The isolation signal iso_pl_pmc_b is also by the first V ccintThe level shifter 485b receives to generate the isolation signal iso_pmc_pl_b. The isolation signal iso_pmc_pl_b can enable the level shifter to transfer data from the PMC 265 to the PL 230. The four-input AND gate 480d receives the filtered V ccint , the filtered V ccint_soc , and the inverted second control signal ctrl_iso_pl_soc to generate the fifth AND signal. The fifth AND signal is received by the second V ccint level shifter 485c to generate the isolation signal iso_soc_pl_b. The isolation signal iso_soc_pl_b can be used to enable the level shifter to transfer data from the SoC 215 to the PL 230. For example, the fifth AND signal is also processed by the V ccint_soc level shifter 485d, delayed by about 100 ns during a power ramp-down, and processed by the OR gate 490 to generate the isolation signal iso_pl_soc_b. The isolation signal iso_pl_soc_b can be used to enable the level shifter to transfer data from the PL 230 to the SoC 215. An exemplary data sheet of the isolation signals generated by the second logic circuit is referenced to Figure 5 described.

[0058] For example, in one mode, all voltages in the PMC domain (e.g., V ccint_pmc , V ccaux_pmc ) and the V ccint of the PL may all be at a high level. By controlling the ctrl_iso_pmc_pl signal, the isolation signals iso_pmc_pl_b and iso_pl_pmc_b can be generated at a high level (e.g., digital 1). Therefore, the corresponding level shifters arranged between the PMC and the PL controlled by the isolation signals can be enabled. In another mode, when all voltages in the PMC domain (e.g., V ccint_pmc , V ccaux_pmc ) are at a high level, and the voltage V ccint in the PL domain and the voltage V ccaux_soc in the NoC / XPIO domain are at a high level, by controlling the ctrl_iso_pl_soc signal, the isolation signals iso_soc_pl_b 310 and iso_pl_soc_b 320 can be generated at a high level (e.g., digital 1). Therefore, the corresponding level shifters controlled by the isolation signals can be enabled.

[0059] In some embodiments, for example, in response to a disturbance (e.g., a power-off glitch) less than approximately 40 ns in any of the PMC power domains or the SoC power domains, the first glitch filter circuit 415, the second glitch filter circuit 475a, and / or the third glitch filter circuit 475b may be configured to keep the generated isolation signal enabled. The disturbance may be a voltage that drops below a predetermined minimum operating voltage threshold within a time less than a predetermined time threshold. When there is a glitch power-off greater than 40 ns on the PL power supply (e.g., V ccint_ram , V ccint , V ccaux ), compared to the isolation signal iso_soc_pl_b 310, the generation of the isolation signal iso_pl_soc_b 320 may be delayed. For example, the isolation signal iso_pl_soc_b 320 may be generated approximately 100 ns later than the isolation signal iso_soc_pl_b 310. Thus, the second level shifter 315 may be enabled approximately 100 ns later than the first level shifter 305. Then PORS 270 generates a por_pl_b signal with a 200 ns delay compared to the isolation signal iso_soc_pl_b 310 to reset the V ccint domain. This way of sequencing the isolation signals can prevent noise or glitches from propagating to the XPIO 256 during a power-off. The level shifter (e.g., the second level shifter 315) from the interconnect (PL domain) to the XPIO (SoC domain) clamps for 100 ns (iso_pl_soc_b = 0) before turning off the PL domain by setting por_pl_b low. Then, the interconnect block 232 can be reset to por_pl_b by the por_int_b signal later within 3 us to avoid any contention in the interconnect due to the V gg storage cells.

[0060] Figure 5 Describes an exemplary data table related to exemplary isolation signals generated by a power-on reset system. The data table includes isolation signals between different power domains. For example, the data table includes the isolation signal iso_soc_pmc_b and the isolation signal iso_pl_pmc_b. The data table also includes isolation signals between the math engine and the PL (e.g., iso_1_me_pl, iso_1_pl_me, iso_2_me_pl, etc.), and isolation signals between the math engine and the SoC (e.g., iso_1_me_soc, iso_1_soc_me, iso_2_me_soc, etc.). Splitting a portion of the POR to meet the requirements of the math engine (ME) can significantly reduce or eliminate buffering / loading requirements.

[0061] Figure 6A flowchart depicting an exemplary method for coordinating power transitions between power domains in an IC. The power transitions may include powering on and / or off power domains in the IC 215. In method 600, at 605, a controller (e.g., PS 235) detects whether the PMC power domain 300 (e.g., main power) is powered on. If the PMC power domain 300 is not yet powered on (e.g., V ccint_pmc and V ccaux_pmc are at a low level), the controller continuously monitors the status of the PMC power domain 300. If the PMC power domain 300 is powered on (e.g., V ccint_pmc , V ccaux_pmc are at a high level), then, in the example described, at 610, the controller instructs a voltage detection circuit to detect the power status S0 (e.g., voltage) of the PMC power domain 300, the power status S1 (e.g., voltage) of the first power domain (e.g., 300a) (e.g., auxiliary power), and the power status S2 of the second power domain (e.g., 300b) (e.g., auxiliary power). For example, the voltage detection circuit detects the power V ccint_soc of the XPIO domain and the power V ccint of the interconnect domain. In some embodiments, the first power domain and the second power domain may be any power domains in the IC 215 other than the PMC power domain (e.g., PL, PS, NoC, XPIO, or ME). In some embodiments, the controller may instruct the voltage detection circuit to detect the power status S0 (e.g., voltage) of the PMC power domain 300 and the power status S1 (e.g., voltage) of the first power domain (e.g., 300a) and generate an isolation signal and / or a POR signal as needed for the PMC power domain and / or the first power domain 300a.

[0062] At 615, the controller determines whether the PMC power domain, the first power domain, and / or the second power domain have glitches not less than a predetermined threshold (e.g., 40 ns). For example, in this illustrative embodiment, the controller determines whether the second power domain has glitches greater than or equal to 40 ns.

[0063] If the glitches are less than 40 ns, then at 620, the controller instructs the PORS 270 to generate a first isolation signal (e.g., 310) to allow a first level shifter (e.g., level shifter circuit 305) to transfer data from the first power domain (e.g., the first power domain 300a) to the second power domain (e.g., the second power domain 300b), and at 625, the controller instructs the PORS270 to generate a second isolation signal (e.g., the second isolation signal 320) to allow a second level shifter (e.g., level shifter circuit 315) to transfer data from the second power domain to the first power domain. And the method loops back to 615 to continue monitoring whether the second power domain has glitches greater than or equal to 40 ns.

[0064] If the glitch is greater than or equal to 40 ns (e.g., the glitch is between 40 ns and 80 ns), then at 630, the controller instructs PORS 270 to generate a first isolation signal to disable a first level shifter that transfers data from a first power domain to a second power domain, and at 635 and 640, the controller instructs PORS 270 to generate a second isolation signal to disable a second level shifter that transfers data from the first power domain to the second power domain after a first predetermined delay (e.g., 100 ns) after the generation of the first isolation signal. At 645 and 650, the controller instructs PORS 270 to generate a POR signal to reset the second power domain with a second predetermined delay (e.g., 200 ns after the generation of the first isolation signal, or 100 ns after the generation of the second isolation signal).

[0065] In some embodiments, when the first power domain or the PMC power domain has a large glitch (e.g., has a voltage perturbation greater than 40 ns), PORS 270 may generate a POR signal to reset the first power domain or the PMC power domain.

[0066] Different subsystems (e.g., PL (interconnect), NoC (SoC), XPIO, ME, and / or PS) may be controlled for different isolation signals. By generating isolation signals and POR signals with different predetermined delays (e.g., approximately 100 ns delay, 3 us delay, 200 ns delay), smooth power sequencing can be controlled to avoid contention among various powers during power-on and / or power-off. For example, when one of the PL powers ramps down, the sequencing of the isolation signal between PL and SoC can be controlled to avoid glitch propagation to XPIO when one of the PL powers ramps down. The event sequence for avoiding glitches may include: first, isolating XPIO / SoC from PL by using iso_soc_pl_b. Then, isolating PL from SoC by using the iso_pl_soc_b signal that is delayed by approximately 100 ns during power-off, and then releasing the signal por_pl_b that is delayed by approximately 200 ns compared to the isolation from XPIO / SoC to PL during power-off. Thus, by setting por_pl_b low, the level shifter from the interconnect module in the PL domain to the SoC domain of XPIO is fixed before turning off the PL domain.

[0067] Although various embodiments have been described with reference to the accompanying drawings, other embodiments are also possible. For example, a small PORS may be used when adding a new power domain. In some embodiments, the PL interface 232 (e.g., level shifters 305, 320) may be arranged on the PS 235 or the PL 230.

[0068] In some embodiments, some or all of the voltage detection circuits 410, 470a, 470b may be disposed on the PS 235 or the PL 230. In another embodiment, some or all of the logic gates (e.g., AND gates, OR gates) in the first circuit 405 and the second circuit 465 may be disposed on the PS 235 or the PL 230.

[0069] Various examples of modules may be implemented by using circuits, including various electronic hardware. By way of example and not limitation, the hardware may include transistors, resistors, capacitors, switches, integrated circuits, and / or other modules. In various examples, a module may include: analog and / or digital logic, discrete components, traces, and / or memory circuits fabricated on a silicon substrate including various integrated circuits (e.g., FPGA, ASIC). In some embodiments, a module may involve the execution of pre-programmed instructions and / or software by a processor. For example, various modules may involve hardware or software.

[0070] In various embodiments, a communication system may communicate using suitable communication methods, devices, and technologies. For example, the system may communicate with compatible devices (e.g., devices capable of transmitting data to and / or from the system) using point-to-point communication, where messages are transmitted directly from a source to a receiver via a dedicated physical link (e.g., fiber optic link, infrared link, ultrasonic link, point-to-point wiring, daisy chain). Components of the system may exchange information via analog or digital data communication in any form or medium, including packet-based messages on a communication network. Examples of communication networks include, for example, LAN (Local Area Network), WAN (Wide Area Network), MAN (Metropolitan Area Network), wireless and / or optical networks, and the computers and networks that form the Internet. Other embodiments may transmit messages by broadcasting to all or substantially all of the devices coupled together via a communication network, e.g., by using an omnidirectional radio frequency (RF) signal. Other embodiments may transmit messages having highly directional characteristics, e.g., RF signals transmitted using a directional (i.e., narrow beam) antenna or optionally infrared signals used in conjunction with focusing optics. Other embodiments using appropriate interfaces and protocols are also possible, e.g., by way of example and not limitation, USB2.0, FireWire, ATA / IDE, RS-232, RS-422, RS-485, 802.11a / b / g / n, Wi-Fi, WiFi-Direct, Li-Fi, Bluetooth, Ethernet, IrDA, FDDI (Fiber Distributed Data Interface), token ring networks, or multiplexing techniques based on frequency, time, or code division. Some embodiments may optionally include functions such as error checking and correction (ECC) for data integrity, or security measures such as encryption (e.g., WEP) and password protection.

[0071] Numerous embodiments have been described. However, it should be understood that various modifications can be made. For example, favorable results can be achieved if the steps of the disclosed technology are performed in a different order, or if the components of the disclosed system are combined in a different manner, or if these components are supplemented with other components. Accordingly, other embodiments are within the scope of the following claims.

Claims

1. An integrated circuit, characterized in that, The integrated circuit includes: A first region powered by a first power domain; A second region powered by a second power domain; A first level shifter circuit coupled to convert first data from the first power domain to the second power domain; A second level shifter circuit coupled to convert second data from the second power domain to the first power domain; A power-on reset system, which includes: A voltage detection circuit configured to detect the voltages of the first power domain and the second power domain; A glitch filter circuit coupled to the voltage detection circuit to indicate a voltage change in the second power domain; and A control circuit coupled to the first level shifter circuit and the second level shifter circuit, and configured to generate a first isolation signal for controlling the first level shifter circuit and a second isolation signal for controlling the second level shifter circuit in response to the detected voltages of the first power domain and the second power domain, wherein, when the voltage change in the second power domain exceeds a predetermined time period, the control circuit is further configured to disable the second level shifter circuit after a first predetermined delay after disabling the first level shifter circuit.

2. The integrated circuit according to claim 1, wherein, The control circuit is further configured to release a power-on reset signal to reset the second power domain after a second predetermined delay after disabling the second level shifter circuit.

3. The integrated circuit according to claim 1, characterized in that, The second region is disposed in a portion of the integrated circuit that does not overlap with the first region.

4. The integrated circuit according to claim 1, characterized in that, The first region includes a platform management controller configured to act as a main power source and provide power management for the integrated circuit.

5. The integrated circuit according to claim 4, wherein The second region includes a processor system or a programmable logic block.

6. The integrated circuit according to claim 5, wherein, The integrated circuit further includes: A third region powered by a third power domain; A third level shifter circuit coupled to convert third data from the second power domain to the third power domain; and, A fourth level shifter circuit coupled to convert fourth data from the third power domain to the second power domain, wherein the voltage detection circuit is further configured to detect the voltages of the first power domain, the second power domain, and the third power domain, the control circuit is further coupled to the third level shifter circuit and the fourth level shifter circuit, and is configured to generate a third isolation signal for controlling the third level shifter circuit and a fourth isolation signal for controlling the fourth level shifter circuit in response to the detected voltages of the first power domain, the second power domain, and the third power domain.

7. A method for power-on sequencing of a system-on-chip, characterized in that, The method includes: Powering a first region by a first power domain; Powering a second region by a second power domain, wherein a first level shifter circuit is coupled to transfer first data from the first power domain to the second power domain, and a second level shifter circuit is coupled to transfer second data from the second power domain to the first power domain; Detecting the voltages of the first power domain and the second power domain; and Generating a first isolation signal for controlling the first level shifter circuit and a second isolation signal for controlling the second level shifter circuit in response to the detected voltages of the first power domain and the second power domain; Wherein, when the voltage change of the second power supply domain exceeds a predetermined time period, using the first isolation signal to disable the first level-shifting circuit; after a first predetermined delay after disabling the first level-shifting circuit, using the second isolation signal to disable the second level-shifting circuit; and after a second predetermined delay after disabling the second level-shifting circuit, releasing a power-on reset signal to reset the second power supply domain.

8. The method according to claim 7, wherein The second region is disposed in a portion of the integrated circuit that does not overlap with the first region.

9. The method according to claim 8, characterized in that The first region includes a platform management controller, which is configured to serve as a main power supply and provide power management for the integrated circuit.

10. The method according to claim 9, wherein The second region includes a processor system, an extended performance I / O block, or a programmable logic block.

11. The method according to claim 10, wherein The method further includes: powering a third region by a third power supply domain, wherein a third level-shifting circuit is coupled to transfer third data from the second power supply domain to the third power supply domain, and a fourth level-shifting circuit is coupled to transfer fourth data from the third power supply domain to the second power supply domain; detecting the voltages of the first power supply domain, the second power supply domain, and the third power supply domain; and in response to the detected voltages of the first power supply domain, the second power supply domain, and the third power supply domain, generating a third isolation signal for controlling the third level-shifting circuit and a fourth isolation signal for controlling the fourth level-shifting circuit.

12. The method according to claim 11, wherein The method further includes, when the voltage change of the third power supply domain exceeds a predetermined time period, using the third isolation signal to disable the third level-shifting circuit; after a third predetermined delay after disabling the third level-shifting circuit, using the fourth isolation signal to disable the fourth level-shifting circuit; and, after a fourth predetermined delay after disabling the fourth level-shifting circuit, releasing a power-on reset signal to reset the third power supply domain.

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