Area efficient dual-port and multi-port SRAM, area efficient memory cells for SRAM

Abstract

The present disclosure relates to a static random access memory and a memory cell for the static random access memory, the memory cell comprising: a first transistor (M1), a second transistor (M2), a third transistor (M3) and a fourth transistor (M4) forming first and second cross-coupled inverters (INV1, INV2), wherein the first and second cross-coupled inverters (INV1, INV2) define a first storage node (D) and an inverted first storage node (D'), wherein the first inverter (INV1) is connected to a first reference voltage (GND1) and a first power supply voltage (VDD1), and wherein the second inverter (INV2) is connected to a second reference voltage (GND2) and a second power supply voltage (VDD2); a fifth transistor (M5) connected between the first storage node (D) and a first bit line (BL1); a sixth transistor (M6) connected between the inverted first storage node (D') and a second bit line (BL2); a first word line ( WL1), the first word line (WL1) controls the access of the first bit line (BL1) to the first storage node (D); and a second word line (WL2) independent of the first word line (WL1), the second word line is connected to the sixth transistor (M6), the second word line (WL2) controls the access of the second bit line (BL2) to the inverted first storage node (D') independently of the first word line (BL1); wherein the relative voltage level of the first word line (WL1) and the first reference voltage (GND1), or the relative voltage level of the first power supply voltage (VDD1) and the first reference voltage (GND1), or the relative voltage level of the second word line (WL2) and the second reference voltage (GND2), or the relative voltage level of the second power supply voltage (VDD2) and the second reference voltage (GND2), or the relative voltage level of the first reference voltage (GND1) and the second reference voltage (GND2) are configured so that data of the first storage node (D) and the inverted first storage node (D') can be read and written independently.

Description

Technical Field

[0001] The present disclosure relates to an area efficient memory cell for a static random access memory (SRAM), a memory array of the memory cell, and an area efficient dual-port or multi-port SRAM. Background Art

[0002] Static random access memory is widely used in integrated circuits and can account for a large portion of the circuit area and power consumption. A typical memory cell of SRAM memory is a six-transistor (6T) memory cell consisting of six MOSFETs. Each bit is stored on four transistors that form two cross-coupled inverters. In addition to these four transistors, the two cross-coupled inverters are connected to the bit line and the inverted bit line through two additional access transistors, which are controlled by the common word line in a standard single-port 6T SRAM cell. The transistors must be sized appropriately to perform single read and write operations in a reliable manner.

[0003] In the case of dual-port or multi-port SRAMs, two transistors must be added to the 6T memory cell for each additional required port. Therefore, conventional dual-port memories are implemented as 8T memory cells. It can be appreciated that the advantages of having additional ports in an SRAM come with an increase in cost, namely the number of transistors, which in turn means an increase in manufacturing cost due to the larger chip area. In addition to the increased area, dual-port SRAMs consume more power than single-port SRAMs. These disadvantages generally outweigh the advantages of using dual-port SRAMs.

[0004] Attempts have been made to address the above shortcomings by designing new memory cells. However, these approaches are generally not portable to different technology nodes and may be associated with many manufacturing challenges. Most of the previous work on emulating dual-port functionality using 6T bit cells is based on time division multiplexing. At this point, time division multiplexing refers to a method in which the 6T bit cell has been accessed by a scheduling scheme or delay scheme that schedules two sequential read / write operations in a single clock cycle. This is similar to performing two operations in a faster single-port SRAM and distributing the data to two different ports. Summary of the invention

[0005] The object of the present invention is to provide an area efficient static random access memory and a memory cell for a static random access memory, wherein a 6T memory cell can be used in a dual-port SRAM. The present disclosure relates in a first embodiment to a memory cell for a static random access memory, the memory cell comprising:

[0006] - a first transistor (M1), a second transistor (M2), a third transistor (M3) and a fourth transistor (M4) forming first and second cross-coupled inverters (INV1, INV2), wherein the first and second cross-coupled inverters (INV1, INV2) define a first storage node (D) and an inverted first storage node (D'), wherein the first inverter (INV1) is connected to a first reference voltage (GND1) and a first supply voltage (VDD1), and wherein the second inverter (INV2) is connected to a second reference voltage (GND2) and a second supply voltage (VDD2);

[0007] - a fifth transistor (M5) connected between the first storage node (D) and the first bit line (BL1);

[0008] - a sixth transistor (M6) connected between the inverted first storage node (D') and the second bit line (BL2);

[0009] - a first word line (WL1) connected to the fifth transistor (M5), the first word line (WL1) controlling access of the first bit line (BL1) to the first storage node (D); and

[0010] a second word line (WL2) independent of the first word line (WL1), the second word line being connected to the sixth transistor (M6), the second word line (WL2) controlling access of the second bit line (BL2) to the inverted first storage node (D') independently of the first bit line (BL1);

[0011] Among them, the relative voltage level of the first word line (WL1) and the first reference voltage (GND1), or the relative voltage level of the first power supply voltage (VDD1) and the first reference voltage (GND1), or the relative voltage level of the second word line (WL2) and the second reference voltage (GND2), or the relative voltage level of the second power supply voltage (VDD2) and the second reference voltage (GND2), or the relative voltage level of the first reference voltage (GND1) and the second reference voltage (GND2), or the relative voltage level of the first bit line (BL1) and the first reference voltage (GND1) or the first power supply voltage (VDD1), or the relative voltage level of the second bit line (BL2) and the second reference voltage (GND2) or the second power supply voltage (VDD2) are configured so that data of the first storage node (D) and the inverted first storage node (D') can be read and written independently.

[0012] The inventors have realized that a dual-port 6T memory cell can be obtained by breaking the practice of using the access transistor pair (M5, M6) in conjunction with each other for read and write access, and accessing them independently. Figure 1In the conventional 6T design shown, writing operations, especially writing logic "1", are challenging. A "1" is written by pushing the complementary inverted value onto BL. WL is then asserted. The transistors are sized so that the latched value overrides the previous state of the cross-coupled inverters. In practice, the access NMOS transistors M5 and M6 must be stronger than the bottom NMOS (M2, M4) or top PMOS (M1, M3) transistors to override the previous state of the inverters. Sizing the inverters can be challenging. The transistors in an SRAM cell need to be carefully sized to ensure proper operation. In general, the goal is to minimize the transistors while keeping reads and writes as fast and reliable as possible. In order to write a "1" in a reliable manner, the complementary inverted value has been previously latched into BL and In the memory cell and corresponding memory of the present disclosure, the relative voltage level of the first word line (WL1) to the first reference voltage (GND1), or the relative voltage level of the first power supply voltage (VDD1) to the first reference voltage (GND1), or the relative voltage level of the second word line (WL2) to the second reference voltage (GND2), or the relative voltage level of the second power supply voltage (VDD2) to the second reference voltage (GND2) can alternatively be dynamically processed by increasing or decreasing one or more of the individual reference levels so that the value can only be written from one side. In addition, the accessed bit line can be boosted, preferably in combination with the dynamic processing of the mentioned relative voltage levels, in order to force the value stored in the cross-coupled inverter. It may be advantageous to boost the voltage of the first bit line (BL1) to a level significantly higher than VDD1 during a write access, for example to a level at least twice, or at least 2.5 times, or at least 3 times the first power supply voltage (VDD1). Similarly, during write access, the second bit line (BL2) can be boosted to a level of at least twice, or at least 2.5 times, or at least 3 times the first power supply voltage (VDD2). This can be combined with boosting of the first and second word lines, which will be explained in further detail below. In one embodiment, the bit lines and word lines of the port can be boosted simultaneously. According to one embodiment, the first word line voltage of the first word line (WL1) is boosted, for example, to a level of at least twice the first power supply voltage (VDD1), and the first bit line voltage of the first bit line (BL1) is boosted, for example, to a level of at least twice the first power supply voltage (VDD1) during write access of the first storage node (D). Similarly, the second word line voltage of the second word line (WL2) can be boosted, for example, to a level at least twice the first power supply voltage (VDD2), and the second bit line voltage of the second bit line (BL2) can be boosted, for example, to a level at least twice the second power supply voltage (VDD2) during a write access of the second storage node (D'). By boosting the bit lines and word lines, efficient access from one side can be achieved. This technique can be repeated on the third and fourth ports, i.e., boosting the third word line (WL3) and the third bit line (BL3) simultaneously, and boosting the fourth word line (WL4) and the fourth bit line (BL4) simultaneously, and so on.

[0013] In order to use area-efficient memory cells in a memory structure, the memory cells can be arranged in a cell array, for example, m*n cells. Instead of using a first bit line (BL1) and a second bit line (BL2) (usually BL and ) have an association between accesses to the bit cells, and the bit lines can be completely independent for read and write accesses. Thus, a dual-port 6T memory cell can be obtained. In the same way, instead of having an association between a first word line (WL1) and a second word line (WL2) (usually the same WL is used for the bit cells), the word lines can be completely independent for read and write accesses. Therefore, in another embodiment, the present disclosure relates to a static random access memory, comprising:

[0014] - Multiple memory cells described in this disclosure - those skilled in the art will appreciate that different embodiments may be used;

[0015] - row decoder;

[0016] - column decoder;

[0017] - sense amplifier;

[0018] - A voltage supply controller for providing voltages for a power supply voltage, a reference voltage, a word line and a bit line of a memory cell.

[0019] Typically a random access memory will include multiple address and data ports, and often read and write enable ports. The address decoders (ie row and column decoders) generate signals for the bit lines and word lines to the memory cell array.

[0020] In addition, the static random access memory may include a boost unit for providing a voltage level to each of the first reference voltage (GND1), the second reference voltage (GND2), the first power supply voltage (VDD1) and the second power supply voltage (VDD2), the first bit line (BL1), the second bit line (BL2), the first word line (WL1) and the second word line (WL2). Preferably, the boost unit is configured so that the relative voltage level of the first word line (WL1) and the first reference voltage (GND1), or the relative voltage level of the first power supply voltage (VDD1) and the first reference voltage (GND1), or the relative voltage level of the second word line (WL2) and the second reference voltage (GND2), or the relative voltage level of the second power supply voltage (VDD2) and the second reference voltage (GND2) of each memory cell is configured so that data of the first storage node (D) and the inverted first storage node (D') can be read and written independently.

[0021] The concepts of the present disclosure can be extended to memories with more than two ports. For example, if a true dual-port random access memory (allowing independent reading and writing) can be implemented using six transistors, a four-port random access memory can also be implemented using eight transistors, such as Figure 3 shown.

[0022] These and other aspects of the invention are set forth in the following detailed description of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A prior art memory cell of a static random access memory is shown, wherein the WL and BL signals are interrelated.

[0024] Figure 2 An example of a memory cell for static random access memory of the present disclosure is shown in the form of a 6T dual-port memory cell.

[0025] Figure 3 An example of a memory cell for static random access memory of the present disclosure is shown in the form of an 8T quad-port memory cell.

[0026] Figure 4 Examples of voltage levels that are boosted (increased) during read or write access and voltage levels that are reduced during read or write access are shown.

[0027] Figure 5 An example of a static random access memory including a memory cell array of the present disclosure is shown, wherein the bit lines and word lines of the memory cells are independent of each other.

[0028] Figure 6 An example of a boost unit is shown.

[0029] Figure 7 An example of a boost cell is shown, which is configured to provide 2*VDD in a single cycle.

[0030] Figure 8 An example of a boost cell is shown, which is configured to provide X*VDD in a single cycle. DETAILED DESCRIPTION

[0031] The present disclosure relates to a static random access memory, including a memory cell array, wherein the memory cell includes: a first transistor (M1), a second transistor (M2), a third transistor (M3) and a fourth transistor (M4) forming first and second cross-coupled inverters (INV1, INV2), wherein the first and second cross-coupled inverters (INV1, INV2) define a first storage node (D) and an inverted first storage node (D'), wherein the first inverter (INV1) is connected to a first reference voltage (GND1) and a first power supply voltage (VDD1), and wherein the second inverter (INV2) is connected to a second reference voltage (GND2) and a second power supply voltage (VDD2). The memory cell may also include a fifth transistor (M5) connected between the first storage node (D) and a first bit line (BL1) for accessing the first storage node (D). The memory cell may also include a sixth transistor (M6) connected between the inverted first storage node (D') and a second bit line (BL2) for accessing the inverted first storage node (D'). Preferably, the first word line (WL1) is connected to the fifth transistor (M5), wherein the first word line (WL1) controls the access of the first bit line (BL1) to the first storage node (D). Similarly, a second word line (WL2) independent of the first word line (WL1) may be connected to the sixth transistor (M6), wherein the second word line (WL2) controls the access of the second bit line (BL2) to the inverted first storage node (D') independently of the first bit line (BL1). In order to allow independent use of word lines and bit lines, the memory may further include a voltage supply controller, preferably a voltage boosting unit, for providing voltage to the power supply voltage (VDD1, VDD2), reference voltage (GND1, GND2), word lines and bit lines of the memory cell. Preferably, the voltage supply controller is configured so that the relative voltage level of the first word line (WL1) and the first reference voltage (GND1), or the relative voltage level of the first power supply voltage (VDD1) and the first reference voltage (GND1), or the relative voltage level of the second word line (WL2) and the second reference voltage (GND2), or the relative voltage level of the second power supply voltage (VDD2) and the second reference voltage (GND2), or the relative voltage level of the first reference voltage (GND1) and the second reference voltage (GND2) is configured so that data of the first storage node (D) and the inverted first storage node (D') can be read and written independently.

[0032] The static random access memory may also include a row decoder for accessing a row (word line) of the memory based on a logic value on a memory port. The row decoder may accordingly use a word line boost unit to boost the voltage of the accessed word line. The static random access memory may also include a column decoder for accessing a column (bit line) of the memory based on a logic value on a memory port. The column decoder may accordingly use a bit line boost unit to boost the voltage of the accessed bit line. Figure 5 In the example of , the bit lines BL11 and BL12 (as well as BL21 and BL22, etc.) can be accessed independently. This is possible because, for example, the relative voltage of the first word line (WL1) to the first reference voltage (GND1), or the relative voltage of the first power supply voltage (VDD1) to the first reference voltage (GND1), or the relative voltage of the second word line (WL2) to the second reference voltage (GND2), or the relative voltage of the second power supply voltage (VDD2) to the second reference voltage (GND2), or the relative voltage of the first reference voltage (GND1) to the second reference voltage (GND2) can be configured. Similarly, the word lines WL11 and WL12 (as well as WL21 and WL22, etc.) can be accessed independently. The row decoder can accordingly use the word line boost unit to boost the voltage of the accessed word line. The voltage supply controller can also be arranged to provide voltage to the GND1 and GND2 voltages of the memory cell.

[0033] The static random access memory may also include a sense amplifier, a precharge circuit, and any other peripheral memory logic. The voltage supply controller may include a boost unit for providing a voltage level to a first reference voltage (GND1) and / or a second reference voltage (GND2) and / or a first power supply voltage (VDD1) and / or a second power supply voltage (VDD2) and / or a first bit line (BL1) and / or a second bit line (BL2) and / or a first word line (WL1) and / or a second word line (WL2) of the memory cell.

[0034] By controlling the relative voltage level of the first word line (WL1) and the first reference voltage (GND1), or the relative voltage level of the first power supply voltage (VDD1) and the first reference voltage (GND1), or the relative voltage level of the second word line (WL2) and the second reference voltage (GND2), or the relative voltage level of the second power supply voltage (VDD2) and the second reference voltage (GND2), the first storage node (D) and the inverted first storage node (D') can be accessed from only one side. For example, in Figure 5In the example of , the first port of the dual-port memory can be used to read or write a memory cell in the left column by accessing BL11, and the second port can be used to read or write another memory cell by accessing BL12. The first power supply voltage (VDD1), the second power supply voltage (VDD2), the first bit line (BL1), the first word line (WL1), the second bit line (BL2), and the second word line (WL2) can be separate voltages that are controlled independently of each other. The first reference voltage (GND1) and the second reference voltage (GND2) can also be separate voltages that are controlled independently of each other.

[0035] Dual-port memory can be defined as a memory that allows multiple reads or writes to occur simultaneously or nearly simultaneously on two ports. "True" dual-port memory is sometimes referred to as a memory in which a shared array of memory cells can be accessed simultaneously from each port. The static random access memory of the present disclosure can have a first bidirectional port or a first unidirectional port and a second bidirectional port or a second unidirectional port (in the case of a dual-port memory). The port can include any necessary configuration of data, address, enable, and clock ports. The memory cell of the dual-port SRAM of the present disclosure can be a 6T SRAM dual-port memory cell. Compared with the prior art solution in which an internal faster clock signal is used to read or write multiple times, the memory of the present disclosure can be a static random access memory with an array of 6T SRAM dual-port memory cells, and the 6T SRAM dual-port memory cell is a 6T SRAM single-cycle dual-port memory cell.

[0036] Each memory cell of the static random access memory may include:

[0037] - a first transistor (M1), a second transistor (M2), a third transistor (M3) and a fourth transistor (M4) forming first and second cross-coupled inverters (INV1, INV2), wherein the first and second cross-coupled inverters (INV1, INV2) define a first storage node (D) and an inverted first storage node (D'), wherein the first inverter (INV1) is connected to a first reference voltage (GND1) and a first supply voltage (VDD1), and wherein the second inverter (INV2) is connected to a second reference voltage (GND2) and a second supply voltage (VDD2);

[0038] - a fifth transistor (M5) connected between the first storage node (D) and the first bit line (BL1);

[0039] - a first word line (WL1) connected to the fifth transistor (M5), the first word line (WL1) controlling access of the first bit line (BL1) to the first storage node (D); and

[0040] Among them, the relative voltage level of the first word line (WL1) and the first reference voltage (GND1), or the relative voltage level of the first power supply voltage (VDD1) and the first reference voltage (GND1), or the relative voltage level of the second power supply voltage (VDD2) and the second reference voltage (GND2), or the relative voltage level of the first reference voltage (GND1) and the second reference voltage (GND2) is configured so that data of the first storage node (D) and the inverted first storage node (D') can be read and written independently.

[0041] The memory unit may also include:

[0042] - a sixth transistor (M6) connected between the inverted first storage node (D') and the second bit line (BL2); and

[0043] a second word line (WL2) independent of the first word line (WL1), the second word line being connected to the sixth transistor (M6), the second word line (WL2) controlling access of the second bit line (BL2) to the inverted first storage node (D') independently of the first bit line (BL1);

[0044] The relative voltage levels of the second word line (WL2) and the second reference voltage (GND2) may also be configured accordingly so that the data of the first storage node (D) and the inverted first storage node (D') can be read and written independently.

[0045] Boost circuit

[0046] The static random access memory of the present disclosure may include a voltage supply controller for providing voltages for power supply voltages, reference voltages, word lines, and bit lines of memory cells. The voltage supply controller may be configured to control a combination of voltages of a first word line (WL1), a second word line (WL2), a first reference voltage (GND1), a second reference voltage (GND2), a first power supply voltage (VDD1), a second power supply voltage (VDD2), a first bit line (BL1), and a second bit line (BL2) of a memory cell of the memory. The voltages may be raised and lowered independently to enable efficient reading and writing of the memory cells. Preferably, the voltage supply controller is dynamic in the sense that the voltage may be raised or lowered during an access cycle, such as Figure 4 shown.

[0047] To increase one or more voltages, the memory may include a boost circuit. The boost circuit may be a central unit or a sub-unit customized for any individual signal of a first word line (WL1), a second word line (WL2), a first reference voltage (GND1), a second reference voltage (GND2), a first power supply voltage (VDD1), a second power supply voltage (VDD2), a first bit line (BL1), and a second bit line (BL2) of a memory cell of the memory. Figure 5 An example can be seen in FIG, where there are two separate bit line boost cells and two word line boost cells (one for each port) for the BL1 and BL2 bit lines. In one embodiment, the boost cells are configured to provide voltage levels to the first bit line (BL1), the second bit line (BL2), the first word line (WL1), and the second word line (WL2).

[0048] The boost unit(s) may be implemented in a variety of ways. In one embodiment, the boost unit includes a plurality of charge pump circuits for providing separate voltages to a first reference voltage (GND1), a second reference voltage (GND2), a first power supply voltage (VDD1) and a second power supply voltage (VDD2), a first bit line (BL1), a second bit line (BL2), a first word line (WL1) and a second word line (WL2), or any combination of any other bit lines or word lines. At least one of the charge pump units may include four cross-coupled transistors and two capacitors for providing the boosted voltages. Figure 6 An example of a charge pump based boost cell is shown.

[0049] In one embodiment of the static random access memory of the present disclosure, the boost unit is configured to boost the first word line voltage during a write access to the first storage node (D). The boost unit may be configured to provide a first word line voltage of the first word line (WL1), which is at least doubled or boosted to a level of at least twice, preferably at least 2.5 times, and even more preferably at least 3 times the first power supply voltage (VDD1) during a write access to the first storage node (D). The boost unit may also be configured to provide a first bit line voltage of the first bit line (BL1), which is at least doubled or boosted to a level of at least twice, preferably at least 2.5 times, and even more preferably at least 3 times the first power supply voltage (VDD1) during a write access to the first storage node (D).

[0050] In one embodiment of the static random access memory of the present disclosure, the boost unit is configured to boost the second word line voltage during a write access to the inverted first storage node (D'). The boost unit may be configured to provide a second word line voltage of the second word line (WL2), which is at least doubled or boosted to a level of at least twice, preferably at least 2.5 times, and even more preferably at least 3 times the second power supply voltage (VDD2) during a write access to the inverted first storage node (D'). The boost unit may also be configured to provide a second bit line voltage of the second bit line (BL2), which is at least doubled or boosted to a level of at least twice, preferably at least 2.5 times, and even more preferably at least 3 times the second power supply voltage (VDD2) during a write access to the inverted first storage node (D').

[0051] The signal may also be boosted and / or bucked to improve read access. Therefore, in one embodiment of the static random access memory of the present disclosure, the boost unit is configured to provide a first bit line voltage of the first bit line (BL1) that is lowered during read access to the first storage node (D). The boost unit may also be configured to provide a second bit line voltage of the second bit line (BL2) that is lowered during read access to the inverted first storage node (D').

[0052] Since reading / writing to a memory cell of the memory may have to be completed within a single clock cycle, the boosting unit may be implemented to provide a boosted voltage, even a significantly boosted voltage, within a single cycle. Figure 7 An example of a boost circuit configured to provide 2VDD in a single clock cycle is shown. The boost circuit includes two charge pumps, each charge pump including four cross-coupled transistors and two capacitors. The four cross-coupled transistors in each charge pump include 2 NMOS transistors connected to the supply voltage VDD, and two PMOS transistors connected to the output of the NMOS transistors and the CP unit. Each charge pump unit is arranged to receive a clock signal IN and a 180 degree phase shifted version of the clock signal through two capacitors. As will be appreciated by those skilled in the art, variations of this architecture are contemplated.

[0053] Further increasing some of the boosted voltage levels may be another advantage. Therefore, the static random access memory of the present disclosure may include a boost unit that is capable of generating even higher voltages in a single clock cycle. An example of such a boost circuit is Figure 8 shown. Figure 8 The boost circuit of VDD uses X number of stages. Therefore, the output OUT of such a boost circuit is X times VDD.

[0054] Dynamic configuration of voltage levels

[0055] In the memory cell and the corresponding memory disclosed in the present invention, the relative voltage level of the first word line (WL1) and the first reference voltage (GND1), or the relative voltage level of the first power supply voltage (VDD1) and the first reference voltage (GND1), or the relative voltage level of the second word line (WL2) and the second reference voltage (GND2), or the relative voltage level of the second power supply voltage (VDD2) and the second reference voltage (GND2) can be dynamically processed by increasing or decreasing one or more separate reference levels, so that a value can only be written from one side. In the absence of a conventional method ( Figure 1 ) in the sense that there is a common WL as in ), but there are separate WL1 and WL2 signals associated with different ports of the memory, and the BL and The signal is not like the existing technology ( Figure 1 ) are not associated with each other, but the separate BL1 and BL2 signals are associated with different ports of the memory. Therefore, the static random access memory of the present disclosure can be a true dual-port 6T memory.

[0056] In one embodiment of the memory cell and static random access memory of the present disclosure, the first power supply voltage (VDD1) is lowered during a write access to the first storage node (D). The second power supply voltage (VDD2) may be lowered during a write access to the inverted first storage node (D').

[0057] Alternatively or in combination, the first reference voltage (GND1) may be raised during a write access to the first storage node (D). The second reference voltage (GND2) may be raised during a write access to the inverted first storage node (D').

[0058] In another embodiment of the memory cell and static random access memory disclosed herein, during a write access to a first storage node (D), a first power supply voltage (VDD1) is lowered and a first reference voltage (GND1) is raised. During a write access to an inverted first storage node (D'), a second power supply voltage (VDD2) is lowered and a second reference voltage (GND2) is raised.

[0059] The second power supply voltage (VDD2) may also be lowered during a write access to the first storage node (D). The first power supply voltage (VDD1) may be lowered during a write access to the inverted first storage node (D'). The second reference voltage (GND2) may be lowered during a write access to the first storage node (D). The first reference voltage (GND1) may be lowered during a write access to the inverted first storage node (D').

[0060] In one embodiment, two reference voltages (GND1 and GND2) are changed simultaneously. Preferably, one of the reference voltages is lowered and the other reference voltage is increased. In one embodiment, during a write access to the first storage node (D), the first reference voltage (GND1) is raised and the second reference voltage (GND2) is lowered. During a write access to the inverted first storage node (D'), the first reference voltage (GND1) may alternatively or in combination be lowered and the second reference voltage (GND2) be raised.

[0061] In such Figure 1 In the conventional 6T design shown, write operations, especially the operation of writing a logic “1”, are challenging. A “1” is usually written by writing a logic “1” between BL and CL when WL is asserted. In the memory cell and static random access memory of the present disclosure, write access may include the process of writing any value (logical "0" or "1") to the first storage node (D) or the inverted first storage node (D'). In particular, write access may include the process of writing a logical "1" to the first storage node (D) or the inverted first storage node (D') by applying the teachings described herein.

[0062] When reading a value from the first storage node (D) or the inverted first storage node (D'), the relative voltage level of, for example, the first word line (WL1) and the first reference voltage (GND1), or the relative voltage level of the first power supply voltage (VDD1) and the first reference voltage (GND1), or the relative voltage level of the second power supply voltage (VDD2) and the second reference voltage (GND2), or the relative voltage level of the first reference voltage (GND1) and the second reference voltage (GND2) may also be raised and / or lowered.

[0063] In one embodiment, during a word line controlled read access to a storage node, a word line voltage is lowered. A first word line voltage of a first word line (WL1) may be lowered during a read access to a first storage node (D). A second word line voltage of a second word line (WL2) may be lowered during a read access to an inverted first storage node (D').

[0064] In addition, the levels of the power supply voltage (VDD1, VDD2) and / or the reference voltage (GND1, GND2) can be increased or decreased to achieve independent control and access to the storage nodes. In one embodiment, the first power supply voltage (VDD1) is raised during a read access to the first storage node (D). In one embodiment, the first reference voltage (GND1) is lowered during a read access to the first storage node (D). A combination is also possible, i.e., during a read access to the first storage node (D), the first power supply voltage (VDD1) is raised and the first reference voltage (GND1) is lowered. The same applies to the inverted first storage node (D'). Therefore, in one embodiment, the second power supply voltage (VDD2) is raised during a read access to the inverted first storage node (D'). In one embodiment, the second reference voltage (GND2) is lowered during a read access to the inverted first storage node (D'). A combination is also possible, i.e., during a read access to the inverted first storage node (D'), the second power supply voltage (VDD2) is raised and the second reference voltage (GND2) is lowered.

[0065] The inventors have also discovered that it may be useful to adjust the levels of the supply voltage and the reference voltage on opposite sides of the cross-coupled inverters (i.e., adjusting the voltages VDD1 and / or GND1 during access to the inverted first storage node (D') and adjusting the voltages VDD2 and / or GND2 during access to the first storage node (D)). In one embodiment, the second supply voltage (VDD2) is raised during a read access to the first storage node (D). In one embodiment, the second reference voltage (GND2) is raised during a read access to the first storage node (D). In one embodiment, the first supply voltage (VDD1) is raised during a read access to the inverted first storage node (D'). In one embodiment, the first reference voltage (GND1) is raised during a read access to the inverted first storage node (D').

[0066] Multi-port SRAM

[0067] The present disclosure also relates to a multi-port static random access memory and a memory unit for the static random access memory. The static random access memory is not necessarily limited to a single-port 5T static random access memory and a 6T dual-port static random access memory. The memory unit of the present disclosure may therefore further include:

[0068] - a seventh transistor (M7) connected between the first storage node (D) and the third bit line (BL3);

[0069] - optionally, an eighth transistor (M8) connected between the inverted first storage node (D') and the fourth bit line (BL4);

[0070] - a third word line (WL3) connected to the seventh transistor (M7), said third word line (WL3) controlling access of a third bit line (BL3) to the first storage node (D), preferably independently of the first and second bit lines (BL1, BL2); and

[0071] -Optionally, a fourth word line (WL4) independent of the first, second and third word lines (WL1, WL2, WL3), connected to an eighth transistor (M8), said fourth word line (WL4) controlling access of the fourth bit line (BL4) to the inverted first storage node (D') independently of the first, second and third bit lines (BL1, BL2, BL3).

[0072] The memory cell and memory may thus be a 7T SRAM three-port memory cell / memory or an 8T SRAM four-port memory cell / memory.

[0073] Preferably, the relative voltage level of the third word line (WL3) and the first reference voltage (GND1), or the relative voltage level of the first power supply voltage (VDD1) and the first reference voltage (GND1), or the relative voltage level of the fourth word line (WL4) and the second reference voltage (GND2), or the relative voltage level of the second power supply voltage (VDD2) and the second reference voltage (GND2) are configured so that data of the first storage node (D) and the inverted first storage node (D') can be read from the third and / or fourth bit lines (BL3, BL4) and data of the first storage node (D) and the inverted first storage node (D') can be written to the third and / or fourth bit lines (BL3, BL4), respectively and independently.

[0074] This concept can be further extended to m+n port memory and memory unit. The memory unit / memory can therefore further include:

[0075] - m left access transistors connected between the first storage node (D) and m corresponding left access bit lines;

[0076] - n right access transistors connected between the inverted first storage node (D) and n corresponding right access bit lines;

[0077] - m left access word lines connected to the m left access transistors; and

[0078] - n right-side access word lines connected to the n right-side access transistors,

[0079] In which, data of the first storage node (D) and the inverted first storage node (D') can be read independently from m left access bit lines and n right access bit lines, and data of the first storage node (D) and the inverted first storage node (D') can be written to m left access bit lines and n right access bit lines.

[0080] The memory cell may thus be an SRAM memory cell having (4+m+n) ports (eg unidirectional ports or bidirectional ports), implemented with (8+m+n) transistors.

[0081] Detailed description of the drawings

[0082] The present invention will be described in more detail below with reference to the accompanying drawings. The accompanying drawings are exemplary and are intended to illustrate some features of the static random access memory and memory cell for the static random access memory of the present disclosure and should not be interpreted as limiting the present invention.

[0083] Figure 1 A prior art memory cell of a static random access memory is shown, wherein the WL and BL signals are interrelated. A common WL and BL are used. The values ​​are complementary and inverted.

[0084] Figure 2 An example of a memory cell for a static random access memory of the present disclosure is shown, in the form of a 6T dual-port memory cell. The memory cell has a first (PMOS) transistor (M1), a second (NMOS) transistor (M2), a third (PMOS) transistor (M3), and a fourth (NMOS) transistor (M4) forming first and second cross-coupled inverters (INV1, INV2). A fifth (NMOS) transistor (M5) is connected between a first storage node (D) and a first bit line (BL1). A sixth (NMOS) transistor (M6) is connected between an inverted first storage node (D') and a second bit line (BL2). A first word line (WL1) is connected to (the gate terminal of) the fifth transistor (M5) to control access of the first bit line (BL1) to the first storage node (D). A second word line (WL2) is connected to (the gate terminal of) the sixth transistor (M6) to control access of the second bit line (BL2) to the inverted first storage node (D'). BL1 and WL1 are independent of BL2 and WL2, which means that two different ports can be used to access D and D'. The voltages VDD1, VDD2, GND1, and GND2 can be controlled individually, and the relative voltage levels of BL1, WL1, VDD1, GND1, BL2, WL2, VDD2, and GND2 can be applied to allow independent write and read access to D and D'.

[0085] Figure 3An example of a memory cell for a static random access memory disclosed in the present invention is shown, in the form of an 8T four-port memory cell. The memory cell has a first transistor (M1), a second transistor (M2), a third transistor (M3) and a fourth transistor (M4) forming first and second cross-coupled inverters (INV1, INV2). A fifth transistor (M5) is connected between a first storage node (D) and a first bit line (BL1). A sixth transistor (M6) is connected between an inverted first storage node (D') and a second bit line (BL2). A seventh transistor (M7) is connected between a first storage node (D) and a third bit line (BL3). An eighth transistor (M8) is connected between an inverted first storage node (D') and a fourth bit line (BL4). A first word line (WL1) is connected to a fifth transistor (M5) to control access of a first bit line (BL1) to a first storage node (D). A second word line (WL2) is connected to a sixth transistor (M6) to control access of a second bit line (BL2) to an inverted first storage node (D'). The third word line (WL3) is connected to the seventh transistor (M7) to control the access of the third bit line (BL3) to the first storage node (D). The fourth word line (WL4) is connected to the eighth transistor (M8) to control the access of the fourth bit line (BL4) to the inverted first storage node (D'). All BL-WL pairs (BL1, WL1, BL2, WL2, BL3, WL3, BL4, WL4) are independent of each other, which means that four different ports can be used to access D and D'. The voltages VDD1, VDD2, GND1 and GND2 can be controlled individually, and the relative voltage levels of BL1, WL1, BL3, WL3, VDD1, GND1, BL2, WL2, BL4, WL4, VDD2 and GND2 can be applied to allow independent write and read access to D and D'.

[0086] Figure 4 Examples of voltage levels that are raised (increased) during read or write access and voltage levels that are lowered during read or write access are shown. Vref may refer to any individual voltage level and is intended to illustrate the concept of raising or lowering voltage levels during read / write access.

[0087] Figure 5An example of a static random access memory including a memory cell array of the present disclosure is shown, wherein the bit lines and word lines of the memory cells are independent of each other. The first port of the dual-port memory can, for example, read or write a memory cell in the left column by accessing BL11, and the second port can read or write another memory cell in the left column by accessing BL12. In the example, BL1 and BL2 have separate precharge and boost units. Similarly, the first port WL can have a WL boost unit, and the second port WL can have another WL boost unit. In this example, the memory includes a sense amplifier on the bit line.

[0088] Figure 6 An example of a boost unit is shown in the form of two parallel capacitors C 1 and C 2 and four switches arranged to provide a boosted output voltage.Other implementations of the boost unit are contemplated.

[0089] Figure 7 An example of a boost unit is shown, which is configured to provide 2*VDD in a single cycle. The boost unit includes a first and a second charge pump unit. Each charge pump unit includes four cross-coupled transistors and two capacitors. The four cross-coupled transistors include 2 NMOS transistors connected to the power supply voltage VDD, and two PMOS transistors connected to the NMOS transistors and the output of the charge pump unit. Each charge pump unit is arranged to receive a clock signal IN and a 180-degree phase-shifted version of the clock signal through two capacitors. The charge pump units are connected in parallel, which means that the input of the second charge pump is connected to the output of the first charge pump through an inverter controlled by the clock signal. Figure 8 An example of a boost cell is shown, which is configured to provide X*VDD in a single cycle using Figure 7 Expansion of ideas.

[0090] Further details of the invention

[0091] 1. A memory cell for a static random access memory, the memory cell comprising:

[0092] - a first transistor (M1), a second transistor (M2), a third transistor (M3) and a fourth transistor (M4) forming first and second cross-coupled inverters (INV1, INV2), wherein the first and second cross-coupled inverters (INV1, INV2) define a first storage node (D) and an inverted first storage node (D'), wherein the first inverter (INV1) is connected to a first reference voltage (GND1) and a first supply voltage (VDD1), and wherein the second inverter (INV2) is connected to a second reference voltage (GND2) and a second supply voltage (VDD2);

[0093] - a fifth transistor (M5) connected between the first storage node (D) and the first bit line (BL1);

[0094] - a sixth transistor (M6) connected between the inverted first storage node (D') and the second bit line (BL2);

[0095] - a first word line (WL1) connected to the fifth transistor (M5), the first word line (WL1) controlling access of the first bit line (BL1) to the first storage node (D); and

[0096] a second word line (WL2) independent of the first word line (WL1), the second word line being connected to the sixth transistor (M6), the second word line (WL2) controlling access of the second bit line (BL2) to the inverted first storage node (D') independently of the first bit line (BL1);

[0097] Among them, the relative voltage level of the first word line (WL1) and the first reference voltage (GND1), or the relative voltage level of the first power supply voltage (VDD1) and the first reference voltage (GND1), or the relative voltage level of the second word line (WL2) and the second reference voltage (GND2), or the relative voltage level of the second power supply voltage (VDD2) and the second reference voltage (GND2), or the relative voltage level of the first reference voltage (GND1) and the second reference voltage (GND2), or the relative voltage level of the first bit line (BL1) and the first reference voltage (GND1) or the first power supply voltage (VDD1), or the relative voltage level of the second bit line (BL2) and the second reference voltage (GND2) or the second power supply voltage (VDD2) are configured so that data of the first storage node (D) and the inverted first storage node (D') can be read and written independently.

[0098] 2. A memory cell according to any of the preceding items, wherein the first word line voltage of the first word line (WL1) is at least doubled or boosted to a level of at least twice, preferably at least 2.5 times, and even more preferably at least 3 times, the first power supply voltage (VDD1) during a write access to the first storage node (D).

[0099] 3. A memory cell according to item 2, wherein the first line voltage of the first line (BL1) is at least doubled or boosted to a level of at least twice, preferably at least 2.5 times, and even more preferably at least 3 times the first power supply voltage (VDD1) during a write access to the first storage node (D).

[0100] 4. A memory cell according to any of the preceding items, wherein the second word line voltage of the second word line (WL2) is at least doubled or boosted to a level of at least twice, preferably at least 2.5 times, and even more preferably at least 3 times the second power supply voltage (VDD2) during a write access to the inverted first storage node (D').

[0101] 5. A memory cell according to item 4, wherein the second bit line voltage of the second bit line (BL2) is at least doubled or boosted to a level of at least twice, preferably at least 2.5 times, and even more preferably at least 3 times the second power supply voltage (VDD2) during a write access to the inverted first storage node (D').

[0102] 6. The memory cell according to any of the preceding items, wherein the first supply voltage (VDD1) is lowered during a write access to the first storage node (D).

[0103] 7. The memory cell according to any of the preceding items, wherein the second supply voltage (VDD2) is lowered during a write access to the inverted first storage node (D').

[0104] 8. The memory cell according to any of the preceding items, wherein the first reference voltage (GND1) is boosted during a write access to the first storage node (D).

[0105] 9. The memory cell according to any of the preceding items, wherein the second reference voltage (GND2) is boosted during a write access to the inverted first storage node (D').

[0106] 10. The memory cell according to any of the preceding items, wherein during a write access of the first storage node (D), the first supply voltage (VDD1) is lowered and the first reference voltage (GND1) is boosted.

[0107] 11. The memory cell according to any of the preceding items, wherein during a write access to the inverted first storage node (D') the second supply voltage (VDD2) is lowered and the second reference voltage (GND2) is boosted.

[0108] 12. The memory cell according to any of the preceding items, wherein the second supply voltage (VDD2) is reduced during a write access to the first storage node (D).

[0109] 13. The memory cell according to any of the preceding items, wherein the first supply voltage (VDD1) is lowered during a write access to the inverted first storage node (D').

[0110] 14. The memory cell according to any of the preceding items, wherein the second reference voltage (GND2) is lowered during a write access to the first storage node (D).

[0111] 15. The memory cell according to any of the preceding items, wherein the first reference voltage (GND1) is lowered during a write access to the inverted first storage node (D').

[0112] 16. The memory cell according to any of the preceding items, wherein the first reference voltage (GND1) is boosted and the second reference voltage (GND2) is lowered during a write access to the first storage node (D).

[0113] 17. The memory cell according to any of the preceding items, wherein during a write access to the inverted first storage node (D') the first reference voltage (GND1) is lowered and the second reference voltage (GND2) is boosted.

[0114] 18. The memory cell according to any of the preceding items, wherein a write access is a process of writing a logic "1" to the first storage node (D) or the inverted first storage node (D').

[0115] 19. A memory cell according to any of the preceding items, wherein the first power supply voltage (VDD1), the second power supply voltage (VDD2), the first bit line (BL1), the first word line (WL1), the second bit line (BL2) and the second word line (WL2) are separate voltages.

[0116] 20. The memory cell according to item 19, wherein the first reference voltage (GND1) and the second reference voltage (GND2) are separate voltages.

[0117] 21. The memory cell according to any of the preceding items, wherein a first word line voltage of the first word line (WL1) is lowered during a read access to the first storage node (D).

[0118] 22. The memory cell according to any of the preceding items, wherein a second word line voltage of the second word line (WL2) is lowered during a read access to the inverted first storage node (D').

[0119] 23. The memory cell according to any of the preceding items, wherein the first supply voltage (VDD1) is boosted during a read access to the first storage node (D).

[0120] 24. The memory cell according to any of the preceding items, wherein the second supply voltage (VDD2) is boosted during a read access to the inverted first storage node (D').

[0121] 25. The memory cell according to any of the preceding items, wherein the first reference voltage (GND1) is lowered during a read access to the first storage node (D).

[0122] 26. The memory cell according to any of the preceding items, wherein the second reference voltage (GND2) is lowered during a read access to the inverted first storage node (D').

[0123] 27. The memory cell according to any of the preceding items, wherein during a read access to the first storage node (D) the first supply voltage (VDD1) is boosted and the first reference voltage (GND1) is lowered.

[0124] 28. The memory cell according to any of the preceding items, wherein during a read access to the inverted first storage node (D') the second supply voltage (VDD2) is boosted and the second reference voltage (GND2) is lowered.

[0125] 29. The memory cell according to any of the preceding items, wherein the second supply voltage (VDD2) is boosted during a read access to the first storage node (D).

[0126] 30. The memory cell according to any of the preceding items, wherein the first supply voltage (VDD1) is boosted during a read access to the inverted first storage node (D').

[0127] 31. The memory cell according to any of the preceding items, wherein the second reference voltage (GND2) is boosted during a read access to the first storage node (D).

[0128] 32. The memory cell according to any of the preceding items, wherein the first reference voltage (GND1) is boosted during a read access to the inverted first storage node (D').

[0129] 33. The memory cell according to any of the preceding items, wherein a first bit line voltage of the first bit line (BL1) is lowered during a read access to the first storage node (D).

[0130] 34. The memory cell according to any of the preceding items, wherein a second bit line voltage of the second bit line (BL2) is lowered during a read access to the inverted first storage node (D').

[0131] 35. A memory cell according to any of the preceding items, wherein the first bit line (BL1) and the first word line (WL1) constitute a first bidirectional port or a first unidirectional port, and wherein the second bit line (BL2) and the second word line (WL2) constitute a second bidirectional port or a second unidirectional port.

[0132] 36. The memory cell according to any of the preceding items, wherein the memory cell is a 6TSRAM dual-port memory cell.

[0133] 37. The memory cell according to item 36, wherein the 6T SRAM dual-port memory cell is a 6T SRAM single-cycle dual-port memory cell.

[0134] 38. The memory unit according to any one of items 1 to 35, further comprising:

[0135] - a seventh transistor (M7) connected between the first storage node (D) and the third bit line (BL3);

[0136] - an eighth transistor (M8) connected between the inverted first storage node (D') and the fourth bit line (BL4);

[0137] - a third word line (WL3) connected to the seventh transistor (M7), the third word line (WL3) controlling access of the third bit line (BL3) to the first storage node (D); and

[0138] - A fourth word line (WL4) which is independent of the first, second and third word lines (WL1, WL2, WL3), the fourth word line being connected to an eighth transistor (M8), the fourth word line (WL4) being independent of the first, second and third bit lines (BL1, BL2, BL3) for controlling access of the fourth bit line (BL4) to the inverted first storage node (D').

[0139] 39. A memory cell according to item 38, wherein the relative voltage level of the third word line (WL3) and the first reference voltage (GND1), or the relative voltage level of the first power supply voltage (VDD1) and the first reference voltage (GND1), or the relative voltage level of the fourth word line (WL4) and the second reference voltage (GND2), or the relative voltage level of the second power supply voltage (VDD2) and the second reference voltage (GND2) are configured so that data of the first storage node (D) and the inverted first storage node (D') are read from / written to the third and fourth bit lines (BL3, BL4) respectively and independently.

[0140] 40. The memory cell of any one of items 38-39, wherein the memory cell is an 8T SRAM quad-port memory cell.

[0141] 41. The memory unit according to any one of items 38-39, further comprising:

[0142] - m left access transistors connected between the first storage node (D) and m corresponding left access bit lines;

[0143] - n right access transistors connected between the inverted first storage node (D) and n corresponding right access bit lines;

[0144] - m left access word lines connected to the m left access transistors; and

[0145] - n right-side access word lines connected to the n right-side access transistors,

[0146] In which, data of the first storage node (D) and the inverted first storage node (D') can be read independently from m left access bit lines and n right access bit lines / data of the first storage node (D) and the inverted first storage node (D') can be written to m left access bit lines and n right access bit lines.

[0147] 42. The memory cell of item 41, wherein the memory cell is an SRAM memory cell having (4+m+n) ports (eg, unidirectional ports or bidirectional ports) and implemented with (8+m+n) transistors.

[0148] 43. A memory array comprising a plurality of memory cells according to any one of items 1-42.

[0149] 44. A static random access memory comprising:

[0150] - a plurality of memory cells according to any one of items 1 to 42;

[0151] - row decoder;

[0152] - column decoder;

[0153] - sense amplifier;

[0154] - A voltage supply controller for providing voltages for a power supply voltage, a reference voltage, a word line and a bit line of a memory cell.

[0155] 45. The static random access memory according to item 44, further comprising:

[0156] - a voltage boost unit for providing voltage levels for a first reference voltage (GND1), a second reference voltage (GND2), a first power supply voltage (VDD1) and a second power supply voltage (VDD2).

[0157] 46. ​​The static random access memory according to item 45, wherein the boost unit is configured to provide voltage levels to the first bit line (BL1), the second bit line (BL2), the first word line (WL1) and the second word line (WL2).

[0158] 47. A static random access memory according to any one of items 45-46, wherein the boost unit includes multiple charge pump circuits for providing separate voltages for a first reference voltage (GND1), a second reference voltage (GND2), a first power supply voltage (VDD1) and a second power supply voltage (VDD2), a first bit line (BL1), a second bit line (BL2), a first word line (WL1) and a second word line (WL2), or any other combination of bit lines or word lines.

[0159] 48. A static random access memory according to any one of items 45 to 47, wherein the static random access memory is a single-port 5T static random access memory, or a dual-port 6T static random access memory, or a triple-port 7T static random access memory, or a quad-port 8T static random access memory, or a penta-port 9T static random access memory, or a six-port 10T static random access memory.

Claims

1. A memory cell for a static random access memory, the memory cell comprising: - a first transistor (M1), a second transistor (M2), a third transistor (M3) and a fourth transistor (M4) forming a first cross-coupled inverter and a second cross-coupled inverter (INV1, INV2), wherein the first cross-coupled inverter (INV1) and the second cross-coupled inverter (INV2) define a first storage node (D) and an inverted first storage node (D'), wherein the first cross-coupled inverter (INV1) is connected to a first reference voltage (GND1) and a first supply voltage (VDD1), and wherein the second cross-coupled inverter (INV2) is connected to a second reference voltage (GND2) and a second supply voltage (VDD2); - a fifth transistor (M5) connected between the first storage node (D) and the first bit line (BL1); - a sixth transistor (M6) connected between the inverted first storage node (D') and the second bit line (BL2); - a first word line (WL1) connected to the fifth transistor (M5), the first word line (WL1) controlling access of the first bit line (BL1) to the first storage node (D); and - a second word line (WL2) independent of the first word line (WL1), the second word line being connected to a sixth transistor (M6), the second word line (WL2) controlling access of the second bit line (BL2) to the inverted first storage node (D') independently of the first bit line (BL1); wherein the relative voltage level between the first word line (WL1) and the first reference voltage (GND1), or the relative voltage level between the first power supply voltage (VDD1) and the first reference voltage (GND1), or the relative voltage level between the second word line (WL2) and the second reference voltage (GND2), or the relative voltage level between the second power supply voltage (VDD2) and the second reference voltage (GND2), or the relative voltage level between the first reference voltage (GND1) and the second reference voltage (GND2), or the relative voltage level between the first bit line (BL1) and the first reference voltage (GND1) or the first power supply voltage (VDD1), or the relative voltage level between the second bit line (BL2) and the second reference voltage (GND2) or the second power supply voltage (VDD2) are configured so that data of the first storage node (D) and the inverted first storage node (D') can be read and written independently, wherein a first word line voltage of a first word line (WL1) is boosted, and wherein a first bit line voltage of a first bit line (BL1) is boosted during a write access to a first storage node (D), and wherein a second word line voltage of the second word line (WL2) is boosted, and wherein, during a write access to the inverted first storage node (D'), a second bit line voltage of the second bit line (BL2) is boosted, The write access is a process of writing a logic "1" into the first storage node (D) or the inverted first storage node (D'). wherein the second power supply voltage (VDD2) is reduced during a write access to the first storage node (D), and / or wherein the first power supply voltage (VDD1) is reduced during a write access to the inverted first storage node (D'), and / or wherein a first word line voltage of a first word line (WL1) is lowered during a read access to a first storage node (D), and / or wherein a second word line voltage of a second word line (WL2) is lowered during a read access to an inverted first storage node (D'), and / or wherein the first supply voltage (VDD1) is boosted during a read access to the first storage node (D), and / or wherein the second supply voltage (VDD2) is boosted during a read access to the inverted first storage node (D').

2. The memory cell according to claim 1, wherein: A first word line voltage of a first word line (WL1) is boosted to a level at least twice that of a first power supply voltage (VDD1), and wherein, during a write access to a first storage node (D), a first word line voltage of a first bit line (BL1) is boosted to a level at least twice that of the first power supply voltage (VDD1).

3. The memory cell according to claim 1, wherein: A second word line voltage of the second word line (WL2) is boosted to a level at least twice the first power supply voltage (VDD1), and wherein, during a write access to the inverted first storage node (D'), a second bit line voltage of the second bit line (BL2) is boosted to a level at least twice the second power supply voltage (VDD2).

4. A memory cell according to any one of the preceding claims, wherein: A first word line voltage of a first word line (WL1) is at least doubled or boosted to a level of at least twice the first power supply voltage (VDD1) during a write access to a first storage node (D), and / or, wherein a second word line voltage of a second word line (WL2) is at least doubled or boosted to a level of at least twice the second power supply voltage (VDD2) during a write access to an inverted first storage node (D').

5. A memory cell according to any one of the preceding claims, wherein: A first bit line voltage of a first bit line (BL1) is at least doubled or boosted to a level of at least twice the first power supply voltage (VDD1) during a write access to a first storage node (D), and / or, wherein a second bit line voltage of a second bit line (BL2) is at least doubled or boosted to a level of at least twice the second power supply voltage (VDD2) during a write access to an inverted first storage node (D').

6. A memory cell according to any one of the preceding claims, wherein: The first supply voltage (VDD1) is lowered during a write access to the first storage node (D), and / or wherein the second supply voltage (VDD2) is lowered during a write access to the inverted first storage node (D').

7. A memory cell according to any one of the preceding claims, wherein: The first reference voltage (GND1) is boosted during a write access to the first storage node (D), and / or wherein the second reference voltage (GND2) is boosted during a write access to the inverted first storage node (D').

8. A memory cell according to any one of the preceding claims, wherein: The first supply voltage (VDD1) is lowered and the first reference voltage (GND1) is boosted during a write access to the first storage node (D), and / or, wherein the second supply voltage (VDD2) is lowered and the second reference voltage (GND2) is boosted during a write access to the inverted first storage node (D').

9. A memory cell according to any one of the preceding claims, wherein: The first bit line (BL1) and the first word line (WL1) constitute a first bidirectional port or a first unidirectional port, and the second bit line (BL2) and the second word line (WL2) constitute a second bidirectional port or a second unidirectional port.

10. A memory cell according to any one of the preceding claims, wherein: The memory cell is a 6T SRAM dual-port memory cell.

11. The memory cell according to claim 10, wherein: The 6T SRAM dual-port memory cell is a 6T SRAM single-cycle dual-port memory cell.

12. A static random access memory, comprising: - a plurality of memory cells according to any one of claims 1 to 11; - row decoder; - column decoder; - sense amplifier; - A voltage supply controller for providing voltages for a power supply voltage, a reference voltage, a word line and a bit line of a memory cell.

13. The static random access memory according to claim 12, further comprising: - a boost unit for providing voltage levels to a first reference voltage (GND1), a second reference voltage (GND2), a first power supply voltage (VDD1) and a second power supply voltage (VDD2).

14. The static random access memory according to claim 13, wherein: The boosting unit is configured to provide voltage levels to a first bit line (BL1), a second bit line (BL2), a first word line (WL1), and a second word line (WL2).

15. The static random access memory according to any one of claims 13 to 14, wherein: The boost unit includes a plurality of charge pump circuits for providing separate voltages to a first reference voltage (GND1), a second reference voltage (GND2), a first power supply voltage (VDD1) and a second power supply voltage (VDD2), a first bit line (BL1), a second bit line (BL2), a first word line (WL1) and a second word line (WL2), or any other combination of bit lines or word lines.

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