Circuit arrangement and method for operating the secondary side of a dc-ac converter

Abstract

The invention relates to a circuit arrangement (10) for controlling the through current of the secondary side (20) of a DC / AC converter, having a controllable switching element (1) with a first connection (la), a second connection (lc) and a control connection (lb), a snubber circuit coupled to the source connection (la) and the second connection (lc), and a regulating circuit (5) which is set up to control the turn-off time of the controllable switching element (1) via the control connection (lb), wherein the regulating circuit (5) is electrically coupled to the snubber circuit and is set up to control the turn-off time as a function of the coupled electrical variable.

Description

Technical Field

[0001] The present invention relates to a circuit device for controlling the current flowing through the secondary side of a DC converter. Background Technology

[0002] To improve efficiency, so-called synchronous rectifiers (SGRs) are often used in higher-power DC converters. Here, for example, a controllable switching element, such as a MOSFET transistor, replaces the rectifier diode at the output of the converter. As long as current flows through the intrinsic diode of the MOSFET transistor, the channel of the MOSFET transistor is actively regulated to a conducting state, that is, turned on, so that it conducts electricity. Here, the lower on-state voltage of the conducting channel compared to the intrinsic diode of the MOSFET transistor significantly reduces losses, especially for DC converters with low output voltage and high output current.

[0003] To minimize further losses, ideally, the MOSFET transistor should be turned off precisely at the moment the current crosses zero, especially when the direction of current flow through the switching element reverses. This minimizes conduction losses and significantly reduces the reverse recovery losses of the intrinsic diode. Ideally, only the parasitic capacitance of the switching element is charged during turn-off, and the energy stored in the capacitor is recovered during the subsequent turn-on process. Therefore, the operation of the switching element can be achieved with almost no switching losses.

[0004] Many control circuits are known from the literature in order to control the cut-off time of, for example, MOSFET transistors as optimally as possible.

[0005] One possible approach is to use measurements of the current flowing through the switch to detect zero crossings. However, this method has proven to be costly and, especially for steep current edges, unsuitable for future high-frequency applications due to delays in measurement and signal processing.

[0006] Another approach uses precise measurement of the MOSFET transistor's turn-on voltage. However, for steep edges, the measured voltage is dominated by the voltage drop across the inductor, requiring precise compensation for the inductor, which is nearly impossible at different operating points of the DC converter. Furthermore, this method is difficult due to the consistently lower impedance of MOSFET transistors, for example, less than 1 mOhm. Therefore, accuracy in the mV range may be required for correctly setting the turn-off time, where the voltage drop across the parasitic inductance of the component can reach several volts for steep current edges. In addition, the latency of signal processing and gate control represents another obstacle to using this method.

[0007] A DC converter is described in DE 10 2012 202 869 A1, comprising: a transformer having a primary winding and a secondary winding with an intermediate tap; a storage reactor coupled between the intermediate tap and a first output terminal of the DC converter; a rectifier circuit; a buffer circuit; and a control device. The rectifier circuit is connected to the taps on the end sides of the secondary winding and is designed to generate a rectified output voltage at a second output terminal of the DC converter. The buffer circuit, connected to the rectifier circuit, is designed to store the vibrational energy of resonance occurring in the rectifier circuit. The control device has a switching time determination mechanism and a control signal generator, wherein the switching time determination mechanism is designed to determine the time interval based on the output voltage, the charge stored in the buffer circuit, and the current fluctuations due to rectification of the current flowing through the storage reactor. The control signal generator is designed to generate control signals for discharging the buffer circuit based on the determined time interval.

[0008] The objective of this invention is to describe a circuit arrangement that adaptively adjusts, or identifies, the turn-off timing of controllable switching elements on the secondary side of a DC-DC converter to obtain an optimized turn-off timing, thereby generating minimal turn-off losses at each operating point of the synchronous rectifier circuit. Preferably, the circuit arrangement is adapted as much as possible to existing circuit topologies. Summary of the Invention

[0009] According to the present invention, a circuit arrangement for controlling the current flowing through the secondary side of a DC converter, a method for manipulating the secondary side of a DC converter, a computer program product, and a computer-readable storage medium, as characterized in the independent claims, are described. Advantageous embodiments are the subject of the dependent claims and the following description.

[0010] This invention is based on the understanding that if the turn-off or switching of a controllable switching element does not occur at the optimal moment within the switching cycle, the storage element of the buffer circuit must absorb a large charge. The buffer circuit is used to provide overvoltage protection for the controllable switching element in the secondary circuit of the DC converter. The turn-off of the controllable switching element is typically performed at a time interval relative to the turn-off process of another switching element on the primary side of the DC converter. However, the optimal moment varies depending on the operating point of the DC converter, so it is desirable that the turn-off moment always matches the corresponding operating point of the DC converter. The buffer circuit is also referred to as a reset element, buffer circuit, or unloading network.

[0011] The circuit arrangement according to the invention is used to control the current flowing through the secondary side of a DC converter, particularly a synchronous rectifier. The circuit arrangement includes a controllable switching element for switching the current flowing through the secondary side of the DC converter, a buffer circuit, and a regulating circuit. The switching element has a first terminal, a second terminal, and a control terminal. The buffer circuit is electrically coupled to the first and second terminals. The regulating circuit is configured to periodically turn off the controllable switching element at a predetermined time by means of the control terminal, wherein this time has a predetermined interval relative to the periodic primary-side turn-off process, particularly relative to the turn-off process of another switching element on the primary side of the DC converter. The regulating circuit is also configured to determine the optimized turn-off time of the controllable switching element in the next cycle or switching cycle. The optimized turn-off time is advanced or delayed relative to the predetermined time. Furthermore, the regulating circuit is configured to correspondingly turn off the controllable switching element at the optimized turn-off time by means of the control terminal in the next cycle. The regulating circuit is electrically coupled to the buffer circuit and is configured to determine the optimized turn-off time based on the electrical parameters of the buffer circuit.

[0012] For current-isolated DC-DC converters, current flows from the secondary windings to the output or output terminal of the DC-DC converter during the transmission cycle phase—when power is supplied to the secondary windings of the transformer—by means of the switching on of controllable switching elements on the secondary side. During the transmission cycle phase—when no power is supplied to the secondary windings of the transformer—current flows from the secondary windings to the output or output terminal of the DC-DC converter are interrupted and prevented by the switching off of controllable switching elements on the secondary side. This switching corresponds to the switching of the current flowing through the secondary side of the DC-DC converter. This switching occurs periodically due to the alternating phases of energy transmission. Similarly, on the primary side of the DC-DC converter, there are switching elements that periodically switch the current or energy flow supplied to the primary side of the transformer. The secondary-side switching elements are typically turned off at predetermined intervals relative to a given moment, depending on the primary-side turning-off process. Based on the operating point of the DC converter (especially the current, input voltage, output load, and temperature), a current flows on the secondary side between the secondary winding and the output of the DC converter at this moment. This current causes losses when the controllable switching elements on the secondary side are turned off. To reduce losses, the turn-off time is advanced or delayed to a minimum so that the secondary side current is at least partially reduced during the optimized turn-off time. A buffer circuit protects the secondary side switching elements from overvoltage. The storage elements of the buffer circuit, especially capacitors, are charged according to the losses during turn-off. Therefore, it is possible to determine the turn-off losses by detecting the electrical parameters of the buffer circuit and to determine the optimized turn-off time for the subsequent turn-off cycle based on the determined losses.

[0013] As controllable switching elements, switching elements with parasitic capacitance, such as single-pole structural elements used to control the through current, are used to achieve the advantage of lower turn-on voltage. Examples of such controllable switching elements include HEMT (high-electron-mobility transistor), jFET (junction-fet or non-insulated-gate-fet, NIGFET) (barrier-layer field-effect transistor), power MOSFET, IGBT (insulated-gate bipolar transistor), or thyristor. Furthermore, cascaded, i.e., series circuits of normally open structural elements and low-voltage semiconductors, can be used to control the through current.

[0014] According to one design of the invention, it is proposed that the regulating circuit detects the voltage on the storage element by means of a voltage tap on the storage element of the buffer circuit, particularly on the capacitor.

[0015] To determine the optimal turn-off time based on electrical parameters, the voltage across the storage element in the buffer circuit is detected. The voltage across the storage element is a measure of commutation charge and thus reverse recovery losses during the operation of the synchronous rectifier circuit. Therefore, the magnitude of the losses can be determined using this circuit. These losses can then be minimized using additional measures.

[0016] According to the improved invention, it is proposed that the regulating circuit be configured to: perform a first detection on the first voltage on the storage element of the buffer circuit after the first shutdown of the controllable switching element;

[0017] The shutdown time is selected to follow the second shutdown, which is earlier or later than the first shutdown time relative to a predetermined interval of the shutdown process with the primary side.

[0018] After the selected shutdown time, the second voltage on the storage element of the buffer circuit is detected a second time after the controllable switching element is shut down for the second time.

[0019] Determine the difference between the first voltage and the second voltage;

[0020] Furthermore, based on the identified positive or negative difference, the optimal shutdown time for the immediately following cycle is determined, wherein the optimized shutdown time is earlier or later than the last identified shutdown time.

[0021] The detection of the first voltage is performed after the first shutdown. This means that the controllable switching element is first in the on, i.e., conducting state, and then, after being shut down, in a state that is especially fully off. During the transition time from the on state to the off state, the voltage on the storage element rises: the voltage is detected only after this transition time, typically, especially in the intermediate time between shutdown and on, the voltage is detected.

[0022] Subsequently, an earlier or later turn-off time is selected relative to the previous turn-off time. The turn-off time is changed with typical durations, such as 2 and 100 ns. Similar to the first detection, a second voltage detection is performed after the second turn-off of the switching element. If the second detected voltage is lower, the loss is at least partially minimized compared to the previous turn-off. The difference between the first and second voltages is positive. To optimize the subsequent turn-off time, the direction of earlier or later is maintained. If the detected voltage is higher, the loss will be higher. A negative voltage difference is produced. To optimize the subsequent turn-off time, the direction of earlier or later is reversed. Correspondingly, the optimized turn-off time is determined based on the difference in the detected voltages. The earlier or later turn-off time is performed here relative to the previous turn-off time, which also depends on the timing of the turn-off process on the primary side and the pre-given interval relative to the turn-off process on the primary side. The corresponding earlier or later turn-off time is repeated. If the voltage rises again after reaching the minimum value, it is preferable to operate the circuit with minimal losses by reversing the change at the turn-off time.

[0023] The described circuit arrangement utilizes existing buffer hardware for voltage limiting on controllable switching elements to set the optimal turn-off time of the controllable switching elements. The hardware changes required to determine and evaluate the voltage on the buffer storage element are minor. Advantageously, no special requirements are placed on the detection dynamics of voltage determination, as the system dynamics are determined by the relatively long time constant of the buffer circuit. Operating time effects such as latency, temperature dependence, and aging are compensated for by this circuit arrangement.

[0024] It is particularly recommended that the regulating circuit be configured to change the voltage drop across the storage element of the buffer circuit during the repeated turn-off time, which causes a decrease in voltage in the previous cycle, so as to deliver the minimum value to the voltage across the storage element of the buffer circuit.

[0025] The regulating circuit is configured such that the cut-off time of the controllable switching element in a given cycle varies slightly relative to the previous cut-off time. The decision to advance or delay the cut-off time in the next cycle is determined based on the detection of the voltage across the storage element in the buffer circuit, and particularly based on the difference between the last two detected voltages, so that the detected voltage becomes minimal at each stable operating point of the DC converter after several cycles. This establishes the optimal operation of the DC converter.

[0026] In another design embodiment of the invention, it is suggested that the regulating circuit incorporates a microcontroller circuit. This facilitates the implementation of an algorithm optimized based on the current design of the DC converter and the operating point of the DC converter.

[0027] Accordingly, according to another design of the present invention, it is suggested that the first terminal of the controllable switching element is connected to the positive potential terminal of the secondary winding of the transformer of the DC converter, and the buffer circuit is electrically connected to the first terminal of the controllable switching element, the second terminal of the controllable switching element, and the negative potential terminal of the secondary winding of the transformer.

[0028] According to another design of the invention, it is suggested that the buffer circuit has a capacitor as a storage element.

[0029] According to another design of the invention, a buffer circuit is proposed to have a series circuit consisting of a diode and a capacitor as a storage element, the series circuit being connected in parallel with a first terminal and a second terminal of a controllable switching element, and the buffer circuit having a discharge resistor connected to an intermediate tap between the diode and the capacitor and a negative potential terminal of the secondary winding of the transformer.

[0030] In this embodiment, the buffer circuit has the three structural elements described in the illustrated wiring and the capacitor serves as a storage element. However, it is known that a buffer circuit with three structural elements can be implemented on the secondary side of a DC-DC converter, which has an equivalent alternative topology, without altering the functionality or originality of the circuit arrangement.

[0031] Because such buffer circuits are often already incorporated into synchronous rectifier circuits, it is only necessary to connect the two input contacts of the regulating circuit to the first and second contacts of the capacitor and to establish voltage measurement or detection for the regulating circuit. Other necessary adjustments involve the implementation of the described algorithm. For such approximation to the minimum, a number of other algorithms are known, which can also be selected for further optimization if necessary, to rapidly approach the minimum voltage across the storage capacitor.

[0032] Furthermore, the present invention relates to a method for controlling the secondary side of a DC converter, particularly a synchronous rectifier. The secondary side of the DC converter has a controllable switching element and a buffer circuit, wherein the switching element has a first connector, a second connector, and a control connector, and the buffer circuit is electrically coupled to the first connector and the second connector.

[0033] The method involves periodically turning off a controllable switching element at a predetermined interval relative to the turn-off process on the primary side; determining an optimized turn-off time for the next switching cycle based on electrical parameters of a buffer circuit, particularly based on the detection of voltage on a storage element in the buffer circuit, for manipulating the controllable switching element.

[0034] The described method utilizes buffer hardware for voltage limiting on the MOSFET in order to iteratively set the optimal turn-off time of the MOSFET transistor based on the voltage determined on the storage element.

[0035] In one design of the method, the method determines the optimized turn-off time for manipulating the controllable switching element by performing a first detection (Sl) on the storage element of the buffer circuit after the first turn-off of the controllable switching element.

[0036] To select an optimized shutdown time (S4, S5) that is earlier or later than the first shutdown time relative to a pre-given interval in the shutdown process with the primary side for the second shutdown that follows immediately afterward.

[0037] After the second shutdown of the controllable switching element, a second detection is performed on the second voltage on the storage element of the buffer circuit.

[0038] Determine the difference between the first voltage and the second voltage.

[0039] Furthermore, based on the positive or negative difference identified, the optimized shutdown time is identified by advancing or delaying the shutdown time relative to the last identified shutdown time.

[0040] The considerations and advantages suitable for circuit devices also apply to methods for controlling synchronous rectifiers. In particular, this method can control circuit devices having the same structural features as different embodiments of the circuit devices according to the invention described above.

[0041] Furthermore, a computer program product is described, which includes instructions that, when executed by a computer, cause the computer to perform the methods explained above.

[0042] Furthermore, a computer-readable storage medium is described, comprising instructions that, when executed by a computer, cause the computer to perform the methods described above.

[0043] A drive system is provided, comprising a first DC power supply having a first voltage and a second DC power supply having a second voltage, wherein the first voltage is higher than the second voltage. Furthermore, the drive system includes a drive unit and an inverter that electrically couples the first DC power supply to the drive unit. According to the above description, this drive system includes a DC converter with circuitry, which is electrically connected to the first DC power supply on its primary side and to the second DC power supply on its secondary side. Thus, the DC converter is capable of supplying electrical energy from the first DC power supply to the second DC power supply. Attached Figure Description

[0044] An embodiment of the present invention and its function Figure 1 and 2 The following is an explanation of what is shown in the diagram and will be presented in detail below. Wherein:

[0045] Figure 1 The effect of the cutoff time in a MOSFET transistor on the reverse recovery current generated during cutoff is shown.

[0046] Figure 2 The circuitry, including the secondary circuitry of the DC-DC converter, is shown.

[0047] Figure 3 A flowchart is shown for a method of controlling the secondary side of a DC converter. Detailed Implementation

[0048] In this embodiment, a MOSFET transistor, representing one of the many possible switching elements described above, is used as the controllable switching element. Figure 1 a and lb illustrate the effect of the cutoff time on the reverse recovery current generated at cutoff in an example of a controlled MOSFET transistor with an inductive load. Figure 1 In curve a, two measurement curves illustrate the variation of current i in amperes on the MOSFET transistor with respect to time t in nanoseconds, where the MOSFET transistor is turned off prematurely. Specifically, the MOSFET transistor is turned off 10 ns prematurely in measurement curve aa, and the current is turned off 200 ns prematurely in measurement curve ab. It can be clearly seen that the further the turn-off time is from the optimal time, the greater the increase in reverse recovery current and the generated charge.

[0049] Figure 1b shows the variation curves of the reverse recovery current as measured according to Figure 1a, but with the turn-off delayed. Here, the measured curve ba represents a turn-off delayed by 10 ns, bb represents a turn-off delayed by 20 ns, and bc represents a turn-off delayed by 50 ns. For this so-called "shoot-through," the channel of the MOSFET transistor in the synchronous rectifier closes too late. Due to the large current steepness in this stage, very large reverse current and charge are also generated here. Significant turn-off losses occur in the controlled MOSFET transistor due to the suboptimal selection of the turn-off time. This is particularly important at the high switching frequency of DC converters.

[0050] Figure 2 A simplified equivalent circuit diagram of the secondary side 20 of a DC-DC converter having the circuit arrangement 10 according to the invention is shown. The topology of the DC-DC converter 20 can, for example, have a flyback converter, a forward converter, a resonant converter topology, or a topology derived therefrom. The secondary side 20 of the DC-DC converter is fed as an AC voltage source via the secondary winding 6 of an ideally assumed transformer, which is powered by the DC-DC converter's... Figure 2 The primary side (not shown) is supplied with power. The leakage inductance 7 in the equivalent circuit diagram represents the inductance of the secondary side of the transformer (not shown) and the parasitic leakage inductance of the secondary side of the DC converter. This leakage inductance 7 is connected to the first contact of the AC voltage source in the equivalent circuit diagram and forms the positive potential terminal 9 of the secondary winding 6 of the transformer on the side opposite to the secondary winding 6 of the transformer.

[0051] Furthermore, the first contact 1a, especially the source contact, of the MOSFET transistor 1 in the circuit device 10 for controlling the current is connected to the positive potential terminal 9, and the current I on the secondary side 20 of the DC converter is rectified by means of the first contact. The second contact 1c, especially the drain contact, of the MOSFET transistor 1 is connected to the first terminal 8a of the output terminal of the secondary side 20 of the DC converter.

[0052] exist Figure 2 In the diagram, the intrinsic diode ld of MOSFET transistor 1 is shown in parallel with the source contact 1a and the drain contact 1c. The negative potential terminal 11 of the transformer's secondary winding is connected to the second terminal 8b of the output terminal of the secondary side 20 of the DC converter, which is represented here in the equivalent circuit diagram by the lower contact of the AC voltage source 6. The current I rectified by the rectifier circuit is fed to the output terminals 8a and 8b of the secondary side 20 of the DC converter.

[0053] A buffer circuit is used to limit overvoltage on the MOSFET transistor 1 in the rectifier circuit during the cut-off process. Here, the buffer circuit has a series circuit consisting of a diode 2 and a storage capacitor 3, which is connected in parallel with the MOSFET transistor 1 at its source contact 1a and drain contact 1c. Furthermore, the buffer circuit has a discharge resistor 4 connected between the common contact of the diode 2 and the capacitor 3 and the negative potential terminal 11.

[0054] The described buffer circuit is a special arrangement of what is known as an RCD buffer (resistor, capacitor, diode). In principle, other arrangements of these components are also known from the literature and can be used in the described method.

[0055] In circuit arrangement 10, the initially positive current I is reduced by the negative rectangular edge of the AC voltage source 6. Finally, the sign of the current I changes and it flows in the positive direction through the MOSFET transistor 1 until the intrinsic diode can accept the cutoff voltage. The voltage across the intrinsic diode continues to increase and eventually reaches the sum of the voltages at the output terminals of the secondary side 8a and 8b of the DC converter and at the negative edge of the AC voltage source on the secondary side 6 of the transformer.

[0056] At this moment, no voltage is applied to the leakage inductance 7, thus no current change occurs. The maximum forward current I is also reached at this moment. As a result, the voltage on MOSFET transistor 1 continues to increase. Once the cutoff voltage exceeds the voltage on capacitor 3, the voltage on diode 2 is forward polarized, and current is switched from MOSFET transistor 1 to the snubber circuit. Thus, the maximum voltage appearing on MOSFET transistor 1 is limited. Through this process, energy is stored in storage capacitor 3. This energy is partially converted into heat through resistor 4 and partially output to the output terminals 8a, 8b of the secondary side 10 of the DC-DC converter. The energy transferred to storage capacitor 3 during each switching process depends directly on the energy stored at the cutoff moment. The more power supplied to storage capacitor 3, the higher the voltage rises on it. In the quiescent state, a voltage is generated on storage capacitor 3 for which power balance is compensated. Therefore, by measuring the slowly changing voltage on storage capacitor 3, control parameters for optimizing the cutoff moment of MOSFET transistor 1 can be determined.

[0057] The regulating circuit 5 is connected in parallel with capacitor 3 via its first input terminal 5a and second input terminal 5b for voltage tapping. The gate contact 1b of MOSFET transistor 1 is connected to the output terminal 5c of the regulating circuit 5. Through this contact 5c, the regulating circuit 5 can turn off MOSFET transistor 1. For simplicity, the control circuit for turning on MOSFET transistor 1 is not shown.

[0058] The regulating circuit 5 is configured such that the cut-off time of the MOSFET transistor 1 in one cycle varies slightly relative to the previous cut-off time, especially with respect to a predetermined interval between the cut-off processes on the primary side. The optimized cut-off time is determined based on the voltage detected on the capacitor 3 of the buffer circuit, so as to minimize the voltage in the following cycle. This establishes optimal operation of the synchronous rectification circuit.

[0059] Figure 3 A flowchart illustrating a method for controlling the secondary side of a DC converter is shown as an example.

[0060] In step S1, a voltage measurement is performed on the storage element 3 of the buffer circuit, and the voltage V(k) on the storage capacitor 3 is detected and compared with the voltage V(kl) measured in the previous cycle in step S2.

[0061] If the value V(k) < V(kl), then in step S3, the change in the cutting time dT(k) is set accordingly in the same direction as the previous change in the cutting time dT(kl), that is, the cutting time is advanced or delayed:

[0062] dT(k) = dT(kl).

[0063] If the value V(k) >= V(kl), then in step S5, the change of the cut-off time dT(kl) is set to the negative of the previous change of the cut-off time dT(kl):

[0064] dT(k) = -dT(kl).

[0065] In step S4, the new optimized cutoff time A(k) is obtained by adding dT(k) to the old cutoff time A(kl) for two cases:

[0066] A(k)=A(kl)+dT(k)

[0067] Then a new process begins, which starts again with S1.

Claims

1. Circuit arrangement (10) for controlling a through current of a secondary side (20) of a DC / DC converter, having: a controllable switching element (1) for switching a through current through the secondary side of the DC / DC converter, having a first connection (la), a second connection (lc) and a control connection (lb); a snubber circuit electrically coupled to the first connection (la) and the second connection (lc), which protects the controllable switching element (1) from overvoltage; and an adjusting circuit (5) which is set up for: periodically switching off the controllable switching element (1) at one time instant, wherein the time instant has a predefinable interval with respect to a switching-off process of a primary side, ascertaining an optimized switching-off time instant for a next cycle of the controllable switching element (1), the adjusting circuit (5) being electrically coupled to the snubber circuit and being set up for ascertaining the optimized switching-off time instant from an electrical quantity of the snubber circuit, the adjusting circuit (5) being set up for: detecting a first voltage on a storage element of the snubber circuit after a first switching off of the controllable switching element (1), selecting a switching-off time instant for a second subsequent switching off, which is advanced or delayed with respect to the predefinable interval with respect to the switching-off process of the primary side compared to the first switching-off time instant, detecting a second voltage on the storage element of the snubber circuit after a second subsequent switching off of the controllable switching element (1) at the selected optimized switching-off time instant, ascertaining a difference between the first voltage and the second voltage, and ascertaining an optimized switching-off time instant for a subsequent cycle as an optimized switching-off time instant which is advanced or delayed with respect to the last ascertained switching-off time instant depending on the ascertained positive or negative difference. The adjusting circuit (5) detects the voltage on the storage element of the snubber circuit via a voltage tap on the storage element. The DC / DC converter is configured as a synchronous rectifier. The adjusting circuit (5) has a microcontroller circuit. The first connection (la) of the controllable switching element (1) is connected to a positive potential connection (9) of a winding (6) of a transformer of the DC / DC converter, and the snubber circuit is electrically connected to the first connection (la) of the controllable switching element (1), to the second connection (lc) of the controllable switching element (1) and to a negative potential connection (11) of the winding (6) of the secondary side of the transformer. and the controllable switching element (1) is switched off at the optimised switch-off time in the following cycle by means of the control connection (lb), characterised in that The snubber circuit has a capacitor (3) as storage element. The snubber circuit has a series circuit consisting of a diode (2) and a capacitor (3) as storage element, which is connected in parallel to the first connection (la) and the second connection (lc) of the controllable switching element (1), and the snubber circuit has a discharge resistor (4), which is connected to an intermediate tap between the diode (2) and the capacitor (3) and to the negative potential connection (11) of the winding (6) of the secondary side of the transformer. ​ ​ ​ 2. The circuit arrangement (10) according to claim 1, characterized in that ​ 3. The circuit arrangement (10) according to claim 1 or 2, characterized in that ​ 4. The circuit arrangement (10) according to claim 1 or 2, characterized in that ​ 5. The circuit arrangement (10) according to claim 1 or 2, characterized in that ​ ​ 6. The circuit arrangement (10) as claimed in claim 5, characterized by ​ 7. The circuit arrangement (10) as claimed in claim 6, characterized by ​ 8. Method for operating a secondary side of a DC / AC converter (20), wherein the secondary side has controllable switching elements (1) and a snubber circuit (2, 3, 4), wherein The snubber circuit (2, 3, 4) protects the controllable switching element (1) from overvoltage, wherein the controllable switching element has a first terminal (la), a second terminal (lc) and a control terminal (lb), and the snubber circuit is electrically coupled with the first terminal (la) and the second terminal (lc), wherein the method periodically switches off the controllable switching element (1) at a time, wherein the time has a predefinable interval to the primary-side switching-off process; and identifies an optimized switching-off time for the following switching cycle depending on a detection of a voltage on a storage element of the snubber circuit for operating the controllable switching element (1), wherein the method identifies an optimized switching-off time for operating the controllable switching element (1) by: detecting a first voltage on a storage element of the snubber circuit after a first switching-off of the controllable switching element (1) (S1), for a second following switching-off, selecting a switching-off time which is advanced or delayed compared to the first switching-off time with respect to the predefinable interval to the primary-side switching-off process, detecting a second voltage on the storage element of the snubber circuit after a second switching-off of the controllable switching element (1) (S1), identifying a difference between the first voltage and the second voltage (S2), and identifying a following optimized switching-off time depending on the identified positive or negative difference as a switching-off time which is advanced or delayed with respect to the last identified switching-off time (S3, S5, S4).

9. The method according to claim 8, wherein the DC-to-DC converter is configured as a synchronous rectifier.

10. Computer program product comprising instructions which, when the program is executed by a computer, cause the computer to carry out the method according to any one of claims 8 to 9.

11. Computer-readable storage medium comprising instructions which, when executed by a computer, cause the computer to carry out the method according to any one of claims 8 to 9.

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