Display device

Abstract

This application discloses a display device capable of suppressing image quality degradation. The display device includes: a plurality of first sub-pixels displaying red, a plurality of second sub-pixels displaying green, a plurality of third sub-pixels displaying blue, and a plurality of fourth sub-pixels displaying white; a first signal line, a second signal line, and a third signal line, wherein the first signal line is connected to the plurality of first sub-pixels, the second signal line is connected to the plurality of second sub-pixels, and the third signal line is connected to the plurality of third sub-pixels and the plurality of fourth sub-pixels; a plurality of detection electrodes arranged in a matrix and respectively overlapping the plurality of first sub-pixels, the plurality of second sub-pixels, the plurality of third sub-pixels, and the plurality of fourth sub-pixels; and a plurality of signal supply wirings respectively connected to the plurality of detection electrodes, wherein the signal supply wirings are arranged overlapping at least one of the first signal line and the second signal line, and are not overlapping the third signal line.

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] Patent document 1 describes a display device with a sensor, which has a plurality of detection electrodes arranged in a matrix and a plurality of sensor wirings connected to one detection electrode. Patent document 2 also describes a display device, which has a sub-pixel that displays white in addition to sub-pixels that display red, green, and blue, respectively. Patent document 2 also describes a column inversion drive method as a method for driving the display device.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2019-148855

[0004] Patent Document 2: Japanese Patent Application Publication No. 2015-230343

[0005] In the display device of Patent Document 2, when a plurality of detection electrodes are provided by inserting slits in the common electrode as in the technology of Patent Document 1, so-called crosstalk may occur, resulting in a reduction in image quality. Therefore, it is desirable to reduce the parasitic capacitance formed between the signal line and the detection electrode (common electrode), especially the parasitic capacitance of the signal line commonly connected to the blue sub-pixel and the white sub-pixel. Summary of the invention

[0006] An object of the present invention is to provide a display device capable of suppressing degradation of image quality.

[0007] A display device according to one embodiment of the present invention comprises: a plurality of first sub-pixels, a plurality of second sub-pixels, a plurality of third sub-pixels and a plurality of fourth sub-pixels, wherein the plurality of first sub-pixels display red, the plurality of second sub-pixels display green, the plurality of third sub-pixels display blue and the plurality of fourth sub-pixels display white; a first signal line, a second signal line and a third signal line, wherein the first signal line is connected to the plurality of first sub-pixels, the second signal line is connected to the plurality of second sub-pixels, and the third signal line is connected to the plurality of third sub-pixels and the plurality of fourth sub-pixels; a plurality of detection electrodes, wherein the plurality of detection electrodes are arranged in a matrix and are respectively arranged to overlap with the plurality of first sub-pixels, the plurality of second sub-pixels, the plurality of third sub-pixels and the plurality of fourth sub-pixels; and a plurality of signal supply wirings, wherein the plurality of signal supply wirings are respectively connected to the plurality of detection electrodes, the signal supply wirings are arranged to overlap with at least one of the first signal line and the second signal line, and are arranged not to overlap with the third signal line.

[0008] A display device according to one embodiment of the present invention comprises: a plurality of first sub-pixels, a plurality of second sub-pixels, a plurality of third sub-pixels, and a plurality of fourth sub-pixels, wherein the plurality of first sub-pixels display red, the plurality of second sub-pixels display green, the plurality of third sub-pixels display blue, and the plurality of fourth sub-pixels display white; a first signal line, a second signal line, and a third signal line, wherein the first signal line is connected to the plurality of first sub-pixels, the second signal line is connected to the plurality of second sub-pixels, and the third signal line is connected to the plurality of third sub-pixels and the plurality of fourth sub-pixels; and a first insulating film, wherein the first insulating film is provided on the first signal line, the second signal line, and the third signal line. and the third signal line; a second insulating film, which is arranged on the first insulating film; a signal supply wiring, which is arranged between the first insulating film and the second insulating film; and a plurality of detection electrodes, which are arranged on the second insulating film and arranged in a matrix, the signal supply wiring is connected to the detection electrode via a contact hole arranged in the second insulating film in an area overlapping with at least one of the first signal line and the second signal line, and in an area overlapping with the third signal line, a dummy contact hole with the first insulating film as a bottom surface is provided in the second insulating film. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is an exploded perspective view showing the display device according to the first embodiment.

[0010] Figure 2 FIG. 1 is a schematic top view of an array substrate.

[0011] Figure 3 Schematic diagram showing the pixel arrangement of the display device according to the first embodiment.

[0012] Figure 4 is an equivalent circuit diagram showing the structure of a pixel.

[0013] Figure 5 It is a timing waveform chart showing an operation example of the display device according to the first embodiment and the comparative example.

[0014] Figure 6 This is an explanatory diagram for explaining the relationship between a plurality of detection electrodes, a plurality of drive signal supply wirings, and a plurality of dummy wirings.

[0015] Figure 7 It is a top view for explaining the detection electrode in the schematic top view of the pixel.

[0016] Figure 8 This is a plan view for explaining a drive signal supply wiring and a dummy wiring in a schematic plan view of a pixel.

[0017] Fig. 9 yes Figure 8 IX-IX' section view.

[0018] Fig.10 It is a plan view for explaining the switching element according to the first embodiment.

[0019] Fig.11 It is a cross-sectional view for explaining a contact hole.

[0020] Fig.12 It is a cross-sectional view for explaining a dummy contact hole.

[0021] Fig.13 It is a plan view for explaining a display device according to a second embodiment.

[0022] Fig.14 It is a plan view for explaining a display device according to a third embodiment.

[0023] Fig.15 This is a plan view for explaining a drive signal supply wiring and a dummy wiring in a schematic plan view of a pixel according to the third embodiment.

[0024] Fig.16 It is a plan view for explaining a display device according to a fourth embodiment.

[0025] Fig.17 This is a plan view for explaining a drive signal supply wiring and a dummy wiring in a schematic plan view of a pixel according to the fourth embodiment.

[0026] Description of Reference Numerals

[0027] 10…first insulating substrate; 14…first organic insulating film; 15…second organic insulating film; 20…second insulating substrate; CE, CE1, CE2, CE3, CE4…detection electrodes; CH, CH11, CH12…contact holes; CHD…dummy contact holes; G1, G2, G3, GL…scanning lines; PE1, PE2, PE3, PE4…pixel electrodes; PX…pixel; PX1…first pixel; PX2…second pixel; PNL…display device; S1 , S2, S3, S4, S5, S6, SL…signal line; SPX…sub-pixel; SPX1…first sub-pixel; SPX2…second sub-pixel; SPX3…third sub-pixel; SPX4…fourth sub-pixel; SPA, SPB, SPL…slit; SUB1…array substrate; SUB2…opposing substrate; TL, TL1, TL2…driving signal supply wiring; TLD1…first dummy wiring; TLD2…second dummy wiring; TLD3…third dummy wiring. DETAILED DESCRIPTION

[0028] The mode (implementation method) for implementing the present invention is described in detail with reference to the accompanying drawings. The present disclosure is not limited by the contents described in the following implementation methods. In addition, the constituent elements described below include substantially the same constituent elements that can be easily thought of by a person skilled in the art. Further, the constituent elements described below can be appropriately combined. In addition, what is disclosed is only an example, and the appropriate changes that can be easily thought of by a person skilled in the art to maintain the main purpose of the present disclosure are of course also included in the scope of the present disclosure. In addition, in order to explain more clearly, the drawings sometimes schematically indicate the width, thickness, shape, etc. of each part compared to the actual method, but these are merely examples and are not used to limit the interpretation of the present disclosure. In addition, in the present disclosure and the drawings, the same figure mark is sometimes used to mark the same elements as those described in the drawings that have appeared, and the detailed description is appropriately omitted.

[0029] In the present specification and claims, when expressing the manner of configuring other structures above a certain structure, when simply expressed as "above...", unless otherwise specified, it includes the following two situations: the situation where the other structures are configured above (or directly above) the certain structure in such a manner as to be in contact with the certain structure; and the situation where the other structures are further configured above the certain structure via another structure.

[0030] (First Embodiment)

[0031] Figure 1 FIG. 2 is an exploded perspective view showing the display device of the first embodiment. Figure 1 As shown, the display device PNL includes an array substrate SUB1 and an opposing substrate SUB2. Figure 1 As shown, in the display device PNL, a peripheral area BE is provided outside the display area DA. The display area DA is formed into a quadrilateral, but the shape of the outer shape of the display area DA is not limited. For example, there may be a notch in the display area DA, or the display area DA may be formed into other polygons, or the display area DA may be formed into other shapes such as a circle or an ellipse.

[0032] In this embodiment, the first direction X is a direction along the short side of the display area DA. The second direction Y is a direction intersecting (or orthogonal to) the first direction X. It is not limited to this, and the second direction Y may also intersect with the first direction X at an angle other than 90°. The plane defined by the first direction X and the second direction Y is parallel to the surface of the array substrate SUB1. In addition, the third direction Z orthogonal to the first direction X and the second direction Y is the thickness direction of the array substrate SUB1. In addition, the top view indicates the positional relationship when viewed from the third direction Z.

[0033] The display area DA is an area for displaying an image and is an area overlapping with a plurality of pixels PX. The peripheral area BE refers to an area that is inside the periphery of the array substrate SUB1 and outside the display area DA. In addition, the peripheral area BE may also be a frame that surrounds the display area DA. In this case, the peripheral area BE may also be a frame area.

[0034] The display area DA that displays an image includes a sensor area included in the detection device that detects the electrostatic capacitance. Figure 1 As shown, a plurality of detection electrodes CE are arranged in a matrix in the display area DA in the first direction X and the second direction Y. Each detection electrode CE is schematically shown as a rectangle or a square in a plan view, and the detailed shape of the detection electrode CE will be described later. The detection electrode CE is made of a light-transmitting conductive material such as ITO (Indium Tin Oxide).

[0035] like Figure 1 As shown, peripheral wiring CE-G and integrated circuit CP are provided in the peripheral area BE on one side of the array substrate SUB1. For example, the peripheral wiring CE-G is continuously provided along the long side and the short side of the display area DA to surround the display area DA.

[0036] The display device PNL is a display device with a sensor in which the sensor region and the display region DA are integrated. Specifically, in the display region PNL, a part of the components of the display region DA constitutes the detection electrode CE of the sensor region.

[0037] Figure 2 FIG. 1 is a schematic top view of an array substrate. Figure 2 As shown, the detection electrodes CE are divided into a matrix shape in the first direction X and the second direction Y by the slits SPB. A connection circuit MP and an integrated circuit CP are provided on the short side of the peripheral area BE. In addition, a wiring substrate not shown is connected to the short side of the peripheral area BE. The wiring substrate is, for example, a flexible printed substrate. In addition, the configuration of the connection circuit MP and the integrated circuit CP is not limited thereto, and for example, they may also be provided on a control substrate or a flexible printed substrate outside the module.

[0038] The detection electrode CE is electrically connected to the integrated circuit CP via the drive signal supply wiring TL and the connection circuit MP. The drive signal supply wiring TL is connected to the plurality of detection electrodes CE respectively, and during touch detection, the drive signal is supplied to the plurality of detection electrodes CE respectively, and the signal corresponding to the change in static electricity is sent to the analog front end. Alternatively, the drive signal supply wiring TL supplies a reference potential VCOM to the detection electrode CE during the display period. The plurality of drive signal supply wirings TL are electrically connected to the plurality of detection electrodes CE arranged in the display area DA, respectively, and are led out to the peripheral area BE. The plurality of drive signal supply wirings TL extend respectively along the second direction Y, and the plurality of drive signal supply wirings TL are arranged side by side in the first direction X. For example, the drive circuit built into the integrated circuit CP is connected to the plurality of detection electrodes CE respectively via the connection circuit MP and the drive signal supply wiring TL arranged in the peripheral area BE.

[0039] The contact hole CH has a connection portion for electrically connecting the detection electrode CE and the drive signal supply wiring TL overlapping with the detection electrode CE. Figure 2 In the diagram, the driving signal supply wiring TL is schematically connected to one detection electrode CE. As described later, in reality, the driving signal supply wiring TL bundles a plurality of wirings and routes them into the display area DA.

[0040] The display device PNL further includes a connection circuit MP. The connection circuit MP is provided between the detection electrode CE and the integrated circuit CP. The connection circuit MP is a circuit that switches the connection and disconnection between the detection electrode CE and the integrated circuit CP that are the detection drive objects based on a control signal supplied from the integrated circuit CP. The connection circuit MP is, for example, a multiplexer. The integrated circuit CP has an analog front end.

[0041] Figure 3 Schematic diagram showing the pixel arrangement of the display device of the first embodiment. Figure 3 As shown, a plurality of pixels PX are arranged in a matrix. The pixel PX includes a first sub-pixel SPX1, a second sub-pixel SPX2, a third sub-pixel SPX3, and a fourth sub-pixel SPX4. The first sub-pixel SPX1 displays red as a first primary color. The second sub-pixel SPX2 displays green as a second primary color. The third sub-pixel SPX3 displays blue as a third primary color. The fourth sub-pixel SPX4 displays white. In addition, when there is no need to distinguish between the first sub-pixel SPX1, the second sub-pixel SPX2, the third sub-pixel SPX3, and the fourth sub-pixel SPX4, they are sometimes represented as sub-pixels SPX.

[0042] The pixel PX includes a first pixel PX1 and a second pixel PX2. The first pixel PX1 includes a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The second pixel PX2 includes a first sub-pixel SPX1, a second sub-pixel SPX2, and a fourth sub-pixel SPX4. The first pixel PX1 and the second pixel PX2 are alternately arranged in the first direction X and the second direction Y, respectively.

[0043] More specifically, the first sub-pixels SPX1 are arranged in the second direction Y. A first sub-pixel column composed of the first sub-pixels SPX1 arranged in the second direction Y is connected to common signal lines S1 and S4 (first signal lines). The second sub-pixels SPX2 are arranged in the second direction Y. A second sub-pixel column composed of the second sub-pixels SPX2 arranged in the second direction Y is arranged adjacent to the first sub-pixel column in the first direction X. The second sub-pixel column is connected to common signal lines S2 and S5 (second signal lines).

[0044] The third sub-pixel SPX3 and the fourth sub-pixel SPX4 are alternately arranged in the second direction Y. The third sub-pixel column composed of the third sub-pixel SPX3 and the fourth sub-pixel SPX4 arranged in the second direction Y is adjacent to the second sub-pixel column in the first direction X. The third sub-pixel column is connected to common signal lines S3 and S6 (third signal lines). The first sub-pixel column, the second sub-pixel column, and the third sub-pixel column are repeatedly arranged in the first direction X in sequence.

[0045] In addition, the first pixels PX1 and the second pixels PX2 arranged in the first direction X are connected to the scanning lines G1, G2, and G3 in each row. In the following description, the plurality of scanning lines G1, G2, and G3 are sometimes collectively referred to as scanning lines GL. The plurality of signal lines S1, S2, S3, S4, S5, and S6 are sometimes collectively referred to as signal lines SL.

[0046] Figure 4 is an equivalent circuit diagram showing the structure of a pixel. Figure 4 The switching element Tr, signal line SL, scanning line GL, etc. of each sub-pixel SPX are shown. The signal line SL is used to connect the pixel electrode PE (see Figure 8 ) is a wiring for supplying pixel signals. The scanning lines G1, G2, and G3 are wirings for supplying gate signals VGL1, VGL2, and VGL3 for driving each switching element Tr.

[0047] like Figure 4As shown in FIG. 1 , each sub-pixel SPX includes a switching element Tr and a holding capacitor Cs of the liquid crystal layer LC. The switching element Tr is composed of a thin film transistor, and in this example, it is composed of an n-channel MOS (Metal Oxide Semiconductor) type TFT. An insulating film 16 (see FIG. 1 ) is provided between the pixel electrode PE and the detection electrode CE described later. Fig. 9 ), formed by them Figure 4 The holding capacitor Cs is shown.

[0048] The gate of the switching element Tr is connected to the scanning line GL. The source of the switching element Tr is connected to the signal line SL. The drain of the switching element Tr is connected to the pixel electrode PE. Figure 4 In the equivalent circuit diagram shown, the drain of the switching element Tr is connected to one end of the storage capacitor Cs and one end of the capacitor of the liquid crystal layer LC. The other end of the storage capacitor Cs and the other end of the capacitor of the liquid crystal layer LC are connected to the detection electrode CE.

[0049] Furthermore, parasitic capacitances Csg, Csc, and Cgc are formed in the sub-pixel SPX. The parasitic capacitance Csg is a capacitance component formed between the scanning line GL and the signal line SL. The parasitic capacitance Csc is a capacitance component formed between the detection electrode CE and the signal line SL. The parasitic capacitance Cgc is a capacitance component formed between the detection electrode CE and the scanning line GL.

[0050] Next, refer to Figures 3 to 5 , an example of a driving method of the display device PNL of this embodiment and a driving method of the display device of the comparative example are described. Figure 5 1 is a timing waveform diagram showing an operation example of the display device according to the first embodiment and the comparative example. Figure 5 , the waveform supplied to the detection electrode CE is shown by a solid line in the display device PNL of the first embodiment, and by a dotted line in the display device of the comparative example. In addition, regarding the gate signal VGL, the control signal supplied to the selectors SELR, SELG, SELBW, and the pixel signal SIG, the case where a common signal is supplied to the display devices of the first embodiment and the comparative example is described.

[0051] The display device PNL of the present embodiment and the driving method of the comparative example are column inversion driving. Column inversion driving is a driving method in which voltages of opposite polarities are applied to a line (column) of sub-pixels or pixels formed by combining sub-pixels, and the polarity of the applied voltage is reversed at a predetermined cycle.

[0052] For example, for the image displayed in the n-1th cycle, pixel signals SIG1, SIG3, SIG5 corresponding to negative voltages based on the reference potential VCOM are supplied to the signal lines SL1, SL3, SL5. Pixel signals SIG2, SIG4, SIG6 corresponding to positive voltages based on the reference potential VCOM are supplied to the signal lines SL2, SL4, SL6.

[0053] Next, relative to the image displayed in the nth cycle, Figure 3 As shown, pixel signals SIG1, SIG3, SIG5 corresponding to positive voltages based on the reference potential VCOM are supplied to the signal lines SL1, SL3, SL5. Pixel signals SIG2, SIG4, SIG6 corresponding to negative voltages based on the reference potential VCOM are supplied to the signal lines SL2, SL4, SL6.

[0054] In addition, in the following description, it is assumed that Figure 3 Among the plurality of sub-pixels SPX included in the region 101 shown, a pixel signal SIG for displaying blue is supplied to the third sub-pixel SPX3, and a voltage GND is supplied to the other sub-pixels SPX to display black. It is assumed that the plurality of sub-pixels SPX included in the display region DA other than the region 101 are supplied with a pixel signal SIG for displaying a gray image. In the following description, the region composed of the plurality of sub-pixels SPX other than the region 101 is referred to as a background portion. For the gray image displayed in the background portion, the voltage supplied to the plurality of sub-pixels SPX is referred to as a voltage for displaying an image of a halftone, for example.

[0055] like Figure 5 As shown, the gate signal VGL2 is supplied to the scanning line G2. During the period when the gate signal VGL2 is on, pulse signals are supplied to the selectors SELR, SELG, and SELBW, respectively. The selectors SELR, SELG, and SELBW are connected to the circuit MP (see Figure 1 ) has a switching element. For example, when the pulse signal becomes conductive, the selector SELR selects the signal lines S1 and S4 respectively, and supplies pixel signals SIG1 and SIG4 to the first sub-pixel SPX1 connected to the signal lines S1 and S4. When the pulse signal becomes conductive, the selector SELG selects the signal lines S2 and S5 respectively, and supplies pixel signals SIG2 and SIG5 to the second sub-pixel SPX2 connected to the signal lines S2 and S5. When the pulse signal becomes conductive, the selector SELBW selects the signal lines S3 and S6 respectively, and supplies pixel signals SIG3 and SIG6 to the third sub-pixel SPX3 and the fourth sub-pixel SPX4 connected to the signal lines S3 and S6.

[0056] like Figure 5As shown in FIG. 1 , when a pulse signal is supplied to the selector SELBW, the signal line S3 rises from a negative potential to a potential GND, and a white pixel signal SIG3 corresponding to the potential GND is supplied to the fourth sub-pixel SPX4 selected by the scanning line G2. The negative potential supplied during the period before being selected by the selector SELBW is a potential corresponding to the blue pixel signal SIG supplied to the third sub-pixel SPX3 selected by the scanning line G1 of the previous row.

[0057] Furthermore, when a pulse signal is supplied to the selector SELBW, the signal line S6 rises from the potential GND to a positive potential, and a blue pixel signal SIG6 corresponding to the positive potential is supplied to the third sub-pixel SPX3 selected by the scan line G2. The potential GND supplied during the period before selection by the selector SELBW is a potential corresponding to the white pixel signal SIG supplied to the fourth sub-pixel SPX4 selected by the scan line G1 of the previous row.

[0058] That is, the potential supplied to the signal lines S3 and S6 both rises. As described above, the signal line SL and the detection electrode CE are connected by the parasitic capacitance Csc (see Figure 4 ) capacitive coupling. Therefore, as the potential of the signal lines S3 and S6 rises, the potential of the detection electrode CE also rises. Figure 2 The plurality of drive signal supply wirings TL shown are electrically connected to the plurality of detection electrodes CE. Therefore, the potentials of the plurality of detection electrodes CE and the plurality of drive signal supply wirings TL also rise in the background portion other than the region 101 to which the pixel signals SIG3 and SIG6 are supplied.

[0059] like Figure 5 As shown in FIG. 1 , the potential of the detection electrode CE decreases with time according to the time constant of the detection electrode CE and the drive signal supply wiring TL, and converges to the original potential. However, in the display device of the comparative example having a large parasitic capacitance Csc, as shown in FIG. Figure 5 As shown by the dotted line GQ, the voltage of the crosstalk component does not converge until the moment Toff when the pulse signal supplied to the selector SELBW turns off. The voltage difference generated at the detection electrode CE may increase the effective voltage of the fourth sub-pixel SPX4, and an image that would not have been generated in the background may appear. In addition, the change in the brightness of the fourth sub-pixel SPX4 is greater than the change in the brightness of other sub-pixels SPX, and there is a tendency to be easily affected.

[0060] Furthermore, when the display device PNL is driven at high speed, that is, when the pulse width of the pulse signal supplied to the selector SELBW is narrowed, the voltage difference at the time Toff becomes larger, and the possibility of display quality degradation increases.

[0061] In this embodiment, the parasitic capacitance Csc between the signal line SL and the detection electrode CE is suppressed, so that the time constant of the detection electrode CE and the drive signal supply wiring TL can be reduced. As a result, the potential of the detection electrode CE converges to the original potential faster than in the prior art, and the potential difference generated by the detection electrode CE at the time Toff is suppressed. Therefore, in this embodiment, the potential difference of the crosstalk component can be suppressed, and the reduction of the display quality can be suppressed.

[0062] in addition, Figure 5 The timing waveform diagram shown is only an example and is not limited to Figure 5 Example shown.

[0063] Next, a specific configuration for reducing the time constant for supplying the detection electrode CE and the drive signal to the wiring TL will be described. Figure 6 This is an explanatory diagram for explaining the relationship between a plurality of detection electrodes, a plurality of drive signal supply wirings, and a plurality of dummy wirings.

[0064] like Figure 6 As shown, the detection electrodes CE1, CE2, CE3, and CE4 are arranged in the second direction Y. The detection electrodes CE1, CE2, CE3, and CE4 are respectively arranged to overlap with a plurality of sub-pixels SPX (a plurality of first sub-pixels SPX1, a plurality of second sub-pixels SPX2, a plurality of third sub-pixels SPX3, and a plurality of fourth sub-pixels SPX4). In addition, in order to facilitate observation of the drawings, Figure 6 In FIG. 1 , one row of sub-pixels SPX is shown overlapping with the detection electrodes CE. However, in reality, one detection electrode CE is arranged to overlap with a plurality of rows of sub-pixels SPX.

[0065] In the following description, when there is no need to distinguish between the detection electrodes CE1, CE2, CE3, and CE4, they are referred to as the detection electrodes CE. The detection electrodes CE include a main detection electrode CEP and sub-detection electrodes CEA and CEB (for the sub-detection electrode CEA, refer to Figure 7 ). Slits SPA are formed between the main detection electrodes CEP adjacent to each other in the first direction X. The detailed structure of the detection electrode CE will be described later.

[0066] The drive signal supply wiring TL1 is provided corresponding to the first sub-pixel column composed of a plurality of first sub-pixels SPX1. The drive signal supply wiring TL2 is provided corresponding to the second sub-pixel column composed of a plurality of second sub-pixels SPX2. The drive signal supply wirings TL1 and TL2 are connected to the detection electrode CE via the contact hole CH, respectively. In addition, in the following description, when it is not necessary to distinguish between the drive signal supply wirings TL1 and TL2, they are simply represented as the drive signal supply wiring TL.

[0067] More specifically, a set of drive signal supply wirings TL1 and TL2 adjacent in the first direction X is set as a wiring group TLG. The wiring groups TLG1, TLG2, TLG3, and TLG4 are arranged in the first direction X and are respectively connected to the detection electrodes CE1, CE2, CE3, and CE4. The lengths of the wiring groups TLG1, TLG2, TLG3, and TLG4 in the second direction Y are successively longer. The wiring group TLG1 connected to the detection electrode CE1 does not overlap with the detection electrodes CE2, CE3, and CE4. The wiring group TLG2 connected to the detection electrode CE2 does not overlap with the detection electrodes CE3 and CE4. The wiring group TLG3 connected to the detection electrode CE3 does not overlap with the detection electrode CE4.

[0068] Two drive signal supply wirings TL1 and TL2 are connected to one detection electrode CE. The drive signal supply wiring TL1 is connected to the detection electrode CE via two contact holes CH, and the drive signal supply wiring TL2 is connected to the detection electrode CE via two contact holes CH. Figure 6 In the embodiment, the detection electrode CE is electrically connected to the drive signal supply wirings TL1 and TL2 through a total of four contact holes CH. However, this is not limited to this, as long as at least one drive signal supply wiring TL is provided. In addition, one contact hole CH may be provided for one drive signal supply wiring TL, or three or more contact holes CH may be provided.

[0069] The display device PNL further includes a first dummy wiring TLD1, a second dummy wiring TLD2, and a third dummy wiring TLD3. The first dummy wiring TLD1 is provided corresponding to a first sub-pixel column composed of a plurality of first sub-pixels SPX1, and is arranged adjacent to the drive signal supply wiring TL1 in the second direction Y. The second dummy wiring TLD2 is provided corresponding to a second sub-pixel column composed of a plurality of second sub-pixels SPX2, and is arranged adjacent to the drive signal supply wiring TL2 in the second direction Y.

[0070] In the sub-pixel column provided with the wiring group TLG1, the first dummy wiring TLD1 and the second dummy wiring TLD2 overlap with the detection electrodes CE2, CE3, and CE4, and are separately arranged on each detection electrode CE2, CE3, and CE4. In the sub-pixel column provided with the wiring group TLG2, the first dummy wiring TLD1 and the second dummy wiring TLD2 overlap with the detection electrodes CE3 and CE4, and are separately arranged on each detection electrode CE3 and CE4. In the sub-pixel column provided with the wiring group TLG3, the first dummy wiring TLD1 and the second dummy wiring TLD2 are arranged to overlap with the detection electrode CE4.

[0071] The third dummy wiring TLD3 is provided corresponding to the third sub-pixel column composed of the plurality of third sub-pixels SPX3 and the plurality of fourth sub-pixels SPX4. The third dummy wiring TLD3 is arranged adjacent to the drive signal supply wirings TL1 and TL2 in the first direction X. Alternatively, the third dummy wiring TLD3 is arranged adjacent to the first dummy wiring TLD1 and the second dummy wiring TLD2 in the first direction X.

[0072] The length of the third dummy wiring TLD3 in the second direction Y is shorter than the lengths of the first dummy wiring TLD1 and the second dummy wiring TLD2 in the second direction Y. For example, the first dummy wiring TLD1 and the second dummy wiring TLD2 are separately provided at each detection electrode CE arranged in the second direction Y, and the third dummy wiring TLD3 is separately provided at each sub-pixel SPX or pixel PX arranged in the second direction Y.

[0073] In this embodiment, the first dummy wiring TLD1 is electrically connected to the detection electrode CE via the contact hole CH and is supplied with the same potential as the detection electrode CE. The number of contact holes CH provided in one first dummy wiring TLD1 is equal to the number of contact holes CH provided in one drive signal supply wiring TL1.

[0074] The second dummy wiring TLD2 is not provided with a contact hole CH and is not connected to the detection electrode CE. The second dummy wiring TLD2 is not supplied with a drive signal, a reference potential VCOM or other signals and is in a floating state. The third dummy wiring TLD3 is also not connected to the detection electrode CE and is in a floating state.

[0075] The dummy contact hole CHD is provided between the third dummy wirings TLD3 adjacent to each other in the second direction Y. The dummy contact hole CHD is provided so as not to be connected to various wirings such as the third dummy wiring TLD3 and the signal line SL. For example, when focusing on the detection electrode CE2, in the area corresponding to the leftmost pixel PX, two dummy contact holes CHD are provided in the third dummy wiring TLD3 arranged adjacent to the first dummy wiring TLD1 and the second dummy wiring TLD2. In the pixel PX in which the contact holes CH are provided in the wiring group TLG2, respectively, the dummy contact hole CHD is not provided in the third dummy wiring TLD3 arranged adjacent to the drive signal supply wirings TL1 and TL2. In the pixel PX overlapping with the wiring groups TLG3 and TLG4 and not provided with the contact holes CH respectively, four dummy contact holes CHD are provided in the third dummy wiring TLD3 arranged adjacent to the drive signal supply wirings TL1 and TL2.

[0076] In this way, the dummy contact hole CHD is provided in each predetermined region (for example, the main detection electrode CEP) in such a manner as to suppress the difference in the total number of the contact holes CH and the dummy contact holes CHD. Therefore, the deviation in the arrangement density of the contact holes CH and the dummy contact holes CHD is suppressed, thereby suppressing the reduction in display quality.

[0077] In addition, the number of contact holes CH provided in the first dummy wiring TLD1 and the number of dummy contact holes CHD provided in the third dummy wiring TLD3 can be appropriately changed. For example, the number of contact holes CH provided in the first dummy wiring TLD1 may be different from the number of contact holes CH provided in the drive signal supply wiring TL1. In the main detection electrode CEP in which the contact holes CH are provided in the drive signal supply wirings TL1 and TL2, the dummy contact holes CHD may also be provided in the third dummy wiring TLD3.

[0078] Next, the detailed structure of each sub-pixel SPX will be described. Figure 7 It is a top view for explaining the detection electrode in the schematic top view of the pixel. Figure 8 This is a plan view for explaining a drive signal supply wiring and a dummy wiring in a schematic plan view of a pixel. Fig. 9 yes Figure 8 IX-IX' section view. Fig.10 It is a plan view for explaining the switching element according to the first embodiment.

[0079] like Fig. 9 As shown, a plurality of signal lines S1, S2, S3, a plurality of pixel electrodes PE1, PE2, PE3, a plurality of detection electrodes CE, and a plurality of drive signal supply wirings TL1, TL2, TLD are formed above the first insulating substrate 10. Hereinafter, the plurality of pixel electrodes PE1, PE2, PE3 are sometimes collectively referred to as pixel electrodes PE.

[0080] like Figure 7 As shown, the scanning lines G1, G2, and G3 extend along the first direction X and are arranged side by side with equal spacing in the second direction Y. Fig. 9 However, it is formed above the first insulating substrate 10.

[0081] exist Figure 7 as well as Figure 8In the figure, the direction intersecting the second direction Y at an acute angle counterclockwise is defined as direction D1, and the direction intersecting the second direction Y at an acute angle clockwise is defined as direction D2. In addition, the angle θ1 formed by the second direction Y and the direction D1 and the angle θ2 formed by the second direction Y and the direction D2 are substantially the same. The signal lines S1, S2, and S3 extend approximately along the second direction Y, respectively, and are arranged side by side at equal intervals in the first direction X. In the example shown in the figure, the signal lines S1, S2, and S3 extend along the direction D1 between the scanning line G1 and the scanning line G2, and extend along the direction D2 between the scanning line G2 and the scanning line G3. These scanning lines G1, G2, and G3 intersect with the signal lines S1, S2, and S3 when viewed from above.

[0082] like Fig.10 As shown, the switch element Tr1 is located near the intersection of the scan line G2 and the signal line S1, and is electrically connected to the scan line G2 and the signal line S1. The switch element Tr2 is located near the intersection of the scan line G2 and the signal line S2, and is electrically connected to the scan line G2 and the signal line S2. The switch element Tr3 is located near the intersection of the scan line G2 and the signal line S3, and is electrically connected to the scan line G2 and the signal line S3.

[0083] like Figure 8 As shown, a plurality of pixel electrodes PE1, PE2, and PE3 are arranged side by side at intervals in a first direction X. The pixel electrode PE1 is located between two signal lines SL. A plurality of pixel electrodes PE1, PE2, and PE4 are arranged side by side at intervals in a second direction Y with a plurality of pixel electrodes PE1, PE2, and PE3. The pixel electrode PE1 is located between two scanning lines GL. A plurality of pixel electrodes PE1, PE2, PE3, and PE4 are respectively located in an area surrounded by two signal lines SL and two scanning lines GL.

[0084] The pixel electrode PE includes a contact portion PA, an electrode portion PB, and a connecting portion PC. The contact portion PA and the switching element Tr (see Fig.10 ) is electrically connected. The electrode portion PB extends from the contact portion PA to the side closer to the scanning line G1 from the scanning line G2. The electrode portion PB is sometimes also called a strip electrode, a linear electrode, a comb electrode, etc. Figure 8 In the embodiment, one pixel electrode PE has two electrode portions PB. The two electrode portions PB are connected to the contact portion PA. The electrode portions PB are arranged side by side with a gap in the first direction X. The connecting portion PC is connected to the ends of the two electrode portions PB.

[0085] In addition, the shape of the pixel electrode PE is not limited to Figure 8 For example, the connection portion PC may be omitted, and the number of electrode portions PB may not be two, but may be three or four, for example.

[0086] The pixel electrodes PE1, PE2, PE3, and PE4 are formed into substantially the same shape. For example, in the pixel electrodes PE1, PE2, and PE3 arranged in the first direction X, each electrode portion PB extends in the same direction and extends in a direction parallel to the direction D1. In addition, in the pixel electrodes PE1, PE2, and PE4 arranged in the first direction X, each electrode portion PB extends in the same direction and extends in a direction parallel to the direction D2. In addition, the shapes of the pixel electrodes PE1, PE2, PE3, and PE4 are not limited to the same shape, and the shapes and areas of the pixel electrodes PE1, PE2, PE3, and PE4 may also be different.

[0087] like Figure 7 As shown, the detection electrode CE includes a main detection electrode CEP, and sub-detection electrodes CEA and CEB. Figure 1 ) is formed on substantially the entire area of ​​the first pixel PX1. That is, the first pixel PX1 has pixel electrodes PE1, PE2, PE3, and the main detection electrode CEP (detection electrode CE) is provided in the area overlapping with the pixel electrodes PE1, PE2, PE3. Alternatively, the second pixel PX2 has pixel electrodes PE1, PE2, PE4, and the main detection electrode CEP (detection electrode CE) is provided in the area overlapping with the pixel electrodes PE1, PE2, PE4.

[0088] In the following description, the structure of the first pixel PX1 is described, and the repeated description of the second pixel PX2 is omitted. In a plan view, the main detection electrode CEP overlaps with the pixel electrodes PE1, PE2, PE3, the signal lines S1, S2, S3, the drive signal supply wirings TL1, TL2 and the third dummy wiring TLD3, and does not overlap with the scanning lines G1, G2, G3.

[0089] like Figure 7 As shown, the sub-detection electrode CEA extends in the second direction Y to electrically connect the adjacent main detection electrodes CEP in the second direction Y. In a top view, the sub-detection electrode CEA overlaps with the scan lines G1, G2, G3, the signal lines S2, S5, and the drive signal supply wiring TL2, and does not overlap with the pixel electrodes PE1, PE2, PE3, the signal lines S1, S3, S4, S6, the drive signal supply wiring TL1, TL2, and the third dummy wiring TLD3. When there is no sub-detection electrode CEA between the adjacent main detection electrodes CEP in the second direction Y, a slit SPB is formed (refer to Figure 2 ).

[0090] The sub-detection electrode CEB extends in the first direction X and electrically connects the main detection electrodes CEP adjacent to each other in the first direction X. A slit SPA is formed in the region between the main detection electrode CEP and the sub-detection electrode CEB adjacent to each other in the first direction X. The slit SPA is formed overlapping the signal lines S1 and S4 connected to the first sub-pixel SPX1 and the drive signal supply wiring TL1. When there is no sub-detection electrode CEB between the main detection electrodes CEP adjacent to each other in the first direction X, a slit SPB is formed (see Figure 2 ).

[0091] In a plan view, the sub-detection electrode CEB overlaps with the signal line S1, the drive signal supply wiring TL1, and the widened portion TC, and does not overlap with the pixel electrodes PE1, PE2, PE3, the scanning lines G1, G2, G3, the signal lines S2, S3, the drive signal supply wiring TL2, and the third dummy wiring TLD3. By forming the slit SPA, the difference in visibility of the slit SPB between the detection electrodes CE adjacent to each other in the first direction X can be reduced, and the parasitic capacitance generated between the detection electrode CE and the drive signal supply wiring TL1 can be reduced.

[0092] As described above, the detection electrode CE has a main detection electrode CEP and sub-detection electrodes CEA and CEB. The main detection electrode CEP is island-shaped. The main detection electrodes CEP adjacent to each other in the first direction X or the second direction Y are electrically connected through the sub-detection electrodes CEA or CEB. As a result, the detection electrode CE can have an area of ​​any size. The main detection electrode CEP is arranged in each pixel PX (each first pixel PX1 and second pixel PX2), and the slit SPA is arranged at a position overlapping with the drive signal supply wiring TL1 and the signal line S1. The same potential as that of the detection electrode CE is supplied to the drive signal supply wiring TL1 and the first dummy wiring TLD1 overlapping with the slit SPA. Thus, in the present embodiment, compared with the case where the slit SPA is arranged at a position overlapping with the second dummy wiring TLD2 or the third dummy wiring TLD3 in a floating state, the leakage electric field from the signal line SL can be suppressed by the drive signal supply wiring TL1 and the first dummy wiring TLD1. Therefore, the degradation of image quality caused by the leakage electric field from the signal line SL can be suppressed.

[0093] like Figure 8 As shown, the plurality of drive signal supply wirings TL1 and TL2 overlap the signal lines S1 and S2 respectively in a plan view and extend in parallel with the signal lines S1 and S2. The drive signal supply wirings TL1 and TL2 do not overlap the signal line S3. The drive signal supply wirings TL1 and TL2 are respectively provided with widened portions TC, and the contact holes CH are provided so as to overlap the widened portions TC.

[0094] The third dummy wiring TLD3 overlaps with the signal line S3 when viewed from above, and extends in parallel with the signal line S3. The third dummy wiring TLD3 is provided with a slit SPL for each pixel PX arranged in the second direction Y. The dummy contact hole CHD is provided overlapping with the slit SPL. In other words, the third dummy wiring TLD3 is arranged in a separated manner in the second direction Y, and the dummy contact hole CHD overlaps with the signal line S3 and is formed between the third dummy wirings TLD3 adjacent to each other in the second direction Y. The slit SPL and the dummy contact hole CHD are arranged side by side with the widening portion TC and the contact hole CH in the first direction X. In addition, the dummy contact hole CHD is provided on the signal line S3 adjacent to the pixel electrode PE3 (the third sub-pixel SPX3), but is not provided on the signal line S3 adjacent to the pixel electrode PE4 (the fourth sub-pixel SPX4).

[0095] In addition, similarly to the plurality of drive signal supply wirings TL1 and TL2, Figure 6 The first dummy wiring TLD1 and the second dummy wiring TLD2 shown overlap with the signal lines S1 and S2, respectively, and extend in parallel with the signal lines S1 and S2. Fig.15 Schematic diagram showing a first dummy wiring TLD1 and a second dummy wiring TLD2 .

[0096] As described above, the drive signal supply wirings TL1 and TL2 are respectively provided to overlap with the signal lines S1 and S2, and are provided to not overlap with the signal line S3. In addition, the third dummy wiring TLD3 is provided to overlap with the signal line S3 and is in a floating state. Thus, compared with a structure in which the drive signal supply wiring TL is provided to overlap with the signal line S3, the parasitic capacitance Csc formed on the signal line S3 (third signal line) connected to the third sub-pixel SPX3 and the fourth sub-pixel SPX4 can be effectively reduced (refer to Figure 4 ).

[0097] More specifically, in a structure in which a drive signal supply wiring TL is provided overlapping with the signal line S3, a parasitic capacitance Csc formed on the signal line S3 includes a capacitance formed between the signal line S3 and the drive signal supply wiring TL. In the present embodiment, since a third dummy wiring TLD3 in a floating state is provided overlapping with the signal line S3, a parasitic capacitance Csc formed on the signal line S3 includes a capacitance obtained by connecting in series a capacitance formed between the signal line S3 and the third dummy wiring TLD3 and a capacitance formed between the third dummy wiring TLD3 and the detection electrode CE. Therefore, by providing the third dummy wiring TLD3, the parasitic capacitance Csc can be suppressed. As a result, the display device PNL of the present embodiment can reduce the time constant of the detection electrode CE and the drive signal supply wiring TL, suppress the potential difference of the crosstalk component, and suppress the reduction of the display quality.

[0098] like Fig. 9 As shown, the array substrate SUB1 uses a first insulating substrate 10 having light transmittance such as a glass substrate or a resin substrate as a base. The array substrate SUB1 has insulating films 11, 12, 13, a first organic insulating film 14 (first insulating film), a second organic insulating film 15 (second insulating film), an insulating film 16, signal lines S1, S2, S3, pixel electrodes PE1, PE2, PE3, detection electrodes CE, a first alignment film AL1, etc. on the side opposite to the counter substrate SUB2 of the first insulating substrate 10. In the following description, the direction from the array substrate SUB1 toward the counter substrate SUB2 is referred to as the upper side or simply as the upper side.

[0099] The insulating film 11 is located on the first insulating substrate 10. The insulating film 12 is located on the insulating film 11. The insulating film 13 is located on the insulating film 12. The signal lines S1, S2, and S3 are located on the insulating film 13. The first organic insulating film 14 is located on the insulating film 13 and covers the signal lines S1, S2, and S3.

[0100] The drive signal supply wirings TL1, TL2 and the third dummy wiring TLD3 are located on the first organic insulating film 4. The drive signal supply wirings TL1, TL2 and the third dummy wiring TLD3 are formed of a metal material including any one of Al, Mo and W. The resistance of the drive signal supply wirings TL1, TL2 and the third dummy wiring TLD3 is lower than the resistance of the detection electrode CE and has conductivity. In addition, the drive signal supply wirings TL1, TL2 and the third dummy wiring TLD3 are opposite to the signal lines S1, S2 and S3 via the first insulating film 14. That is, the drive signal supply wirings TL1, TL2 and the third dummy wiring TLD3 overlap on the signal lines S1, S2 and S3.

[0101] In addition, regarding Fig. 9 The first dummy wiring TLD1 and the second dummy wiring TLD2 not shown are also located on the first organic insulating film 14 in the same layer as the third dummy wiring TLD3. The first dummy wiring TLD1 and the second dummy wiring TLD2 are opposed to the signal lines S1 and S2 via the first organic insulating film 14.

[0102] The second organic insulating film 15 is provided on the first organic insulating film 14, and the drive signal supply wirings TL1, TL2 and the third dummy wiring TLD3 are covered by the second organic insulating film 15. The insulating films 11, 12, 13 and the insulating film 16 are formed of, for example, inorganic materials having light transmittance such as silicon oxide and silicon nitride. The first organic insulating film 14 and the second organic insulating film 15 are formed of resin materials having light transmittance such as acrylic resin, and have a thicker film thickness than other insulating films formed of inorganic materials. For example, the first organic insulating film 14 is greater than 2 μm and less than 3 μm. The second organic insulating film 15 is greater than 1 μm and less than 2 μm. The first organic insulating film 14 is formed thicker than the second organic insulating film 15.

[0103] The detection electrode CE is located on the second organic insulating film 15. Fig. 9 In the embodiment, the detection electrode CE faces the drive signal supply wirings TL1 and TL2 via the second organic insulating film 15 . The slit SPA of the detection electrode CE is located right above the drive signal supply wiring TL1 . The detection electrode CE is covered by the insulating film 16 .

[0104] The pixel electrode PE is located on the insulating film 16 and faces the detection electrode CE via the insulating film 16. The pixel electrode PE and the detection electrode CE are formed of a light-transmitting conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The pixel electrode PE is covered by the first alignment film AL1. The first alignment film AL1 also covers the insulating film 16.

[0105] The counter substrate SUB2 has a second light-transmissive insulating substrate 20 such as a glass substrate or a resin substrate as a base. The counter substrate SUB2 includes a light shielding layer BM, color filters CFR, CFG, CFB, an overcoat layer OC, a second alignment film AL2, etc. on the side of the second insulating substrate 20 facing the array substrate SUB1.

[0106] like Fig. 9 As shown, the light shielding layer BM is located on the side opposite to the array substrate SUB1 of the second insulating substrate 20. Moreover, the light shielding layer BM defines openings opposite to the pixel electrodes PE1, PE2, and PE3 respectively. The light shielding portion BM is formed of a black resin material or a light shielding metal material.

[0107] The color filters CFR, CFG, and CFB are respectively located on the side of the second insulating substrate 20 opposite to the array substrate SUB1, and each end overlaps with the light shielding layer BM. The color filter CFR is opposite to the pixel electrode PE1. The color filter CFG is opposite to the pixel electrode PE2. The color filter CFB is opposite to the pixel electrode PE3. In one example, the color filters CFR, CFG, and CFB are formed of resin materials colored in blue, red, and green, respectively.

[0108] The overcoat layer OC covers the color filters CFR, CFG, and CFB. The overcoat layer OC is formed of a light-transmitting resin material. The second alignment film AL2 covers the overcoat layer OC. The first alignment film AL1 and the second alignment film AL2 are formed of, for example, a material exhibiting horizontal alignment.

[0109] In addition, the light shielding layer BM may be formed between any one of the color filters CFR, CFG, and CFB and the overcoat layer OC. Furthermore, the light shielding layer BM may be formed between the overcoat layer OC and the second alignment film AL2.

[0110] As described above, the counter substrate SUB2 includes the light shielding layer BM, the color filters CFR, CFG, CFB, etc. The light shielding layer BM is disposed on Figure 4 The scanning lines G1, G2, G3, the signal lines S1, S2, S3, the contact portion PA, the switching element Tr, etc. shown are located in a region facing the wiring portion.

[0111] exist Fig. 9 In the embodiment, the counter substrate SUB2 has three color filters CFR, CFG, and CFB, but may also have other colors different from blue, red, and green, for example, four or more color filters including white, transparent, yellow, magenta, and cyan. In addition, these color filters CFR, CFG, and CFB may also be provided on the array substrate SUB1.

[0112] The array substrate SUB1 and the counter substrate SUB2 are arranged so that the first alignment film AL1 and the second alignment film AL2 face each other. The liquid crystal layer LC is sealed between the first alignment film AL1 and the second alignment film AL2. The liquid crystal layer LC is composed of a negative liquid crystal material with a negative dielectric anisotropy or a positive liquid crystal material with a positive dielectric anisotropy.

[0113] The array substrate SUB1 faces the backlight unit IL, and the counter substrate SUB2 is located on the display surface side. Various structures can be applied to the backlight unit IL, and the detailed structure thereof will be omitted.

[0114] The first optical element OD1 including the first polarizing plate PL1 is arranged on the outer surface of the first insulating substrate 10 or the surface opposite to the backlight unit IL. The second optical element OD2 including the second polarizing plate PL2 is arranged on the outer surface of the second insulating substrate 20 or the surface on the observation position side. The first polarizing axis of the first polarizing plate PL1 and the second polarizing axis of the second polarizing plate PL2 are in a positional relationship of Crossed Nicol, for example, in the XY plane. In addition, the first optical element OD1 and the second optical element OD2 may also include other optical functional elements such as phase difference plates.

[0115] For example, in the case where the liquid crystal layer LC is a negative liquid crystal material, in the state where no voltage is applied to the liquid crystal layer LC, the liquid crystal molecules LM are initially oriented in the XY plane with their long axes along the first direction X. On the other hand, in the state where a voltage is applied to the liquid crystal layer LC, that is, when an electric field is formed between the pixel electrode PE and the detection electrode CE, the liquid crystal molecules LM are affected by the electric field and their orientation state changes. When turned on, the polarization state of the incident linear polarization light changes according to the orientation state of the liquid crystal molecules LM when the linear polarization light passes through the liquid crystal layer LC.

[0116] Next, Fig.10 The structure of the switching elements Tr1, Tr2, and Tr3 shown in the figure is described in more detail. In addition, the switching elements Tr1, Tr2, and Tr3 described below are top-gate type. The switching elements Tr1, Tr2, and Tr3 may also be bottom-gate type. Fig.10 In the figure, only main parts necessary for explaining the switching elements Tr1, Tr2, Tr3 are shown, and illustration of the detection electrode CE, the pixel electrodes PE1, PE2, PE3, the drive signal supply wirings TL1, TL2, etc. are omitted.

[0117] The switching elements Tr1, Tr2, and Tr3 are arranged side by side in the first direction X. The switching element Tr1 includes a semiconductor layer SC1. The switching element Tr2 includes a semiconductor layer SC2. The switching element Tr3 includes a semiconductor layer SC3. The semiconductor layers SC1, SC2, and SC3 are all formed in a substantially U-shape and intersect the scanning line G2 at two locations. The switching element Tr1 is described below, but the description of the switching element Tr1 can also be applied to the switching elements Tr2 and Tr3.

[0118] In the switching element Tr1, the semiconductor layer SC1 has a first portion E11 at one end and a second portion E12 at the other end. The first portion E11 is electrically connected to the signal line S1 via the contact hole CH11. The second portion E12 is electrically connected to the pixel electrode PE1 (see FIG. 1 ) via the contact hole CH12. Figure 8 )Electrical connection.

[0119] In the scanning line G2 , two portions intersecting the semiconductor layer SC1 are gate electrodes WG11 and WG12 .

[0120] like Figure 8 as well as Fig.10 As shown, in this embodiment, in each sub-pixel SPX, the pixel electrode PE is electrically connected to the signal line SL located on the left side of each sub-pixel SPX via the switching element Tr. In addition, at the boundary of the pixel PX composed of three sub-pixels SPX, signal lines S1 and S4 (first signal lines) connected to the first sub-pixel SPX1 are arranged.

[0121] Next, the cross-sectional structures of the contact hole CH and the dummy contact hole CHD will be described. Fig.11 It is a cross-sectional view for explaining a contact hole. Fig.12 It is a cross-sectional view for explaining a dummy contact hole.

[0122] like Fig.11 As shown, a first organic insulating film 14, a drive signal supply wiring TL, and a second organic insulating film 15 are sequentially stacked on the signal line SL. In other words, the drive signal supply wiring TL is provided between the first organic insulating film 14 and the second organic insulating film 15. In the second organic insulating film 15, a contact hole CH is provided at a position overlapping with the widened portion TC of the drive signal supply wiring TL. The contact hole CH is formed by passing through the second organic insulating film 15, and has the widened portion TC of the drive signal supply wiring TL as the bottom surface. The detection electrode CE is provided on the second organic insulating film 15, and contacts with the widened portion TC of the drive signal supply wiring TL at the bottom surface of the contact hole CH. In this way, the drive signal supply wiring TL is connected to the detection electrode CE via the contact hole CH provided in the second organic insulating film 15 in the area overlapping with the signal line SL (signal line S1). In addition, the first alignment film AL1 covers the insulating film 16 and also exists inside the contact hole CH.

[0123] exist Fig.11 In the above description, the cross-sectional structure of the contact portion between the detection electrode CE and the drive signal supply wiring TL is described. However, the cross-sectional structure of the contact hole CH connecting the detection electrode CE and the first dummy wiring TLD1 is also described. Fig.11 It's the same.

[0124] like Fig.12 As shown, in the region where the dummy contact hole CHD is provided, the third dummy wiring TLD3 is not provided on the first organic insulating film 14. As described above, in the slit SPL (refer to Figure 8) is provided in the area of ​​the dummy contact hole CHD. The dummy contact hole CHD is formed by penetrating the second organic insulating film 15 in the area overlapping with the signal line S3, and has the first organic insulating film 14 as the bottom surface. The detection electrode CE is provided on the second organic insulating film 15, and contacts the first organic insulating film 14 at the bottom surface of the dummy contact hole CHD. In other words, the detection electrode CE is formed to cover the dummy contact hole CHD, and is not connected to the metal wiring such as the third dummy wiring TLD3. In addition, the first alignment film AL1 covers the insulating film 16, and also exists inside the dummy contact hole CHD. By forming the dummy contact hole CHD, the uneven coating of the first alignment film AL1 in the display area DA is suppressed, which helps to make the film thickness of the first alignment film AL1 uniform.

[0125] As described above, the display device PNL of the present embodiment includes: a plurality of first sub-pixels SPX1, a plurality of second sub-pixels SPX2, a plurality of third sub-pixels SPX3, and a plurality of fourth sub-pixels SPX4, wherein the plurality of first sub-pixels SPX1 display red, the plurality of second sub-pixels SPX2 display green, the plurality of third sub-pixels SPX3 display blue, and the plurality of fourth sub-pixels SPX4 display white; a first signal line (signal line S1), a second signal line (signal line S2), and a third signal line (signal line S3), wherein the first signal line (signal line S1) is connected to the plurality of first sub-pixels SPX1. , the second signal line (signal line S2) is connected to the plurality of second sub-pixels SPX2, the third signal line (signal line S3) is connected to the plurality of third sub-pixels SPX3 and the plurality of fourth sub-pixels SPX4; a plurality of detection electrodes CE, the plurality of detection electrodes CE are arranged in a matrix, and are respectively overlapped with the plurality of first sub-pixels SPX1, the plurality of second sub-pixels SPX2, the plurality of third sub-pixels SPX3 and the plurality of fourth sub-pixels SPX4; and a drive signal supply wiring TL, the drive signal supply wiring TL is respectively connected to the plurality of detection electrodes CE, and supply drive signals to the plurality of detection electrodes CE. The drive signal supply wiring TL is overlapped with at least one of the first signal line and the second signal line, and is not overlapped with the third signal line.

[0126] In addition, the display device PNL includes a first dummy wiring TLD1 provided to overlap with the first signal line and a second dummy wiring TLD2 provided to overlap with the second signal line. The first signal line, the second signal line, and the third signal line are arranged adjacent to each other in a first direction X, and at least one of the first dummy wiring TLD1 and the second dummy wiring TLD2 is arranged adjacent to the drive signal supply wiring TL in a second direction Y intersecting the first direction X. In addition, the display device PNL includes a third dummy wiring TLD3 provided to overlap with the third signal line, not connected to the detection electrode CE, and in a floating state.

[0127] According to this, compared with the structure in which the drive signal supply wiring TL is provided overlapping with the signal line S3, the parasitic capacitance Csc formed in the third signal line connected to the third sub-pixel SPX3 and the fourth sub-pixel SPX4 can be effectively reduced (refer to Figure 4 As a result, the time constant of the detection electrode CE and the drive signal supply wiring TL can be reduced, the voltage difference of the crosstalk component can be suppressed, and the reduction in display image quality can be suppressed.

[0128] (Second Embodiment)

[0129] Fig.13 It is a plan view for describing a display device according to Embodiment 2. In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0130] In the first embodiment described above, the second dummy wiring TLD2 is described as being in a floating state, but the present invention is not limited thereto. Fig.13 As shown, in the second embodiment, the second dummy wiring TLD2 is electrically connected to the detection electrode CE via the contact hole CH. That is, the first dummy wiring TLD1 and the second dummy wiring TLD2 are electrically connected to the detection electrode CE, and the third dummy wiring TLD3 is in a floating state. The number of contact holes CH provided in the second dummy wiring TLD2 is equal to the number of contact holes CH provided in the drive signal supply wiring TL2. In addition, the number of contact holes CH provided in the second dummy wiring TLD2 is equal to the number of contact holes CH provided in the first dummy wiring TLD1.

[0131] In addition, in the present embodiment, compared with the above-mentioned first embodiment, the third dummy wiring TLD3 adjacent to the first dummy wiring TLD1 and the second dummy wiring TLD2 is different in that the dummy contact hole CHD is not provided. For example, when focusing on the detection electrode CE2, the third dummy wiring TLD3 arranged adjacent to the first dummy wiring TLD1 and the second dummy wiring TLD2 is not provided with a dummy contact hole CHD. In addition, the third dummy wiring TLD3 arranged adjacent to the drive signal supply wirings TL1 and TL2 of the wiring group TLG2 is not provided with a dummy contact hole CHD. In the sub-pixel column overlapping with the wiring groups TLG3 and TLG4 and not provided with the contact hole CH respectively, four dummy contact holes CHD are provided in the third dummy wiring TLD3 arranged adjacent to the drive signal supply wirings TL1 and TL2.

[0132] In this embodiment, the parasitic capacitance of the signal line S2 is increased compared to the case where the second dummy wiring TLD2 is set to a floating state. Even in this case, the third dummy wiring TLD3 is also in a floating state, and the parasitic capacitance Csc of the signal line S3 connected to the third sub-pixel SPX3 and the fourth sub-pixel SPX4 can be suppressed. In addition, in this embodiment, the configuration pattern of the contact hole CH of the drive signal supply wiring TL1 and TL2 and the configuration pattern of the contact hole CH of the first dummy wiring TLD1 and the second dummy wiring TLD2 can be common.

[0133] (Third Embodiment)

[0134] Fig.14 It is a plan view for explaining a display device according to a third embodiment. Fig.15 This is a plan view for explaining a drive signal supply wiring and a dummy wiring in a schematic plan view of a pixel according to the third embodiment. Fig.15 Yes Fig.14 A portion of the region A is shown in an enlarged plan view.

[0135] like Fig.14 as well as Fig.15 As shown, in this embodiment, compared with the above-mentioned first embodiment and second embodiment, the third dummy wiring TLD3 is different. That is, the metal wiring including the drive signal supply wiring TL1, TL2, the first dummy wiring TLD1 and the second dummy wiring TLD2 does not overlap with the signal line S3 (third signal line). In addition, the first dummy wiring TLD1 and the second dummy wiring TLD2 overlap with the signal lines S1 and S2, respectively, and extend in parallel with these signal lines S1 and S2. In addition, the first dummy wiring TLD1 and the second dummy wiring TLD2 are electrically connected to the detection electrode CE via the contact hole CH.

[0136] like Fig.14 As shown, a dummy contact hole CHD is provided in a pixel PX where a contact hole CH is not provided. For example, when focusing on the detection electrode CE2, a dummy contact hole CHD is not provided in a sub-pixel SPX arranged adjacent to the first dummy wiring TLD1 and the second dummy wiring TLD2. In addition, a dummy contact hole CHD is not provided in a sub-pixel SPX arranged adjacent to the drive signal supply wirings TL1 and TL2 of the wiring group TLG2. In a sub-pixel column overlapping with the wiring groups TLG3 and TLG4 and not provided with contact holes CH, four dummy contact holes CHD are provided in a sub-pixel SPX arranged adjacent to the drive signal supply wirings TL1 and TL2. According to such a structure, the deviation of the contact hole CH and the dummy contact hole CHD can be suppressed.

[0137] In the present embodiment, since the third dummy wiring TLD3 is not provided so as to overlap with the signal line S3, the parasitic capacitance Csc formed on the signal line S3 includes the capacitance formed between the signal line S3 and the detection electrode CE. In this case, the distance between the signal line S3 and the detection electrode CE can be increased compared to the distance between the signal line S3 and the drive signal supply wiring TL when the drive signal supply wiring TL is provided so as to overlap with the signal line S3. As a result, in the present embodiment, the parasitic capacitance Csc formed on the signal line S3 can be reduced.

[0138] In addition, a structure in which the second dummy wiring TLD2 is electrically connected to the detection electrode CE via the contact hole CH is shown, but the present invention is not limited thereto. As in the first embodiment, the second dummy wiring TLD2 may also be set to a floating state. In addition, in the sub-pixel SPX adjacent to the first dummy wiring TLD1 and the second dummy wiring TLD2, a dummy contact hole CHD may also be provided to overlap with the signal line S3 as required.

[0139] (Fourth Embodiment)

[0140] Fig.16 It is a plan view for explaining a display device according to a fourth embodiment. Fig.17 This is a plan view for explaining a drive signal supply wiring and a dummy wiring in a schematic plan view of a pixel according to the fourth embodiment. Fig.17 Yes Fig.16 A portion of the region A is shown in an enlarged plan view.

[0141] like Fig.16 as well as Fig.17 As shown, in this embodiment, compared with the above-mentioned embodiment, the number of contact holes CH provided in one drive signal supply wiring TL1 is different from the number of contact holes CH provided in one first dummy wiring TLD1. For example, two contact holes CH are provided in one drive signal supply wiring TL1, and one contact hole CH is provided in one first dummy wiring TLD1. In addition, the second dummy wiring TLD2 is not provided with a contact hole CH, but is in a floating state. That is, in this embodiment, the first dummy wiring TLD1 is electrically connected to the detection electrode CE, and the second dummy wiring TLD2 is in a floating state.

[0142] In addition, the third dummy wiring TLD3 and the dummy contact hole CHD are not provided. That is, in this embodiment, the metal wiring including the drive signal supply wiring TL1, TL2, the first dummy wiring TLD1 and the second dummy wiring TLD2 does not overlap with the signal line S3 (third signal line). The dummy contact hole CHD also does not overlap with the signal line S3 (third signal line).

[0143] According to such a structure, in this embodiment, the number of contact holes CH and dummy contact holes CHD can be reduced compared with the first to third embodiments described above. Fig. 9 As a result, even when the third dummy wiring TLD3 is not provided, the distance between the signal line S3 and the detection electrode CE can be ensured, and the parasitic capacitance Csc formed on the signal line S3 can be suppressed.

[0144] In addition, Figure 6 In the embodiment, one contact hole CH is provided in one first dummy wiring TLD1, but this is only an example and can be changed appropriately. The number of contact holes CH provided in one first dummy wiring TLD1 can be less than the number of contact holes CH provided in one driving signal supply wiring TL1, and for example, more than two contact holes CH can be provided. In addition, the second dummy wiring TLD2 is not limited to the floating state, and one or more contact holes CH can also be provided.

[0145] The structures of the first to fourth embodiments described above may be appropriately changed, or parts of the structures may be appropriately combined. For example, in the first and second embodiments, the third dummy wiring TLD3 may be provided without providing the dummy contact hole CHD.

[0146] The above describes the preferred embodiments of the present invention, but the present invention is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various changes can be made without departing from the scope of the gist of the present invention. Appropriate changes made without departing from the scope of the gist of the present invention also belong to the technical scope of the present invention. At least one of the various omissions, replacements and changes of the constituent elements can be made without departing from the scope of the gist of the above-mentioned embodiments and the modifications.

Claims

1. A display device, characterized in that: have: a plurality of first sub-pixels, a plurality of second sub-pixels, a plurality of third sub-pixels and a plurality of fourth sub-pixels, wherein the plurality of first sub-pixels display red, the plurality of second sub-pixels display green, the plurality of third sub-pixels display blue, and the plurality of fourth sub-pixels display white; a first signal line, a second signal line and a third signal line, wherein the first signal line is connected to the plurality of the first sub-pixels, the second signal line is connected to the plurality of the second sub-pixels, and the third signal line is connected to the plurality of the third sub-pixels and the plurality of the fourth sub-pixels; A plurality of detection electrodes, wherein the plurality of detection electrodes are arranged in a matrix and are respectively disposed to overlap with the plurality of first sub-pixels, the plurality of second sub-pixels, the plurality of third sub-pixels, and the plurality of fourth sub-pixels; as well as a plurality of signal supply wirings, wherein the plurality of signal supply wirings are connected to the plurality of detection electrodes respectively; The signal supply wiring is provided so as to overlap with at least one of the first signal line and the second signal line, and is provided so as not to overlap with the third signal line.

2. The display device according to claim 1, characterized in that The display device comprises: a first dummy wiring, the first dummy wiring being arranged to overlap with the first signal line; as well as a second dummy wiring, the second dummy wiring being provided so as to overlap with the second signal line, The first signal line, the second signal line and the third signal line are arranged adjacent to each other in a first direction, At least one of the first dummy wiring and the second dummy wiring is arranged adjacent to the signal supply wiring in a second direction intersecting the first direction.

3. The display device according to claim 2, characterized in that: The display device includes a third dummy wiring in a floating state, the third dummy wiring being provided so as to overlap with the third signal line and not connected to the detection electrode.

4. The display device according to claim 3, characterized in that: The first dummy wiring is electrically connected to the detection electrode. The second dummy wiring and the third dummy wiring are in a floating state.

5. The display device according to claim 3, characterized in that: The first dummy wiring and the second dummy wiring are electrically connected to the detection electrode. The third dummy wiring is in a floating state.

6. The display device according to claim 3, characterized in that: The first dummy wiring and the second dummy wiring are arranged separately on each of the plurality of detection electrodes. The third dummy wiring is separately arranged in each of the third sub-pixels and the fourth sub-pixels.

7. The display device according to claim 2, characterized in that: The metal wiring including the signal supply wiring, the first dummy wiring, and the second dummy wiring does not overlap with the third signal line, The first dummy wiring and the second dummy wiring are electrically connected to the detection electrode.

8. The display device according to claim 2, characterized in that: The metal wiring including the signal supply wiring, the first dummy wiring, and the second dummy wiring does not overlap with the third signal line, The first dummy wiring is electrically connected to the detection electrode. The second dummy wiring is in a floating state.

9. The display device according to claim 8, characterized in that: The detection electrode is provided on the upper side of the signal supply wiring, the first dummy wiring, and the second dummy wiring via an insulating film. The signal supply wiring and the first dummy wiring are connected to the detection electrode via contact holes provided in the insulating film, respectively. The number of the contact holes provided in one of the signal supply wirings is different from the number of the contact holes provided in one of the first dummy wirings.

10. The display device according to claim 1, characterized in that: The display device comprises: a first insulating film provided on the first signal line, the second signal line, and the third signal line; and a second insulating film, the second insulating film being provided on the first insulating film, The signal supply wiring is provided between the first insulating film and the second insulating film, The detection electrode is disposed on the second insulating film. The signal supply wiring is connected to the detection electrode via a contact hole provided in the second insulating film in a region overlapping at least one of the first signal line and the second signal line. In a region overlapping with the third signal line, a dummy contact hole having the first insulating film as a bottom surface is provided in the second insulating film.

11. The display device according to claim 3, characterized in that: The display device comprises: a first insulating film provided on the first signal line, the second signal line, and the third signal line; and a second insulating film, the second insulating film being provided on the first insulating film, The signal supply wiring is provided between the first insulating film and the second insulating film, The detection electrode is disposed on the second insulating film. The signal supply wiring is connected to the detection electrode via a contact hole provided in the second insulating film in a region overlapping at least one of the first signal line and the second signal line. In a region overlapping with the third signal line, a dummy contact hole having the first insulating film as a bottom surface is provided in the second insulating film, A plurality of the third dummy wirings are arranged separately in the second direction, The dummy contact hole is arranged between a plurality of the third dummy wirings adjacent to each other in the second direction.

12. The display device according to any one of claims 1 to 11, characterized in that: The detection electrode includes a plurality of main detection electrodes and sub-detection electrodes, the plurality of main detection electrodes overlap with a plurality of sub-pixels and are arranged in a first direction, and the sub-detection electrodes connect the main detection electrodes adjacent to each other in the first direction. A slit is provided between the main detection electrodes adjacent to each other in the first direction so as to overlap with the first signal line.

13. A display device, characterized in that: have: a plurality of first sub-pixels, a plurality of second sub-pixels, a plurality of third sub-pixels and a plurality of fourth sub-pixels, wherein the plurality of first sub-pixels display red, the plurality of second sub-pixels display green, the plurality of third sub-pixels display blue, and the plurality of fourth sub-pixels display white; a first signal line, a second signal line and a third signal line, wherein the first signal line is connected to the plurality of the first sub-pixels, the second signal line is connected to the plurality of the second sub-pixels, and the third signal line is connected to the plurality of the third sub-pixels and the plurality of the fourth sub-pixels; a first insulating film, the first insulating film being disposed on the first signal line, the second signal line, and the third signal line; a second insulating film, the second insulating film being disposed on the first insulating film; a signal supply wiring provided between the first insulating film and the second insulating film; as well as a plurality of detection electrodes, wherein the plurality of detection electrodes are disposed on the second insulating film and arranged in a matrix; The signal supply wiring is connected to the detection electrode via a contact hole provided in the second insulating film in a region overlapping at least one of the first signal line and the second signal line. In a region overlapping with the third signal line, a dummy contact hole having the first insulating film as a bottom surface is provided in the second insulating film.

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