Data reading method and device for host performance acceleration mode

Abstract

The present invention relates to a data reading method and device in a host performance acceleration mode, wherein the method is executed by a host end, and comprises: searching a host performance acceleration buffer in a system memory to obtain a logical-physical comparison record associated with a logical block address; issuing a switch command to a flash memory controller, for requesting the flash memory controller to start a host performance acceleration function, but not starting a function to obtain a logical-physical comparison table; issuing a write-multiple-block command to the flash memory controller, for writing a data block to the flash memory controller, the data block including a logical-physical comparison record; and issuing a read-multiple-block command to the flash memory controller, for obtaining data corresponding to the logical-physical comparison record from the flash memory controller. The present invention enables the host end to send a read command with a logical-physical comparison record to the flash memory controller through the setting of a host performance acceleration buffer, for reducing the time and computing resources spent by the flash memory controller on the logical-physical comparison conversion.

Description

Technical Field

[0001] The present invention relates to a storage device, and in particular to a data reading method and device in a host performance acceleration mode. Background Art

[0002] Flash memory is usually divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processing unit (Host) can provide any address to access NOR flash memory on the address pin and obtain the data stored at the address from the data pin of NOR flash memory in a timely manner. In contrast, NAND flash memory is not random access, but serial access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the central processing unit needs to write serial byte values ​​to NAND flash memory to define the type of request command (such as read, write, erase, etc.) and the address used in this command. The address can point to a page (the smallest data block for write operation in flash memory) or a block (the smallest data block for erase operation in flash memory).

[0003] In order to improve the data writing and reading performance of the flash memory module, the device side will perform data writing and reading in parallel with multiple channels. In order to achieve the purpose of parallel processing, a continuous piece of data will be stored in a dispersed manner in the flash memory units connected to multiple channels, and a logical-to-physical mapping table (Logical-to-physical, L2P Mapping Table) is used to record the correspondence between the logical address (managed by the host side) and the physical address (managed by the flash memory controller) of the user data. However, in the storage device of the embedded Multi-Media Controller (embedded Multi-Media Controller, e·MMC), with the rapid increase in device capacity, the length of the logical-to-physical mapping table has also grown exponentially, making the traditional management method executed by the device side unbearable. Even if the use of hierarchical sub-areas to manage the logical-to-physical mapping table can improve the performance of the logical-to-physical mapping conversion, the time spent on the logical-to-physical mapping conversion is still significantly higher than the time (tR) for transferring data from the flash memory array of the flash memory module to the data register of the flash memory controller. Therefore, the present invention proposes a data reading method and device in a host performance acceleration mode, which is used to improve the data reading performance of the storage device of the embedded multimedia card. Summary of the invention

[0004] In view of this, how to alleviate or eliminate the above-mentioned defects in related fields is indeed a problem to be solved.

[0005] The present invention relates to a data reading method in a host performance acceleration mode, which is executed by a host end and comprises: searching a host performance acceleration buffer in a system memory to obtain a logical-physical comparison record associated with a logical block address; issuing a switching command to a flash memory controller to request the flash memory controller to start a host performance acceleration function but not to start a function to obtain a logical-physical comparison table; issuing a write-multi-block command to the flash memory controller to write a data block to the flash memory controller, the data block including the logical-physical comparison record; and issuing a read-multi-block command to the flash memory controller to obtain data corresponding to the logical-physical comparison record from the flash memory controller.

[0006] The present invention also relates to a data reading method in a host performance acceleration mode, which is executed by a flash memory controller and includes: receiving a switching command from a host end, for requesting the flash memory controller to start a host performance acceleration function, but not starting a function of obtaining a logical-physical comparison table; entering a default state according to the switching command; receiving a write multi-block command from the host end during the period of entering the default state; obtaining a logical-physical comparison record from a data block received from the host end according to the write multi-block command, and reading data corresponding to the logical-physical comparison record from the flash memory device; receiving a read multi-block command from the host end during the period of entering the default state; and transmitting data corresponding to the logical-physical comparison record to the host end according to the read multi-block command.

[0007] The present invention also relates to a device for reading data in a host performance acceleration mode, comprising: a host interface; a flash memory interface; and a processing unit. The processing unit receives a switching command from a host end through the host interface, which is used to request the device to start the host performance acceleration function, but not start the acquisition function of the logical-physical comparison table; enters a default state according to the switching command; receives a write-multiple-block command from the host end through the host interface during the period of entering the default state; acquires a logical-physical comparison record from a data block received by the host end through the host interface according to the write-multiple-block command, and reads data corresponding to the logical-physical comparison record from a flash memory device through the flash memory interface; receives a read-multiple-block command from the host end through the host interface during the period of entering the default state; and transmits data corresponding to the logical-physical comparison record to the host end through the host interface according to the read-multiple-block command.

[0008] The host side and the flash memory controller communicate with each other using the embedded multimedia card communication protocol, and each logical-physical comparison records information about the physical address where the data used to store the logical address is actually stored.

[0009] One of the advantages of the above embodiment is that the host performance acceleration buffer can be set as described above to allow the host to send a read command with a logical-physical comparison record to the flash memory controller, thereby reducing the time and computing resources spent by the flash memory controller on logical-physical comparison conversion.

[0010] Other advantages of the present invention will be explained in more detail with reference to the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0012] Figure 1 FIG. 4 is a system architecture diagram of an electronic device according to an embodiment of the present invention.

[0013] Figure 2 FIG. 4 is a schematic diagram of a flash memory device according to an embodiment of the present invention.

[0014] Figure 3 FIG. 4 is a schematic diagram of the association between a high-level lookup table and a logical-physical lookup sub-table according to an embodiment of the present invention.

[0015] Figure 4 FIG. 4 is a schematic diagram of the association between the logical-physical reference subtable and the physical page according to an embodiment of the present invention.

[0016] Figure 5 FIG. 4 is a schematic diagram of establishing and using a host performance acceleration (HPA) cache according to an embodiment of the present invention.

[0017] Figure 6 FIG. 4 is an operation sequence diagram of initializing the HPA buffer according to an embodiment of the present invention.

[0018] Figure 7 and Figure 8 FIG. 4 is an operation sequence diagram of HPA reading according to an embodiment of the present invention.

[0019] Fig. 9 FIG. 4 is an operation sequence diagram of updating the HPA buffer according to an embodiment of the present invention.

[0020] Fig.10 FIG. 4 is a flow chart of a method for executing a switching command according to an embodiment of the present invention.

[0021] Fig.11 The flowchart is a method for executing a write multiple blocks command according to an embodiment of the present invention.

[0022] Among them, the simple description of the symbols in the accompanying drawings is as follows:

[0023] 10: electronic device; 110: host end; 130: flash memory controller; 131: host interface; 132: bus; 134: processing unit; 135: read-only memory; 136: random access memory; 137: register; 139: flash memory interface; 150: flash memory device; 151: interface; 153#0~153#15: NAND flash memory unit; CH#0~CH#3: channel; CE#0~CE#3: start signal; 310: high-level comparison table; 330#0~330#15: L2P Comparison subtable; 400: L2P comparison record; 410: logical block address information; 430: physical block address information; 430-0: logical unit number and physical block number; 430-1: physical page number; 440: physical block; 450: physical page; 450#2: physical segment; 500: HPA cache; 610~655, 711~755, 835~839, 915, 931, 955: operation; S1010~S1060, S1110~S1147: method steps. DETAILED DESCRIPTION

[0024] The embodiments of the present invention will be described below with reference to the accompanying drawings. In these drawings, the same reference numerals represent the same or similar components or method flows.

[0025] It must be understood that the words "comprise", "include" and the like used in this specification are used to indicate the existence of specific technical features, values, method steps, job processing, components and / or assemblies, but do not exclude the addition of more technical features, values, method steps, job processing, components, assemblies, or any combination of the above.

[0026] The words "first", "second", "third", etc. used in the present invention are used to modify the components in the claims, and are not used to indicate a priority order, a prior relationship, or that one component precedes another, or a time sequence when executing method steps. They are only used to distinguish components with the same name.

[0027] It should be understood that when a component is described as being "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, and there may be intervening components. Conversely, when a component is described as being "directly connected" or "directly coupled" to another component, there are no intervening components. Other words used to describe the relationship between components can also be interpreted in a similar manner, such as "between" versus "directly between", or "adjacent" versus "directly adjacent", etc.

[0028] refer to Figure 1. The electronic device 10 includes a host device (also referred to as a host side) 110, a flash memory controller 130, and a flash memory device 150, and the flash memory controller 130 and the flash memory device 150 can be collectively referred to as a device side. The electronic device 10 can be implemented in electronic products such as personal computers, laptop computers (Laptop PCs), tablet computers, mobile phones, digital cameras, and digital video cameras. The host device 110 and the host interface (Host Interface) 131 of the flash memory controller 130 can communicate with each other using an embedded Multi-Media Controller (embedded Multi-Media Controller, e·MMC / eMMC) communication protocol. The flash memory interface 139 of the flash memory controller 130 and the flash memory device 150 can communicate with each other using a double data rate (Double Data Rate, DDR) communication protocol, for example, an open NAND flash interface (Open NAND Flash Interface, ONFI), a double data rate switch (DDR Toggle) or other communication protocols. The flash controller 130 includes a processing unit 134, which can be implemented in a variety of ways, such as using general hardware (e.g., a microcontroller unit, a central processing unit, a multiprocessor with parallel processing capabilities, a graphics processor, or other processors with computing capabilities), and provides the functions described later when executing software and / or firmware instructions. The processing unit 134 receives eMMC commands through the host interface 131 and executes these commands. The flash controller 130 includes a random access memory (Random Access Memory, RAM) 136, which can be implemented as a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM) or a combination of the above two, for configuring space as a data buffer. The random access memory 136 can also store data required during the execution process, such as variables, data tables, etc. The flash controller 130 includes a read-only memory (ReadOnly Memory, ROM) 135, which is used to store program code that needs to be executed when booting. The flash memory interface 139 includes a NAND Flash Controller (NFC) that provides functions required for accessing the flash memory device 150, such as a command serializer (Command Sequencer) and a low-density parity check (LDPC).

[0029] The flash controller 130 includes a register 137 for storing various parameter values. In the eMMC specification (e.g., the eMMC Electrical Standard 5.1 published in July 2014), the register 137 includes a 32-bit Operation Condition Register (OCR), a 128-bit Device IDentification Register (CID Register), a 128-bit Device-Specific Data Register (CSD Register), a 512-byte Extended CSD Register (Ext_CSD Register), etc. The Ext_CSD register defines device properties and selected modes, wherein the most significant 320 bytes are the Properties Segment, which is used to define the capabilities of the device and cannot be modified by the host 110, and the other less significant 192 bytes are the Modes Segment, which defines the settings currently being run by the device. The host 110 can change these modes through a switch command (SWITCH command, CMD6). The eMMC specification reserves several parts in the Ext_CSD register for device manufacturers to use freely to implement the host performance acceleration mode (HPA Mode) function.

[0030] The flash controller 130 may be configured with a bus architecture 132 for coupling components to each other to transfer data, addresses, control signals, etc. These components include a host interface 131, a processing unit 134, a ROM 135, a RAM 136, a register 137, a flash interface 139, etc. In some embodiments, the host interface 131, the processing unit 134, the ROM 135, the RAM 136, the register 137, and the flash interface 139 may be coupled to each other via a single bus. In other embodiments, the flash controller 130 may be configured with a high-speed bus for coupling the processing unit 134, the ROM 135, the RAM 136, and the register 137 to each other, and a low-speed bus for coupling the processing unit 134, the host interface 131, and the flash interface 139 to each other. The bus includes parallel physical lines that connect two or more components in the flash controller 130.

[0031] The flash memory device 150 provides a large amount of storage space, usually hundreds of gigabytes (GB) or even multiple terabytes (TB), for storing a large amount of user data, such as high-resolution pictures, movies, etc. The flash memory device 150 includes a control circuit and a memory array, and the storage cells in the memory array can be configured as single-level cells (SLCs), multiple-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs) or any combination thereof. The processing unit 134 writes user data to a specified address (destination address) in the flash memory device 150 through the flash memory interface 139, and reads user data and a specified portion of the L2P comparison table from a specified address (source address) in the flash memory device 150. The flash memory interface 139 uses a plurality of electronic signals to coordinate the data and command transmission between the flash memory controller 130 and the flash memory device 150, including a data line, a clock signal, and a control signal. The data line can be used to transmit commands, addresses, read and write data; the control signal line can be used to transmit control signals such as chip enable (CE), address latch enable (ALE), command latch enable (CLE), write enable (WE), etc.

[0032] refer to Figure 2 The interface 151 in the flash memory device 150 may include four input / output channels (I / O channels, hereinafter referred to as channels) CH#0 to CH#3, each of which is connected to four NAND flash memory units. For example, channel CH#0 is connected to NAND flash memory units 153#0, 153#4, 153#8, and 153#12. Each NAND flash memory unit may be packaged as an independent chip (die). The flash memory interface 139 may send one of the start signals CE#0 to CE#3 through the interface 151 to start the NAND flash memory units 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11, or 153#12 to 153#15, and then read user data from the started NAND flash memory units in parallel, or write user data to the started NAND flash memory units.

[0033] Since a continuous segment (i.e., a continuous segment of logical block addresses, Logical Block Addresses, LBAs) of data is dispersedly stored in NAND flash memory units connected to multiple channels, the flash memory controller 130 uses a logical-physical mapping table (Logical-block-address to Physical-block-address, L2P Mapping Table) to record the correspondence between the logical address (managed by the host device 110) and the physical address (managed by the flash memory controller 130) of the user data. The L2P mapping table contains multiple records, which store information about which physical address the user data of each logical address is actually stored in, in the order of the logical address. A segment of continuous LBA data can be divided into multiple regions, identified by region numbers, and each region can be divided into multiple sub-regions, identified by sub-region numbers. For example, 128GB of data addressed using LBA can be divided into 16 8GB regions, and each 8GB region can be further divided into 256 32MB sub-regions. In the eMMC specification, each LBA is associated with (or points to) 512 bytes of data. However, since the RAM 136 cannot provide enough space to store the entire L2P lookup table for the processing unit 134 to quickly search for it during future data reading operations, the entire L2P lookup table can be divided into multiple sub-tables based on the division of the local area and the sub-area, and stored in different physical addresses of the non-volatile flash memory device 150, so that in the future data reading operations, it is only necessary to read the corresponding sub-table from the flash memory device 150 to the RAM 136. Figure 3 , the entire L2P mapping table can be divided into sub-tables 330#0 to 330#15. The processing unit 134 also maintains a high-level mapping table (High-level Mapping Table) 310, which includes multiple records and stores the physical address information of the sub-table associated with each LBA segment in the order of logical addresses. For example, the associated sub-table 330#0 for the 0th to 4095th LBA is stored in the 0th physical page in a specific physical block of a specific logical unit number (Logical Unit Number, LUN) (the letter "Z" can represent the number of LUN and physical block), and the associated sub-table 330#1 for the 4096th to 8191th LBA is stored in the 1st physical page in a specific physical block of a specific LUN, and so on. Although Figure 3 Only 16 sub-tables are included, but those skilled in the art can set more sub-tables according to the capacity of the flash memory device 150, and the present invention is not limited thereto.

[0034] In order to match the physical configuration of the flash memory device 150, the flash memory controller 130 can allow a physical block address (PBA) to be associated with (or point to) 4KB, 8KB, or 16KB of data, which is longer than the length of data associated with an LBA in the eMMC specification (512B). Because the length of data associated with LBA and PBA is inconsistent, each record in each subtable contains information about the logical address and the physical address to accurately point out the address in the flash memory device 150. Figure 4 , subtable 330#0 stores addressing information from LBA#0 to LBA#4095 in sequence. Addressing information can be represented by eight bytes: four bytes represent LBA; the other four bytes represent PBA. For example, record 400 associated with LBA#2 in subtable 330#0 stores information of LBA 410 and PBA 430. Two bytes 430-0 in PBA 430 record the logical unit number and the physical block number (Physical Block Number); the other two bytes 430-1 record the physical page number (Physical Page Number). Therefore, the physical address information 400 corresponding to LBA#2 can point to a specific sector (Sector) 450#2 in the physical page 450 of the physical block 440.

[0035] In order to solve the problem that the flash controller 130 spends too much time on logical-physical comparison conversion, the embodiment of the present invention adds a new function of HPA based on the host-device communications architecture of the current eMMC specification. HPA allows the workload of logical-physical comparison conversion that originally required a lot of time to be implemented by the flash controller 130 to be transferred to the host end 110, which can improve the random read performance of short-length data, which can refer to data with a length ranging from 512B to 32KB. Figure 5, the host side 110 configures space in its system memory as the HPA cache 500, which is used to temporarily store the information of the L2P mapping table maintained and managed by the device side. The HPA cache 500 stores multiple L2P mapping records (L2P Mapping Records) received from the device side, and each L2P mapping record records the addressing information corresponding to an LBA. Then, the host side 110 can issue a command carrying the L2P mapping record to the device side to obtain the user data of the specified LBA. The flash memory controller 130 can directly drive the flash memory interface 139 to read the user data of the specified LBA from the flash memory device 150 according to the information in the L2P mapping record, without having to spend time and computing resources to read the corresponding sub-table from the flash memory device 150 and perform logical-physical address conversion before reading the user data of the specified LBA from the flash memory device 150 as before. The establishment and use of the HPA cache 500 can be divided into three stages:

[0036] Phase I (HPA initialization): The host 110 reads the value of register 137 in the flash controller 130 to check whether the eMMC storage device (or device side, including at least the flash controller 130 and the flash device 150) supports the HPA function. If yes, the host 110 configures space in the system memory as the HPA L2P reference table area.

[0037] Phase II (HPA mapping table management): If the eMMC storage device supports the HPA function, the host 110 issues a series of commands to request the flash controller 130 to read the L2P mapping table. In response to this series of commands, the flash controller 130 transmits all or part of the L2P mapping table to the host 110, allowing the host 110 to store the obtained mapping table in the HPA L2P mapping table area (this may be referred to as a mirrored L2P mapping table, Mirrored L2P Mapping Table). When the actual L2P mapping table corresponding to the mirrored L2P mapping table is changed due to data writing, data trimming (Data Trimming), garbage collection (Garbage Collection, GC), wear leveling (Wear Leveling) and other procedures, the flash controller 130 notifies the host 110 that all or a corresponding part of the L2P mapping table in the system memory of the host 110 needs to be updated.

[0038] Phase III (HPA read): The host 110 sends a series of commands with L2P comparison records to the eMMC storage device to request data of a specific LBA (especially discontinuous data of small block length, such as discontinuous data of 512B to 32KB), wherein the L2P comparison record is searched from the mirror L2P comparison table. Then, the flash controller 130 reads the data of the specified LBA from the PBA of the flash device 150 according to the content of the L2P comparison record, and replies the read data to the host 110, so that the eMMC storage device can save the time of reading and searching the L2P comparison table for logical-physical comparison conversion.

[0039] In the eMMC specification, Ext_CSD

[160] (also known as PARTITIONING_SUPPORT

[160] ) defines supported partition features, where Bits[7:3] are reserved for free use by the manufacturer of the eMMC storage device. The third bit (Ext_CSD

[160] , Bit[3]) of the 160th byte of the Ext_CSD register can be used to define whether the eMMC storage device supports the HPA function, which is set to "1" if supported and "0" if disabled. During the initialization of the eMMC storage device, the processing unit 134 can set Ext_CSD

[160] , Bit[3] in the register 137 to "1". Although the embodiment of the present invention describes a technical solution for defining whether the eMMC storage device supports the HPA function by using Ext_CSD

[160] , Bit[3], a person skilled in the art may change the design to use other reserved bits in the Ext_CSD register, such as Ext_CSD[511:506], Ext_CSD[485:309], Ext_CSD

[306] , Ext_CSD

[233] , Ext_CSD

[227] , Ext_CSD

[204] , Ext_CSD

[195] , Ext_CSD

[193] , , Ext_CSD

[190] , Ext_CSD

[188] , Ext_CSD

[186] , Ext_CSD

[184] , Ext_CSD

[182] , Ext_CSD

[180] , Ext_CSD

[176] , Ext_CSD

[172] , Ext_CSD

[170] , Ext_CSD

[135] , Ext_CSD[129:128], Ext_CSD[127:64], Ext_CSD[28:27], Ext_CSD[14:0], etc., but the present invention is not limited thereto.

[0040] In addition, the flash controller 130 may use a pair of Ext_CSD registers to record information of the designated regions and sub-regions that need to be updated in the L2P lookup table cached by the host 110. For example, the 64th byte (Ext_CSD

[64] ) and the 66th byte (Ext_CSD

[66] ) of the Ext_CSD register are a pair, which are used to indicate the 0th region (Region#0) and the 160th sub-region (SubRegion#160), respectively. The 65th byte (Ext_CSD

[65] ) and the 67th byte (Ext_CSD

[67] ) of the Ext_CSD register are another pair, which are used to indicate the 0th region (Region#0) and the 18th sub-region (SubRegion#18), respectively.

[0041] In the eMMC specification, the switch command (CMD6) is issued by the host 110 to switch the operating mode of the selected device or modify the value of the Ext_CSD register, and the 26th to 31st bits (Bits[31:26]) of the parameter are reserved bits. The host 110 can set the 26th bit (CMD6, Bit

[26] ) of CMD6 to indicate whether the HPA function is enabled, and if enabled, it is set to "1", and if disabled, it is set to "0". Although the embodiment of the present invention describes a technical solution that defines whether the HPA function is enabled by CMD6, Bit

[26] , personnel in the relevant technical field can change the design to use other reserved bits in the parameters of CMD6, and the present invention is not limited thereto. The host 110 can set the 27th bit (CMD6, Bit

[27] ) of CMD6 to indicate whether the L2P reference table acquisition function is enabled, and if enabled, it is set to "1", and if disabled, it is set to "0". Although the embodiment of the present invention describes a technical solution for defining whether to start the L2P reference table acquisition function by using CMD6, Bit

[27] , persons skilled in the art may change the design to use other reserved bits in the parameters of CMD6, and the present invention is not limited thereby.

[0042] In the eMMC specification, the set block number command (CMD23) is issued by the host end 110 to indicate the number of blocks of the subsequent package write command, or the number of blocks of the header (Header) of the subsequent package read command. When CMD23 is associated with the subsequent package write command, the 30th bit (Bit

[30] ) in the parameter is set to "0b1", and the 0th to 15th bits (Bits[15:0]) in the parameters of CMD23 are used to indicate the number of blocks. When CMD23 is associated with the subsequent package write command or package read command, the 30th bit (Bit

[30] ) in the parameter is set to "0b1". The 0th to 15th bits (Bits[15:0]) in the parameters of CMD23 are used to indicate the number of blocks.

[0043] In the eMMC specification, the write multiple blocks command (CMD25) is issued by the host 110 to continuously write data blocks to the eMMC storage device until a stop transfer command (STOP_TRANSMISSION Command, CMD12) is issued, or the requested number of data blocks has been written. The host 110 can transmit the information of the specified local and sub-area in the L2P comparison table through CMD23 and CMD25, and request the flash controller 130 to prepare the L2P comparison record for the specified local and sub-area. In addition, the host 110 can transmit the L2P comparison record through CMD23 and CMD25, and request the flash controller 130 to prepare data for future reading. The 0th to 31st bits (Bits[31:0]) in the parameters of CMD25 represent the data address.

[0044] In the eMMC specification, the read multiple blocks command (CMD18) is issued by the host 110 to continuously read data blocks from the eMMC storage device until the requested number of data blocks has been read or interrupted by a stop command (Stop Command). In other words, CMD18 requests the eMMC storage device to transmit the previously specified number of data blocks to the host 110. The 0th to 31st bits (Bits[31:0]) in the parameters of CMD18 represent the data address. The host 110 can request the flash controller 130 to transmit the L2P comparison record of the specified local and sub-area (defined in the previous CMD25) through CMD23 and CMD18. Refer to Figure 4 In the example shown, the length of each L2P comparison record is 8B, so that each data block can carry a maximum of 32 L2P comparison records. In addition, the host 110 can request the flash controller 130 to transmit data corresponding to the L2P comparison record (defined in the previous CMD25) through CMD23 and CMD18.

[0045] In the eMMC specification, a normal response command (R1) is issued by the flash controller 130 to tell the host 110 specific information. The length of R1 is 48 bits, of which the 40th to 45th bits (Bits[45:40]) record the index of the command to be responded to, and the 8th to 39th bits (Bits[39:8]) record the device status (DeviceStatus). When the 31st bit (Bit

[31] ) of R1 is set to "0b1", it means that the address is out of range (ADDRESS_OUT_OF_RANGE). When the 30th bit (Bit

[30] ) of R1 is set to "0b1", it means that the address does not match (ADDRESS_MISALIGN). When the HPA function is enabled but the L2P reference table acquisition function is not enabled, if some PBAs in the L2P reference records carried in CMD25 are invalid, the flash controller 130 may set the 31st bit (Bit

[31] ) and the 30th bit (Bit

[30] ) of R1 used to reply to CMD18 to "0b1", indicating that the L2P reference records cached in the host side 110 need to be updated.

[0046] Regarding the establishment of the HPA L2P comparison table area (also referred to as the HPA buffer) in phases I and II, after the eMMC storage device is initialized, the host 110 reads the L2P comparison table from the device for the first time and stores it in the HPA buffer. Table 1 describes the command sequence details of an example for initializing the HPA buffer:

[0047] Table 1

[0048]

[0049] References Figure 6 The operation sequence diagram of the HPA buffer initialization is shown in detail as follows:

[0050] Operation 611: the host 110 sends a command to the flash memory controller 130 to request the flash memory controller 130 to obtain the value of the Ext_CSD register.

[0051] Operation 613 : In response to the register read command received through the host interface 131 , the processing unit 134 obtains the value of the Ext_CSD register in the register 137 , and replies to the host end 110 through the host interface 131 .

[0052] Operation 615: The host 110 may check the value of the Ext_CSD register (eg, Ext_CSD

[160] , Bit[3]) to determine whether the eMMC storage device supports the HPA function. If yes, the process proceeds to operation 617. If no, the HPA function is not enabled.

[0053] Operation 617: The host 110 issues a switch command (CMD6) to the flash controller 130 to enable the HPA function and the L2P table acquisition function. For example, referring to the second row of Table 1, the host 110 may set the parameter of CMD6 to "0x0C000000", that is, including Bit

[26] ="0b1" and Bit

[27] ="0b1", to instruct the flash controller 130 to enable these two functions.

[0054] Operation 619 : After receiving the switching command as shown above, the flash controller 130 enters the HPA mapping table reading state (HPA_Mapping_READ state) to prepare to transmit a portion of the L2P mapping table to the host 110 .

[0055] Operation 631: The host 110 allocates space in the system memory for the HPA buffer, and determines the local and sub-area L2P comparison records to be obtained from the eMMC storage device according to the needs of the operating system, driver, application, etc.

[0056] Operation 633: The host 110 issues a set block number command (CMD23) to the flash controller 130 to inform the flash controller 130 how many data blocks will be transmitted. For example, referring to the third row of Table 1, the host 110 may set the parameter of CMD23 to "0x40000001", which includes Bit

[30] ="0b1" and Bits[15:0]="0x0001", indicating that a data block will be written to the flash controller 130. Next, the host 110 issues a write multiple blocks command (CMD25) to the flash controller 130 to continuously write data blocks to the flash controller 130 until the requested number of data blocks has been written. For example, referring to the fourth row of Table 1, the host 110 may set the parameter of CMD25 to "0x01E2A3E0", which represents a specific data address. Each data block can be divided into 32 packets, and the length of each packet is 16B. Two bytes in each packet may indicate the number of a specific local region, and the remaining 14 bytes may indicate the numbers of multiple specific sub-regions. For example, when a packet includes information {Region#0, SubRegion#0, SubRegion#1, SubRegion#2, SubRegion#3}, it means that the specified portion of the L2P comparison table is associated with the 0th to 3rd sub-regions in the 0th local region. Next, the host end 110 issues a set block number command (CMD23) to the flash memory controller 130 to notify the flash memory controller 130 of how many data blocks will be received. For example, referring to the fourth row of Table 1, the host end 110 may set the parameter of CMD23 to "0x40000020", that is, including Bit

[30] = "0b1" and Bits[15:0] = "0x0020", indicating that 32 data blocks will be read from the flash memory controller 130, that is, a maximum of 1024 L2P comparison records. Next, the host 110 issues a read multiple blocks command (CMD18) to the flash controller 130, for continuously reading data blocks from the flash controller 130 until the requested number of data blocks have been read. For example, referring to the fifth row of Table 1, the host 110 may set the parameter of CMD18 to "0x01E2A3E0", which represents a specific data address.

[0057] Operation 635: Since the HPA comparison table reading state has been entered, when the flash controller 130 receives the data block corresponding to CMD25 from the host 110, it knows that each packet therein carries the information of the specified part of the L2P comparison table, and can read the requested L2P comparison record from the flash memory device 150 accordingly. In addition, when the flash controller 130 receives CMD18 from the host 110, it knows that it can start to transmit the specified part of the L2P comparison record to the host 110. Since the parameters of CMD18 are set to be the same as the parameters of CMD25, the data transmitted by the flash controller 130 is the specified part of the L2P comparison record read from the flash memory device 150 according to the content of the data block previously written by CMD25.

[0058] Operation 651: Flash controller 130 organizes the requested L2P comparison records into multiple packets in a specified number of data blocks.

[0059] Operation 653: The flash controller 130 continues to transmit the organized data blocks to the host 110 until the specified number of data blocks are transmitted. Then, when receiving the packet read completion information from the host 110, it leaves the HPA table read state and enters the transfer state (Transfer State) of the eMMC specification.

[0060] Operation 655: The host 110 receives the L2P comparison record carried in each packet and stores it in the HPA buffer. After storing the L2P comparison record carried in the last packet, the host 110 sends a send status command (SEND_STATUS command, CMD13) to the flash controller 130, which contains information that the packet read is completed.

[0061] For data reading in Phase III, Table 2 describes the command sequence details of an example for reading data using the HPA function:

[0062] Table 2

[0063]

[0064] References Figure 7 The operation sequence diagram of HPA reading is shown in detail as follows:

[0065] Operation 711: The host end 110 finds that a random read of short-length data is about to be performed.

[0066] Operation 713: The host 110 sends a switch command (CMD6) to the flash controller 130 to enable the HPA function. For example, referring to the second row of Table 2, the host 110 can set the parameter of CMD6 to "0x04000000", that is, including Bit

[26] ="0b1" and Bit

[27] ="0b0", to instruct the flash controller 130 to only enable the HPA function.

[0067] Operation 715: After receiving the switching command as shown above, the flash controller 130 enters the HPA read state (HPA_READ state).

[0068] Operation 731: The host 110 searches the mirror L2P lookup table in the HPA buffer to obtain L2P lookup records corresponding to the plurality of LBAs.

[0069] Operation 733: The host 110 issues a set block number command (CMD23) to the flash controller 130 to inform the flash controller 130 how many data blocks will be transmitted. For example, referring to the third row of Table 2, the host 110 may set the parameter of CMD23 to "0x40000001", which includes Bit

[30] ="0b1" and Bits[15:0]="0x0001", indicating that a data block will be written to the flash controller 130. Next, the host 110 issues a write multiple blocks command (CMD25) to the flash controller 130 to continuously write data blocks to the flash controller 130 until the requested number of data blocks has been written. For example, referring to the fourth row of Table 2, the host 110 may set the parameter of CMD25 to "0x01521182", which represents a specific data address. Each data block can be divided into 32 packets, and the length of each packet is 16B. Each packet is associated with a pair of LBA and PBA information, 8 bytes of which can indicate a specific LBA, and the remaining 8 bytes can indicate a specific PBA. Next, the host end 110 issues a set block number command (CMD23) to the flash memory controller 130 to inform the flash memory controller 130 how many data blocks will be received. For example, referring to the fifth row of Table 2, the host end 110 can set the parameter of CMD23 to "0x40000020", that is, including Bit

[30] = "0b1" and Bits[15:0] = "0x0020", indicating that 32 data blocks will be read from the flash memory controller 130, that is, data of a maximum of 1024 LBAs. Next, the host end 110 issues a read multiple blocks command (CMD18) to the flash memory controller 130 to continuously read data blocks from the flash memory controller 130 until the requested number of data blocks have been read. For example, referring to the sixth row of Table 2, the host end 110 may set the parameter of CMD18 to "0x01521182", which represents a specific data address.

[0070] Operation 735: Since the HPA read state has been entered, when the flash controller 130 receives the data block corresponding to CMD25 from the host 110, it knows that each packet carries information of a pair of LBA and PBA for data reading, and can read the requested data from the flash device 150 accordingly. In addition, when the flash controller 130 receives CMD18 from the host 110, it knows that it can start to transmit the specified data to the host 110. Since the parameters of CMD18 are set to be the same as the parameters of CMD25, the data transmitted by the flash controller 130 is the data of the specified LBA read from the flash device 150 according to the content of the data block previously written by CMD25.

[0071] Operation 751: Flash controller 130 organizes the requested data into multiple packets in a specified number of data blocks.

[0072] Operation 753: The flash controller 130 continues to transmit the organized data blocks to the host 110 until the specified number of data blocks are transmitted. Then, when receiving the packet read completion information from the host 110, it leaves the HPA read state and enters the eMMC specification transmission state.

[0073] Operation 755: The host 110 receives the data carried in each packet and stores it in the data buffer of the system memory. After storing the data carried in the last packet, the host 110 issues a transfer status command (CMD13) to the flash controller 130, which contains information that the packet read is completed.

[0074] Regarding the update of the HPA buffer in Phase II, during the operation of the device, the host 110 may request the flash controller 130 to perform operations such as data writing, data trimming, and block erasing, and the flash controller 130 may actively perform procedures such as garbage collection (GC) and wear leveling (WL), causing part of the content of the L2P comparison table to be changed. Therefore, the content in the HPA buffer (that is, the mirror L2P comparison table) needs to be updated according to the changes in the L2P comparison table. Refer to Figure 8 The operation sequence diagram of HPA reading shown in FIG. 1 is the same as that of operation 711 to 733 and operation 751 to 753. Figure 7 The remaining operations are described in detail as follows:

[0075] Operation 835: Since the HPA read state has been entered, when the flash controller 130 receives the data block corresponding to CMD25 from the host 110, it knows that each packet carries the information of the paired LBA and PBA for a data read, and checks whether the LBA comparison record of the LBA data to be read has been changed (that is, whether it is invalid). If so, the flash controller 130 ignores the information carried in the data block and reads the data from the flash device 150 according to the changed corresponding LBA comparison record. When the flash controller 130 receives CMD18 from the host 110, it knows that it can start to transmit the specified data to the host 110. Since the parameters of CMD18 are set to be the same as the parameters of CMD25, the data transmitted by the flash controller 130 is the data of the specified LBA read from the flash device 150 according to the content of the data block written by the previous CMD25 or the content of the changed corresponding LBA comparison record. In addition, when the LBA comparison record of the LBA data to be read is invalid, the flash memory controller 130 sets the related Ext_CSD register to store the information of the local and sub-areas that need to be updated in the HPA buffer of the host 110 .

[0076] Operation 837: The flash controller 130 sends R1 in reply to CMD18, in which the 31st bit (Bit

[31] ) and the 30th bit (Bit

[30] ) are both set to "0b1", indicating that the mirror L2P reference table in the host side 110 needs to be updated.

[0077] After the host 110 receives the information that the mirror L2P comparison table needs to be updated from the device, the host 110 obtains the information of the local and sub-areas that need to be updated from the device, and reads the L2P comparison record of the specified part of the L2P comparison table from the device accordingly, and updates the corresponding content in the HPA buffer. Table 3 describes the command sequence details of the example, which is used to update the HPA buffer:

[0078] Table 3

[0079]

[0080] References Fig. 9 The operation sequence diagram of the HPA buffer update shown in FIG. 1 , wherein the technical solutions of operations 611, 613, 617, 619, 633, 635, 651 and 653 are the same as those of Figure 6 The remaining operations are described in detail as follows:

[0081] Operation 915: The host 110 obtains the information of the local and sub-areas that need to be updated from the value of the Ext_CSD register (eg, Ext_CSD[67:64]).

[0082] Operation 931 : The host 110 determines the local and sub-area L2P comparison records to be obtained from the eMMC storage device according to the information obtained from the flash controller 130 .

[0083] Operation 955: The host 110 receives the L2P comparison record carried in each packet and updates the corresponding part of the content in the HPA buffer. After updating the L2P comparison record carried in the last packet, the host 110 sends CMD13 to the flash controller 130, which contains the information that the packet reading is completed.

[0084] The execution details of CMD6 in command processing operations 619 and 715 can be found in Fig.10 The method flow chart shown in FIG. 1 is implemented by the processing unit 134 when loading and executing the relevant software or firmware program code, and is further described as follows:

[0085] Step S1010 : A switching command ( CMD6 ) is received from the host end 110 via the host interface 131 .

[0086] Step S1020: Determine whether the reserved bits of CMD6 contain information for starting the HPA function and the L2P table acquisition function. If yes, the process continues with the processing of step S1030. Otherwise, the process continues with the processing of step S1040.

[0087] Step S1030: The information of entering the HPA comparison table reading state is stored in the RAM 136, so as to be used as a basis for determining the current device state when CMD25 is received later.

[0088] Step S1040: Determine whether the reserved bits of CMD6 contain information for starting the HPA function. If yes, the process continues with the processing of step S1050. Otherwise, the process continues with the processing of step S1060.

[0089] Step S1050: The information of entering the HPA reading state is stored in the RAM 136, so as to be used as a basis for determining the current device state when CMD25 is received later.

[0090] Step S1060: Execute a conventional switching procedure, for example, switching the operation mode of the device end, modifying the value of the Ext_CSD register, etc.

[0091] The execution details of CMD25 in command processing operations 635, 735 and 835 can be referred to as follows. Fig.11 The method flow chart shown in FIG. 1 is implemented by the processing unit 134 when loading and executing the relevant software or firmware program code, and is further described as follows:

[0092] Step S1110 : A write multiple blocks command ( CMD25 ) and the following data blocks are received from the host end 110 through the host interface 131 .

[0093] Step S1121: Determine whether to enter the HPA table reading state or the HPA reading state according to the information stored in the RAM 136. If yes, the process continues to further determine in step S1131. Otherwise, the process continues to process in step S1123.

[0094] Step S1123 : Execute a conventional Packed Write Procedure to drive the flash memory interface 139 to write multiple packets of data into the flash memory device 150 .

[0095] Step S1131: Determine whether to enter the HPA table reading state according to the information stored in RAM 136. If yes, the process continues to process step S1133. Otherwise (i.e., entering the HPA reading state), the process continues to determine step S1141.

[0096] Step S1133: driving the flash memory interface 139 to read the L2P comparison record of the specified part in the L2P comparison table from the flash memory device 150 according to the information carried in the data block (ie, the information of the specific part and the specific sub-area).

[0097] Step S1135: Store the L2P comparison record in the multi-packet format as described above to the RAM 136, so that the L2P comparison record can be transmitted to the host end 110 in the multi-packet format after receiving CMD18 in the future.

[0098] Step S1141: Determine whether the LBA comparison record associated with the LBA data to be read has been changed. If yes, the process continues to process step S1145. Otherwise, the process continues to process step S1143.

[0099] Step S1143: drive the flash memory interface 139 to read the data of the designated LBA from the flash memory device 150 according to the information carried in the data block (ie, the information recorded in the L2P comparison).

[0100] Step S1145: drive the flash memory interface 139 to read the data of the designated LBA from the flash memory device 150 according to the changed corresponding LBA comparison record.

[0101] Step S1147: Store the data of the specified LBA in the multi-packet format as described above to RAM 136, so that the data of the specified LBA can be transmitted to the host end 110 in the multi-packet format after receiving CMD18 in the future.

[0102] All or part of the steps in the method described in the present invention can be implemented by a computer program, such as a firmware translation layer (Firmware Translation Layer, FTL) in a storage device, a driver for a specific hardware, or a software program. In addition, it can also be implemented in other types of programs as shown above. A technician in the relevant technical field can write the method of the embodiment of the present invention into a program code, which will not be described for simplicity. The computer program implemented according to the method of the embodiment of the present invention can be stored in an appropriate computer-readable storage medium, such as a DVD, CD-ROM, USB flash drive, hard disk, or can be placed in a network server that can be accessed through a network (e.g., the Internet, or other appropriate media).

[0103] Although Figure 1 to Figure 2 The above-described components are included, but it does not exclude the use of more additional components to achieve better technical effects without violating the spirit of the invention. Fig.10 , Fig.11 The flowchart is executed in a specified order, but without violating the spirit of the invention, a person skilled in the art can modify the order of these steps while achieving the same effect, so the present invention is not limited to using only the order described above. In addition, a person skilled in the art can also integrate several steps into one step, or execute more steps sequentially or in parallel in addition to these steps, and the present invention should not be limited thereto.

[0104] The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person familiar with this technology can make further improvements and changes on this basis without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims of this application.

Claims

1. A data reading method in a host performance acceleration mode, executed by a host, characterized in that: Include: Searching the host performance acceleration buffer in the system memory to obtain a first logical-physical comparison record associated with the logical block address; issuing a first switching command to the flash memory controller, for requesting the flash memory controller to start a host performance acceleration function but not start a logical-physical comparison table acquisition function, wherein the host end and the flash memory controller communicate with each other through an embedded multimedia card communication protocol; issuing a first write multiple blocks command to the flash memory controller, for writing a first data block to the flash memory controller, wherein the first data block includes the first logical-physical comparison record, wherein the first logical-physical comparison record is used to store information about a physical address where data at a logical address is actually stored; and A first read multiple blocks command is issued to the flash memory controller to obtain data corresponding to the first logical-physical comparison record from the flash memory controller.

2. The data reading method in the host performance acceleration mode as claimed in claim 1, characterized in that: The first logical-physical comparison record includes a logical block address and a physical block address, the logical block address is associated with data of a first length, the physical block address is associated with data of a second length, and the second length is greater than the first length.

3. The data reading method in the host performance acceleration mode as claimed in claim 2, characterized in that: The first length is 512 bytes.

4. The data reading method in the host performance acceleration mode as claimed in claim 1, characterized in that: Also includes: receiving a normal reply command corresponding to the first read multiple blocks command from the flash memory controller, indicating that the content in the host performance acceleration buffer needs to be updated; After receiving the normal reply command, obtaining information of a portion to be updated in the host performance acceleration buffer from the flash memory controller; issuing a second switching command to the flash memory controller, for requesting the flash memory controller to start the host performance acceleration function and the acquisition function of the logical-physical comparison table; issuing a second write multiple blocks command to the flash memory controller, for writing a second data block to the flash memory controller, wherein the second data block includes a local number and a sub-area number of a portion to be updated; issuing a second read multiple block command to the flash memory controller, for obtaining a plurality of second logical-physical comparison records corresponding to the local number and the sub-area number from the flash memory controller; and The corresponding portion of the content in the host performance acceleration buffer is updated as the second logical-physical comparison record.

5. A data reading method in a host performance acceleration mode, executed by a flash memory controller, characterized in that: Include: receiving a switching command from a host end, for requesting the flash memory controller to start a host performance acceleration function but not start a logical-physical comparison table acquisition function, wherein the host end and the flash memory controller communicate with each other via an embedded multimedia card communication protocol; Entering a state according to the switching command; receiving a write multiple blocks command from the host during entering the state; Obtaining a logical-physical comparison record from the data block received from the host end according to the write multiple blocks command, and reading data corresponding to the logical-physical comparison record from the flash memory device, wherein the logical-physical comparison record is used to store information about the physical address where the data of the logical address is actually stored; receiving a read multiple blocks command from the host during entering the state; and The data corresponding to the logical-physical comparison record is transmitted to the host end according to the read multiple blocks command.

6. The data reading method in the host performance acceleration mode as claimed in claim 5, characterized in that: The first reserved bit in the switching command includes information for starting the host performance acceleration function, and the second reserved bit in the switching command includes information for not starting the acquisition function of the logical-physical comparison table.

7. The data reading method in the host performance acceleration mode as claimed in claim 5, characterized in that: Also includes: When it is detected that the logical-physical comparison record is invalid, a normal reply command corresponding to the read multiple blocks command is sent, indicating that the content in the host performance acceleration buffer in the system memory needs to be updated.

8. The data reading method in the host performance acceleration mode as claimed in claim 5, characterized in that: The write multiple blocks command is used to allow the host to continuously write data blocks to the flash memory controller until a default number of data blocks have been written.

9. The data reading method in the host performance acceleration mode as claimed in claim 5, characterized in that: The read multiple blocks command is used to allow the host to continuously read data blocks from the flash memory controller until a default number of data blocks have been read.

10. A data reading device in a host performance acceleration mode, characterized in that: Include: A host interface, coupled to a host end; A flash memory interface coupled to a flash memory device; as well as A processing unit is coupled to the host interface and the flash memory interface, and receives a switching command from the host end through the host interface to request the device to start the host performance acceleration function, but not to start the acquisition function of the logical-physical comparison table, wherein the host end and the device communicate with each other through the embedded multimedia card communication protocol; enters a state according to the switching command; receives a write multi-block command from the host end through the host interface during the entry into the state; obtains a logical-physical comparison record from the data block received by the host end through the host interface according to the write multi-block command, and reads data corresponding to the logical-physical comparison record from the flash memory device through the flash memory interface, wherein the logical-physical comparison record is used to store information on the physical address where the data of the logical address is actually stored; receives a read multi-block command from the host end through the host interface during the entry into the state; and transmits the data corresponding to the logical-physical comparison record to the host end through the host interface according to the read multi-block command.

11. The data reading device in the host performance acceleration mode as claimed in claim 10, characterized in that: The first reserved bit in the switching command includes information for starting the host performance acceleration function, and the second reserved bit in the switching command includes information for not starting the acquisition function of the logical-physical comparison table.

12. The data reading device in the host performance acceleration mode as claimed in claim 10, characterized in that: The logical-physical comparison record includes a logical block address and a physical block address, wherein the logical block address is associated with data of a first length, and the physical block address is associated with data of a second length, wherein the second length is greater than the first length.

13. The data reading device in the host performance acceleration mode as claimed in claim 12, characterized in that: The first length is 512 bytes.

14. The data reading device in the host performance acceleration mode as claimed in claim 10, characterized in that: When the processing unit detects that the logical-physical comparison record is invalid, it sends a normal reply command corresponding to the read multiple blocks command through the host interface, indicating that the content in the host performance acceleration buffer in the system memory needs to be updated.

15. The data reading device in the host performance acceleration mode as claimed in claim 10, characterized in that: The write multiple blocks command is used to allow the host to continuously write data blocks to the device until a default number of data blocks have been written.

16. The data reading device in the host performance acceleration mode as claimed in claim 10, characterized in that: The read multiple blocks command is used to allow the host to continuously read data blocks from the device until a default number of data blocks have been read.

Images