A method and apparatus for simulating chemical mechanical polishing of a multilevel interconnect structure

Abstract

The application provides a method and device for simulating a chemical mechanical polishing process of a multi-layer interconnection structure. The height of a pattern area at each position of a lower structure of a semiconductor interconnection structure and the height of a blank area of the lower structure are calculated. The difference between the height of the pattern area at each position and the height of the blank area is taken as a height difference of an unevenness representation parameter at each position. The height difference of the unevenness representation parameter is superimposed on a single-layer CMP model to obtain a new model. The new model is used to simulate a chemical mechanical polishing of an upper structure of the semiconductor interconnection structure. Thus, the single-layer CMP model is corrected to obtain the new model. Since the new model considers the superposition effect of the lower structure of the semiconductor interconnection structure on the upper structure, more accurate simulation prediction results of the upper structure can be obtained. The prediction accuracy of the simulation model according to the chemical mechanical polishing is improved. Possible defects in the design stage are avoided. The period from design to manufacturing is shortened. The production yield of the product is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and in particular, to a method and device for simulating a chemical mechanical polishing process of a multi-layer interconnection structure. BACKGROUND

[0002] Chemical mechanical polishing (CMP) process simulation is one of the key technologies in the field of semiconductor structure design for manufacture (DFM), and plays an important role in the entire integrated circuit design and manufacture. In the process of manufacturing semiconductor structures, the chemical mechanical polishing process of semiconductor structures can be guided according to the simulation results of the chemical mechanical polishing process. Therefore, in order to pursue higher product yield, the accuracy of the CMP simulation results is required to be higher.

[0003] At present, many scholars have carried out research on the material removal mechanism of chemical mechanical polishing, and have formed corresponding chemical mechanical polishing simulation models and software tools. In order to balance the calculation rate of simulation and the accuracy of simulation results, the Density-Step-Height (DSH) CMP calculation model proposed by the Boning research group of Massachusetts Institute of Technology is widely used, that is, the DSH CMP model is used to simulate the chemical mechanical polishing process. The DSH CMP model divides the chemical mechanical polishing process into three stages, the first stage is the polishing of large metal blocks, the second stage is the polishing of metal and barrier layers, and the third stage is the polishing of dielectric layers, also known as the over-polishing stage.

[0004] However, many CMP simulation models such as the DSH CMP model are only applicable to the chemical mechanical polishing simulation of single-layer semiconductor structures. If the CMP simulation is performed on a multi-layer semiconductor interconnection structure, for example, a two-layer interconnection structure, in the actual polishing process, the bottom layer structure will have an uneven area, as shown in FIG. 1, a part of the area 101 of the bottom layer structure is recessed. Due to the unevenness of the bottom layer structure, the initial heights of the areas of the upper layer metal are inconsistent, which increases the complexity of the CMP simulation process of the upper layer metal, which is called the stack effect. Since the current single-layer CMP model does not consider the stack effect of the lower layer structure on the upper layer structure, the accuracy of the simulation results may be low. Figure 1

[0005] Therefore, how to further improve the accuracy of the chemical mechanical polishing process simulation and thus improve the yield of the actual process product is a technical problem to be solved in the field. SUMMARY

[0006] ​To solve the above technical problems, the application provides a method and device for simulating a chemical mechanical polishing process of a multi-layer interconnection structure, which can improve the accuracy of the simulation of the chemical mechanical polishing process, and thus improve the product yield of the actual process.

[0007] In a first aspect, the application provides a method for simulating a chemical mechanical polishing process of a multi-layer interconnection structure, comprising:

[0008] calculating the height of a pattern area at each position of a lower structure of the semiconductor interconnection structure and the height of a blank area of the lower structure;

[0009] subtracting the height of the blank area from the height of the pattern area at each position to obtain a height difference of a non-flatness characterization parameter at each position;

[0010] adding the height difference of the non-flatness characterization parameter to a single-layer CMP model to obtain a new model, and using the new model to simulate a chemical mechanical polishing process of an upper structure of the semiconductor interconnection structure.

[0011] Optionally, the adding of the height difference of the non-flatness characterization parameter to the single-layer CMP model to obtain the new model comprises:

[0012] adding the height difference of the non-flatness characterization parameter and the surface height of a corresponding position of the upper structure of the semiconductor interconnection structure to obtain a corrected height, and using the single-layer CMP model including the corrected height as the new model.

[0013] Optionally, the using of the new model to simulate the chemical mechanical polishing process of the upper structure of the semiconductor interconnection structure comprises:

[0014] using the new model to simulate a chemical mechanical polishing process of a bulk copper removal polishing stage;

[0015] using the new model to simulate a chemical mechanical polishing process of a copper and barrier layer polishing stage;

[0016] using the new model to simulate a chemical mechanical polishing process of a copper and dielectric layer polishing stage.

[0017] Optionally, the material of the metal line of the pattern area is copper, the material of the dielectric layer of the blank area is silicon oxide, and the material of the barrier layer of the blank area is silicon nitride.

[0018] Optionally, the lower structure is adjacent to the lower side of the upper structure.

[0019] In a second aspect, the application provides a device for simulating a chemical mechanical polishing process of a multi-layer interconnection structure, comprising:

[0020] The first computing unit is used to calculate the height of the pattern area and the height of the blank area of ​​the lower layer structure of the semiconductor interconnect structure at each position;

[0021] The second calculation unit is used to subtract the height of the blank area from the height of the graphic area at each position, and use the difference as the height difference value of the unevenness characterization parameter at each position.

[0022] The stacking unit is used to stack the height difference of the unevenness characterization parameter onto a single-layer CMP model to obtain a new model, so as to use the new model to perform chemical mechanical polishing simulation on the upper structure of the semiconductor interconnect structure.

[0023] Optionally, the superposition unit includes:

[0024] The correction unit is used to add the height difference of the unevenness characterization parameter and the surface height of the corresponding position of the upper structure of the semiconductor interconnect structure to obtain the corrected height, and to use the single-layer CMP model including the corrected height as the new model.

[0025] Optionally, the step of performing chemical mechanical polishing simulation on the upper structure of the semiconductor interconnect structure using the new model includes:

[0026] The new model was used to simulate the chemical mechanical grinding process of removing bulk copper.

[0027] The new model was used to simulate the chemical mechanical polishing process of copper and the barrier layer.

[0028] The new model was used to simulate the chemical mechanical polishing process of copper and dielectric layers.

[0029] Optionally, the material of the metal lines in the patterned area is copper; the material of the dielectric layer in the blank area is silicon oxide; and the material of the barrier layer in the blank area is silicon nitride.

[0030] Optionally, the lower structure is adjacent to the lower side of the upper structure.

[0031] Compared with the prior art, this application has at least the following advantages:

[0032] This application provides a method and apparatus for simulating chemical mechanical polishing (CMP) processes on multilayer interconnect structures. The method calculates the height of the patterned area and the height of the blank area at each location in the lower layer of the semiconductor interconnect structure. The difference between the height of the patterned area and the height of the blank area at each location is used as the height difference of the unevenness characterization parameter. This height difference is then superimposed onto a single-layer CMP model to obtain a new model. This new model is used to simulate the upper layer of the semiconductor interconnect structure using CMP. This allows for the modification of the single-layer CMP model to obtain a new model. Because the new model considers the stacking effect of the lower layer on the upper layer, it provides more accurate simulation prediction results for the upper layer, improving the prediction accuracy of the CMP simulation model. This helps avoid potential defects during the design phase, shortens the product design-to-manufacturing cycle, and synergistically improves product yield. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 A schematic diagram of a semiconductor interconnect structure provided in an embodiment of this application is shown;

[0035] Figure 2 A schematic diagram of a copper electroplating result provided in an embodiment of this application is shown;

[0036] Figure 3 A flowchart illustrating a method for simulating a chemical mechanical polishing process for a multilayer interconnect structure, as provided in an embodiment of this application, is shown.

[0037] Figure 4 This illustration shows a schematic diagram of the topography of a lower-level structure after CMP (Continuous Mechanical Processing) according to an embodiment of this application.

[0038] Figure 5 This diagram illustrates the morphology of a lower-level structure after CMP (Continuous Mechanical Processing) according to an embodiment of this application.

[0039] Figure 6 A schematic diagram of an apparatus for simulating a chemical mechanical polishing process with a multilayer interconnect structure, as provided in an embodiment of this application, is shown. Detailed Implementation

[0040] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0041] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0042] As described in the background section, chemical mechanical planarization (CMP) process simulation is one of the key technologies in the field of semiconductor structure design for manufacturability (DFM). In the manufacturing of semiconductor structures, the simulation results of the chemical mechanical planarization process can be used to guide the production process of semiconductor structure chemical mechanical planarization. Therefore, in order to improve product yield, the accuracy of the simulation results is particularly important.

[0043] Currently, numerous scholars have conducted mechanistic studies on chemical mechanical polishing (CMP) and completed corresponding CMP simulation models and software tools. To balance the computational speed and accuracy of simulation results, the Density-Step-Height (DSH) CMP model proposed by Boning's research group at MIT is widely used. This model uses the DSH CMP model to simulate the CMP process. The DSH CMP model divides the CMP process into three stages: the first stage is the polishing of bulk metal, the second stage is the polishing of the metal and the barrier layer, and the third stage is the polishing of the dielectric layer, also known as the over-polishing stage.

[0044] However, many CMP simulation models, such as the DSH CMP model, are only suitable for chemical mechanical polishing simulations of single-layer semiconductor structures. For multi-layer semiconductor interconnect structures, taking a two-layer interconnect structure as an example, uneven areas will appear in the bottom layer during the actual polishing process. (See...) Figure 1 As shown, the bottom layer structure exhibits a depression in region 101. If the DSH CMP model is still used to simulate the chemical mechanical polishing (CMP) process on the upper layer structure, the unevenness of the bottom layer structure causes inconsistent initial heights in different regions of the upper metal, which will continue to affect the process flow of the upper layer structure, potentially leading to uneven regions 102 in the upper layer structure as well. The second and third stages of CMP are particularly affected by the stacking effect. Because the current single-layer DSHCMP model does not consider the stacking effect of the lower layer structure on the upper layer structure when performing CMP simulations, the simulation accuracy may be low, resulting in a low yield of products produced in actual manufacturing processes.

[0045] Therefore, improving the accuracy of chemical mechanical polishing (CMP) process simulation, thereby increasing product yield, is a pressing technical problem in this field. To address this issue, this application provides a method and apparatus for simulating CMP processes in multilayer interconnect structures. The method calculates the height of the patterned area and the height of the blank area at each location in the lower layer of the semiconductor interconnect structure. The difference between the height of the patterned area and the height of the blank area at each location is used as the height difference of the unevenness characterization parameter. This height difference is then superimposed onto a single-layer CMP model to obtain a new model. This new model is then used to simulate the upper layer of the semiconductor interconnect structure using CMP. This allows for the modification of the single-layer CMP model to obtain a new model. Because the new model considers the stacking effect of the lower layer on the upper layer of the semiconductor interconnect structure, it provides more accurate simulation prediction results for the upper layer, improving the prediction accuracy of CMP based on the simulation model. This helps avoid potential defects during the design phase, shortens the product design-to-manufacturing cycle, and synergistically improves product yield.

[0046] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0047] Exemplary method

[0048] See Figure 1 As shown, this application embodiment uses a two-layer semiconductor interconnect structure for illustration, which is divided into an upper layer structure and a lower layer structure. It should be noted that this application embodiment does not specifically limit the number of layers in the semiconductor interconnect structure. For semiconductor interconnect structures with more than two layers, the technical solution of this application embodiment can be referred to for simulation. Since the stacking effect only has a significant impact on adjacent layers, when performing chemical mechanical polishing simulation on a multi-layer interconnect structure, only the stacking effect of the lower adjacent layer of the semiconductor structure to be simulated needs to be considered, and there is no need to accumulate the multi-layer stacking effect for calculation.

[0049] In the manufacturing process of the lower layer structure, chemical mechanical polishing (CMP) is the final step. After CMP, subsequent dielectric layer deposition and via processes are performed, followed by the manufacturing process of the upper layer structure. The morphology of the upper layer structure after copper electroplating is shown in the image. Figure 2 As shown, the structural morphology formed after copper electroplating is quite complex due to differences in structural linewidth, spacing, and growth morphology. The gray shaded area in the figure is the metallic copper part, and the white area below is the silicon oxide dielectric layer.

[0050] As described in the background section, the DSH CMP model divides the chemical mechanical polishing process into three stages: the first stage is the polishing of bulk metal, the second stage is the polishing of the metal and the barrier layer, and the third stage is the polishing of the dielectric layer, also known as the over-polishing stage.

[0051] The first stage involves grinding large pieces of metal. Due to the varying initial thickness of the copper, a step difference is created. According to the DSH CMP model calculation principle, this results in different pressures in different areas, leading to different material removal rates. Since the distribution of high and low areas in the pattern does not match the distribution of the metal areas in the layout, an equivalent density parameter, distinct from the structural metal density, is introduced in the first stage. Its specific calculation method is related to the copper electroplating model. As the process progresses, the large copper pieces are continuously ground, and the step difference gradually decreases until the first stage ends.

[0052] In the subsequent second and third stages of polishing, particularly in the polishing of the copper-barrier layer and copper-dielectric layer, the metal density differs from the equivalent density in the first stage. The metal density is the actual layout metal density, i.e., metal linewidth / (metal linewidth + spacing). At the start of the second stage, some areas may still have incomplete copper removal from the first stage. If the polishing is still the copper-copper removal process of the first stage, it will continue to be polished according to the equivalent density of the first stage until the second stage copper-barrier layer polishing and removal stage begins, at which point the calculation will be based on the layout metal density.

[0053] In this embodiment, because the material removal selectivity ratios of the second and third stages are different, the unevenness of the underlying structure is more sensitive. Therefore, a novel method for simulating chemical mechanical polishing processes is proposed, incorporating the stacking effect into the second and third stages. See also Figure 3 The flowchart shown is a simulation of a chemical mechanical polishing process for a multilayer interconnect structure provided in an embodiment of this application, including the following steps:

[0054] S101: Calculate the height of the patterned area and the height of the blank area of ​​the lower layer structure of the semiconductor interconnect structure at each location.

[0055] See Figure 4 As shown, the height of the patterned area and the height of the blank area of ​​the lower layer structure of the semiconductor interconnect structure can be calculated at each location.

[0056] In the actual grinding process, uneven areas will appear in the lower structure. In this embodiment, the uneven area is taken as the recessed area 101 as an example. The gray shaded part in the figure is a metal line, such as a copper wire. The area where it is located is called the pattern area. In the chemical mechanical polishing process, the pattern area is prone to defects such as disc shape and erosion, forming an uneven area. Since the unevenness of different positions of the pattern area is different, it is necessary to calculate the height of the pattern area at each position. Specifically, the height of the pattern area at each position can be calculated according to the layout calculation grid.

[0057] To characterize the unevenness of the underlying structure, it is also necessary to calculate the height (blank) of the blank area of ​​the underlying structure so that the unevenness of the graphic region can be calculated subsequently.

[0058] S102: The difference between the height of the graphic area and the height of the blank area at each position is used as the height difference value, which is the non-flatness characterization parameter at each position.

[0059] In this embodiment of the application, in order to calculate the degree of unevenness of the graphic area, the difference h' obtained by subtracting the height of the blank area from the height of the graphic area at each position can be used as the height difference value of the unevenness characterization parameter at each position.

[0060] That is, h'=Height-Height(blank).

[0061] For example, see Figure 5 As shown, the height of the graphic area at the first position 501 is 'a', the height of the graphic area at the second position 502 is 'b', and the height of the blank area is 'c'. Therefore, the height difference of the unevenness characterization parameter at the first position 501 is h' = ac, and the height difference of the unevenness characterization parameter at the second position 502 is h' = bc. The height difference of the unevenness characterization parameter is used to characterize the degree of unevenness of the uneven region 101.

[0062] S103: The height difference of the non-flatness characterization parameter is superimposed on the single-layer CMP model to obtain a new model, and the new model is used to perform chemical mechanical polishing simulation on the upper structure of the semiconductor interconnect structure.

[0063] In this embodiment, due to the stacking effect between the lower and upper layers of the semiconductor interconnect structure, the single-layer CMP model needs to be modified to account for this effect. The height difference of the unevenness characterization parameter can be superimposed onto the single-layer CMP model to obtain a new model. This new model is then used to simulate the chemical mechanical polishing (CMP) process on the upper layer of the semiconductor interconnect structure. The new model, which incorporates the height difference of the unevenness characterization parameter, considers the stacking effect on the upper layer, thus resulting in higher simulation accuracy.

[0064] Optionally, the height difference of the non-flatness characterization parameter and the surface height of the corresponding position of the upper structure of the semiconductor interconnect structure can be added to obtain the corrected height, and the single-layer CMP model including the corrected height can be used as the new model.

[0065] Therefore, the single-layer CMP model including the modified height is used as the new model. Since the new model takes into account the stacking effect of the lower layer structure on the upper layer structure of the semiconductor interconnect structure, more accurate simulation prediction results can be obtained, thereby helping to improve the product yield of the process manufacturing.

[0066] Optionally, during the CMP simulation of the upper structure, the new model is applied to perform chemical mechanical polishing simulation of the copper-copper material removal stage, the copper and barrier layer polishing stage, and the copper and dielectric layer polishing stage.

[0067] Optionally, the material of the metal lines in the pattern area is copper, the material of the dielectric layer in the blank area is silicon oxide, and the material of the barrier layer in the blank area is silicon nitride. It should be noted that this embodiment does not specifically limit the materials of the metal lines, dielectric layer, and barrier layer; these can be set by those skilled in the art according to actual circumstances.

[0068] Optionally, the lower structure is adjacent to the lower side of the upper structure, and the impact of the unevenness of the lower structure that is not in direct contact with the upper structure does not need to be considered.

[0069] This application provides a method for simulating the chemical mechanical polishing (CMP) process of a multilayer interconnect structure. The method calculates the height of the patterned area and the height of the blank area at each location in the lower layer of the semiconductor interconnect structure. The difference between the height of the patterned area and the height of the blank area at each location is used as the height difference of the unevenness characterization parameter. This height difference is then superimposed onto a single-layer CMP model to obtain a new model. This new model is used to simulate the CMP process of the upper layer of the semiconductor interconnect structure. This allows for the modification of the single-layer CMP model to obtain a new model. Because the new model considers the stacking effect of the lower layer on the upper layer of the semiconductor interconnect structure, it can obtain more accurate simulation prediction results for the upper layer, improving the prediction accuracy of CMP based on the simulation model. This helps avoid potential defects during the design phase, shortens the product design-to-manufacturing cycle, and synergistically improves product yield.

[0070] Exemplary device

[0071] See Figure 6 As shown, an apparatus for simulating a chemical mechanical polishing process provided in an embodiment of this application includes:

[0072] The first calculation unit 601 is used to calculate the height of the pattern area and the height of the blank area of ​​the lower structure of the semiconductor interconnect structure at each position;

[0073] The second calculation unit 602 is used to subtract the height of the blank area from the height of the graphic area at each position, and use the difference as the height difference of the unevenness characterization parameter at each position.

[0074] The superposition unit 603 is used to superimpose the height difference of the unevenness characterization parameter onto a single-layer CMP model to obtain a new model, so as to use the new model to perform chemical mechanical polishing simulation on the upper structure of the semiconductor interconnect structure.

[0075] Optionally, the superposition unit includes:

[0076] The correction unit is used to add the height difference of the unevenness characterization parameter and the surface height of the corresponding position of the upper structure of the semiconductor interconnect structure to obtain the corrected height, and to use the single-layer CMP model including the corrected height as the new model.

[0077] Optionally, the step of performing chemical mechanical polishing simulation on the upper structure of the semiconductor interconnect structure using the new model includes:

[0078] The new model was used to simulate the chemical mechanical grinding process of removing bulk copper.

[0079] The new model was used to simulate the chemical mechanical polishing process of copper and the barrier layer.

[0080] The new model was used to simulate the chemical mechanical polishing process of copper and dielectric layers.

[0081] Optionally, the material of the metal lines in the patterned area is copper; the material of the dielectric layer in the blank area is silicon oxide; and the material of the barrier layer in the blank area is silicon nitride.

[0082] Optionally, the lower structure is adjacent to the lower side of the upper structure.

[0083] This application provides an apparatus for simulating the chemical mechanical polishing (CMP) process of a multilayer interconnect structure. It calculates the height of the patterned area and the height of the blank area at each location in the lower layer of the semiconductor interconnect structure. The difference between the height of the patterned area and the height of the blank area at each location is used as the height difference of the unevenness characterization parameter. This height difference is superimposed onto a single-layer CMP model to obtain a new model. This new model is then used to simulate the CMP process of the upper layer of the semiconductor interconnect structure. This allows for the modification of the single-layer CMP model to obtain a new model. Because the new model considers the stacking effect of the lower layer on the upper layer of the semiconductor interconnect structure, it can obtain more accurate simulation prediction results for the upper layer, improving the prediction accuracy of CMP based on the simulation model. This helps avoid potential defects during the design phase, shortens the product design-to-manufacturing cycle, and synergistically improves product yield.

[0084] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0085] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for simulating a chemical mechanical polishing process with a multilayer interconnect structure, characterized in that, include: The height of the patterned area and the height of the blank area of ​​the lower layer structure of the semiconductor interconnect structure are calculated at each position. The difference between the height of the graphic area and the height of the blank area at each location is used as the height difference parameter representing the unevenness at each location. The height difference of the non-flatness characterization parameter is superimposed on the single-layer CMP model to obtain a new model, and the new model is used to perform chemical mechanical polishing simulation on the upper structure of the semiconductor interconnect structure. The step of superimposing the height difference of the unevenness characterization parameter into a single-layer CMP model to obtain a new model includes: The corrected height is obtained by adding the height difference of the unevenness characterization parameter and the surface height of the corresponding position of the upper structure of the semiconductor interconnect structure. The single-layer CMP model including the corrected height is used as the new model.

2. The method according to claim 1, characterized in that, The process of performing chemical mechanical polishing simulation on the upper structure of the semiconductor interconnect structure using the new model includes: The new model was used to simulate the chemical mechanical grinding process of removing bulk copper. The new model was used to simulate the chemical mechanical polishing process of copper and the barrier layer. The new model was used to simulate the chemical mechanical polishing process of copper and dielectric layers.

3. The method according to claim 2, characterized in that, The material of the metal lines in the patterned area is copper; the material of the dielectric layer in the blank area is silicon oxide; and the material of the barrier layer in the blank area is silicon nitride.

4. The method according to any one of claims 1-3, characterized in that, The lower structure is adjacent to the lower side of the upper structure.

5. An apparatus for simulating a chemical mechanical polishing process with a multilayer interconnected structure, characterized in that, include: The first computing unit is used to calculate the height of the pattern area and the height of the blank area of ​​the lower layer structure of the semiconductor interconnect structure at each position; The second calculation unit is used to subtract the height of the blank area from the height of the graphic area at each position, and use the difference as the height difference value of the unevenness characterization parameter at each position. The stacking unit is used to stack the height difference of the unevenness characterization parameter onto a single-layer CMP model to obtain a new model, so as to use the new model to perform chemical mechanical polishing simulation on the upper structure of the semiconductor interconnect structure; The superposition unit includes: The correction unit is used to add the height difference of the unevenness characterization parameter and the surface height of the corresponding position of the upper structure of the semiconductor interconnect structure to obtain the corrected height, and to use the single-layer CMP model including the corrected height as the new model.

6. The apparatus according to claim 5, characterized in that, The process of performing chemical mechanical polishing simulation on the upper structure of the semiconductor interconnect structure using the new model includes: The new model was used to simulate the chemical mechanical grinding process of removing bulk copper. The new model was used to simulate the chemical mechanical polishing process of copper and the barrier layer. The new model was used to simulate the chemical mechanical polishing process of copper and dielectric layers.

7. The apparatus according to claim 6, characterized in that, The material of the metal lines in the patterned area is copper; the material of the dielectric layer in the blank area is silicon oxide; and the material of the barrier layer in the blank area is silicon nitride.

8. The apparatus according to any one of claims 5-7, characterized in that, The lower structure is adjacent to the lower side of the upper structure.

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