Memory device including page buffer circuit

Abstract

A memory device including a page buffer is provided. The memory device includes an array of memory cells including a plurality of memory cells, and a page buffer circuit including page buffer cells in a first horizontal direction connected to the memory cells via bit lines, and cache latches in the first horizontal direction corresponding to the page buffer cells, wherein each of the page buffer cells includes one or more pass transistors connected to a sense node of the page buffer cell, the sense node electrically connected to a respective bit line. The sense node included in each of the page buffer cells and the combined sense node are electrically connected to each other through the pass transistors.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0089163, filed on July 17, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a storage device, and more specifically, to a page buffer circuit and a storage device including the page buffer circuit. Background Technology

[0004] Recently, the increasing multifunctionality, high performance, and miniaturization of information and communication devices have led to a need for large-capacity and highly integrated storage devices. Storage devices may include page buffer circuitry for storing or outputting data from storage cells, and this page buffer circuitry may include semiconductor devices such as transistors. Due to the increased integration of storage devices necessitates a reduction in the size of the page buffer circuitry and the development of process technologies, the size of the device components included in the page buffer circuitry can be reduced. Consequently, the layout of the wiring connecting the device components may become more complex. Summary of the Invention

[0005] According to one aspect of the present invention, a storage device is provided, comprising: a storage cell array including a plurality of storage cells; and a page buffer circuit including: a plurality of page buffer cells in a first horizontal direction, the plurality of page buffer cells being connected to the storage cells via a plurality of bit lines; and a plurality of cache latches corresponding to the plurality of page buffer cells and connected to a combined sensing node in the first horizontal direction. The storage device is configured to transfer data from the plurality of cache latches to the plurality of page buffer cells or from the plurality of page buffer cells to the plurality of cache latches via the combined sensing node. Each of the plurality of page buffer cells includes one or more channel transistors connected to a sensing node of that page buffer cell, the sensing node being electrically connected to a corresponding bit line. The sensing node of each of the plurality of page buffer cells and the combined sensing node are electrically connected to each other via the channel transistors.

[0006] Further, according to another aspect of the present inventive concept, there is provided a memory device including: a first semiconductor layer including a plurality of memory cells connected to a plurality of bit lines extending in a first horizontal direction; and a second semiconductor layer located in a vertical direction of the first semiconductor layer and including a page buffer circuit, wherein the page buffer circuit includes: a main area including a plurality of page buffer cells in the first horizontal direction; and a cache area adjacent to the main area in the first horizontal direction, the cache area including a plurality of cache latches in the first horizontal direction connected to a combined sense node, wherein each of the plurality of page buffer cells includes a main latch and one or more pass transistors connected to a sense node of the page buffer cell, the sense node electrically connected to a corresponding bit line, and wherein the sense node included in each of the plurality of page buffer cells and the combined sense node are electrically connected to each other through the pass transistors, such that the plurality of page buffer cells are electrically connected to the plurality of cache latches.

[0007] Further, according to another aspect of the present inventive concept, there is provided a memory device including: a memory cell area including a plurality of memory cells and a first metal pad; and a peripheral circuit area including a second metal pad, the peripheral circuit area connected to the memory cell area vertically via the first metal pad and the second metal pad, wherein the peripheral circuit area includes a page buffer circuit including: a plurality of page buffer cells in a first horizontal direction, the plurality of page buffer cells connected to the memory cells via a plurality of bit lines; and a plurality of cache latches in the first horizontal direction, the plurality of cache latches respectively corresponding to the plurality of page buffer cells and connected to a combined sense node, wherein each of the plurality of page buffer cells includes a pass transistor connected to a sense node of the page buffer cell, the sense node electrically connected to a corresponding bit line, and wherein the sense node included in each of the plurality of page buffer cells and the combined sense node are electrically connected to each other through the pass transistor included in the plurality of page buffer cells.

[0008] Further, according to another aspect of the inventive concepts, there is provided a memory device including: a memory cell array including a plurality of first memory cells connected to a plurality of first bit lines extending in a first horizontal direction and a plurality of second memory cells connected to a plurality of second bit lines extending in the first horizontal direction; a page buffer circuit including a plurality of main regions in a second horizontal direction perpendicular to the first horizontal direction and a plurality of cache regions in the second horizontal direction; and a page buffer decoder adjacent to the page buffer circuit in the first horizontal direction, the page buffer decoder configured to generate a decoder output signal corresponding to a number of failed bits from the plurality of first memory cells and the plurality of second memory cells, wherein the plurality of main regions includes: a first main region including a plurality of first page buffer cells in the first horizontal direction, each first page buffer cell connected to the plurality of first memory cells via the plurality of first bit lines, each first page buffer cell including one or more first pass transistors connected to a sense node of the first page buffer cell; and a second main region adjacent to the first main region in the second horizontal direction, the second main region including a plurality of second page buffer cells in the first horizontal direction, each second page buffer cell connected to the plurality of second memory cells via the plurality of second bit lines, each second page buffer cell including one or more second pass transistors connected to a sense node of the second page buffer cell, wherein the plurality of cache regions includes: a first cache region including a plurality of first cache latches in the first horizontal direction and corresponding to the plurality of first page buffer cells, respectively, the plurality of first cache latches connected to a first combined sense node; and a second cache region adjacent to the first cache region in the second horizontal direction, the second cache region including a plurality of second cache latches in the first horizontal direction and corresponding to the plurality of second page buffer cells, respectively, the plurality of second cache latches connected to a second combined sense node, wherein each sense node of each first page buffer cell of the plurality of first page buffer cells and the first combined sense node are electrically connected to each other through the first pass transistors, and wherein each sense node of each second page buffer cell of the plurality of second page buffer cells and the second combined sense node are electrically connected to each other through the second pass transistors.

[0009] In addition, according to another aspect of the present invention, a page buffer circuit is provided, comprising: a plurality of page buffer units; and a plurality of cache latches, the plurality of cache latches being commonly connected to the plurality of page buffer units via a combined sensing node, wherein each of the plurality of page buffer units includes a pair of channel transistors and a sensing node connected to the pair of channel transistors, and wherein each sensing node line included in each of the plurality of page buffer units and the combined sensing node are electrically connected to each other, such that the plurality of page buffer units are electrically connected to the plurality of cache latches. Attached Figure Description

[0010] The embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram of a storage device according to an embodiment of the present invention;

[0012] Figure 2 An embodiment of the invention is illustrated schematically. Figure 1 The structure of the storage device;

[0013] Figure 3 An embodiment of the invention is illustrated schematically. Figure 1 The storage cell array in;

[0014] Figure 4 This is an embodiment of the concept of the present invention. Figure 3 A perspective view of the storage blocks in the memory;

[0015] Figure 5 This is a schematic diagram of the connection between the memory cell array and the page buffer circuit according to an embodiment of the present invention.

[0016] Figure 6 An embodiment of the invention is shown. Figure 1 The page buffer in;

[0017] Figure 7 This is a timing diagram illustrating an example of the voltage level of a pass control signal according to a core operation sequence, based on an embodiment of the present invention.

[0018] Figure 8 This is a timing diagram of another example of the voltage level of the control signal according to the core operation sequence, based on an embodiment of the present invention.

[0019] Figure 9 This is a plan view of a page buffer circuit according to an embodiment of the present invention.

[0020] Figure 10 This is a circuit diagram of a page buffer circuit according to an embodiment of the present invention.

[0021] Figure 11 A page buffer according to an embodiment of the present invention is shown in detail;

[0022] Figure 12 This is a plan view of a page buffer circuit according to an embodiment of the present invention.

[0023] Figure 13 This is a circuit diagram of a page buffer circuit according to an embodiment of the present invention.

[0024] Figure 14 It is a timing diagram of the voltage levels of multiple sensing nodes according to a core operation sequence based on an embodiment of the present invention.

[0025] Figure 15 This is a timing diagram illustrating an example of a data dumping operation of a page buffer circuit according to an embodiment of the present invention.

[0026] Figure 16 This is a circuit diagram of a high-speed buffer unit according to an embodiment of the present invention.

[0027] Figure 17 This is a timing diagram illustrating an example of a data dumping operation of a page buffer circuit according to an embodiment of the present invention.

[0028] Figure 18 This is a timing diagram illustrating an example of a data dumping operation of a page buffer circuit according to an embodiment of the present invention.

[0029] Figure 19 The arrangement of page buffer units and cache units in a page buffer circuit according to an embodiment of the present invention is shown;

[0030] Figure 20 This is a block diagram of a storage device according to an embodiment of the present invention;

[0031] Figure 21 This is a plan view of a page buffer circuit and a page buffer decoder according to an embodiment of the present invention.

[0032] Figure 22 A page buffer circuit and a page buffer decoder according to an embodiment of the present invention are shown;

[0033] Figure 23 A page buffer decoder and a mass bit counter according to an embodiment of the present invention are shown;

[0034] Figure 24This is a graph of the digital output signal of the quality bit counter according to an embodiment of the present invention;

[0035] Figure 25 Multiple page buffers according to embodiments of the present invention are shown;

[0036] Figure 26 A cross-sectional view of a storage device according to an embodiment of the present invention; and

[0037] Figure 27 This is a block diagram illustrating an example of applying a storage device to a solid-state drive (SSD) system according to an embodiment of the present invention. Detailed Implementation

[0038] In the following, embodiments of the inventive concept are described in detail with reference to the accompanying drawings.

[0039] Figure 1 This is a block diagram of a storage device 10 according to an embodiment of the present invention. (Refer to...) Figure 1 The storage device 10 may include a storage cell array 100 and peripheral circuitry 200, and the peripheral circuitry 200 may include a page buffer circuit 210, a control circuit 220, a voltage generator 230, and a row decoder 240. Although in Figure 1 Although not shown in the diagram, the peripheral circuit 200 may also include data input / output circuits, input / output interfaces, etc. Additionally, the peripheral circuit 200 may also include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc.

[0040] The memory cell array 100 can be connected to the page buffer circuit 210 via the bit line BL, and can be connected to the row decoder 240 via the word line WL, the serial select line SSL, and the ground select line GSL. The memory cell array 100 may include a plurality of memory cells, and the plurality of memory cells may include, for example, flash memory cells. Embodiments of the inventive concept will now be described with respect to the case where the plurality of memory cells include NAND flash memory cells. However, the invention is not limited thereto. In some embodiments, the plurality of memory cells may include resistive memory cells such as resistive random access memory (RRAM), phase-change RAM (PRAM), and magnetoresistive RAM (MRAM).

[0041] In an embodiment, the memory cell array 100 may include a three-dimensional (3D) memory cell array, which may include a plurality of NAND strings, and each NAND string may include memory cells respectively connected to word lines WL vertically stacked on a substrate, as shown in reference. Figure 3 and Figure 4Detailed description is provided in U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648, which disclose suitable configurations of 3D memory arrays configured in multiple tiers and where word lines and / or bit lines are shared between tiers, and are incorporated herein by reference. However, the invention is not limited thereto; in some embodiments, the memory cell array 100 may include a two-dimensional (2D) memory cell array, and the 2D memory cell array may include a plurality of NAND strings arranged in the row and column directions.

[0042] The control circuit 220 can program data in the memory cell array 100 based on the command CMD, address ADDR, and control signal CTRL, read data from the memory cell array 100, or output various control signals for erasing data stored in the memory cell array 100, such as the voltage control signal CTRL_vol, row address X-ADDR, and column address Y-ADDR. In this way, the control circuit 220 can control all kinds of operations in the storage device 10.

[0043] Voltage generator 230 can generate various types of voltages for performing programming, reading, and erasing operations in memory cell array 100 based on the voltage control signal CTRL_vol. Voltage generator 230 can generate word line voltages VWL, such as programming voltage, read voltage, pass voltage, erase voltage, erase verification voltage, or programming verification voltage. Additionally, voltage generator 230 can also generate serial select line voltage and ground select line voltage based on the voltage control signal CTRL_vol.

[0044] Row decoder 240 can select one of the memory blocks, one of the word lines (WL) of the selected memory block, and one of the multiple string select lines (SSL) in response to row address X-ADDR. Page buffer circuit 210 can select some bit lines (BL) in response to column address Y-ADDR. Page buffer circuit 210 can be used as a write driver or a sense amplifier depending on the operating mode.

[0045] The page buffer circuit 210 may include a plurality of page buffers PB, each connected to a plurality of bit lines BL. In this embodiment, each page buffer PB includes a page buffer unit (e.g., Figure 5 The first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn) and the cache latch (e.g., in each of the multiple page buffers PB) included in the multiple page buffers PB) Figure 5The first cache latch CL0 to the (n+1)th cache latch CLn can be separated from each other and have individual structures. Therefore, the routing freedom on the page buffer unit can be increased, and the layout complexity can be reduced. Furthermore, because the cache latches are adjacent to the data input / output lines, the distance between the cache latches and the data input / output lines can be reduced, thus increasing the data input / output speed. As used herein, "unit" can refer to "circuit".

[0046] In an embodiment, each page buffer unit may include a pair of pass transistors (e.g., Figure 9 TR0 and TR0' in the diagram) and sensing node lines (e.g., for connecting pairs of channel transistors to each other) for connecting pairs of channel transistors to each other. Figure 9 In this case, the sensing node line can be implemented as the lower metal layer (e.g., MT0a). Figure 9 The page buffer circuit 210 is a track (LM0) and can correspond to a sensing node. During the data sensing period, the channel transistors in each page buffer unit included in the multiple page buffer units may not be electrically connected to each other, and therefore, the sensing node lines in each page buffer unit included in the multiple page buffer units may not be electrically connected to each other. On the other hand, during the data transmission period, the channel transistors in each page buffer unit included in the multiple page buffer units may be connected in series with each other, and therefore, the sensing node lines in each page buffer unit included in the multiple page buffer units may be electrically connected to each other and can be used as data transmission lines. Therefore, since the page buffer circuit 210 does not need to include multiple data transmission lines for electrically connecting the multiple page buffer units to the multiple cache latches respectively, the area occupied by the page buffer circuit 210 can be reduced.

[0047] Figure 2 An embodiment of the invention is illustrated schematically. Figure 1 The structure of the storage device 10. (Refer to...) Figure 2 The storage device 10 may include a first semiconductor layer L1 and a second semiconductor layer L2, and the first semiconductor layer L1 may be stacked on a vertical direction VD relative to the second semiconductor layer L2. The second semiconductor layer L2 may be located below the first semiconductor layer L1 in the vertical direction VD, and therefore, the second semiconductor layer L2 may be close to the substrate.

[0048] In an embodiment, Figure 1 The memory cell array 100 can be formed on the first semiconductor layer L1, and Figure 1The peripheral circuitry 200 can be formed on the second semiconductor layer L2. Therefore, the memory device 10 can have a structure in which the memory cell array 100 is located on the peripheral circuitry 200, i.e., a cell-on-periphery (COP) structure. The COP structure can effectively reduce the area in the horizontal direction and improve the integration density of the memory device 10.

[0049] In an embodiment, the second semiconductor layer L2 may include a substrate, and transistors and metal patterns for wiring the transistors are formed on the substrate (e.g., Figure 9 The peripheral circuitry 200 can be formed in the second semiconductor layer L2, which contains a first lower metal layer L0 and a second lower metal layer L2. After the peripheral circuitry 200 is formed on the second semiconductor layer L2, a first semiconductor layer L1 including the memory cell array 100 can be formed, and a metal pattern for connecting the word lines WL and bit lines BL of the memory cell array 100 to the peripheral circuitry 200 formed in the second semiconductor layer L2 can be formed. For example, the bit line BL can extend in a first horizontal direction HD1, and the word line WL can extend in a second horizontal direction HD2.

[0050] As the number of stages in the memory cell array 100 increases with the development of semiconductor technology, i.e., as the number of stacked word lines WL increases, the area of ​​the memory cell array 100 decreases, and therefore, the area of ​​the peripheral circuitry 200 also decreases. According to this embodiment, in order to reduce the area occupied by the page buffer circuitry 210, the page buffer circuitry 210 may have a structure where the page buffer cells and cache latches are separated from each other, and the sensing nodes included in each page buffer cell may be commonly connected to a combined sensing node. (Refer to...) Figure 9 This will be explained in detail.

[0051] Figure 3 An embodiment of the invention is illustrated schematically. Figure 1 The storage cell array 100 in the middle. (Refer to...) Figure 3 The storage cell array 100 may include first storage blocks BLK0 to (i+1)th storage blocks BLKi, where i can be a positive integer. Each of the first storage blocks BLK0 to (i+1)th storage blocks BLKi may have a 3D structure (or a vertical structure). Each of the first storage blocks BLK0 to (i+1)th storage blocks BLKi may include multiple NAND strings extending in the vertical direction VD. In this case, the multiple NAND strings may be set to be spaced apart from each other by a specific distance in the first horizontal direction HD1 and the second horizontal direction HD2. The first storage blocks BLK0 to (i+1)th storage blocks BLKi may be decoded by a row decoder (…). Figure 1The row decoder 240 can select the storage block corresponding to the block address from the first storage block BLK0 to the (i+1)th storage block BLKi.

[0052] Figure 4 This is an embodiment of the concept of the present invention. Figure 3 A perspective view of the storage block BLKa. (See reference...) Figure 4 The memory block BLKa can be formed in a direction perpendicular to the substrate SUB. The substrate SUB can have a first conductivity type (e.g., p-type) and can be provided with a common source line CSL extending along a second horizontal direction HD2 on the substrate SUB and having a second conductivity type (e.g., n-type). In the region between two adjacent common source lines CSL on the substrate SUB, a plurality of insulating layers IL extending in the second horizontal direction HD2 can be sequentially provided in the vertical direction VD, and the plurality of insulating layers IL can be spaced apart from each other in the vertical direction VD. For example, the plurality of insulating layers IL can comprise an insulating material such as silicon oxide.

[0053] Multiple pillars P can be sequentially disposed along a first horizontal direction HD1 in the region between two adjacent common source lines CSL of the substrate SUB, and pass through multiple insulating layers IL in the vertical direction VD. For example, the multiple pillars P can contact the substrate SUB via multiple insulating layers IL. The surface layer S of each pillar P can include a silicon material of a first type and can be used as a channel region. The inner layer I of each pillar P can include an insulating material such as silicon oxide or an air gap.

[0054] In the region between two adjacent common source lines CSL, a charge storage layer CS can be disposed along the exposed surfaces of the insulating layer IL, pillar P, and substrate SUB. The charge storage layer CS may include a gate insulating layer (or tunneling insulating layer), a charge trapping layer, and a barrier insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. Additionally, in the region between the two adjacent common source lines CSL, gate electrodes GE, including select lines (e.g., GSL and SSL) and first word lines WL0 to eighth word lines WL7, can be disposed on the exposed surface of the charge storage layer CS.

[0055] The drain or source contact DR can be disposed on each of the plurality of pillars P. For example, the drain or source contact DR may comprise silicon material doped with impurities of a second conductivity type. On the drain or source contact DR, first bit lines BL1 to third bit lines BL3 may be disposed extending in a first horizontal direction HD1 and spaced apart from each other by a specific distance in a second horizontal direction HD2.

[0056] Figure 5This is a schematic diagram showing the connection between the memory cell array 100 and the page buffer circuit 210 according to an embodiment of the present invention. (Refer to...) Figure 5 The memory cell array 100 may include a first NAND string NS0 to a (n+1)th NAND string NSn. Each of the first NAND string NS0 to the (n+1)th NAND string NSn may include a ground selection transistor GST connected to the ground selection line GSL, a plurality of memory cells MC connected to the first word line WL0 to the (m+1)th word line WLm respectively, and a string selection transistor SST connected to the string selection line SSL. The ground selection transistor GST, the plurality of memory cells MC and the string selection transistor SST may be connected in series with each other. In this case, m may be a positive integer.

[0057] Page buffer circuit 210 may include a first page buffer unit PBU0 to a (n+1)th page buffer unit PBUn. The first page buffer unit PB0 may be connected to a first NAND string NS0 via a first bit line BL0, and the (n+1)th page buffer unit PBUn may be connected to the (n+1)th NAND string NSn via a (n+1)th bit line BLn. In this case, n can be a positive integer. For example, n can be 7, and page buffer circuit 210 may have eight levels of page buffer units or a structure where the first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn are in a single line. For example, the first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn may be located in a row along the extension direction of the first bit line BL0 to the (n+1)th bit line BLn.

[0058] The page buffer circuit 210 may further include first cache latches CL0 to (n+1) cache latches CLn, respectively corresponding to the first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn. For example, n can be 7, and the page buffer circuit 210 may have an eight-level cache latch structure or the first cache latches CL0 to (n+1)th cache latches CLn may be arranged in a single line. For example, the first cache latches CL0 to (n+1)th cache latches CLn may be located in a single line along the extension direction of the first bit line BL0 to the (n+1)th bit line BLn.

[0059] The sensing nodes of each page buffer unit from the first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn can be commonly connected to the combined sensing node SOC. Additionally, the first cache latch CL0 to the (n+1)th cache latch CLn can be commonly connected to the combined sensing node SOC. Therefore, the first page buffer unit PBU0 to the (n+1)th page buffer unit PBUn can be connected to the first cache latch CL0 to the (n+1)th cache latch CLn via the combined sensing node SOC.

[0060] Figure 6 The page buffer PB according to an embodiment of the present invention is shown in detail.

[0061] Reference Figure 6 The page buffer PB can correspond to Figure 1 An example of a page buffer PB is provided. The page buffer PB may include a page buffer unit PBU and a cache unit CU. Because the cache unit CU includes a cache latch (C-LATCH) CL, and the C-LATCH CL is connected to the data input / output lines, the cache unit CU can be adjacent to the data input / output lines. Therefore, the page buffer unit PBU and the cache unit CU can be separate from each other, and the page buffer PB can have a structure where the page buffer unit PBU and the cache unit CU are separate from each other.

[0062] The page buffer unit (PBU) may include the master unit (MU). The master unit (MU) may include the master transistor in the page buffer (PB). The page buffer unit (PBU) may also include a bit line selection transistor (TR_hv) connected to the bit line (BL) and driven by the bit line selection signal (BLSLT). The bit line selection transistor (TR_hv) may include a high-voltage transistor; therefore, the bit line selection transistor (TR_hv) may be located in a different well region from the master unit (MU), i.e., in the high-voltage unit (HVU).

[0063] The master unit MU may include a sensing latch (S-LATCH) SL, a force latch (F-LATCH) FL, an upper bit latch (M-LATCH) ML, and a lower bit latch (L-LATCH) LL. According to embodiments, S-LATCH SL, F-LATCH FL, M-LATCH ML, or L-LATCH LL may be referred to as the master latch. The master unit MU may also include a precharge circuit PC capable of controlling the precharge operation of the bit line BL or sensing node SO based on the bit line clamp control signal BLCLAMP, and may further include a transistor PM' driven by the bit line setup signal BLSETUP.

[0064] S-LATCH SL can store data stored in the memory cell MC or the sensing result of the threshold voltage of the memory cell MC during read or program verification operations. Additionally, S-LATCH SL can be used during programming operations to apply a programming bit line voltage or a programming disable voltage to the bit line BL. F-LATCH FL can be used to improve the threshold voltage distribution during programming operations. F-LATCH FL can store forced data. After the forced data is initially set to "1", it can be converted to "0" when the threshold voltage of the memory cell MC enters a forced region with a lower voltage than the target region. By utilizing forced data during programming execution operations, the bit line voltage can be controlled, and a narrower programming threshold voltage distribution can be formed.

[0065] M-LATCH ML, L-LATCH LL, and C-LATCH CL can be used to store data input from an external source during programming operations and can be referred to as data latches. When programming 3 bits of data into a memory cell MC, the 3 bits of data can be stored in M-LATCH ML, L-LATCH LL, and C-LATCH CL respectively. The stored data can be held in M-LATCH ML, L-LATCH LL, and C-LATCH CL until programming of the memory cell MC is complete. Additionally, C-LATCH CL can receive data read from the memory cell MC from S-LATCH SL during read operations and can output the received data externally via the data input / output lines.

[0066] Additionally, the main unit MU may also include first transistors NM1 to fourth transistors NM4. First transistor NM1 can be connected between sensing node SO and S-LATCH SL, and can be controlled by the ground control signal SOGND. Second transistor NM2 can be connected between sensing node SO and F-LATCH FL, and can be driven by the forced monitoring signal MON_F. Third transistor NM3 can be connected between sensing node SO and M-LATCH ML, and can be driven by the high-order monitoring signal MON_M. Fourth transistor NM4 can be connected between sensing node SO and L-LATCH LL, and can be driven by the low-order monitoring signal MON_L.

[0067] Additionally, the main unit MU may also include a fifth transistor NM5 and a sixth transistor NM6 connected in series between the bit line selection transistor TR_hv and the sensing node SO. The fifth transistor NM5 can be driven by the bit line off signal BLSHF, and the sixth transistor NM6 can be driven by the bit line connection control signal CLBLK. Furthermore, the main unit MU may also include a precharge transistor PM. The precharge transistor PM can be connected to the sensing node SO, can be driven by the load signal LOAD, and can precharge the sensing node SO to a precharge level during the precharge period.

[0068] In this embodiment, the main unit MU may further include a pair of channel transistors connected to the sensing node SO, or a first channel transistor TR and a second channel transistor TR'. According to the embodiment, the first channel transistor TR and the second channel transistor TR' may also be referred to as a first sensing node connection transistor and a second sensing node connection transistor, respectively. The first channel transistor TR and the second channel transistor TR' can be driven by a pass control signal SO_PASS. According to the embodiment, the pass control signal SO_PASS may be referred to as a sensing node connection control signal. The first channel transistor TR may be connected between the first terminal SOC_U and the sensing node SO, and the second channel transistor TR' may be connected between the sensing node SO and the second terminal SOC_D.

[0069] For example, when the Page Buffer Unit (PBU) is Figure 5 When the second page buffer unit PBU1 is connected, the first terminal SOC_U can be connected to one end of the channel transistor included in the first page buffer unit PBU0, and the second terminal SOC_D can be connected to one end of the channel transistor included in the third page buffer unit PBU2. In this way, the sensing node SO can be electrically connected to the combined sensing node SOC via the channel transistor included in each of the third page buffer unit PBU2 to the (n+1)th page buffer unit PBUn.

[0070] During programming operations, the page buffer PB can verify whether programming has been completed in the selected memory cell MC among the memory cells MC included in the NAND string connected to the bit line BL. The page buffer PB can store data sensed via the bit line BL during programming verification operations in the S-LATCH SL. The M-LATCH ML and L-LATCH LL, which store the target data, can be set based on the sensed data stored in the S-LATCH SL. For example, when the sensed data indicates programming completion, the M-LATCH ML and L-LATCH LL can be switched to the programming-disabled setting of the selected memory cell MC in a subsequent programming cycle. The C-LATCH CL can temporarily store input data provided from an external source. During programming operations, the target data to be stored in the C-LATCH CL can be stored in the M-LATCH ML and L-LATCH LL.

[0071] Figure 7 This is a timing diagram illustrating an example of the voltage level of the control signal SO_PASS according to a core operation sequence, based on an embodiment of the present invention. (See also...) Figure 6 and Figure 7 The core operation sequence can represent the operation of the page buffer PB. For example, the core operation sequence may include a data sensing period 71 that performs data sensing operations and a data dumping period or data transfer period 72 that performs data dumping operations.

[0072] During the data sensing period 71, the control signal SO_PASS can be deactivated, and the first channel transistor TR and the second channel transistor TR' can be turned off. Therefore, the page buffer unit PBU may not be electrically connected to the combined sensing node SOC; for example, the page buffer unit PBU may not be electrically connected to the cache unit CU. Additionally, the page buffer unit PBU may not be electrically connected to an adjacent page buffer unit PBU. For example, the data sensing period 71 may include a pre-charging period for pre-charging the voltage of the bit line BL or the voltage of the sensing node SO to a pre-charge level, a forming period for electrically connecting the bit line BL to the sensing node SO and forming (develop) the voltage of the sensing node SO based on the voltage level of the bit line BL, and a sensing period for sensing the voltage of the sensing node SO.

[0073] During data transmission period 72, the control signal SO_PASS can be activated, and the first channel transistor TR and the second channel transistor TR' can be turned on. Therefore, the page buffer unit PBU can be electrically connected to the combined sensing node SOC; for example, the page buffer unit PBU can be electrically connected to the cache unit CU. Additionally, the page buffer unit PBU can be electrically connected to an adjacent page buffer unit PBU. For example, data transmission period 72 may include periods for performing operations such as dumping read data stored in S-LATCH SL to C-LATCH CL, dumping programming data stored in C-LATCH CL to S-LATCH SL, or transferring data stored in C-LATCH CL to the data input / output circuit, etc.

[0074] Figure 8 This is a timing diagram of another example of the voltage level of the control signal SO_PASS according to an embodiment of the concept of the present invention, based on the core operation sequence.

[0075] Refer to together Figure 6 and Figure 8 The core operation sequence can represent the operations of the page buffer (PB). For example, the core operation sequence could be bit line setting period 81, forced dump period 82, bit line forced period 83, data transfer period or data dump period 84, and mass bit count (MBC) period 85.

[0076] During the bit line setup period 81, the control signal SO_PASS can be activated, and the first channel transistor TR and the second channel transistor TR' can be turned on. In this case, the sensing node SO and the combined sensing node SOC can be electrically connected to each other, so data can be dumped from the main latch (e.g., S-LATCH SL, F-LATCH FL, M-LATCH ML, or L-LATCH LL) included in the page buffer unit PBU to C-LATCH CL.

[0077] During the forced dump period 82 and the bit line forced period 83, the control signal SO_PASS can be deactivated, and the first channel transistor TR and the second channel transistor TR' can be turned off. Therefore, the page buffer unit PBU can be de-electrically connected to the cache unit CU, and also de-electrically connected to the adjacent page buffer unit PBU. During the forced dump period 82, a dump operation can be performed during programming to select the bit line BL to be forced to a bias voltage lower than the supply voltage level. For example, data can be dumped from F-LATCH FL to S-LATCH SL. During the bit line forced period 83, the voltage applied to the bit line BL can vary according to the value stored in F-LATCH FL during programming execution.

[0078] During data transmission period 84, the control signal SO_PASS can be activated, and the first channel transistor TR and the second channel transistor TR' can be turned on. For example, during data transmission period 84, a dump operation can be performed to mark the data stored in S-LATCHSL as logic low. This S-LATCHSL is connected to a memory cell MC that failed due to a programming verification operation and is to be programmed to the target programming state when programming is performed. In this case, because the sensing node SO and the combined sensing node SOC are electrically connected to each other, logic low data can be dumped from C-LATCH CL to the main latch (e.g., S-LATCH SL).

[0079] During the quality bit counting period 85, the control signal SO_PASS can be deactivated, and the first channel transistor TR and the second channel transistor TR' can be turned off. Therefore, the page buffer unit PBU can be de-electrically connected to the cache unit CU, and also de-electrically connected to adjacent page buffer units. During the quality bit counting period 85, the number of S-LATCH SLs marked as logic low during the previous data transmission period 84 can be counted.

[0080] Figure 9 This is a plan view of a page buffer circuit 210a according to an embodiment of the present invention. See also... Figure 2 and Figure 9 The first semiconductor layer L1 may include a memory cell array 100, and the memory cell array 100 may include a plurality of memory cells MC respectively connected to a plurality of bit lines BL extending in a first horizontal direction HD1. In an embodiment, the plurality of bit lines BL may be implemented as a first metal layer M1. For example, the first metal layer M1 may be formed using a dual patterning technique (DPT).

[0081] The second semiconductor layer L2 may include a page buffer circuit 210a, and a first lower metal layer LM0 extending in the first horizontal direction HD1 may be located above the page buffer circuit 210a. A third lower metal layer LM2 extending in the first horizontal direction HD1 may be located above the first lower metal layer LM0. Although not shown, a second lower metal layer extending in the second horizontal direction HD2 may be further disposed between the first lower metal layer LM0 and the third lower metal layer LM2. For example, the first lower metal layer LM0 and the third lower metal layer LM2 may be formed without using DPT, so the pitch of the metal pattern included in each of the first lower metal layer LM0 and the third lower metal layer LM2 may be greater than the pitch of the metal pattern included in the first metal layer L1.

[0082] The page buffer circuit 210a may include first page buffer units PBU0 to eighth page buffer units PBU7 and first cache units CU0 to eighth cache units CU7 on the first horizontal direction HD1. The first page buffer units PBU0 to eighth page buffer units PBU7 may be located in the main region MR, and the first cache units CU0 to eighth cache units CU7 may be located in the cache region CR, with the main region MR and the cache region CR being adjacent to each other on the first horizontal direction HD1. The first lower metal layer LM0 and the third lower metal layer LM2 may be used to send control signals to each transistor included in the first page buffer units PBU0 to eighth page buffer units PBU7 and the first cache units CU0 to eighth cache units CU7, or may be used to connect each transistor to a power supply terminal or a ground terminal.

[0083] Figure 10 This is a circuit diagram of a page buffer circuit 210a according to an embodiment of the present invention. It will be referred to together with the following description. Figure 9 and Figure 10 The configuration of the page buffer circuit 210a is described in detail.

[0084] Each page buffer unit may include two channel transistors; therefore, the page buffer circuit 210a may include 16 channel transistors TR0, TR0', ..., TR7, and TR7', and these 16 channel transistors TR0, TR0', ..., TR7, and TR7' may be connected in series. For example, the first page buffer unit PBU0 may include a first channel transistor TR0 and a second channel transistor TR0' connected in series. For example, the first channel transistor TR0 may be adjacent to a first boundary of the first page buffer unit PBU0, and the second channel transistor TR0' may be adjacent to a second boundary of the first page buffer unit PBU0, with the first and second boundaries facing each other. For example, the first channel transistor TR0 and the second channel transistor TR0' may be implemented as NMOS transistors and thus may be located at both ends of the P-well of the first page buffer unit PBU0, but the invention is not limited thereto. In embodiments, another semiconductor device (e.g., a PMOS transistor) may be further arranged between the first boundary of the first page buffer unit PBU0 and the first channel transistor TR0. Similarly, another semiconductor device (e.g., a PMOS transistor) may be further arranged between the second boundary of the first page buffer cell PBU0 and the second channel transistor TR0'.

[0085] For example, the first page buffer unit PBU0 may also include a plurality of transistors arranged in a first horizontal direction between the first channel transistor TR0 and the second channel transistor TR0' (e.g., Figure 6 (S-LATCH SL, F-LATCHFL, M-LATCH ML and L-LATCH LL, first transistor NM1 to sixth transistor NM6, etc.). In the following description, the configuration of the first page buffer unit PBU0 will be given in focus, and the second page buffer units PBU1 to the eighth page buffer units PBU7 can all be configured to be the same as the first page buffer unit PBU0.

[0086] The first channel transistor TR0 may include a source S0, a drain D0, and a gate G0. The source S0 of the first channel transistor TR0 may be connected to a first terminal (e.g., Figure 6 In the SOC_U), and the drain D0 of the first channel transistor TR0 can be connected to the first sensing node SO0. The first pass control signal SO_PASS in the control signal SO_PASS[7:0] <0> It can be applied to the gate G0 of the first channel transistor TR0. In the following, the control signal SO_PASS[7:0] will be described, including the first pass control signal SO_PASS corresponding to the first page buffer unit PBU0 to the eighth page buffer unit PBU7 respectively. <0> Up to the eighth control signal SO_PASS <7> .

[0087] The second-channel transistor TR0' may include a source S0', a drain D0', and a gate G0'. The source S0' of the second-channel transistor TR0' may be connected to the first sensing node SO0, and the drain D0' of the second-channel transistor TR0' may be connected to a second terminal (e.g., Figure 6 (SOC_D in the context). First, via the control signal SO_PASS. <0> It can be applied to the gate G0' of the second-channel transistor TR0'.

[0088] The second page buffer unit PBU1 may include a first-channel transistor TR1 and a second-channel transistor TR1' connected in series. The first-channel transistor TR1 may include a source S1, a drain D1, and a gate G1, and the second-channel transistor TR1' may include a source S1', a drain D1', and a gate G1'. The second pass control signal SO_PASS in the control signal SO_PASS[7:0] is used. <1> It can be applied to the gate G1 of the first channel transistor TR1 and the gate G1' of the second channel transistor TR1', respectively.

[0089] The eighth page buffer unit PBU7 may include a first-channel transistor TR7 and a second-channel transistor TR7' connected in series. The first-channel transistor TR7 may include a source S7, a drain D7, and a gate G7, and the second-channel transistor TR7' may include a source S7', a drain D7', and a gate G7'. The eighth control signal SO_PASS[7:0] is used to control the eighth channel. <7> The gate G7 of the first channel transistor TR7 and the gate G7' of the second channel transistor TR7' can be applied respectively. However, the present invention is not limited thereto, and in some embodiments, the combined sensing node can be applied to the gate G7' of the second channel transistor TR7' via the control signal SOC_PASS.

[0090] The first high-speed cache unit CU0 may include a monitoring transistor NM7a, and the monitoring transistor NM7a may include a source S, a drain D, and a gate G (see [link to relevant documentation]). Figure 9 For example, the monitoring transistor NM7a can correspond to... Figure 6The transistor NM7 is used in the monitoring. The source S of the monitoring transistor NM7a can be connected to the combined sensing node SOC, and the first cache monitoring signal MON_C[0] in the cache monitoring signals MON_C[7:0] can be applied to the gate G of the monitoring transistor NM7a. In the following description, the cache monitoring signals MON_C[7:0] will include the first cache monitoring signals MON_C corresponding to the first page buffer unit PBU0 to the eighth page buffer unit PBU7 respectively. <0> Up to the eighth high-speed buffer monitoring signal MON_C <7> Although not shown, the first high-speed cache unit CU0 may also include a plurality of transistors on the first horizontal direction HD1 (e.g., including...). Figure 6 (Multiple transistors in the C-LATCH CL). The second cache unit CU1 to the eighth cache unit CU7 can all have the same configuration as the first cache unit CU0. The monitoring transistors NM7a to NM7h included in each of the first cache units CU0 to the eighth cache unit CU7 can be connected in parallel to the combined sensing node SOC. The source of each of the monitoring transistors NM7a to NM7h can be connected in parallel to the combined sensing node SOC.

[0091] In the first page buffer unit PBU0, the drain D0 of the first channel transistor TR0 and the source S0' of the second channel transistor TR0' can be connected to each other via a first conductive line or a first metal pattern MT0a. The first metal pattern MT0a can correspond to the first sensing node SO0, and therefore can be referred to as the first sensing node line. In the second page buffer unit PBU1, the drain D1 of the first channel transistor TR1 and the source S1' of the second channel transistor TR1' can be connected to each other via a first conductive line or a first metal pattern MT0b. The first metal pattern MT0b can correspond to the second sensing node SO1, and therefore can be referred to as the second sensing node line.

[0092] In the eighth page buffer unit PBU7, the drain D7 of the first channel transistor TR7 and the source S7' of the second channel transistor TR7' can be connected to each other via the first metal pattern MT0c. The first metal pattern MT0c can correspond to the eighth sensing node SO7, and therefore can be referred to as the eighth sensing node line. In the eighth page buffer unit PBU7, the drain D7' of the second channel transistor TR7' and the source S of the monitoring transistor NM7a of the first high-speed cache unit CU0 can be connected to each other via the first metal pattern MT0d. In this case, the first metal pattern MT0d can also be connected to the precharge circuit SOC_PRE. The first metal pattern MT0d can correspond to the combined sensing node SOC, and therefore can be referred to as the combined sensing node line. In the embodiment, the first metal patterns MT0a, MT0b, MT0c and MT0d can be implemented as the first lower metal layer LM0, and can occupy one trace of the first lower metal layer LM0.

[0093] The drain D0' of the second channel transistor TR0' of the first page buffer unit PBU0 and the source S1 of the first channel transistor TR1 of the second page buffer unit PBU1 can be connected to each other via a second conductive line or a second metal pattern MT1a. Therefore, the second metal pattern MT1a can be referred to as a node connection line. For example, the second metal pattern MT1a can be implemented as a third lower metal layer LM2 and can occupy one trace of the third lower metal layer LM2. However, the present invention is not limited to this, and the second metal pattern MT1a can be implemented as a second lower metal layer.

[0094] According to this embodiment, when activated by the control signal SO_PASS, the first channel transistors TR0 to TR7 and the second channel transistors TR0' to TR7' can be turned on. Therefore, the first channel transistors TR0 to TR7 and the second channel transistors TR0' to TR7', respectively included in the first page buffer unit PBU0 to the eighth page buffer unit PBU7, can be connected in series with each other, and all the first sensing nodes SO0 to the eighth sensing node SO7 can be connected to the combined sensing node SOC. The first sensing node SO0 and the second sensing node SO1 can be connected to each other via the first metal patterns MT0a and MT0b and the second metal pattern MT1a, and the eighth sensing node SO7 and the combined sensing node SOC can be connected to each other via the first metal patterns MT0c and MT0d.

[0095] The first metal patterns MT0a, MT0b, and MT0c corresponding to the first sensing node line, the second sensing node line, and the eighth sensing node line, respectively, the second metal pattern MT1a corresponding to the node connection line, and the first metal pattern MT0d corresponding to the combined sensing node line can constitute data transmission lines. As described above, according to this embodiment, it is not necessary to separately require eight data transmission lines for connecting the first page buffer unit PBU0 to the eighth page buffer unit PBU7 to the first cache unit CU0 to the eighth cache unit CU7, and the sensing node line included in each of the first page buffer unit PBU0 to the eighth page buffer unit PBU7 can be used as a data transmission line. Therefore, since the number of metal lines required for the wiring of the page buffer circuit 210a can be reduced, the layout complexity can be reduced, and the size of the page buffer circuit 210a can be reduced.

[0096] The first page buffer unit PBU0 to the eighth page buffer unit PBU7 may further include a first precharge transistor PM0 to an eighth precharge transistor PM7. In the first page buffer unit PBU0, the first precharge transistor PM0 may be connected between the first sensing node SO0 and the voltage terminal to which the precharge voltage is applied, and may include a gate to which the load signal LOAD is applied. The first precharge transistor PM0 may precharge the first sensing node SO0 to the precharge level of the precharge voltage in response to the load signal LOAD.

[0097] The main region MU may include contact regions THVa and THVd. Contact region THVa may be located between the first page buffer unit PBU0 and the second page buffer unit PBU1, and contact region THVd may be located between the seventh page buffer unit and the eighth page buffer unit PBU7. The first bit contact CT0 and the second bit contact CT1, respectively connected to the first bit line and the second bit line, may be located within contact region THVa. The first bit contact CT0 may be connected to the first page buffer unit PBU0, and the second bit line contact CT1 may be connected to the second page buffer unit PBU1.

[0098] The page buffer circuit 210a may further include a precharge circuit SOC_PRE located between the eighth page buffer unit PBU7 and the first high-speed cache unit CU0. The precharge circuit SOC_PRE may include a precharge transistor PMA and a shield transistor NMa for precharging the combined sensing node SOC. The precharge transistor PMA may be driven by the combined sensing node load signal SOC_LOAD, and when the precharge transistor PMA is turned on, the combined sensing node SOC may be precharged to a precharge level. The shield transistor NMa may be driven by the combined sensing node shield signal SOC_SHLD, and when the shield transistor NMa is turned on, the combined sensing node SOC may be precharged to ground.

[0099] As the transistor width WD decreases due to process miniaturization, the area occupied by the page buffer circuit 210a can be reduced. For example, the transistor width WD may correspond to the size of the source S0 or drain D0 of the first channel transistor TR0 in the second horizontal direction HD2. As the transistor width WD decreases, the size of the first page buffer unit PBU0 in the second horizontal direction HD2 can be reduced. However, although the transistor width WD decreases, the pitch of the first lower metal layer LM0 may not decrease. Therefore, the number of wirings (i.e., the number of metal patterns) of the first lower metal layer LM0 on the first page buffer unit PBU0, whose size in the second horizontal direction HD2 has decreased, will also decrease. For example, the number of metal patterns of the first lower metal layer LM0 corresponding to the first page buffer unit PBU0 can be reduced from six to four.

[0100] In this way, the sensing reliability of the first page buffer unit PBU0 decreases when the number of metal patterns in the first lower metal layer LM0 corresponding to the first page buffer unit PBU0 decreases. For example, during sensing operation, to prevent coupling between the first sensing node SO0 and adjacent nodes, the metal pattern adjacent to the first sensing node SO0 is used as a shield line to which a fixed bias voltage is applied. However, when the metal pattern corresponding to the shield line is removed due to the reduction of the metal pattern, a voltage change at the first sensing node SO0 may occur due to coupling between the first sensing node SO0 and adjacent nodes, thus degrading the sensing reliability of the first page buffer unit PBU0.

[0101] According to this embodiment, by separately arranging the first page buffer unit PBU0 and the first high-speed buffer unit CU0, the degrees of freedom of the metal patterns included in the first lower metal layer LM0 and the third lower metal layer LM2 on the first page buffer unit PBU0 can be increased. Therefore, at least one of the metal patterns included in the first lower metal layer LM0 and the third lower metal layer LM2 can be used as a shielding line for the first sensing node SO0. Thus, an increase in voltage fluctuation at the first sensing node SO0 can be prevented, thereby preventing a decrease in the sensing reliability of the first page buffer unit PBU0.

[0102] In some examples, in a structure where the first page buffer unit PBU0 to the eighth page buffer unit PBU7 are separate from the first cache unit CU0 to the eighth cache unit CU7, when eight signal lines are arranged to connect the first page buffer unit PBU0 to the eighth page buffer unit PBU7 to the first cache unit CU0 to the eighth cache unit CU7 respectively, the size of the page buffer circuit 210a in the second horizontal direction HD2 will increase again.

[0103] According to this embodiment, the first sensing nodes SO0 to the eighth sensing nodes SO7 can be interconnected using first channel transistors TR0 to TR7 and second channel transistors TR0' to TR7' included in each of the first page buffer units PBU0 to the eighth page buffer units PBU7, and the first sensing nodes SO0 to the eighth sensing nodes SO7 can be connected to the first cache units CU0 to the eighth cache units CU7 respectively via combined sensing nodes SOC. In this case, because the sensing node lines for connecting the first channel transistors and the second channel transistors to each other are implemented using a metal pattern of a trace of the first lower metal layer LMO (e.g., MTOa and MTOb), the increase in size of the page buffer circuit 210a in the second horizontal direction HD2 can be prevented.

[0104] Figure 11 A page buffer PB' according to an embodiment of the present invention is shown in detail. (Refer to...) Figure 11 Page buffer PB' may include page buffer unit PBU' and cache unit CU, and page buffer unit PBU' may include main unit MU' and high-voltage unit HVU. Page buffer PB' may correspond to Figure 6 An example of modification to the page buffer PB in [the document / platform]. Although... Figure 6The page buffer unit (PBU) in the embodiment includes a first channel transistor TR and a second channel transistor TR', but according to this embodiment, the page buffer unit PBU' may include a single channel transistor TR'". The channel transistor TR' can be driven by the control signal SO_PASS and can be connected between the first terminal SOC_U and the second terminal SOC_D.

[0105] For example, the source of the channel transistor TR" can be connected to the first terminal SOC_U, and the drain of the channel transistor TR" can be connected to the sensing node SO and the second terminal SOC_D. However, the invention is not limited thereto. As another example, the source of the channel transistor TR" can be connected to the first terminal SOC_U and the sensing node SO, and the drain of the channel transistor TR" can be connected to the second terminal SOC_D. In an embodiment, the channel transistor included in one of two adjacent page buffer units on the first horizontal direction HD1 can be connected between the first terminal SOC_U and the sensing node SO, and the channel transistor included in the other page buffer unit can be connected between the sensing node SO and the second terminal SOC_D.

[0106] Figure 12 This is a plan view of the page buffer circuit 210b according to an embodiment of the present invention, and Figure 13 This is a circuit diagram of a page buffer circuit 210b according to an embodiment of the present invention. The page buffer circuit 210b may include... Figure 11 The page buffer PB' in the middle, and corresponding to Figure 9 and Figure 10 A modified example of the page buffer circuit 210a in [the document / reference]. Figure 12 and Figure 13 The page buffer circuit 210b may include a first page buffer unit PBU0' to an eighth page buffer unit PBU7' on the first horizontal direction HD1 and a first cache unit CU0 to an eighth cache unit CU7 on the first horizontal direction HD1. The first page buffer unit PBU0' to the eighth page buffer unit PBU7' may be located in the main region MR', and the first cache unit CU0 to the eighth cache unit CU7 may be located in the cache region CR', and the main region MR' and the cache region CR' may be adjacent to each other on the first horizontal direction HD1.

[0107] Each page buffer unit may include one channel transistor, and the page buffer circuit 210b may also include a channel transistor for connecting two adjacent page buffer units. Therefore, it can be understood that each page buffer unit includes 1.5 channel transistors. The first page buffer unit PBU0' to the eighth page buffer unit PBU7' may each include a first channel transistor TR0" to an eighth channel transistor TR7", and the page buffer circuit 210b may also include four channel transistors TR_A to TR_D. Therefore, the page buffer circuit 210b may include 12 channel transistors TR0" to TR7" and TR_A to TR_D, and these 12 channel transistors TR0" to TR7" and TR_A to TR_D may be connected in series with each other.

[0108] Channel transistor TR_A can be located between the second page buffer unit PBU1' and the third page buffer unit PBU2', channel transistor TR_B can be located between the fourth page buffer unit PBU3' and the fifth page buffer unit PBU4', channel transistor TR_C can be located between the sixth page buffer unit PBU5' and the seventh page buffer unit PBU6', and channel transistor TR_D can be located between the eighth page buffer unit PBU7' and the precharge circuit SOC_PRE.

[0109] For example, the first page buffer unit PBU0' may include a channel transistor TR0", and the first control signal SO_PASS is used. <0> The gate G0" of the channel transistor TR0" can be applied. For example, the channel transistor TR0" can be adjacent to the second boundary of the first page buffer cell PBU0'. For example, the first page buffer cell PBU0' can also include a plurality of transistors arranged in the first horizontal direction between the first boundary and the channel transistor TR0" (e.g., Figure 11 (S-LATCHSL, F-LATCHFL, M-LATCHML and L-LATCHLL, first transistor NM1 to sixth transistor NM6, etc.). In addition, another semiconductor device, such as a PMOS transistor, may be included between the second boundary of the channel transistor TR0" and the first page buffer unit PBU0'.

[0110] For example, the second page buffer unit PBU1' may include a channel transistor TR1", and the first control signal SO_PASS is used. <0> A gate G1" can be applied to the channel transistor TR1". For example, the channel transistor TR1" can be adjacent to the first boundary of the second page buffer unit PBU1'. For example, the second page buffer unit PBU1' can also include a plurality of transistors located on the first horizontal direction HD1 between the channel transistor TR1" and the second boundary. In addition, another semiconductor device, such as a PMOS transistor, can be included between the first boundary of the channel transistor TR1" and the second page buffer unit PBU1'.

[0111] The page buffer circuit 210b may further include first metal patterns MT0a' to MT0f' extending in the first horizontal direction HD1. For example, the first metal patterns MT0a' to MT0f' may be included in the first lower metal layer LM0. In this case, the first metal patterns MT0a' to MT0e' may correspond to the first sensing nodes SO0 to the eighth sensing nodes SO7 respectively, and therefore may be referred to as sensing node lines. For example, the lengths of the first metal patterns MT0a' to MT0e' in the first horizontal direction HD1 may be the same. In addition, the first metal pattern MT0f' may correspond to the combined sensing node SOC, and therefore may be referred to as the combined sensing node line. Furthermore, the page buffer circuit 210b may also include second metal patterns MT1a and MT1b extending in the first horizontal direction HD1. For example, the second metal patterns MT1a and MT1b may be included in the third lower metal layer LM2. In this case, the second metal pattern MT1a may span the contact area THVa, and the second metal pattern MT1b may span the contact area THVb.

[0112] The first step is to use the control signal SO_PASS <0> The gate G0" of channel transistor TR0" and the gate G1" of channel transistor TR1" can be applied respectively, and the second is through the control signal SO_PASS. <1> It can be applied to the gate G_A of the channel transistor TR_A. Thirdly, it is applied via the control signal SO_PASS. <2> The gate G2" of channel transistor TR2" and the gate G3" of channel transistor TR3" can be applied respectively, and the fourth is through the control signal SO_PASS. <3> It can be applied to the gate of the channel transistor TR_B. The fifth step is through the control signal SO_PASS. <4> The gates G4" of channel transistor TR4" and G5" of channel transistor TR5" can be applied respectively, and the sixth is through the control signal SO_PASS. <5> It can be applied to the gate of the channel transistor TR_C. The seventh step is through the control signal SO_PASS. <6> The gate G6" of channel transistor TR6" and the gate G7" of channel transistor TR7" can be applied respectively, and the eighth is through the control signal SO_PASS <7> It can be applied to the gate G_D of the channel transistor TR_D.

[0113] The source S0" of channel transistor TR0" can be connected to the first sensing node SO0, and the drain D0" can be connected to the source S1" of channel transistor TR1" via the second metal pattern MT1a. The drain D1" of channel transistor TR1" and the source S_A of channel transistor TR_A can be connected to each other via the second sensing node SO1. The drain D_A of channel transistor TR_A can be connected to the source S2" of channel transistor TR2" via the third sensing node SO2. The drain D7" of channel transistor TR7" can be connected to the source S_D of channel transistor TR_D via the eighth sensing node SO7.

[0114] Figure 14 According to an embodiment of the present invention, the first sensing node, based on the core operation sequence, controls the SO_PASS signal. <0> The eighth sensing node is reached via the control signal SO_PASS <7> The timing diagram for the voltage level. Refer to it together. Figure 10 and Figure 14 The core operation sequence may include a data sensing period 111 for performing data sensing operations and a data dumping period or data transmission period 112 for performing data dumping operations. However, the present invention is not limited thereto, and Figure 14 The timing diagram can also be applied to Figure 13 The page buffer circuit 210b is shown in the diagram. Therefore, the first step is achieved via the control signal SO_PASS. <0> Up to the eighth control signal SO_PASS <7> It can be applied to the channel transistors TR0" to TR7" and TR_A to TR_D included in the page buffer circuit 210b.

[0115] During the data sensing period 111, all first passes through the control signal SO_PASS <0> Up to the eighth control signal SO_PASS <7> The first page buffer units PBU0 to PBU7 and the second channel transistors TR0' to TR7' in each of the first page buffer units PBU0 to PBU7 can be deactivated and turned off. Therefore, the first page buffer units PBU0 to PBU7 can be electrically disconnected from each other, and the first sensing nodes SO0 to SO7 can be electrically insulated from each other. Furthermore, the first sensing nodes SO0 to SO7 can be electrically disconnected from the combined sensing node SOC; that is, the first page buffer units PBU0 to PBU7 can be electrically disconnected from the first cache units CU0 to CU7.

[0116] During data transmission period 112, in order to individually control the connection between the first page buffer units PBU0 to the eighth page buffer units PBU7 and the first cache units CU0 to the eighth cache units CU7, the first channel transistors TR0 to TR7 and the second channel transistors TR0' to TR7' included in each of the first page buffer units PBU0 to the eighth page buffer units PBU7 can be selectively turned on. Therefore, the amount of current consumed during data dumping operations can be reduced.

[0117] During the first data transmission period 1121, all first pass control signals SO_PASS <0> Up to the eighth control signal SO_PASS <7> This can be activated, therefore, all first-channel transistors TR0 to TR7 and second-channel transistors TR0' to TR7 in the first page buffer unit PBU0 to the eighth page buffer unit PBU7 can be turned on and connected in series. At this time, the first sensing node SO0 can be connected to the combined sensing node SOC via the second sensing node SO1 to the eighth sensing node SO7, and can be connected to the master latch in the first page buffer unit PBU0 (e.g., ...). Figure 6 One of S-LATCH SL, F-LATCH FL, M-LATCH ML, and L-LATCH LL) and the cache latch in the first cache unit CU0 (e.g., Figure 6 Data dumping operations are performed between C-LATCH CL in the first page buffer unit PBU0 and the cache latch in the first cache unit CU0. For example, the main latch in the first page buffer unit PBU0 and the cache latch in the first cache unit CU0 can respond to the transistor NM7 of the first cache unit CU0 (in Figure 6 The first transistor NM1 to the fourth transistor NM4 of the first page buffer unit PBU0 are activated (in the middle). Figure 6At least one of them is activated and electrically connected to each other.

[0118] During the second data transmission period 1122, the first transmission control signal SO_PASS <0> It can be deactivated, and secondly via the control signal SO_PASS. <1> Up to the eighth control signal SO_PASS <7> It can be activated. Therefore, all the first channel transistors TR1 to TR7 and the second channel transistors TR1' to TR7' included in each of the second page buffer units PBU1 to the eighth page buffer unit PBU7 can be turned on and connected in series. In this case, the second sensing node SO1 can be connected to the combined sensing node SOC via the third sensing node SO2 to the eighth sensing node SO7, and a data dump operation can be performed between the main latch in the second page buffer unit PBU1 and the cache latch in the second cache unit CU1. In this case, because the first channel transistor TR0 and the second channel transistor TR0' included in the first page buffer unit PBU0 are turned off, current consumption can be reduced. For example, the main latch in the second page buffer unit PBU1 and the cache latch in the second cache unit CU1 can respond to the transistor NM7 (in the second cache unit CU1) Figure 6 The first transistor NM1 to the fourth transistor NM4 of the second page buffer unit PBU1 are activated (in the middle) Figure 6 At least one of them is activated and electrically connected to each other.

[0119] During the eighth data transmission period 1128, the first transmission is controlled by the SO_PASS signal. <0> Up to the seventh, via the control signal SO_PASS <6> It can be deactivated, and only the eighth one is activated via the control signal SO_PASS. <7> It can be activated. Therefore, the first channel transistor TR7 and the second channel transistor TR7' included in the eighth page buffer unit PBU7 can be turned on and connected in series. In this case, the eighth sensing node SO7 can be connected to the combined sensing node SOC, and a data dump operation can be performed between the main latch in the eighth page buffer unit PBU7 and the cache latch in the eighth cache unit CU7. In this case, because the first channel transistors TR0 to TR6 and the second channel transistors TR0' to TR6' included in the first page buffer units PBU0 to the seventh page buffer units PBU6 are turned off, current consumption can be reduced. For example, the main latch in the eighth page buffer unit PBU7 and the cache latch in the eighth cache unit CU7 can respond to the transistor NM7 of the eighth cache unit CU7 (in Figure 6 The first transistor NM1 to the fourth transistor NM4 of the eighth page buffer unit PBU7 are activated (in the middle) Figure 6At least one of them is activated and electrically connected to each other.

[0120] Figure 15 This is a timing diagram illustrating an example of a data dump operation of the page buffer circuit 210a according to an embodiment of the present invention. (See also...) Figure 10 and Figure 15 The data transfer operation between multiple page buffer units PBU0 to PBU7 and multiple cache units CU0 to CU7 in the page buffer circuit 210a can be executed sequentially. During the period from the first time point t0 to the second time point t1, data can be dumped between the first page buffer unit PBU0 and the first cache unit CU0. At the first time point t0, the control signal SO_PASS[7:0] can be switched to a logic high as an enable level, and all the first channel transistors TR0 to TR7 and the second channel transistors TR0' to TR7' included in the first page buffer unit PBU0 to the eighth page buffer unit PBU7 can be turned on. In the embodiment, the control signal SO_PASS[7:0] can be kept logic high until the data dump operation between the first page buffer unit PBU0 to the eighth page buffer unit PBU7 and the first cache unit CU0 to the eighth cache unit CU7 is completed.

[0121] At the first time point t0, the load signal LOAD can transition to a logic low as an enable level, and all precharge transistors PM0 to PM7 in each of the first page buffer units PBU0 to the eighth page buffer unit PBU7 can be turned on, and the first sensing nodes SO0 to the eighth sensing nodes SO7 can be precharged to the precharge level. Additionally, at the first time point t0, the combined sensing node load signal SOC_LOAD can transition to a logic low as an enable level, and the precharge transistor PMa in the precharge circuit SOC_PRE can be turned on, and the combined sensing node (SOC) can be precharged to the precharge level. Next, the load signal LOAD and the combined sensing node load signal SOC_LOAD can transition to a logic high, and the first ground control signal SOGND in the ground control signal SOGND[7:0] applied to the first page buffer unit PBU0... <0> This can be converted to a logic high as an enable level. In this case, the first sensing node SO0 and S-LATCH SL included in the first page buffer unit PBU0 can be electrically connected to each other, and data can be dumped between S-LATCH SL included in the first page buffer unit PBU0 and the first cache unit CU0. Hereinafter, the ground control signal SOGND[7:0] will be described, including the first ground control signal SOGND corresponding to the first page buffer unit PBU0 to the eighth page buffer unit PBU7 respectively. <0> To the eighth ground control signal SOGND <7> .

[0122] During the period from the second time point t1 to the third time point t2, data can be dumped between the second page buffer unit PBU1 and the second high-speed buffer unit CU1. At the second time point t1, the load signal LOAD and the combined sensing node load signal SOC_LOAD can transition to logic low as an enable level, and the first sensing nodes SO0 to the eighth sensing nodes SO7 and the combined sensing node SOC can be precharged to the precharge level. Next, the load signal LOAD and the combined sensing node load signal SOC_LOAD can transition to logic high, and the second ground control signal SOGND in the ground control signal SOGND[7:0] is applied to the second page buffer unit PBU1. <1> This can be converted to a logic high as an enable level. In this case, the second sensing node SO1 and S-LATCH SL, included in the second page buffer unit PBU1, can be electrically connected to each other, and data can be dumped between S-LATCH SL included in the second page buffer unit PBU1 and the second cache unit CU1. During the period from the third time point t2 to the fourth time point t3, data can be dumped between the third page buffer unit PBU2 and the third cache unit CU2, and during the period from the fourth time point t3 to the time point t4, data can be dumped between the fourth page buffer unit PBU3 and the fourth cache unit CU3.

[0123] Figure 16 This is a circuit diagram of a high-speed cache unit CU according to an embodiment of the present invention. (Refer to...) Figure 6 and Figure 16 The cache unit CU may include a monitoring transistor NM7 and a C-LATCH CL, and the C-LATCH CL may include a first inverter INV1 and a second inverter INV2, a dump transistor 132, and transistors 131, 133 to 135. The monitoring transistor NM7 can be driven according to the cache monitoring signal MON_C and can control the connection between the combined sensing node SOC and the C-LATCH CL.

[0124] The first inverter INV1 can be connected between the first node ND1 and the second node ND2, and the second inverter INV2 can be connected between the second node ND2 and the first node ND1. Therefore, the first inverter INV1 and the second inverter INV2 can form a latch. Transistor 131 may include a gate connected to the combined sensing node SOC. Dump transistor 132 can be driven by the dump signal Dump_C and can send data stored in C-LATCH CL to the main latch (e.g., S-LATCH SL in the page buffer unit PBU). Transistor 133 can be driven by the data signal DI, transistor 134 can be driven by the data inversion signal nDI, and transistor 135 can be driven by the write control signal DIO_W. When the write control signal DIO_W is activated, the voltage levels of the first node ND1 and the second node ND2 can be determined according to the data signal DI and the data inversion signal nDI, respectively.

[0125] The cache unit CU can be connected to the input / output terminal RDi via transistors 136 and 137. Transistor 136 may include a gate connected to the second node ND2 and can be turned on or off according to the voltage level of the second node ND2. Transistor 137 can be driven by the read control signal DIO_R. When the control signal DIO_R is activated and transistor 137 is turned on, the voltage level of the input / output terminal RDi can be determined as "1" or "0" according to the state of C-LATCH CL.

[0126] Figure 17 This is a timing diagram illustrating an example of a data dump operation of the page buffer circuit 210a according to an embodiment of the present invention. (See also...) Figure 10 , Figure 16 and Figure 17 During the data dumping operation of the page buffer circuit 210a, the control signal SO_PASS[7:0] can be kept at a logic high as an enable level, and all first channel transistors TR0 to TR7 and second channel transistors TR0' to TR7' can be turned on. Therefore, the first sensing nodes SO0 to the eighth sensing nodes SO7 can be connected to the combined sensing node SOC, and can be connected to the first cache unit CU0 to the eighth cache unit CU7 via the combined sensing node SOC. During the first time period 141 to the fourth time period 144, data can be sequentially processed in the first to fourth page buffer units (e.g., ...). Figure 10 PBU0 to PBU3) and the first to fourth high-speed buffer units (e.g., Figure 10 Data is transferred between CU0 to CU3 in the first cache unit. During the fifth period 145, data stored in the first cache unit CU0 to the eighth cache unit CU7 can be output via the data input / output line.

[0127] During the first time period 141, a data dump operation can be performed between the first page buffer unit PBU0 and the first cache unit CU0. The first time period 141 can correspond to the time period from the first time point t0 to the seventh time point t6. The operation of the page buffer circuit 210a during the first time period 141 will be described below. The operation of the page buffer circuit 210a during the second time period 142 to the fourth time period 144 can correspond to the operation of the page buffer circuit 210a during the first time period 141.

[0128] At the first time point t0, the load signal LOAD and the combined sensing node load signal SOC_LOAD can transition to a logic low, which is an enable level. All precharge transistors PM0 to PM7 and PMa can be turned on, and the first sensing node SO0 to the eighth sensing node SO7 and the combined sensing node SOC can be precharged to the precharge level. At the second time point t1, the load signal LOAD and the combined sensing node load signal SOC_LOAD can transition to a logic high, which is a disable level. The period from the first time point t0 to the second time point t1 can be referred to as the precharge period.

[0129] At the third time point t2, the first ground control signal SOGND is applied to the first page buffer unit PBU0. <0> It can be converted to a logic high as an enable level, and at the fourth time point t3, the first ground control signal SOGND <0> It can be converted to logic low. At the fifth time point t4, the first dump signal Dump_C in the dump signal Dump_C[7:0] is applied to the first cache unit CU0. <0> And the data signal DI can be converted to a logic high as an enable level. In the following description, the dump signals Dump_C[7:0] will include the first dump signal Dump_C corresponding to the first cache unit CU0 to the eighth cache unit CU7 respectively. <0> Up to the eighth dump signal Dump_C <7> At time point t5, the first dump signal, Dump_C, was generated. <0> The data signal DI can be converted to a logic low as a stop level.

[0130] When the data dump operation between the first page buffer unit PBU0 to the eighth page buffer unit PBU7 and the first cache unit CU0 to the eighth cache unit CU7 is completed, the read control signal DIO_R can be activated to a logic high level as an enable level during the fifth time period 145. Therefore, the data stored in each of the first cache unit CU0 to the eighth cache unit CU7 can be output via the data input / output line.

[0131] Figure 18This is a timing diagram illustrating an example of a data dump operation of the page buffer circuit 210a according to an embodiment of the present invention. (See also...) Figure 10 , Figure 16 and Figure 18 The data dumping operation of the page buffer circuit 210a may include a first time period 151 to a fifth time period 155. Within the first time period 151 to the fourth time period 154, data may be sequentially transferred between the first to fourth page buffer units (e.g., ...). Figure 10 PBU0 to PBU3) and the first to fourth high-speed buffer units (e.g., Figure 10 Data is transferred between CU0 to CU3. During the fifth period 155, data stored in the first cache unit CU0 to the eighth cache unit CU7 can be output via the data input / output line.

[0132] During the first time period 151, a data dump operation can be performed between the first page buffer unit PBU0 and the first cache unit CU0. The first time period 151 can correspond to the time period from the first time point t0 to the sixth time point t5. The operation of the page buffer circuit 210a during the first time period 151 will be described below. The operation of the page buffer circuit 210a during the second time period 152 to the fourth time period 154 can correspond to the operation of the page buffer circuit 210a during the first time period 151.

[0133] At the first time point t0, the load signal LOAD and the combined sensing node load signal SOC_LOAD can transition to a logic low as an enable level, and all precharge transistors PM0 to PM7 and PMa can be turned on, and the first sensing node SO0 to the eighth sensing node SO7 and the combined sensing node SOC can be precharged to the precharge level. Next, the control signal SO_PASS[7:0] can transition to a logic high as an enable level, and all first channel transistors TR0 to TR7 and second channel transistors TR0' to TR7' can be turned on. At the second time point t1, the load signal LOAD and the combined sensing node load signal SOC_LOAD can transition to a logic high as a deactivation level. The period from the first time point t0 to the second time point t1 can be referred to as the precharge period.

[0134] At the third time point t2, the first ground control signal SOGND is applied to the first page buffer unit PBU0. <0> It can be converted to a logic high as an enable level, and at the fourth time point t3, the first dump signal Dump_C is applied to the first cache unit CU0. <0> The data signal DI can be converted to a logic high as an enable level. At the fifth time point t4, through the control signal SO_PASS[7:0] and the first ground control signal SOGND... <0> First dump signal Dump_C <0> Both the data signal DI and the output signal DI can be converted to a logic low level as a disable level.

[0135] When the data dump operation between the first page buffer unit PBU0 to the eighth page buffer unit PBU7 and the first cache unit CU0 to the eighth cache unit CU7 is completed, the read control signal DIO_R can be changed to a logic high as an enable level during the fifth time period 155. Therefore, the data stored in each of the first cache unit CU0 to the eighth cache unit CU7 can be output via the data input / output line.

[0136] Figure 19 The arrangement of the first page buffer units PBU0 to the eighth page buffer unit PBU7 and the first cache unit CU0 to the eighth cache unit CU7 in a page buffer circuit 210c according to an embodiment of the present invention is shown. (See also...) Figure 2 and Figure 19 The first semiconductor layer L1 may include a first metal layer M1 extending in the first horizontal direction HD1, and multiple bit lines BL may be implemented as the first metal layer M1. The second semiconductor layer L2 may include a first lower metal layer LM0 extending in the first horizontal direction HD1. In this case, in the second horizontal direction HD2, the pitch of the first lower metal layer LM0 may be greater than the pitch of the first metal layer M1. For example, the pitch of the first lower metal layer LM0 may be approximately twice the pitch of the first metal layer M1.

[0137] The second semiconductor layer L2 may include a page buffer circuit 210c, and the page buffer circuit 210c may be implemented in the form of a page buffer array comprising multiple columns 2111 to 2114 in the second horizontal direction HD2. Each of the multiple columns 2111 to 2114 may include first page buffer units PBU0 to eighth page buffer units PBU7 and first cache units CU0 to eighth cache units CU7. For example, the configuration of each column in the multiple columns 2111 to 2114 may correspond to... Figure 9 and Figure 10 The page buffer circuit 210a shown in the figure or Figure 12 and Figure 13 The page buffer circuit 210b shown above, therefore, refers to...Figure 9 to Figure 18 The description can also be applied to this embodiment. Because the width of the transistor is reduced, and the size of the first page buffer unit PBU0 to the eighth page buffer unit PBU7 in the second horizontal direction HD2 is reduced, the page buffer circuit 210c can arrange more page buffer units in the same row. Therefore, the page buffer circuit 210c can include multiple columns 2111 to 2114.

[0138] The first column 2111 may include a first main region and a first cache region on the first horizontal direction HD1, where the first page buffer unit PBU0 to the eighth page buffer unit PBU7 may be located in the first main region, and the first cache unit CU0 to the eighth cache unit CU7 may be located in the first cache region. The second column 2112 may include a second main region and a second cache region on the first horizontal direction HD1, where the first page buffer unit PBU0a to the eighth page buffer unit PBU7a may be located in the second main region, and the first cache unit CU0a to the eighth cache unit CU7a may be located in the second cache region. The third column 2113 may include a third main region and a third cache region on the first horizontal direction HD1, where the first page buffer unit PBU0b to the eighth page buffer unit PBU7b may be located in the third main region, and the first cache unit CU0b to the eighth cache unit CU7b may be located in the third cache region. The fourth column 2114 may include a fourth main region and a fourth cache region on the first horizontal direction HD1. The first page buffer unit PBU0c to the eighth page buffer unit PBU7c may be located in the fourth main region, and the first cache unit CU0c to the eighth cache unit CU7c may be located in the fourth cache region.

[0139] In the first column 2111, the sensing nodes of each of the first page buffer units PBU0 to the eighth page buffer units PBU7 can be jointly connected to the first combined sensing node SOC1, and the first high-speed buffer units CU0 to the eighth high-speed buffer units CU7 can be jointly connected to the first combined sensing node SOC1. In the second column 2112, the sensing nodes of each of the first page buffer units PBU0a to the eighth page buffer units PBU7a can be jointly connected to the second combined sensing node SOC2, and the first high-speed buffer units CU0a to the eighth high-speed buffer units CU7a can be jointly connected to the second combined sensing node SOC2. In the third column 2113, the sensing nodes of each of the first page buffer units PBU0b to the eighth page buffer units PBU7b can be jointly connected to the third combined sensing node SOC3, and the first high-speed buffer units CU0b to the eighth high-speed buffer units CU7b can be jointly connected to the third combined sensing node SOC3. In the fourth column 2114, the sensing nodes of each of the first page buffer unit PBU0c to the eighth page buffer unit PBU7c can be jointly connected to the fourth combined sensing node SOC4, and the first high-speed buffer unit CU0c to the eighth high-speed buffer unit CU7c can be jointly connected to the fourth combined sensing node SOC4.

[0140] Figure 20 This is a block diagram of a storage device 10a according to an embodiment of the present invention. (Refer to...) Figure 20 The storage device 10a may include a storage cell array 100 and peripheral circuitry 200a. The storage device 10a may correspond to... Figure 1 A modified example of storage device 10, and refer to Figure 1 to Figure 19 The given description can also be applied to this embodiment. Figure 1 Compared to the storage device 10, the peripheral circuitry 200a may also include a page buffer decoder (PBDEC) 213, a quality bit counter (MBC) 214, and a pass / fail check unit 215.

[0141] PBDEC 213 can generate a decoder output signal DS corresponding to the number of failure bits using the page buffer signal PBS received from the page buffer circuit 210. For example, when the page buffer signal PBS is logic low, programming to the corresponding memory cell MC can be determined as a failure, and the data programmed into the corresponding memory cell MC can be determined as a failure bit. PBDEC 213 can receive a reference current from a current generator (not shown) and generate the decoder output signal DS based on the received reference current.

[0142] MBC 214 can receive the decoder output signal DS from PBDEC 213 and generate a counting result CNT from the decoder output signal DS. For example, MBC 214 may include an analog-to-digital converter that converts the analog-level decoder output signal DS into a counting result CNT as a digital value. MBC 214 can receive a reference current from a current generator (not shown) and generate the counting result CNT based on the received reference current.

[0143] The pass / fail check unit 215 receives the counting result CNT from the MBC 214, generates a pass signal PASS or a failure signal FAIL based on the counting result CNT, and provides the generated pass signal PASS or failure signal FAIL to the control circuit 220. For example, when the counting result CNT is less than or equal to the reference number, the pass / fail check unit 215 can generate a pass signal PASS. For example, when the counting result CNT is greater than the reference number, the pass / fail check unit 215 can generate a failure signal FAIL.

[0144] Figure 21 This is a plan view of the page buffer circuit 210d and the page buffer decoder (PBDEC) 213 according to an embodiment of the present invention. See also... Figure 2 and Figure 21 The first semiconductor layer L1 may include first bit line BL0 to eighth bit line BL7 extending in the first horizontal direction HD1, and the first bit line BL0 to eighth bit line BL7 may be implemented as a first metal layer M1. In an embodiment, the size of the page buffer circuit 210d in the second horizontal direction HD2 may correspond to the arrangement area of ​​the first bit line BL0 to eighth bit line BL7; therefore, the page buffer circuit 210d may include an eight-level page buffer. The page buffer circuit 210d may correspond to... Figure 9 and Figure 10 The page buffer circuit 210a shown in the figure or Figure 12 and Figure 13 The modified example of the page buffer circuit 210b shown is illustrated in the figure, and reference is made to... Figure 9 to Figure 20 The given description can also be applied to this embodiment.

[0145] The page buffer circuit 210d may include a first page buffer unit PBU0 to an eighth page buffer unit PBU7 on the first horizontal direction HD1, and each of the first page buffer units PBU0 to the eighth page buffer unit PBU7 may include a main unit and a high-voltage unit. For example, the first page buffer unit PBU0 may include a first main unit MU0 and a first high-voltage unit HVU0 on the first horizontal direction HD1.

[0146] The page buffer circuit 210d may further include multiple contact regions THVa to THVd. For example, the first contact region THVa may be located between the first page buffer unit PBU0 and the second page buffer unit PBU1, and a first bit line contact CT0 connected to the first bit line BL0 and a second bit line contact CT1 connected to the second bit line BL1 may be arranged in the first contact region THVa. The first bit line contact CT0 may be connected to a high-voltage transistor included in the first high-voltage unit HVU0 (e.g., Figure 6 TR_hv in the second high voltage unit HVU1), and the second bit line contact CT1 can be connected to the high voltage transistor included in the second high voltage unit HVU1.

[0147] The page buffer circuit 210d may further include a cache latch block 212, and the cache latch block 212 may include first to eighth cache latches respectively corresponding to the first page buffer unit PBU0 to the eighth page buffer unit PBU7 (e.g., Figure 5 (CL0 to CL7 in the middle). Page buffer circuit 210d may also include a precharge circuit SOC_PRE located between the eighth page buffer unit PBU7 and the cache latch block 212.

[0148] Additionally, PBDEC 213 can be adjacent to page buffer circuit 210d in the first horizontal direction HD1. PBDEC 213 can determine the number of pass bits and failure bits during programming verification operations. For example, PBDEC 213 may include multiple transistors connected between the cache latch and the global data line. In an embodiment, when a data dump operation is performed on PBDEC 213 via the S-LATCH SL of each of the first page buffer units PBU0 to the eighth page buffer units PBU7, the control signal SO_PASS[7:0] can be activated, and the first channel transistor and the second channel transistor can be turned on. Therefore, the sense node line and the combined sense node line can be used as data transmission lines, and data dump operations can be performed sequentially between the S-LATCH SL of the first page buffer units PBU0 to the eighth page buffer units PBU7 and PBDEC 213.

[0149] Figure 22 A page buffer circuit 210e and a PBDEC 213 according to an embodiment of the present invention are shown. (Refer to...) Figure 22 The page buffer circuit 210e may have a multi-level structure with multiple page buffers on the first horizontal direction HD1, for example, an 8-level structure including the first level STAGE0 to the eighth level STAGE7. In addition, in the page buffer circuit 210e, multiple columns including the first column 2111 and the second column 2112 may be on the second horizontal direction HD2.

[0150] PBDEC 213 may include multiple page buffer decoders, including a first PBDEC 213a and a second PBDEC 213b respectively connected to a first column 2111 and a second column 2112 included in page buffer circuit 210e. The first PBDEC 213a may include an inverter 2131 and transistors N0, N0', and N0" connected in series, and the second PBDEC 213b may include an inverter 2132 and transistors N0a, N0a', and N0a" connected in series. Inverters 2131 and 2132 may each receive a page buffer signal from their respective columns, and a reference current signal REF_CUR may be applied to the gate of each of transistors N0" and N0a".

[0151] For example, the first PBDEC 213a and the second PBDEC 213b can receive a first page buffer signal PBS1 and a second page buffer signal PBS2 from page buffer units PBU0 and PBU0a included in the first stage STAGE0, respectively. For example, when the memory cell MC connected to the page buffer unit PBU0 is determined to be a programming failure cell, a logic low can be stored in the S-LATCH SL of the page buffer unit PBU0. In this case, the first page buffer signal PBS1 can be a logic low as the voltage level of the first sensing node SO0, and the voltage level of the first combined sensing node SOC1 can also be a logic low. In this case, the inverter 2131 can output a logic high signal, so the transistor N0 can be turned on, and then the first PBDEC 213a can operate as a current sink.

[0152] Transistor N0" can output a first signal (i.e., a reference current) to the wiring OR terminal WOR_OUT based on the reference current signal REF_CUR. In this case, when transistor N0" is turned on according to the reference current signal REF_CUR, the reference current can correspond to the current flowing through transistor N0". Similarly, transistor N0a" can output a second signal (i.e., a reference current) to the wiring OR terminal WOR_OUT based on the reference current signal REF_CUR. The wiring OR terminal WOR_OUT can be commonly connected to the first PBDEC 213a and the second PBDEC 213b. Therefore, the first signal output from the first PBDEC 213a and the second signal output from the second PBDEC 213b can be accumulated in the wiring OR terminal WOR_OUT and generated as the decoder output signal DS. For example, the decoder output signal DS can correspond to the current signal I flowing through the wiring OR terminal WOR_OUT. WOR .

[0153] Figure 23 PBDEC 213 and MBC 214, embodiments of the present invention, are shown. See also... Figure 20 , Figure 22 and Figure 23 PBDEC 213 may include N PBDECs. In this case, N is a positive integer and may correspond to the number of columns included in the page buffer circuitry. For example, the first PBDEC 213a may include an inverter 2131 and transistors N0, N0', and N0" and transistor N0' may be referred to as the column enable transistor. MBC 214 may be connected to the wiring OR terminal WOR_OUT connected to the N PBDECs.

[0154] The MBC 214 can output signal DS (i.e., current signal I) from an analog-level decoder. WOR Generate a count result CNT (i.e., OUT) corresponding to the number of failure bits. <0> To OUT <9> MBC 214 may include multiple transistors P11, P12, P21, P22, P31, P32, N11, N12, N21, N22, and N23 constituting a reference current generator, a resistor R, and a differential amplifier 2141. Additionally, MBC 214 may also include transistors P1, P1a, P2, P2a, P9, P9a, N1, N1a, N2, N2a, N2b, N2c, N9, N9a, N9b, and N9c constituting a counting unit, and multiple comparators (comp) 2142 and 2143. In an embodiment, during the period when MBC 214 is enabled, transistors P11, P21, P31, N12, N23, P1a, P2a, P9a, N1a, N2a, N2c, N9a, and N9c may be turned on. In this embodiment, during the period when the operation of MBC 214 is disabled, transistors P11, P21, P31, N12, N23, P1a, P2a, P9a, N1a, N2a, N2c, N9a, and N9c can be turned off.

[0155] Reference voltage V ref The voltage across resistor R can be input to the first input terminal of differential amplifier 2141, and the voltage across resistor R can be input to the second input terminal. Transistors P11 and P12, along with resistor R, can form a feedback variable resistor unit, and the bias current Ibias can flow through resistor R. Transistors P21, P22, N11, and N12 can form a unit that generates the first reference current I. ref1 The first reference current generator, and resistors P31, P32, N21, N22, and N23 can be configured to generate the second reference current I. ref2The second reference current generator. The node voltage between transistors P32 and N21 in the second reference current generator can be provided to PBDEC 213 as a reference current signal REF_CUR.

[0156] Figure 24 This is a graph of the digital output signal OUT<9:0> of the MBC 214 according to an embodiment of the present invention. See also... Figure 22 to Figure 24 Transistors P1 and P2 can form a current mirror, and the current flowing through transistor P1 can correspond to the current signal I flowing through the wiring OR terminal WOR_OUT. WOR With the current signal I flowing through transistor N1 CR The sum. Comparator 2142 can be used to measure the voltage V at the WOR_OUT terminal of the wiring OR terminal. WOR The node voltage V between transistor P2 and transistor N2 R0 Compare to output the comparison result OUT <0> Similarly, comparator 2143 can measure the voltage V at the WOR_OUT terminal of the wiring OR terminal. WOR The node voltage V between transistor P9 and transistor N9 R9 Compare to output the comparison result OUT <9> Because the number of failure bits in the page buffer circuit 210e increases, the digital output signal OUT<9:0> of the MBC 214 can be increased. In this way, the MBC 214 can use comparators 2142 and 2143, and based on the current signal I output from the PBDEC 213... WOR Generate a digital output signal OUT<9:0>.

[0157] Figure 25 Multiple page buffers PGBUFa to PGBUFd, according to an embodiment of the present invention, are illustrated. (Refer to...) Figure 25 Multiple page buffers PGBUFa to PGBUFd can be adjacent to each other in the second horizontal direction HD2. For example, each of the multiple page buffers PGBUFa to PGBUFd can correspond to Figure 22 The page buffer circuit 210e in the circuit can therefore include multiple PBUs and multiple CUs that are adjacent to each other in the first horizontal direction HD1. Multiple page buffers PGBUFa to PGBUFd can be connected to the column driver Y_DRV.

[0158] Multiple PBDECs PBDECa to PBDECd can be configured to correspond to multiple page buffers PGBUFa to PGBUFd respectively. For example, corresponding page buffers PGBUFa and PBDEC PBDECa can be adjacent to each other in the first horizontal direction HD1. Multiple MBC cells 214a to 214d can be configured to correspond to multiple PBDECs PBDECa to PBDECd respectively. For example, the wiring OR terminal WOR_OUT_0 and the reference current signal terminal REF_CUR_0 of PBDEC PBDECa can be connected to MBC cell 214a.

[0159] Figure 26 This is a cross-sectional view of a storage device 500 according to an embodiment of the present invention. (Refer to...) Figure 26 The storage device 500 may have a chip-to-chip (C2C) structure. A C2C structure can refer to a structure where, after an upper chip including cell regions (also called memory cell regions) is fabricated on a first wafer, and a lower chip including peripheral circuit regions (PERIs) is fabricated on a second wafer different from the first wafer, the upper and lower chips are connected to each other using a bonding method. For example, the bonding method may refer to a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip to a bonding metal formed on the uppermost metal layer of the lower chip. For example, when the bonding metal includes copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also include aluminum or tungsten.

[0160] The peripheral circuit region (PERI) and cell region (CELL) of the storage device 500 may each include an external pad bonding region (PA), a word line bonding region (WLBA), and a bit line bonding region (BLBA). The peripheral circuit region (PERI) may include a first substrate 310, an interlayer insulating layer 315, a plurality of circuit elements 320a, 320b, and 320c formed on the first substrate 310, first metal layers 330a, 330b, and 330c respectively connected to the plurality of circuit elements 320a, 320b, and 320c, and second metal layers 340a, 340b, and 340c respectively formed on the first metal layers 330a, 330b, and 330c. Each of the circuit elements 320a, 320b, and 320c may include one or more transistors. In an embodiment, the first metal layers 330a, 330b, and 330c may include tungsten with relatively high resistance, and the second metal layers 340a, 340b, and 340c may include Cu with relatively low resistance.

[0161] In this specification, only the first metal layers 330a, 330b, and 330c and the second metal layers 340a, 340b, and 340c are shown and described; however, the invention is not limited thereto, and at least one or more metal layers may be further formed on the second metal layers 340a, 340b, and 340c. At least some of the metal layers formed on the second metal layers 340a, 340b, and 340c may include aluminum, etc., which have a lower resistivity than Cu formed on the second metal layers 340a, 340b, and 340c.

[0162] The interlayer insulating layer 315 may be located on the first substrate 310 to cover a plurality of circuit elements 320a, 320b and 320c, first metal layers 330a, 330b and 330c and second metal layers 340a, 340b and 340c, and may include insulating materials such as silicon oxide and silicon nitride.

[0163] The lower bonding metals 371b and 372b can be formed on the second metal layer 340b of the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 371b and 372b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 471b and 472b of the cell region CELL by a bonding method, and the lower bonding metals 371b and 372b and the upper bonding metals 471b and 472b can include aluminum, copper, tungsten, etc. The upper bonding metals 471b and 472b of the cell region CELL can be referred to as first metal pads, and the lower bonding metals 371b and 372b of the peripheral circuit region PERI can be referred to as second metal pads.

[0164] A cell region (CELL) can provide at least one memory block. The cell region (CELL) may include a second substrate 410 and a common source line 420. On the second substrate 410, multiple word lines 431 to 438 (i.e., word line 430) may be stacked in a direction VD perpendicular to the upper surface of the second substrate 410. A serial select line and a ground select line may be located above and below the word line 430, and the word line 430 may be located between the serial select line and the ground select line.

[0165] In the bit line bonding region BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 410 and can pass through the word line 430, the string select line, and the ground select line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer, and the channel layer may be electrically connected to the first metal layer 450c and the second metal layer 460c. For example, the first metal layer 450c may be a bit line contact, and the second metal layer 460c may be a bit line BL. In an embodiment, the second metal layer 460c (i.e., the bit line BL) may extend in a first horizontal direction HD1 parallel to the upper surface of the second substrate 410.

[0166] exist Figure 26 In the embodiment shown, the region where the channel structure CH and the second metal layer 460c (i.e., the bit line BL) are arranged can be defined as the bit line bonding region BLBA. The second metal layer 460c (i.e., the bit line BL) can be electrically connected to the circuit element 320c that provides the page buffer 493 in the peripheral circuit region PERI in the bit line bonding region BLBA. For example, the second metal layer 460c (i.e., the bit line BL) can be connected to the upper bonding metals 471c and 472c in the cell region CELL, and the upper bonding metals 471c and 472c can be connected to the lower bonding metals 371c and 372c that are connected to the circuit element 320c of the page buffer 493.

[0167] In the word line bonding area WLBA, word lines WL 430 can extend in a second horizontal direction HD2 parallel to the upper surface of the second substrate 410 and can be connected to a plurality of cell contact plugs 441 to 447 (i.e., cell contact plugs 440). Word lines WL 430 and cell contact plugs 440 can be connected to each other using pads that extend at least some word lines WL 430 to different lengths in the second horizontal direction HD2. A first metal layer 450b and a second metal layer 460b can be sequentially connected to the upper portion of the cell contact plugs 440 connected to the word lines WL 430. Cell contact plugs 440 in the word line bonding area WLBA can be connected to the peripheral circuit area PERI via upper bonding metals 471b and 472b of the cell area CELL and lower bonding metals 371b and 372b of the peripheral circuit area PERI.

[0168] The cell contact plug 440 can be electrically connected to circuit element 320b that provides a row decoder 494 in the peripheral circuitry region PERI. In an embodiment, the operating voltage of the circuit element 320b constituting the row decoder 494 may be different from the operating voltage of the circuit element 320c constituting the page buffer 493. For example, the operating voltage of the circuit element 320c constituting the page buffer 493 may be greater than the operating voltage of the circuit element 320b constituting the row decoder 494.

[0169] A common source line contact plug 480 may be located within the external pad bonding region PA. The common source line contact plug 480 may comprise a conductive material such as a metal, metal compound, or polysilicon, and may be electrically connected to the common source line 420. A first metal layer 450a and a second metal layer 460a may be sequentially stacked on the common source line contact plug 480. For example, the area where the common source line contact plug 480, the first metal layer 450a, and the second metal layer 460a are disposed may be defined as the external pad bonding region PA.

[0170] The first input / output pad 305 and the second input / output pad 405 can be located within the external pad bonding area PA. (Refer to...) Figure 26 A lower insulating layer 301 covering the lower surface of the first substrate 310 may be formed below the first substrate 310, and a first input / output pad 305 may be formed on the lower insulating layer 301. The first input / output pad 305 may be connected to at least one of a plurality of circuit elements 320a, 320b, and 320c in the peripheral circuit region PERI via a first input / output contact plug 303, and may be separated from the first substrate 310 by the lower insulating layer 301. In addition, a side insulating layer may be located between the first input / output contact plug 303 and the first substrate 310, and may electrically isolate the first input / output contact plug 303 from the first substrate 310.

[0171] Reference Figure 26 An upper insulating layer 401 covering the upper surface of the second substrate 410 may be formed on the second substrate 410, and a second input / output pad 405 may be formed on the upper insulating layer 401. The second input / output pad 405 may be connected to at least one of a plurality of circuit elements 320a, 320b and 320c in the peripheral circuit region PERI via a second input / output contact plug 403.

[0172] According to an embodiment, the second substrate 410, common source line 420, etc., may not be located in the area where the second input / output contact plug 403 is disposed. Additionally, the second input / output pad 405 may not overlap with the word line WL 430 in the third direction (vertical direction VD). (Refer to...) Figure 26 The second input / output contact plug 403 can be separated from the second substrate 410 in a direction parallel to the upper surface of the second substrate 410, and can be connected to the second input / output pad 405 through the interlayer insulating layer 415 and the upper insulating layer 401 passing through the cell region CELL.

[0173] According to embodiments, the first input / output pad 305 and the second input / output pad 405 can be selectively formed. For example, the storage device 400 may include only the first input / output pad 305 located on the first substrate 310, or it may include only the second input / output pad 405 located on the second substrate 410. Alternatively, the storage device 400 may include both the first input / output pad 305 and the second input / output pad 405.

[0174] In each of the external pad bonding area PA and bit line bonding area BLBA included in each of the cell region CELL and the peripheral circuit region PERI, the metal pattern of the uppermost metal layer may exist as a dummy pattern, or the uppermost metal layer may be empty.

[0175] In the external pad bonding area PA of the storage device 400, for the upper metal pattern 472a formed on the upper metal layer of the cell region CELL, a lower metal pattern 373a having the same shape as the upper metal pattern 472a in the cell region CELL can be formed on the upper metal layer of the peripheral circuit region PERI. The lower metal pattern 373a formed on the uppermost metal layer of the peripheral circuit region PERI may not be connected to a separate contact in the peripheral circuit region PERI. Similarly, for the lower metal pattern formed on the uppermost metal layer of the peripheral circuit region PERI in the external pad bonding area PA, an upper metal pattern having the same shape as the lower metal pattern in the peripheral circuit region PERI can be formed on the upper metal layer of the cell region CELL.

[0176] Lower bonding metals 371b and 372b can be formed on the second metal layer 340b of the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 371b and 372b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 471b and 472b of the cell region CELL by means of a bonding method.

[0177] Furthermore, in the bit line bonding region BLBA, for the lower metal pattern formed on the uppermost metal layer of the peripheral circuit region PERI, an upper metal pattern 492 having the same shape as the lower metal pattern 352 of the peripheral circuit region PERI can be formed on the upper metal layer of the cell region CELL. No contact may be formed on the upper metal pattern 492 formed on the uppermost metal layer of the cell region CELL.

[0178] In an example embodiment, storage device 500 (such as in...) Figure 26 (as described in) can be based on previous Figure 1 to Figure 25 Operates according to one or more example embodiments described herein and may include, according to, previously described Figure 1 to Figure 25 The apparatus components of one or more example embodiments described herein. In example embodiments, the storage cell region CELL may correspond to Figure 1 Storage cell array 100 and Figure 2 The first semiconductor layer L1. In the example embodiment, the peripheral circuit region PERI can correspond to... Figure 1 Peripheral circuit 200 and Figure 2 The second semiconductor layer L2.

[0179] Figure 27 This is a block diagram illustrating an example of applying a storage device to a solid-state drive (SSD) system 1000 according to some embodiments of the present invention. (Refer to...) Figure 27 The SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 can exchange signals with the host 1100 via a signal connector and receive power via a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and storage devices (MEMs) 1230, 1240, and 1250. Storage devices 1230, 1240, and 1250 may include vertically stacked NAND flash memory devices. In this case, storage devices 1230, 1240, and 1250 can be configured using the references above. Figure 1 to Figure 26 The described embodiments are implemented.

[0180] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the invention as defined in the appended claims.

Claims

1. A storage device, the storage device comprising: A storage cell array, wherein the storage cell array comprises a plurality of storage cells; as well as Page buffer circuit, the page buffer circuit comprising: Multiple page buffer units, the multiple page buffer units being connected to the memory unit in a first horizontal direction and via multiple bit lines, and Multiple cache latches, corresponding to multiple page buffer units, and connected to a combined sensing node in the first horizontal direction. The storage device is configured to: transmit data from the plurality of cache latches to the plurality of page buffer units or from the plurality of page buffer units to the plurality of cache latches via the combined sensing node. Each of the plurality of page buffer units includes one or more channel transistors connected to a sensing node of that page buffer unit, the sensing node being electrically connected to a corresponding bit line, and The sensing node of each of the plurality of page buffer units and the combined sensing node are electrically connected to each other through the channel transistor.

2. The storage device according to claim 1, wherein, The storage device is further configured to sequentially perform data transfer operations between the plurality of page buffer units and the plurality of cache latches.

3. The storage device according to claim 1, wherein, The storage device is also configured to sense data stored in the storage unit during the data sensing period, and The channel transistor is configured to be turned off during the data sensing period, such that the sensing nodes included in the plurality of page buffer units are not electrically connected to each other.

4. The storage device according to claim 1, wherein, The plurality of page buffer units include: A first page buffer unit, the first page buffer unit including a first channel transistor connected between a first sensing node and a first terminal, and a first master latch electrically connected to the first sensing node; and The second page buffer unit includes a second channel transistor connected to the first terminal and the second sensing node, and a second master latch electrically connected to the second sensing node. The first channel transistor and the second channel transistor are configured to be turned on during the data transmission period, so that the first sensing node and the second sensing node are electrically connected to each other.

5. The storage device according to claim 1, wherein, The plurality of page buffer units include: A first page buffer unit, the first page buffer unit including a first channel transistor located between a first terminal and a first sensing node, a second channel transistor located between the first sensing node and a second terminal, and a first master latch electrically connected to the first sensing node; and The second page buffer unit includes a third channel transistor located between the second terminal and the second sensing node, a fourth channel transistor located between the second sensing node and the third terminal, and a second master latch electrically connected to the second sensing node.

6. The storage device according to claim 5, wherein, The first page buffer unit further includes a first transistor connected between the first sensing node and the first master latch. The second page buffer unit further includes a second transistor connected between the second sensing node and the second master latch, and The first transistor and the second transistor are configured to be turned on sequentially during the data transmission period, such that the data stored in the first main latch and the data stored in the second main latch are sequentially transmitted to the first cache latch and the second cache latch of the plurality of cache latches, respectively.

7. The storage device according to claim 5, wherein, The plurality of high-speed cache latches include: A first cache latch, the first cache latch including a first dump transistor and corresponding to the first page buffer cell, the first dump transistor being configured to be driven according to a first dump signal; and A second cache latch, comprising a second dump transistor and corresponding to the second page buffer cell, the second dump transistor being configured to be driven according to a second dump signal. The first dump transistor and the second dump transistor are configured to be turned on sequentially during the data transmission period, such that the data stored in the first main latch and the data stored in the second main latch are sequentially transmitted to the first cache latch and the second cache latch of the plurality of cache latches, respectively.

8. The storage device according to claim 7, wherein, The page buffer circuit further includes a precharge transistor configured to precharge the combined sensing node between the second page buffer unit and the first cache latch. The precharge transistor is configured to be turned on during the precharge period and precharge the combined sensing node to the precharge level.

9. The storage device according to claim 5, wherein, The first channel transistor, the second channel transistor, the third channel transistor, and the fourth channel transistor are configured to be electrically connected in series with each other in response to the first channel transistor, the second channel transistor, the third channel transistor, and the fourth channel transistor being turned on, such that the first sensing node and the second sensing node are electrically connected to each other, and data is transferred from the first cache latch among the plurality of cache latches to the first master latch or from the first master latch to the first cache latch.

10. The storage device according to claim 5, wherein, The third-channel transistor and the fourth-channel transistor are configured to be electrically connected in series with each other in response to the third-channel transistor and the fourth-channel transistor being turned on, such that data is transferred from the second cache latch of the plurality of cache latches to the second master latch or from the second master latch to the second cache latch.

11. The storage device according to claim 5, wherein, Both the first master latch and the second master latch include at least one of a sensing latch, a forced latch, a high-order latch, and a low-order latch.

12. The storage device according to claim 1, wherein, The plurality of page buffer units are plurality of first page buffer units, and the plurality of cache latches are plurality of first cache latches. The page buffer circuit further includes a plurality of second page buffer units in the first horizontal direction and a plurality of second high-speed cache latches in the first horizontal direction, each corresponding to one of the plurality of second page buffer units. Wherein, the plurality of first page buffer units and the plurality of second page buffer units are adjacent to each other in a second horizontal direction perpendicular to the first horizontal direction, and The plurality of first high-speed buffer latches and the plurality of second high-speed buffer latches are adjacent to each other in the second horizontal direction.

13. The storage device according to claim 1, wherein, The memory cell array is located on the first semiconductor layer. The page buffer circuit is located on the second semiconductor layer. Wherein, the first semiconductor layer and the second semiconductor layer are stacked in the vertical direction, and The multiple bit lines all extend in the first horizontal direction.

14. A storage device, the storage device comprising: A first semiconductor layer, the first semiconductor layer including a plurality of memory cells, the plurality of memory cells being respectively connected to a plurality of bit lines extending in a first horizontal direction; as well as A second semiconductor layer, located vertically to the first semiconductor layer, includes a page buffer circuit. The page buffer circuit includes: The main region, comprising a plurality of page buffer units in the first horizontal direction; and A high-speed buffer region, adjacent to the main region in the first horizontal direction, includes a plurality of high-speed buffer latches in the first horizontal direction, the plurality of high-speed buffer latches being connected to a combined sensing node. Each of the plurality of page buffer units includes a main latch and one or more channel transistors connected to a sensing node of that page buffer unit, the sensing node being electrically connected to a corresponding bit line, and The sensing nodes in each of the plurality of page buffer units and the combined sensing node are electrically connected to each other through the channel transistor, such that the plurality of page buffer units are electrically connected to the plurality of cache latches.

15. The storage device according to claim 14, wherein, The plurality of page buffer units include: A first page buffer unit, the first page buffer unit including a first channel transistor located between a first terminal and a first sensing node, a second channel transistor located between the first sensing node and a second terminal, and a first master latch electrically connected to the first sensing node; and The second page buffer unit includes a third channel transistor located between the second terminal and the second sensing node, a fourth channel transistor located between the second sensing node and the third terminal, and a second master latch electrically connected to the second sensing node.

16. The storage device according to claim 14, wherein, The second semiconductor layer further includes a page buffer decoder adjacent to the plurality of cache latches in the first horizontal direction, and The page buffer decoder is connected to the combined sensing node, such that the sensing node and the page buffer decoder in each of the plurality of page buffer units are electrically connected to each other through the channel transistor.

17. A storage device, the storage device comprising: A storage cell region, the storage cell region including a plurality of storage cells and a first metal pad; as well as A peripheral circuit region, including a second metal pad, is vertically connected to the memory cell region via the first and second metal pads. The peripheral circuit region includes a page buffer circuit, which includes: Multiple page buffer units in a first horizontal direction, the multiple page buffer units being connected to the memory unit via multiple bit lines, and Multiple cache latches are provided in the first horizontal direction, each corresponding to a multiple page buffer unit and connected to the combined sensing node. Each of the plurality of page buffer units includes a channel transistor connected to a sensing node of that page buffer unit, the sensing node being electrically connected to a corresponding bit line, and The sensing nodes and the combined sensing nodes included in the plurality of page buffer units are electrically connected to each other through the channel transistors included in the plurality of page buffer units.

18. The storage device according to claim 17, wherein, The first metal pad and the second metal pad comprise copper.

19. The storage device according to claim 17, wherein, The first metal pad and the second metal pad are connected to each other by means of bonding.

20. The storage device according to claim 17, wherein, The memory cell region is located on the first wafer, and the peripheral circuit region is located on the second wafer.

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