Method for manufacturing semiconductor structure

Abstract

An embodiment of the present invention provides a method for manufacturing a semiconductor structure. The method includes: providing a substrate structure; the substrate structure includes a first opening; forming a first dielectric layer of a first thickness on the sidewalls of the first opening; the thickness of the first dielectric layer decreases as the depth of the first opening increases; ion implanting the first dielectric layer to form a doped layer on a portion of the first dielectric layer; etching the doped layer to remove a portion of the doped layer to obtain a first dielectric layer of a second thickness, the second thickness being less than the first thickness; wherein, during the etching process, the amount of etching of the doped layer by the etching source decreases as the depth of the first opening increases.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure. Background Art

[0002] In related technologies, atomic layer deposition (ALD) is typically used to form a dielectric layer with good step coverage in a channel hole (CH) with a certain opening depth. This minimizes the electrical difference between the top and bottom of the channel hole and meets process requirements. However, as the channel hole depth increases, ALD technology faces challenges.

[0003] Therefore, there is an urgent need for an effective method for manufacturing a semiconductor structure that can improve the morphology of a deposited dielectric layer when depositing a thin film in a deep opening, thereby reducing the adverse effects of the poor morphology of the dielectric layer on the electrical performance of the semiconductor device. Summary of the Invention

[0004] To solve related technical problems, the manufacturing method of the semiconductor structure proposed in an embodiment of the present invention can improve the morphology of the deposited dielectric layer when depositing a thin film in a deeper opening, thereby reducing the adverse effects of the poor morphology of the dielectric layer on the electrical performance of the semiconductor device.

[0005] An embodiment of the present invention provides a method for manufacturing a semiconductor structure, comprising:

[0006] Providing a substrate structure; the substrate structure includes a first opening; forming a first dielectric layer of a first thickness on a sidewall of the first opening; the thickness of the first dielectric layer decreases as the depth of the first opening increases;

[0007] Performing ion implantation on the first dielectric layer so that a portion of the first dielectric layer forms a doped layer;

[0008] The doped layer is etched to remove a portion of the doped layer to obtain a first dielectric layer of a second thickness, where the second thickness is less than the first thickness; wherein, during the etching process, the amount of etching of the doped layer by the etching source decreases as the depth of the first opening increases.

[0009] In the above solution, the doping concentration of the doping layer decreases as the depth of the first opening increases;

[0010] The etching of the doped layer comprises:

[0011] The doping layer is wet-etched, wherein during the wet etching process, an etching rate of the doping layer by an etching source decreases as the doping concentration of the doping layer decreases.

[0012] In the above solution, the ion implantation into the first dielectric layer includes:

[0013] Ions are implanted into the first dielectric layer of the first thickness using a plasma doping (PLAD) process.

[0014] In the above solution, during the ion implantation process, the material of the dopant used includes an inert element.

[0015] In the above solution, during the ion implantation process, the doping energy used is 100V-1000V.

[0016] In the above solution, the ratio of the first thickness to the second thickness is in the range of 2:1 to 3:1.

[0017] In the above solution, the material of the first dielectric layer includes silicon oxide, silicon nitride, aluminum oxide, titanium nitride or polysilicon.

[0018] In the above solution, forming a first dielectric layer of a first thickness on the sidewall of the first opening includes:

[0019] A first dielectric layer with a first thickness is formed at least on the sidewall of the first opening by using a chemical vapor deposition method.

[0020] In the above solution, providing a base structure includes:

[0021] Providing a semiconductor substrate, on which a stack structure having insulating layers and sacrificial layers alternately stacked is formed;

[0022] forming a plurality of channel holes penetrating the stacked structure;

[0023] The step of forming a first dielectric layer of a first thickness on the sidewall of the first opening includes:

[0024] A first dielectric layer with a first thickness is formed on the sidewalls of the channel hole.

[0025] In the above solution, the method further includes:

[0026] Before forming a first dielectric layer with a first thickness on the sidewall of the channel hole, forming a second dielectric layer on the sidewall of the channel hole;

[0027] The step of forming a first dielectric layer of a first thickness on the sidewall of the channel hole comprises:

[0028] A first dielectric layer having a first thickness is formed on a surface of the second dielectric layer.

[0029] The present invention provides a method for manufacturing a semiconductor structure, comprising: providing a substrate structure; the substrate structure including a first opening; forming a first dielectric layer of a first thickness on the sidewall of the first opening; the thickness of the first dielectric layer decreasing as the depth of the first opening increases; ion implanting the first dielectric layer to form a doped layer in a portion of the first dielectric layer; etching the doped layer to remove a portion of the doped layer to obtain a first dielectric layer of a second thickness, the second thickness being less than the first thickness; wherein, during the etching process, the amount of etching of the doped layer by the etching source decreases as the depth of the first opening increases. In the present invention, when depositing a thin film in the opening, a dielectric layer thicker than the desired thickness is first deposited, the thickness of the thicker dielectric layer decreasing as the depth of the opening increases; then ion implanting the thicker dielectric layer to form a doped layer, the thickness of the doped layer remaining substantially constant as the depth of the first opening increases; and then, when removing a portion of the doped layer, the thickness of the thicker dielectric layer removed decreases as the depth of the opening increases, thereby significantly improving the uniformity of the thickness of the desired dielectric layer. Thus, the method for manufacturing a semiconductor structure provided by an embodiment of the present invention can improve the morphology of the deposited dielectric layer when depositing a thin film in a deep opening, thereby reducing the adverse effects of the poor morphology of the dielectric layer on the electrical performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1a Schematic diagram of the density distribution of the gas used to form the dielectric layer in the opening in an embodiment of the present invention;

[0031] Figure 1b Schematic diagram of the morphology of the deposited dielectric layer when depositing a thin film in an opening with a high aspect ratio;

[0032] Figure 2 A schematic diagram of a process flow for implementing a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;

[0033] Figure 3a-3d A schematic cross-sectional view of a manufacturing process of a semiconductor structure provided by an embodiment of the present invention;

[0034] Figure 4 Schematic diagram of the distribution of thin films in the ONOP structure of a three-dimensional memory according to an embodiment of the present invention;

[0035] Figure 5a-5f A cross-sectional schematic diagram of a manufacturing process of another semiconductor structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to make the technical solutions and advantages of the embodiments of the present invention more clear, the specific technical solutions of the invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0037] In the manufacturing process of semiconductor devices, it is often necessary to form a dielectric layer in an opening with a high aspect ratio (HAR). The step coverage of the dielectric layer is generally measured by the ratio of the thickness of the dielectric layer at the bottom of the opening (Btop) to the thickness of the dielectric layer at the top of the opening (Ttop). Ideally, the thickness of the dielectric layer remains constant as the depth of the opening increases, that is, the step coverage is 1. However, in actual applications, the density distribution of the gas used to form the dielectric layer in the opening is as follows: Figure 1a As shown, the thickness of the dielectric layer decreases with the increase of the depth, so the thickness of the dielectric layer decreases with the increase of the opening depth, that is, the step coverage is less than 1, showing a thick top and thin bottom shape (such as Figure 1b However, when the step coverage is low, it can affect the electrical performance of the semiconductor device. For example, when the opening is a channel hole of a three-dimensional memory device, and the step coverage of the charge trapping layer in the channel hole is less than 95%, the electrical properties of the upper and lower portions of the channel hole differ significantly, failing to meet process requirements.

[0038] In the manufacturing process of typical semiconductor structures, such as three-dimensional NAND memory, the uniformity of the dielectric layer deposited in the channel hole is required to ensure electrical consistency across the entire channel. In related technologies, ALD (Automatic Lamination) is typically used to deposit the corresponding dielectric layer in a channel hole with a certain opening depth. It is understood that due to the highly controllable deposition parameters and high step coverage of ALD technology, the dielectric layer formed using ALD has relatively high uniformity.

[0039] However, as the number of stacked layers in 3D NAND memories continues to increase, the dielectric layer formed using a single-step ALD process may experience reduced step coverage, resulting in insufficient uniformity and potential current leakage. In this case, a two-step or more ALD process is required to form the required dielectric layer to meet the required step coverage. However, this significantly increases process costs.

[0040] Based on this, in each embodiment of the present invention, when depositing a thin film in an opening with a deeper depth, a dielectric layer thicker than the thickness to be deposited is first deposited, and the thickness of the thicker dielectric layer decreases as the depth of the opening increases; then, ion implantation is performed on the thicker dielectric layer to form a doped layer, and the thickness of the doped layer remains substantially unchanged as the depth of the first opening increases; thereafter, when part of the doped layer is removed, the thickness of the thicker dielectric layer removed decreases as the depth of the opening increases, thereby greatly improving the uniformity of the thickness of the dielectric layer to be deposited. In this way, the manufacturing method of the semiconductor structure provided by the embodiment of the present invention can improve the morphology of the deposited dielectric layer when depositing a thin film in an opening with a deeper depth, thereby reducing the adverse effects of the poor morphology of the dielectric layer on the electrical performance of the semiconductor device. At the same time, the manufacturing method of the semiconductor structure provided by the embodiment of the present invention does not need to be deposited in many steps, thereby reducing the manufacturing cost.

[0041] An embodiment of the present invention provides a method for manufacturing a semiconductor structure. Figure 2 Schematic diagram of the implementation process of the method for manufacturing a semiconductor structure provided by an embodiment of the present invention. Figure 2 As shown, the method includes the following steps:

[0042] Step 201: Providing a base structure; the base structure includes a first opening;

[0043] Step 202: forming a first dielectric layer of a first thickness on the sidewall of the first opening; the thickness of the first dielectric layer decreases as the depth of the first opening increases;

[0044] Step 203: performing ion implantation on the first dielectric layer to form a doped layer on a portion of the first dielectric layer;

[0045] Step 204: Etching the doped layer to remove a portion of the doped layer to obtain a first dielectric layer of a second thickness, where the second thickness is less than the first thickness; wherein, during the etching process, the amount of etching of the doped layer by the etching source decreases as the depth of the first opening increases.

[0046] Figure 3a-3d FIG1 is a cross-sectional diagram of a semiconductor structure manufacturing process according to an embodiment of the present invention. Figure 2 and Figure 3a-3d The method for forming the semiconductor structure of this embodiment is described.

[0047] Among them, in step 201, if Figure 3a As shown, a base structure 30 is mainly provided.

[0048] In practical applications, the base structure 30 may include a semiconductor substrate 301 and a thin film structure 302 formed on the substrate. The specific materials of the thin film structure 302 are not limited herein. The first opening 303 may be a groove or hole structure etched in the base structure 30. In practical applications, the cross-section of the first opening 303 may be circular, elliptical, or elongated. Figure 3a A schematic cross-sectional view of the base structure 30 is shown in FIG.

[0049] It should be noted that the depth of the first opening 303 is greater than the preset depth. It is understandable that when a thin film is deposited in an opening with a very shallow depth using a deposition process, due to the shallow depth of the opening, the deposition environment at the top and bottom of the opening is similar, and the thickness of the film deposited at the top and bottom of the opening is close. However, as the depth of the opening gradually increases, the deposition environment at the top and bottom of the opening, such as the distribution of deposition gas, gradually becomes different. At the same time, the difference in the thickness of the film deposited at the top and bottom of the opening will also widen. The preset depth here refers to the threshold depth at which the difference in the thickness of the film deposited at the top and bottom of the opening begins to become obvious; after the opening depth is greater than the preset depth, the difference in the thickness of the film deposited at the top and bottom of the opening begins to become obvious. In practical applications, the preset depth here can be adjusted according to actual conditions.

[0050] That is to say, in the first opening with a deeper depth, especially in the deep HAR opening, the phenomenon that the density distribution of the gas introduced into the opening decreases with the increase of the opening depth is more obvious. At this time, the phenomenon that the thickness of the film deposited on the side wall of the opening decreases with the increase of the thickness is also more obvious.

[0051] In practical applications, the verticality of the sidewall of the first opening 303 is relatively good, that is, the opening size of the first opening 303 remains substantially unchanged as the depth increases.

[0052] In practical applications, a first opening 303 with good verticality can be obtained through a variety of methods, and the methods for obtaining the first opening 303 with good verticality are not limited here. One specific implementation method includes: performing a first etching on the base structure 30 to remove a portion of the base structure 30, thereby forming a first opening 303 having a first depth in the base structure 30; forming a protective layer that at least covers the sidewalls of the first opening 303; performing a second etching on the first opening 303 to increase the depth of the first opening 303 to a second depth; wherein, during the second etching process, the protective layer is consumed to compensate for the etching effect perpendicular to the sidewalls of the first opening 303. In this way, a first opening 303 with a relatively deep depth can be obtained, and the opening size remains substantially unchanged as the depth increases.

[0053] In step 202, if Figure 3b As shown, a first dielectric layer 304 with a first thickness is mainly formed.

[0054] In practical applications, a first gas is introduced into the first opening 303, forming a first dielectric layer 304 having a first thickness on the sidewalls of the first opening 303. It is understood that within the first opening 303, the distribution of the first gas decreases as the depth of the opening increases, thereby causing the thickness of the formed first dielectric layer to decrease as the depth of the first opening increases. Here, the thickness of the first dielectric layer 304 having the first thickness decreases as the depth of the first opening 303 increases.

[0055] In practical applications, it is necessary to control deposition process parameters so that a first dielectric layer 304 having a first thickness is formed on the sidewall of the first opening 303. Here, the first thickness is greater than the thickness of the dielectric layer to be ultimately obtained.

[0056] In practical applications, the material of the first dielectric layer 304 with the first thickness includes a material capable of ion implantation.

[0057] In some embodiments, the material of the first dielectric layer 304 with the first thickness may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), titanium nitride (TiN), or polysilicon (Poly).

[0058] For example, when the material of the first dielectric layer 304 having the first thickness includes silicon nitride, the first gas may include dihydrogen dichlorosilane and ammonia.

[0059] In practical applications, dichlorosilane gas and ammonia gas are introduced into the first opening 303 . Under reaction conditions of 700° C. to 800° C., the dichlorosilane and ammonia gas react to form silicon nitride, which is deposited on the sidewalls of the first opening 303 to form a first dielectric layer 304 of a first thickness.

[0060] In some embodiments, forming a first dielectric layer 304 having a first thickness on a sidewall of the first opening 303 includes:

[0061] A first dielectric layer 304 with a first thickness is formed at least on the sidewall of the first opening 303 by using a chemical vapor deposition (CVD) method.

[0062] It should be noted that, in actual applications, when the first dielectric layer 304 of the first thickness is formed on the sidewall of the first opening 303, the first dielectric layer is also deposited on the bottom of the first opening 303. Since the improvements involved in the embodiments of the present invention do not focus on the deposition at the bottom of the first opening 303, Figure 3b The bottom deposited first dielectric layer is not shown.

[0063] It can be understood that, here, the density distribution of the first gas in the first opening 303 decreases with the increase of the opening depth, that is, there is more first gas at the top of the first opening 303 and less first gas at the bottom of the first opening 303, so that the first dielectric layer 304 of the first thickness formed also shows that the thickness decreases with the increase of the opening depth.

[0064] In step 203, if Figure 3c As shown, the first dielectric layer having a doped layer is mainly formed.

[0065] In some embodiments, the ion implantation into the first dielectric layer includes: performing ion implantation into the first dielectric layer 304 of the first thickness using a PLAD process. Here, the PLAD process includes a plasma diffusion process and an ion implantation process.

[0066] During the plasma diffusion process, a second gas, which can be understood as a dopant gas, is first introduced into the first opening 303. The plasma diffusion process ionizes the dopant gas into dopant ions, which are then concentrated on the surface of the first dielectric layer 304 having a first thickness. Within the first opening 303, the distribution of dopant ions decreases as the depth of the opening increases. It is understood that the greater the distribution of dopant ions concentrated on the surface of the first dielectric layer 304 having a first thickness, the higher the ion doping concentration in the doped layer 305 after ion implantation.

[0067] In the ion implantation process, a bias voltage of a certain voltage value is applied to the semiconductor substrate 301. Here, the bias voltage is the doping energy. This causes the dopant ions gathered on the surface of the first dielectric layer 304 of the first thickness to be implanted into the first dielectric layer 304 of the first thickness in the form of an ion beam. The high-energy ions lose energy due to collisions with electrons and atomic nuclei in the first dielectric layer 304 of the first thickness, and finally stop at a certain depth within the lattice, so that a doped layer 305 is formed in a partial area of the first dielectric layer 304 of the first thickness. At this point, a first dielectric layer having a doped layer is formed.

[0068] It is understood that PLAD is a doping method that excites a dopant into a plasma state and then implants the dopant ions in the excited plasma into a sample. For example, when a bias voltage is applied to the sample, the dopant ions in the plasma are simultaneously accumulated on the sample surface. Here, the bias voltage can be referred to as the doping energy.

[0069] In some embodiments, during the ion implantation process, the doping energy used is 100V-1000V.

[0070] In some embodiments, during the ion implantation process, the dopant material used includes an inert element.

[0071] Here, during the ion implantation process, an inert element that does not affect the electrical properties of the dielectric layer may be selected; wherein the inert element may include helium (He), argon (Ar), krypton (Kr), and xenon (Xe).

[0072] In practical applications, different doping depths and doping concentrations can be set according to the actual requirements of the semiconductor structure. The doping depth can be controlled by adjusting the acceleration energy of the ion beam.

[0073] Here, a PLAD process is used to perform ion implantation on the first dielectric layer 304 of a first thickness to form a doped layer 305. The depth of the ion implantation is the doping depth, which is also the thickness of the doped layer 305. In practical applications, under a constant doping energy, the thickness of the formed doped layer remains substantially constant as the depth of the first opening 303 increases.

[0074] In practical applications, when performing an ion implantation process, the doping concentration can be controlled by adjusting the doping energy and monitoring the ion current.

[0075] In some embodiments, the doping concentration of the doping layer 305 decreases as the depth of the first opening 303 increases.

[0076] It is understandable that, due to different doping concentrations of the doping layer 305 , the etching rates thereof are different, so that within the same etching time, the amount of the doping layer removed is also different.

[0077] It should be noted that, since the first dielectric layer 304 of the first thickness decreases as the depth of the first opening 303 increases, the doping concentration varies. In practical applications, the degree of doping concentration variation can be adjusted by controlling the dopant dosage. In some specific embodiments, the doping dosage range can be 5.0*10 15 / cm 2 Up to 5.0*10 16 / cm 2 .

[0078] In practical applications, the PLAD process can be used to more accurately control the doping concentration and doping depth in the process of ion implantation to form a doping layer, and it is repeatable.

[0079] In some specific embodiments, in the first dielectric layer having the doped layer, the doping concentration of the doping layer 305 located at the top of the first opening 303 is greater than the doping concentration of the doping layer located at the bottom of the first opening 303; Figure 3c, and the thickness of the formed doping layer remains substantially unchanged as the depth of the first opening 303 increases.

[0080] In step 204, if Figure 3d As shown, a portion of the doped layer 305 is removed to obtain a first dielectric layer 306 of the second thickness.

[0081] In practical applications, when etching the doping layer 305 , the etching method may include wet etching and dry etching.

[0082] In some embodiments, etching the doping layer 305 includes:

[0083] The doping layer 305 is wet-etched, wherein during the wet etching process, the etching speed of the doping layer by the etching source decreases as the doping concentration of the doping layer decreases.

[0084] It is understood that wet etching is a technique of etching by immersing the etching material in an etching solution. Here, the first dielectric layer having the doped layer is immersed in the etching solution so that part of the doped layer 305 is removed.

[0085] In practical applications, in the process of removing a portion of the doping layer 305 using a wet etching process, the wet etching process may include using a hydrofluoric acid (HF) solution or a phosphoric acid (H 3 PO 4 ) solution to perform the removal operation of the doping layer.

[0086] It should be noted that, when the material of the first dielectric layer includes oxide, the etching solution may be HF solution; when the material of the first dielectric layer includes nitride, the etching solution may be H 3 PO 4 solution.

[0087] Here, the dopant ions in the doping layer 305 react with the etching solution, so that a portion of the doping layer 305 is removed.

[0088] Here, the higher the ion doping concentration in the doping layer 305 is, the faster the reaction rate is, the faster the rate at which the doping layer 305 is etched is, and the greater the amount of the doping layer 305 consumed is.

[0089] In actual applications, since the doping concentration of the doping layer 305 located at the top of the first opening 303 is greater than the doping concentration of the doping layer located at the bottom of the first opening 303, within the same etching time, the etching amount of the doping layer 305 located at the top of the first opening 303 is greater than the etching amount of the doping layer located at the bottom of the first opening 303.

[0090] That is, the doping concentration of the doped layer 305 formed in step 203 decreases as the depth of the first opening 303 increases. Therefore, during the wet etching process, the amount of etching of the doped layer 305 by the etching source decreases as the depth of the first opening 303 increases, thereby obtaining a first dielectric layer 306 of the second thickness with better verticality.

[0091] In practical applications, a dry etching process can also be used to remove part of the doped layer 305. During the dry etching process, since the density of the dry etching gas introduced into the first opening 303 decreases as the depth of the first opening 303 increases, the amount of etching on the doped layer 305 also decreases as the depth of the opening increases.

[0092] Therefore, during the dry etching process, the amount of etching gas on the doped layer 305 will decrease as the depth of the first opening 303 increases, thereby obtaining the first dielectric layer 306 of the second thickness with good verticality.

[0093] In some embodiments, a ratio of the first thickness to the second thickness is in a range of 2:1 to 3:1.

[0094] In practical applications, the second thickness of the first dielectric layer 306 can be understood as the final desired dielectric layer; here, the first thickness can be understood as 2 to 3 times the thickness of the final desired dielectric layer. For example, if the final desired dielectric layer thickness is 30 angstroms, the first thickness can be 60 to 90 angstroms.

[0095] It can be understood that after removing part of the doped layer 305, the thickness of the first dielectric layer 304 with the first thickness that is removed decreases as the opening increases. The removed portion well compensates for the original morphological difference of the first dielectric layer 304 with the first thickness, thereby greatly improving the uniformity of the first dielectric layer 306 with the second thickness.

[0096] It should be noted that if Figure 3d As shown, the first dielectric layer 306 of the second thickness includes a portion of the doped layer 305. It is understandable that, because the doping elements are selectively selected when forming the doped layer 305, even if the first dielectric layer 306 of the second thickness has a portion of the doped layer 305, it will not affect the original performance of the first dielectric layer 306 of the second thickness.

[0097] Here, the PLAD process combined with wet / dry etching can well control the thickness of the doped layer, and therefore can well control the uniformity of the second-thickness first dielectric layer 306; so that the step coverage of the formed second-thickness first dielectric layer 306 is better, thereby improving the electrical performance of the semiconductor device.

[0098] In practical applications, the embodiment of the present invention may also be used to improve the morphology of the dielectric layer deposited again in the first opening 303 where the dielectric layer has already been deposited.

[0099] Based on this, in some embodiments, the method further includes:

[0100] Before forming the first dielectric layer 304 with a first thickness on the sidewall of the channel hole, forming a second dielectric layer on the sidewall of the channel hole;

[0101] The step of forming a first dielectric layer 304 of a first thickness on the sidewall of the channel hole comprises:

[0102] A first dielectric layer 304 having a first thickness is formed on the surface of the second dielectric layer.

[0103] Here, the second dielectric layer has good step coverage, meaning that the thickness of the second dielectric layer remains substantially constant as depth increases. When the second dielectric layer is made of a material capable of ion implantation, the method of an embodiment of the present invention can be used to obtain a second dielectric layer with good step coverage. When the second dielectric layer is made of a material not capable of ion implantation, other methods suitable for materials not capable of ion implantation can be used to obtain a second dielectric layer with good step coverage.

[0104] It is understandable that in the related art, the density distribution of the gas used for deposition in the first opening 303 decreases as the depth of the opening increases, and the morphology of the first dielectric layer 304 of the first thickness formed also decreases as the depth of the opening increases. In some embodiments of the present invention, by controlling the PLAD process, ion implantation is performed on the first dielectric layer 304 of the first thickness, and the thickness of the doped layer 305 formed remains substantially unchanged as the depth of the first opening 303 increases, while the ion doping concentration in the doped layer decreases as the depth of the first opening 303 increases. Then, by wet etching the doped layer, the amount of etching of the doped layer 305 by the etching source decreases as the depth of the first opening 303 increases; thereby, the thickness of the final deposited layer above and below the opening is completely consistent. The thickness uniformity of the final dielectric layer is necessarily better than that of the dielectric layer obtained by direct deposition, that is, the morphology of the dielectric layer is improved.

[0105] Thus, the method for manufacturing a semiconductor structure provided by the embodiment of the present invention can improve the morphology of the dielectric layer when depositing a thin film in a deep opening, thereby reducing the adverse effects of the poor morphology of the dielectric layer on the electrical performance of the semiconductor device.

[0106] In practical applications, the first opening 303 can be used to form a channel hole structure of a three-dimensional memory, the second dielectric layer can be used to form a blocking dielectric layer of the three-dimensional memory, and the first dielectric layer 306 of the second thickness can be used to form a charge trapping layer of the three-dimensional memory. Specifically:

[0107] One application scenario of the embodiment of the present invention is to form a charge trapping layer in the channel hole of a three-dimensional memory. In the manufacturing process of the three-dimensional memory, it is necessary to form a memory material layer (i.e., ONOP structure) in the channel hole. Here, the distribution of the thin film in the ONOP structure is as follows: Figure 4 As shown. Figure 4 It can be seen that the ONOP structure includes four thin films, specifically including a blocking dielectric layer, a charge trapping layer, a tunneling dielectric layer and a channel layer stacked in sequence along the radial direction of the channel hole; wherein, the blocking dielectric layer covering the sidewall surface of the channel hole is used to reduce the probability of the charge in the memory cell moving to the gate of the memory cell, and the material of the blocking dielectric layer may include: oxide (OX); the charge trapping layer covering the surface of the blocking dielectric layer is used to capture the charge, and the material of the charge trapping layer may include: silicon nitride (SiN); the tunneling dielectric layer covering the surface of the charge trapping layer is used to tunnel the charge between the channel region and the charge trapping layer under the action of an external voltage, and the material of the tunneling dielectric layer may include: oxide (OX); the channel layer covering the surface of the tunneling dielectric layer is used for the channel layer to play a supporting role, and the material of the channel layer may include: polysilicon (Poly).

[0108] In practical applications, the step coverage of each thin film layer in the ONOP thin film structure is very critical and must reach a step coverage of >95%. Otherwise, as the depth of the channel hole increases, the electrical properties of the upper and lower layers will differ significantly, affecting the yield and reliability of the 3D memory. The charge trapping layer, as the sandwich layer of the ONOP structure, is generally deposited using a single-step ALD technology to achieve SiN deposition. However, as the number of stacked layers in 3D memory increases (greater than or equal to 128 layers), single-step ALD technology makes it difficult to ensure a step coverage of >95% for the charge trapping layer. Furthermore, using multi-step ALD technology for thin film deposition increases manufacturing costs.

[0109] Based on this, in this application embodiment, the single-step or multi-step ALD technology is changed to a plasma doping process to ensure that the step coverage of the charge trapping layer is greater than 95%.

[0110] In order to more clearly understand the purpose of the present invention, the following description is made by taking the manufacturing of the SiN layer (charge trapping layer) in the channel hole as an example.

[0111] In practical applications, an embodiment of the present invention provides another method for manufacturing a semiconductor structure. Figure 5a - Figure 5f The figure is a cross-sectional schematic diagram of the semiconductor structure manufacturing process; the method comprises the following steps:

[0112] Step 1: If Figure 5a As shown, a semiconductor substrate 301 is provided, on which a stack structure 302 having insulating layers 3021 and sacrificial layers 3022 alternately stacked is formed;

[0113] Step 2: If Figure 5b As shown, a plurality of channel holes 303 are formed through the stack structure 302; the depth of the channel holes 303 is greater than a preset depth;

[0114] Step 3: If Figure 5c As shown, a second dielectric layer 307 is formed on the sidewall of the channel hole 303;

[0115] Step 4: If Figure 5d As shown, a first dielectric layer 304 having a first thickness is formed on the surface of the second dielectric layer 307; the thickness of the first dielectric layer decreases as the depth of the channel hole 303 increases;

[0116] Step 5: If Figure 5e As shown, ion implantation is performed on the first dielectric layer 304 of the first thickness, and a portion of the first dielectric layer forms a doping layer 305;

[0117] Step 6: If Figure 5f As shown, the doping layer 305 is etched to remove part of the doping layer 305 to obtain a first dielectric layer 306 of a second thickness, where the second thickness is less than the first thickness; wherein, during the etching process, the amount of etching of the doping layer by the etching source decreases as the depth of the channel hole 303 increases.

[0118] In practical applications, the semiconductor substrate 301 may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one organic semiconductor material, or other semiconductor materials known in the art. A well region may also be formed in the semiconductor substrate. The stacked structure comprises an insulating layer 3021 and a sacrificial layer 3022 arranged at intervals. The material of the insulating layer 3021 includes, but is not limited to, one or more of an oxide layer, a nitride layer, and a silicon carbide layer; the sacrificial layer 3022 may also be referred to as a pseudo gate layer, and the material of the sacrificial layer 3022 includes, but is not limited to, one or more of silicon oxide, silicon nitride layer, and silicon oxynitride layer; in subsequent processes, the sacrificial layer 3022 may be removed, and a gate material (e.g., metal tungsten (W)) may be filled at the position after the removal. After the gate material is filled, the corresponding position of the sacrificial layer 3022 is referred to as a gate layer.

[0119] Here, the channel hole 303 is the aforementioned first opening, and the stacked structure 302 is the aforementioned thin film structure. The channel hole 303 is used to form a memory material layer. The second dielectric layer 307 is a blocking dielectric layer, which is used to block the outflow of charge from the memory layer. The blocking dielectric layer may include an oxide. Here, the thickness of the blocking dielectric layer is relatively consistent along the sidewalls of the channel hole. The first dielectric layer is a charge trapping layer, specifically made of silicon nitride.

[0120] In a specific embodiment of the present invention, when depositing a SiN film in a channel hole, a SiN deposited layer thicker than the desired thickness is first deposited; ion implantation is then performed on the thicker deposited layer to form a doped layer in a portion of the thicker deposited layer; and then, the doped layer in the SiN deposited layer is partially removed. The thickness of the resulting SiN deposited layer is uniform, that is, the step coverage of the resulting charge capture layer can well meet the process requirements.

[0121] It should be noted that: "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0122] In addition, the technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.

[0123] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a base structure; The base structure includes a first opening; forming a first dielectric layer with a first thickness on a sidewall of the first opening; The thickness of the first dielectric layer decreases as the depth of the first opening increases; Ion implantation is performed on the first dielectric layer, so that a portion of the first dielectric layer forms a doped layer; the thickness of the doped layer remains constant as the depth of the first opening increases, and the doping concentration of the doped layer decreases as the depth of the first opening increases; The doped layer is etched to remove a portion of the doped layer to obtain a first dielectric layer of a second thickness, where the second thickness is less than the first thickness; wherein, during the etching process, the amount of etching of the doped layer by the etching source decreases as the depth of the first opening increases.

2. The method according to claim 1, characterized in that The etching of the doped layer comprises: The doping layer is wet-etched, wherein during the wet etching process, an etching rate of the doping layer by an etching source decreases as the doping concentration of the doping layer decreases.

3. The method according to claim 1, characterized in that The step of implanting ions into the first dielectric layer includes: Ions are implanted into the first dielectric layer of the first thickness using a plasma doping (PLA) process.

4. The method according to claim 3, characterized in that During the ion implantation process, the material of the dopant used includes an inert element.

5. The method according to claim 3, characterized in that During the ion implantation process, the doping energy used is 100V-1000V.

6. The method according to claim 1, characterized in that The ratio of the first thickness to the second thickness is in the range of 2:1 to 3:

1.

7. The method according to claim 1, characterized in that The material of the first dielectric layer includes silicon oxide, silicon nitride, aluminum oxide, titanium nitride or polysilicon.

8. The method according to claim 1, characterized in that The step of forming a first dielectric layer of a first thickness on the sidewall of the first opening includes: A first dielectric layer with a first thickness is formed at least on the sidewall of the first opening by using a chemical vapor deposition method.

9. The method according to claim 1, characterized in that The base structure is provided, comprising: Providing a semiconductor substrate, on which a stack structure having insulating layers and sacrificial layers alternately stacked is formed; forming a plurality of channel holes penetrating the stacked structure; The step of forming a first dielectric layer of a first thickness on the sidewall of the first opening includes: A first dielectric layer with a first thickness is formed on the sidewalls of the channel hole.

10. The method according to claim 9, characterized in that The method further comprises: Before forming a first dielectric layer with a first thickness on the sidewall of the channel hole, forming a second dielectric layer on the sidewall of the channel hole; The step of forming a first dielectric layer of a first thickness on the sidewall of the channel hole comprises: A first dielectric layer having a first thickness is formed on a surface of the second dielectric layer.

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