Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor package device and a manufacturing method thereof. By designing the edge of the ground layer of the substrate as a discontinuous edge, in the subsequent process of forming a shielding layer on the sidewall of the substrate using a forward electromagnetic interference shielding technology, the expansion and contraction ratio affecting the ground layer of the substrate is utilized to reduce the generation of stress due to the design of the edge of the ground layer as a discontinuous edge, and when stress is generated, there is no chain reaction due to the continuous edge of the ground layer, and there is no problem of disconnection between the ground layer of the overall substrate and the shielding layer. That is, by changing the design of the ground layer of the substrate, the risk of disconnection and shielding failure between the ground layer of the substrate and the shielding layer can be effectively reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to semiconductor packaging apparatus and manufacturing methods thereof. Background Technology

[0002] Electromagnetic radiation is a frequent concern in semiconductor packaging. Traditionally, a metal cover is used to shield the entire semiconductor package. However, this metal cover occupies a relatively large space, hindering the trend towards miniaturization. Therefore, conformal electromagnetic interference shielding (EMS) technology has been proposed. This technology uses methods such as sputtering or coating to uniformly distribute conductive and magnetically conductive materials on the exterior of the semiconductor packaging material as an EMS layer, thereby reducing product size.

[0003] For details, please refer to [link / reference]. Figure 1A , Figure 1A This is a schematic diagram illustrating the effect of ambient temperature on the longitudinal cross-sectional structure of each layer of the product during the shielding process using existing unidirectional electromagnetic interference shielding technology. (For example...) Figure 1A As shown, in existing products, the substrate 11 may include a first solder resist layer 113, a ground layer 111, and a core layer 112 arranged sequentially, and a shielding layer 14 is provided on the sidewalls of the substrate 11, i.e., the sidewalls of the first solder resist layer 113, the ground layer 111, and the core layer 112. To achieve a good shielding effect, the shielding layer 14 needs to have a good electrical connection with the ground layer 111 in the substrate 11 to guide electromagnetic signals from outside the product to the ground layer 111. Currently, the ground layer 111 is mostly composed of a single layer of copper metal, and the first solder resist layer 113 is mostly composed of various insulating materials, such as PP (Prepreg, also known as prepreg or semi-cured resin, semi-cured sheet). The CTE (Coefficient of Thermal Expansion) of the copper metal layer and the insulating material often differs significantly; for example, the CTE of copper is approximately 17, while the CTE of PP is approximately 14. Due to the difference in CTE between the shielding layer 14 and the first solder resist layer 113, such as... Figure 1AAs shown, during the sputtering process of forming the shielding layer 14, when the ambient temperature is 25°C and the sputtering of the shielding layer 14 has not yet started, it can be seen that the sidewalls of the first solder resist layer 113, the ground layer 111 and the core layer 112 are substantially coplanar. When the sputtering process starts and the ambient temperature reaches 240°C, the first solder resist layer 113, the ground layer 111 and the core layer 112 will all expand due to the increase in temperature, and due to the difference in CTE between the first solder resist layer 113, the ground layer 111 and the core layer 112, the ground layer 111 will expand more than the first solder resist layer 113, so that the outer sidewalls of the first solder resist layer 113, the ground layer 111 and the core layer 112 will not be coplanar, and at this time the shielding layer 14 formed by sputtering will also not be coplanar due to being attached to the outer sidewalls of the first solder resist layer 113, the ground layer 111 and the core layer 112 after expansion. Then, the ambient temperature gradually decreases from 240°C to 25°C, and for the same reason, due to the difference in CTE between the first solder resist layer 113, the ground layer 111 and the core layer 112, the inward shrinking degree of the first solder resist layer 113, the ground layer 111 and the core layer 112 will also be different during the ambient temperature decrease. During the above-mentioned rapid temperature increase and decrease, delamination will occur between the ground layer 111 and the shielding layer 14. For details, please refer to Figure 1B , Figure 1B is Figure 1A the enlarged view of the elliptical dashed portion in the longitudinal cross-sectional structure schematic diagram of each layer of the product after sputtering completion shown in Figure 1B It can be seen from Figure 1B that there is a gap between the ground layer 111 and the shielding layer 14 after delamination. In the prior art, the substrate ground layer is mostly designed as an entire layer as shown in Figure 1C , and the outer edge is a continuous edge, so that the above-mentioned delamination will likely cause a chain reaction of the original stress balance point of the product, causing the delamination to occur around the entire product, and thus causing the entire shielding layer 14 and the ground layer 111 to be disconnected, resulting in the failure to achieve the shielding function. In addition, the above-mentioned delamination problem is difficult to be immediately detected after the formation of the shielding layer 14, and it is usually necessary to wait until the electrical testing stage after the entire process is completed to confirm whether the shielding layer 14 is really failed, thus causing a sharp increase in manufacturing cost. SUMMARY

[0004] The present disclosure provides a semiconductor package device and a manufacturing method thereof.

[0005] In a first aspect, the present disclosure provides a semiconductor package device, comprising:

[0006] a substrate having a ground layer, wherein an edge of the ground layer is a discontinuous edge.

[0007] In some optional embodiments, the ground layer is a copper metal layer.

[0008] In some embodiments, the ground layer has at least two through holes at the edge of the ground layer, and the ground layer is disposed between any two adjacent through holes.

[0009] In some embodiments, the ground layer has a first surface and a second surface opposite to the first surface, and the substrate further comprises:

[0010] a core layer disposed on the first surface;

[0011] a first solder resist layer disposed on the second surface, and a portion of the first solder resist layer is filled into each of the through holes;

[0012] a circuit layer disposed on a surface of the core layer away from the ground layer;

[0013] a second solder resist layer disposed on a surface of the circuit layer away from the core layer.

[0014] In some embodiments, the semiconductor package device further comprises:

[0015] at least one element disposed on a surface of the second solder resist layer away from the circuit layer.

[0016] In some embodiments, the semiconductor package device further comprises:

[0017] a mold encapsulation layer disposed on a surface of the second solder resist layer away from the circuit layer, and covering each of the elements.

[0018] In some embodiments, the semiconductor package device further comprises:

[0019] a shielding layer disposed on the mold encapsulation layer and covering a top surface and a side surface of the mold encapsulation layer, and a side surface of the second solder resist layer, the circuit layer, the core layer, and the ground layer, and the shielding layer is in contact with the ground layer.

[0020] In some embodiments, a ratio of a first length to a second length is a ratio of a coefficient of thermal expansion of the ground layer to a coefficient of thermal expansion of the first solder resist layer, the first length is a cumulative length of the edge of the ground layer corresponding to the first solder resist layer filled into each of the through holes, and the second length is a cumulative length of the edge of the ground layer without the through holes.

[0021] In some embodiments, each of the through holes is a semicircle, a diameter of the semicircle through hole is coincident with the outer edge of the ground layer, and a distance between any two adjacent through holes is equal.

[0022] In some alternative embodiments, each of the through holes is rectangular, one side of the rectangular through hole coincides with the outer edge of the ground layer, and the distance between any two adjacent through holes is equal.

[0023] In a second aspect, the present disclosure provides a semiconductor package device, comprising:

[0024] a substrate comprising a ground layer, the ground layer having at least two through holes at the edge of the ground layer, the through holes being non-contacting with each other, and the ground layer being arranged between any two adjacent through holes;

[0025] at least one element arranged on the substrate;

[0026] a mold encapsulation layer arranged on the substrate and encapsulating the at least one element;

[0027] a shielding layer encapsulating the mold encapsulation layer, the shielding layer contacting the ground layer.

[0028] In a third aspect, the present disclosure provides a method for manufacturing a semiconductor package device, comprising:

[0029] providing a substrate and at least one element, the substrate comprising a ground layer, the ground layer having at least two through holes at the edge of the ground layer, the through holes being non-contacting with each other, and the ground layer being arranged between any two adjacent through holes;

[0030] arranging the at least one element on the substrate;

[0031] mold encapsulating to form a mold encapsulation layer encapsulating the at least one element;

[0032] cutting to form a semiconductor package device unit;

[0033] sputtering outside the semiconductor package device unit to form a shielding layer encapsulating the mold encapsulation layer, the shielding layer contacting the ground layer.

[0034] To solve the problem of delamination between the shielding layer formed by using the forward electromagnetic interference shielding technology and the ground layer of the substrate, the semiconductor package device and the method provided by the present disclosure change the design of the ground layer of the substrate to a non-continuous edge, so that the expansion and contraction ratio affecting the ground layer of the substrate is used to reduce the generation of stress in the process of forming the shielding layer on the sidewall of the substrate by using the forward electromagnetic interference shielding technology. When stress is generated, the continuous edge of the ground layer will not cause a chain reaction, and the problem of disconnection between the ground layer of the whole substrate and the shielding layer will not occur. That is, by changing the design of the ground layer of the substrate, the risk of disconnection between the ground layer of the substrate and the shielding layer and the failure of shielding can be effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0035] Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments made with reference to the following drawings:

[0036] Figure 1A is a schematic diagram of the longitudinal cross-sectional structure of the product corresponding to the changes in the ambient temperature during the sputtering shielding layer process in the prior art;

[0037] Figure 1B is Figure 1A is a schematic diagram of the longitudinal cross-sectional structure of the product corresponding to the changes in the ambient temperature during the sputtering shielding layer process in the prior art;

[0038] Figure 1C is a schematic diagram of the horizontal cross-sectional structure of the ground layer in the prior art;

[0039] Figure 2A-1 and Figure 2A-2 is a schematic diagram of the longitudinal cross-sectional structure of one embodiment 2a of the semiconductor package device according to the present disclosure;

[0040] Figure 2B is a schematic diagram of the horizontal cross-sectional structure of one embodiment of the ground layer 111 according to the present disclosure;

[0041] Figure 2C is a schematic diagram of the horizontal cross-sectional structure of another embodiment of the ground layer 111 according to the present disclosure Figure 2B is a schematic diagram of the horizontal cross-sectional structure of another embodiment of the ground layer 111 according to the present disclosure

[0042] Figure 2D is a schematic diagram of the horizontal cross-sectional structure of another embodiment of the ground layer 111 according to the present disclosure

[0043] Figure 2E is a schematic diagram of the horizontal cross-sectional structure of another embodiment of the ground layer 111 according to the present disclosure Figure 2D is a schematic diagram of the horizontal cross-sectional structure of another embodiment of the ground layer 111 according to the present disclosure

[0044] Figure 3A , 3B , 3C and 3D are schematic diagrams of the longitudinal cross-sectional structure of the semiconductor package devices 3a, 3b, 3c and 3d, respectively, manufactured at various stages of the method of manufacturing a semiconductor package device according to the present disclosure.

[0045] Symbol explanation:

[0046] 11 - substrate; 111 - ground layer; 111a - first surface; 111b - second surface; 112 - core layer; 112a - surface of core layer 112 facing away from ground layer 111; 113 - first solder resist layer; 114 - circuit layer; 114a - surface of circuit layer 114 facing away from core layer 112; 115 - second solder resist layer; 115a - surface of second solder resist layer 115 facing away from circuit layer 114; 12 - component; 13 - mold seal layer; 14 - shield layer; Ldi - length of side of rectangular through hole coinciding with outer edge of ground layer 111; Lgro - distance between two rectangular through holes; H1 - length of side of rectangular through hole perpendicular to outer edge of ground layer 111; Ddi - diameter of semicircular through hole; Dgro - shortest distance between two semicircular through holes; P - point closest to semicircular through hole in two directions closest to vertex corner of ground layer; Tangent - tangent line of semicircular through hole at point P in two directions closest to vertex corner of ground layer; H2 - distance of point P from base of diameter of semicircular through hole in which it is located; D1 - first length; D2 - second length. DETAILED DESCRIPTION

[0047] The specific embodiments of the present disclosure will be described below with reference to the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems solved by the present disclosure and the technical effects generated by the content recorded in the present specification. It should be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, only the parts related to the application are shown in the drawings for ease of description.

[0048] It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the specification are only used to cooperate with the content recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the conditions of the implementation of the present disclosure, so they do not have technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be generated by the present disclosure, should still fall within the scope of the technical content disclosed by the present disclosure. At the same time, the terms such as "upper", "first", "second" and "one" used in the specification are only for the convenience of clear description, and not to limit the scope of the implementation of the present disclosure, and the change or adjustment of the relative relationship, without substantially changing the technical content, is also considered as the implementation of the present disclosure.

[0049] It should also be noted that the embodiments of the present disclosure correspond to the longitudinal cross section, which can be the front view direction cross section, the transverse cross section, which can be the right view direction cross section, and the horizontal cross section, which can be the upper view direction cross section.

[0050] In addition, the embodiments in the present disclosure and the features in the embodiments can be combined with each other in the case of no conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0051] Reference Figure 2A-1 and Figure 2A-2 , Figure 2A-1 and Figure 2A-2 is a longitudinal sectional structure schematic diagram of one embodiment 2a of the semiconductor package device according to the present disclosure.

[0052] As shown in Figure 2A-1 and Figure 2A-2 , the semiconductor package device 2a comprises a substrate 11. Here, the substrate 11 has a ground layer 111. And, the edge of the ground layer 111 is a discontinuous edge.

[0053] Here, the substrate 11 can be various types of substrates, which are not specifically limited in the present disclosure.

[0054] The substrate 11 can comprise organic and / or inorganic materials, wherein the organic materials can be, for example, polyamide (PA), polyimide (PI), epoxy, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, pre-impregnated material or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., and the inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0055] The substrate 11 can also be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate, etc.

[0056] The substrate 11 can further comprise interconnection structures, such as conductive traces, conductive vias, etc. Here, the conductive vias can be through holes, buried holes, or blind holes, and the through holes, buried holes, or blind holes can be filled with conductive materials, such as metals or metal alloys, wherein the metals can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0057] The ground layer 111 can be composed of various conductive materials for connecting to ground signals in the semiconductor package device 2a. The edge of the ground layer 111 can be various discontinuous edges, which are not specifically limited in the present disclosure.

[0058] The semiconductor package device 2a provided by the embodiment has a discontinuous edge of the ground layer 111 of the substrate 11, so that the expansion ratio of the ground layer 111 of the substrate 11 is used to reduce the stress generated in the process of forming the shielding layer 14 on the sidewall of the substrate 11 by using the forward electromagnetic interference shielding technology. When the stress is generated, the ground layer 111 is not a continuous edge, so that the stress will not cause a chain reaction, and the problem of disconnection between the ground layer 111 of the substrate 11 and the shielding layer 14 will not occur. That is, by changing the design of the ground layer 111 of the substrate 11, the risk of disconnection and shielding failure between the ground layer 111 of the substrate 11 and the shielding layer 14 can be effectively reduced.

[0059] In some optional embodiments, the ground layer 111 can be a copper metal layer.

[0060] In some optional embodiments, at least two through holes 1111 that are not in contact with each other can be arranged at the edge of the ground layer 111, and the ground layer 111 is arranged between adjacent two through holes 1111.

[0061] In some optional embodiments, as shown in Figure 2A-1 and Figure 2A-2 The ground layer 111 has opposite first and second surfaces 111a and 111b. The substrate 11 can further include a core layer 112, a first solder mask layer 113, a circuit layer 114, and a second solder mask layer 115. Wherein:

[0062] The core layer 112 is arranged on the first surface 111a. The first solder mask layer 113 is arranged on the second surface 111b, and part of the first solder mask layer 113 fills in each through hole 1111. The circuit layer 114 is arranged on a surface 112a of the core layer 112 away from the ground layer 111. The second solder mask layer 115 is arranged on a surface 114a of the circuit layer 114 away from the core layer 112.

[0063] Here, the core layer 112 can be various core substrates. The first and second solder mask layers 113 and 115 can be solder masks or stop masks.

[0064] In some optional embodiments, as shown in Figure 2A-1 and Figure 2A-2 The semiconductor package device 2a can further include at least one element 12. The element 12 is arranged on a surface 115a of the second solder mask layer 115 away from the circuit layer 114.

[0065] In some optional embodiments, as shown in Figure 2A-1 andFigure 2A-2 As shown in FIG. 1, the semiconductor package device 2a can further include a mold encapsulation layer 13. The mold encapsulation layer 13 is disposed on the surface 115a of the second solder resist layer 115 away from the circuit layer 114, and covers each element 12.

[0066] In some alternative embodiments, as shown in FIG. 2, the semiconductor package device 2a can further include a first solder resist layer 113. The first solder resist layer 113 is disposed on the surface 112a of the core layer 112 away from the circuit layer 114, and covers each element 12. Figure 2A-1 Figure 2A-2 As shown in FIG. 3, the semiconductor package device 2a can further include a shielding layer 14. The shielding layer 14 is disposed on the mold encapsulation layer 13 and covers the upper surface and side surface of the mold encapsulation layer 13, and the side surface of the second solder resist layer 115, the circuit layer 114, the core layer 112 and the ground layer 111, and the shielding layer 14 contacts the ground layer 111.

[0067] In some alternative embodiments, as shown in FIG. 4, the semiconductor package device 2a can further include a first solder resist layer 113. The first solder resist layer 113 is disposed on the surface 112a of the core layer 112 away from the circuit layer 114, and covers each element 12. Figure 2B Figure 2B As shown in FIG. 5, the ratio of the first length D1 to the second length D2 is the ratio of the thermal expansion coefficient of the ground layer 111 to the thermal expansion coefficient of the first solder resist layer 113, wherein the first length D1 is the cumulative length of the edge of the ground layer 111 corresponding to the filling of the first solder resist layer 113 into each through hole 1111, and the second length D2 is the cumulative length of the edge of the ground layer 111 without the through hole 1111. By designing the first length D1 and the second length D2 in this way, the deformation degree of the part of the ground layer 111 edge filled with the first solder resist layer 113 and the part of the ground layer 111 edge without the through hole 1111 can be the same under the same temperature change, thereby preventing delamination between the ground layer 111 and the first solder resist layer 113.

[0068] Reference is made to FIG. 6, which is a schematic view of a horizontal cross-sectional structure of an embodiment of the ground layer 111 according to the present disclosure. Figure 2B Figure 2C As shown in FIG. 7, the edge of the ground layer 111 is provided with at least two rectangular through holes 1111, one side of each rectangular through hole 1111 coincides with the outer edge of the ground layer 111, and the distance between any two adjacent through holes 1111 is equal. With reference to FIG. 8, Figure 2C Figure 2B As shown in FIG. 9, the edge of the ground layer 111 is provided with at least two rectangular through holes 1111, one side of each rectangular through hole 1111 coincides with the outer edge of the ground layer 111, and the distance between any two adjacent through holes 1111 is equal. With reference to FIG. 10, Figure 2C Figure 2D As shown in FIG. 11, the edge of the ground layer 111 is provided with at least two rectangular through holes 1111, one side of each rectangular through hole 1111 coincides with the outer edge of the ground layer 111, and the distance between any two adjacent through holes 1111 is equal. With reference to FIG. 12, Figure 2D ​​​​​As shown, Ldi is the length of the side of the rectangular via 1111 that coincides with the edge of the ground layer 111, Lgro is the distance between two rectangular vias 1111, and H1 is the length of the side of the rectangular via 1111 that is perpendicular to the edge of the ground layer 111. It can be seen that, since the rectangular vias 1111 are arranged at equal intervals, if the rectangular vias 1111 are rectangular vias of the same shape and length, the ratio of the first length to the second length can be equal to the ratio of Ldi to Lgro, and since the ratio of the first length to the second length is the ratio of the thermal expansion coefficient of the ground layer 111 to the thermal expansion coefficient of the first solder resist layer 113, the ratio of Ldi to Lgro is equal to the ratio of the thermal expansion coefficient of the ground layer 111 to the thermal expansion coefficient of the first solder resist layer 113. In addition, in order to ensure that the two rectangular vias 1111 closest to the corner of the edge of the ground layer 111 arranged at the corner do not contact, H1 is optionally less than Lgro, so that the ground layer 111 is not broken due to the contact of the two rectangular vias 1111 closest to the corner of the edge of the ground layer 111 arranged at the corner.

[0069] Reference will now be made to Figure 2D , Figure 2E is a schematic view of the horizontal cross-sectional structure of an embodiment of the ground layer 111 according to the present disclosure. As shown, Figure 2E at least two semicircular vias 1111 are arranged at the edge of the ground layer 111, and the diameter of each semicircular via 1111 coincides with the edge of the ground layer 111, and the distance between any two adjacent vias is equal. With reference to Figure 2D , Figure 2E is a schematic view of the horizontal cross-sectional structure of an embodiment of the ground layer 111 according to the present disclosure Figure 2E As shown, Figures 3A-3D , wherein Ddi is the diameter of the semicircular via 1111, and Dgro is the shortest distance between two semicircular vias 1111.

[0070] It can be seen that, since the semicircular vias 1111 are arranged at equal intervals, if the semicircular vias 1111 are semicircular vias of the same shape and diameter, the ratio of the first length to the second length can be equal to the ratio of Ddi to Dgro, and since the ratio of the first length to the second length is the ratio of the thermal expansion coefficient of the ground layer 111 to the thermal expansion coefficient of the first solder resist layer 113, the ratio of Ddi to Dgro is equal to the ratio of the thermal expansion coefficient of the ground layer 111 to the thermal expansion coefficient of the first solder resist layer 113. In addition, Figures 3A-3DIn the formula, P is the point closest to the two semicircular through holes closest to each other in the two directions of the vertex corner of the ground layer 111, Tangent is the tangent of the two semicircular through holes closest to each other in the two directions of the vertex corner of the ground layer 111 at the point P, and H2 is the distance from the point P to the bottom side of the diameter of the semicircular through hole in which the point P is located. In order to ensure that the two semicircular through holes 1111 closest to the corner at the edge corner of the ground layer 111 do not contact, H2 can be less than Dgro optionally.

[0071] The following will be described with reference to Figure 3A , Figure 3B are schematic longitudinal sectional structure diagrams of semiconductor packaging devices 3a, 3b, 3c and 3d manufactured at various stages of a method of manufacturing a semiconductor packaging device according to the present disclosure. The various diagrams have been simplified for better understanding of aspects of the present disclosure.

[0072] Referring to Figure 3C , a substrate 11 and at least one element 12 are provided, and the at least one element 12 is disposed on the substrate 11.

[0073] Here, the substrate can include a ground layer 111 and a core layer 112, and at least two through holes that do not contact each other can be disposed at the edge of the ground layer 111, and a ground layer is disposed between the two adjacent through holes.

[0074] Referring to Figure 3D , a mold is encapsulated to form a mold encapsulation layer 13 covering the at least one element 12.

[0075] Referring to ​ , cutting is performed to form a semiconductor packaging device unit.

[0076] Referring to ​ , sputtering is performed outside the semiconductor packaging device unit to form a shielding layer 14 covering the mold encapsulation layer 13, and the shielding layer 14 contacts the ground layer 111.

[0077] The method of manufacturing a semiconductor packaging device provided in the present embodiment can achieve the corresponding technical effects of the semiconductor packaging device described above, which will not be described here again.

[0078] While the disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not intended to limit the disclosure. Those skilled in the art can readily devise various changes that fall within the true spirit and scope of the disclosure, as defined by the appended claims. The drawings can not be to scale. There can be differences between the technology reproduction in the disclosure and the actual implementation due to manufacturing process variations, etc. There can be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are, accordingly, to be regarded simply as illustrative and not restrictive. Modifications can be made to adapt a specific situation, material, composition of matter, method, or process to the objective, spirit and scope of the disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations can be combined, sub-divided, or re-ordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated otherwise, the order and grouping of operations is not a limitation of the present disclosure.

Claims

1. A semiconductor packaging device, comprising: A substrate having a ground layer, wherein the edge of the ground layer is a discontinuous edge, and at least two non-contacting through holes are provided at the edge of the ground layer, and the ground layer is provided between two adjacent through holes; The substrate further includes a first solder resist layer, a portion of which is filled into each of the through holes; The ratio of the first length to the second length is the ratio obtained by dividing the thermal expansion coefficient of the grounding layer by the thermal expansion coefficient of the first solder resist layer. The first length is the cumulative length of each through hole in the edge of the grounding layer corresponding to the first solder resist layer. The second length is the cumulative length of the edge of the grounding layer where no through holes are provided.

2. The semiconductor packaging apparatus according to claim 1, wherein, The grounding layer is a copper metal layer.

3. The semiconductor packaging apparatus according to claim 1, wherein, The grounding layer has a first surface and a second surface opposite to each other, and the first solder resist layer is disposed on the second surface; The substrate also includes: The core layer is disposed on the first surface; A circuit layer is disposed on the surface of the core layer away from the ground layer; The second solder mask layer is disposed on the surface of the circuit layer away from the core layer.

4. The semiconductor packaging apparatus according to claim 3, wherein, The semiconductor packaging apparatus further includes: At least one element is disposed on the surface of the second solder mask layer away from the circuit layer.

5. The semiconductor packaging apparatus according to claim 4, wherein, The semiconductor packaging apparatus further includes: A molding layer is disposed on the surface of the second solder mask layer away from the circuit layer and covers each of the components.

6. The semiconductor packaging apparatus according to claim 5, wherein, The semiconductor packaging apparatus further includes: A shielding layer is disposed on the molding layer and covers the upper surface and side surface of the molding layer, as well as the side surface of the second solder mask layer, the circuit layer, the core layer and the grounding layer, and the shielding layer is in contact with the grounding layer.

7. The semiconductor packaging apparatus according to claim 1, wherein, Each of the through holes is semi-circular, and the bottom edge of the diameter of the semi-circular through hole coincides with the outer edge of the grounding layer, and the distance between any two adjacent through holes is equal.

8. The semiconductor packaging apparatus according to claim 1, wherein, Each of the through holes is rectangular, with one side of the rectangular through hole coinciding with the outer edge of the grounding layer, and the distance between any two adjacent through holes is equal.

9. A semiconductor packaging apparatus, comprising: The substrate includes a ground layer and a first solder resist layer. At least two non-contacting through holes are provided at the edge of the ground layer, and the ground layer is provided between two adjacent through holes. A portion of the first solder resist layer is filled into each of the through holes. At least one element is disposed on the substrate; A molding layer is disposed on the substrate and covers the at least one element; A shielding layer covers the molding layer and contacts the grounding layer; The ratio of the first length to the second length is the ratio obtained by dividing the thermal expansion coefficient of the grounding layer by the thermal expansion coefficient of the first solder resist layer. The first length is the cumulative length of each through hole in the edge of the grounding layer corresponding to the first solder resist layer. The second length is the cumulative length of the edge of the grounding layer where no through holes are provided.

10. A method for manufacturing a semiconductor packaging device, comprising: A substrate and at least one component are provided. The substrate includes a ground layer and a first solder resist layer. At least two non-contacting through holes are provided at the edge of the ground layer, and the ground layer is provided between two adjacent through holes. A portion of the first solder resist layer is filled into each of the through holes. The at least one element is disposed on the substrate; Molding to form a molding layer covering the at least one element; Cutting to form semiconductor packaging device units; A shielding layer is sputtered on the outside of the semiconductor packaging unit to form a shielding layer covering the molding layer, and the shielding layer contacts the ground layer; The ratio of the first length to the second length is the ratio obtained by dividing the thermal expansion coefficient of the grounding layer by the thermal expansion coefficient of the first solder resist layer. The first length is the cumulative length of each through hole in the edge of the grounding layer corresponding to the first solder resist layer. The second length is the cumulative length of the edge of the grounding layer where no through holes are provided.

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