Active Pixel Device for Reducing Dark Current and Noise

Abstract

The present invention relates to complementary metal-oxide-semiconductor (CMOS) image sensor pixel technology. To achieve the separation of the charge transfer channel from the surface of the transfer gate channel and reduce the dark current while ensuring the charge transfer efficiency, the technical solution adopted by the present invention is an active pixel device for reducing the dark current and noise, which includes a photodetector PD, a transfer gate TG, a reset transistor RST, a source follower SF, and a row select transistor SEL. Among them, the TG is responsible for transferring the photoelectrons collected in the PD to the charge-voltage conversion node FD. The reset transistor RST can perform a reset operation on FD and PD. The SF is responsible for buffering the voltage signal of the FD node. The SEL transistor strobes a certain row when the row select signal arrives. A layer of N-type ion implantation is added under the transfer gate TG to form a thin N-type region. The present invention is mainly applied to the design and manufacturing of complementary metal-oxide-semiconductor image sensor pixels.

Description

Technical Field

[0001] The present invention relates to the field of CMOS (complementary metal oxide semiconductor) image sensor pixels, and in particular to 4T (4 transistors) active pixels in CMOS image sensors and other pixel structures based on 4T pixels. Background Art

[0002] Image sensors have always been one of the hot topics of research. How to obtain high-quality image information and help humans expand the limits of vision is the fundamental purpose of continuous research on image sensors. With the advancement of process technology, CMOS image sensors have gradually occupied the market and continued to develop. To obtain high-quality images, low-noise design is particularly important. At present, most of the pixel structures used are basically optimized based on the 4T pixel structure. This structure can separate the charge collection area and the charge-voltage conversion node, so that the KTC noise (reset noise) and part of the fixed pattern noise of the reset tube can be eliminated through correlated double sampling. This structure greatly improves the image quality of the pixel and reduces some of the noise pressure. The optimization of noise and dark current has always been one of the development directions of CIS (CMOS image sensor).

[0003] For pixels, the output signals generated under no light conditions can be classified as dark currents. The size of dark currents is closely related to temperature and semiconductor manufacturing process level. Dark currents will bring fixed offsets and noise to the output signals during readout, which seriously limits the dynamic range of image sensors and the imaging quality under low light conditions. Therefore, it is of great significance to optimize the dark current design during pixel design. The main sources of dark currents in the clamping diodes currently used are dark currents generated in the depletion region, dark currents generated on the surface, STI (shallow trench isolation) dark currents, TG (transmission gate) channel region dark currents, and neutral diffusion dark currents. Among them, the dark current in the TG region is mainly due to the generation and recombination effect of trap-assisted carriers in the TG channel region during pixel exposure. The generated carriers directly enter the PPD (embedded photodiode) through the channel and are collected. Therefore, it is of great research value to optimize the dark current in the TG channel region from a design perspective. Summary of the invention

[0004] To overcome the deficiencies of the prior art, the present invention aims to propose a transfer gate ion implantation structure applied to 4T active pixels, which can separate the charge transfer channel from the surface of the transfer gate channel and reduce the dark current while ensuring the charge transfer efficiency. To this end, the technical solution adopted by the present invention is an active pixel device for reducing dark current and noise, including a photodetector PD, a transfer gate TG, a reset transistor RST, a source follower SF, and a row select transistor SEL. Among them, TG is responsible for transferring the photoelectrons collected in PD to the charge-voltage conversion node FD. The reset transistor RST can reset FD and PD. SF is responsible for buffering the voltage signal of the FD node. The SEL transistor gates a certain row when the row select signal arrives. A layer of N-type ion implantation is added under the transfer gate TG to form a thin N-type region.

[0005] According to the formula of electron potential energy:

[0006] E p =-|q|×Ψ

[0007] where q is the electric charge of an electron, Ψ is the electrostatic potential, and the place where the electron potential energy is the smallest is located in the N-type region.

[0008] For the N-type ion implantation under the transfer gate TG on the side close to the photodiode, by setting the position of the mask plate, there is a certain distance between its N-type ion implantation and the N-type implantation of the photodiode. While implanting this N-type region, the implantation position of the CPX layer is also adjusted through this distance. The CPX layer is a P-type ion implantation layer. For the transfer gate on the side close to the charge-voltage conversion node, by setting the position of the mask plate in the same way, its N-type ion implantation extends beyond the transfer gate and can be connected to the FD node region on the right, thus eliminating the influence of the potential barrier under the gate caused by the existence of the sidewall of the transfer gate. The best implantation position is 0.2um away from the left edge of the transfer gate and extends 0.1 - 0.2um beyond the right edge of the transfer gate.

[0009] A P-type ion implantation region is formed at the connection between the photodiode and the transfer gate. The position of the CPXN layer is adjusted to be below the P-type ion implantation region. The best implantation position of the CPXN layer is at the junction of the N-type region of the photodiode and the transfer gate, and extends 0.2um - 0.25um under the N-type region of the photodiode and the transfer gate respectively.

[0010] The ion implantation dose of the P-type ion implantation region is 10 1 ~10 2 orders of magnitude higher than that of the N-type ion implantation. Its best implantation position is below the clamping layer P-PD, in the transition region between the photodiode and the transfer gate. It occupies a length of 0.3um under the transfer gate and a length of 0.1um - 0.2um in the N-type region of the photodiode.

[0011] The features and beneficial effects of the present invention are as follows:

[0012] The ion implantation structure proposed by the present invention, compared with the conventional photodiode structure, can move the maximum potential under the transfer gate channel away from the silicon-silicon dioxide interface through two doping steps, thereby reducing the dark current in the transfer gate region and the noise generated during the charge transfer process, and thus improving the noise of the image sensor. Brief Description of the Drawings

[0013] Figure 1 Schematic diagram of the 4T pixel structure.

[0014] Figure 2 Schematic diagram of the ion implantation structure.

[0015] Figure 3 Depletion region under the transfer gate and its potential diagram. Detailed Embodiments

[0016] This solution is mainly achieved by performing multiple ion implantations under the transfer gate. Based on the basic principle of the 4T pixel, a layer of N-type ion implantation and a layer of P-type ion implantation are added under the transfer gate to achieve the effect of noise improvement. The traditional 4T pixel structure is as shown in the attached... Figure 1 As shown, it includes a photodetector PD, a transfer gate TG, a reset transistor RST, a source follower SF, and a row select transistor SEL. Among them, TG is responsible for transferring the photoelectrons collected in PD to the charge-voltage conversion node FD. The reset transistor RST can reset FD and PD. SF is responsible for buffering the voltage signal of the FD node. The SEL transistor strobes a certain row when the row select signal arrives. Its working principle is that when SEL is turned on, first turn on the RST transistor to reset the FD node, then turn off RST and read out the reset voltage signal of the FD node at this time; then turn on TG, transfer the electrons inside PD to the FD node through TG, and read out the optical signal after turning off TG.

[0017] In the 4T pixel, the design of PD and the transfer gate TG is crucial. As shown in the PD region on the left side of the attached... Figure 1 In the current design, a pinned photodiode (PPD) is usually used, that is, a thin layer of P+-type ion implantation (P-PD) is added above the N-type ion implantation of the photodiode. The addition of this layer makes the N region of the photodiode fully depleted and effectively reduces the dark current caused by surface states. In addition, the CPX layer is a P-type ion implantation, and the implantation of this layer can compensate for the influence of the N-type region under the gate at the channel connection on the channel threshold and eliminate the potential well existing in the channel region when the transfer tube is turned on; CPXN in the figure is an N-type ion implantation, and the implantation of this layer can accelerate the charge transfer and enable the electrons far from the channel to be transferred to FD, that is, the complete transfer of PD can be achieved.

[0018] Based on the traditional design, by controlling the energy and dose of ion implantation, a layer of N-type ion implantation is added under the gate, and a thin N-type region can be formed under the gate, as shown in the appendix Figure 2 shown. Generally speaking, for an NMOS device, the channel region of the MOS transistor is all P-type ions. When there is no appropriate gate voltage applied on the gate, after adding this N-type region, the excess electrons in the N-type layer diffuse into the P-type substrate, and the excess holes in the P-type substrate diffuse into the N-type layer. This structure is the same as that of a PN junction. The above-mentioned diffusion generates an internal electric field, so that the electric potential in the N-type layer reaches the maximum, as shown in the appendix Figure 3 shown.

[0019] According to the formula of electron potential energy:

[0020] E p =-|q|×Ψ

[0021] q is the electric charge of an electron, and Ψ is the electrostatic potential. The place where the electron potential energy is the smallest is located in the N-type region and is at a certain distance from the interface between silicon and silicon dioxide. Therefore, during the charge transmission process, electrons will be transmitted through the channel with the smallest potential energy (or the highest potential), away from the interface between silicon and silicon dioxide, thereby reducing the noise caused by surface defects.

[0022] In order to prevent the charge in the photodiode from entering the charge-voltage conversion node through the transfer gate when the transfer gate is turned off, a P-type ion implantation region can be formed at the connection between the photodiode and the transfer gate, as shown in the appendix Figure 2 shown.

[0023] Through the above analysis, since the charge transmission path is at a certain distance from the surface, it is necessary to adjust the positions of the N-type region of the photodiode and the N-type region of the CPXN layer so that the maximum electric potential of the PPD region also moves down a certain distance. Its maximum electric potential is expressed as:

[0024]

[0025] X D is the depletion region width formed by the N region and the P-type layer on either side, ε is the dielectric constant of silicon, N A and N D are the doping concentrations of P-type and N-type respectively. By setting the dose and energy of ion implantation in the P-PD region, the depletion region width and the position of the maximum electric potential can be adjusted.

[0026] The addition of the CPXN layer is to make the charge transfer smoother. Due to the downward shift of the charge transfer channel, the area of this layer also needs to be adjusted. The position of this layer needs to be below the above-mentioned P-type region and connected to the P-type region to complete the smooth transfer of charges.

[0027] To more intuitively express the implementation conditions, advantages, etc. of the present invention, the implementation manners of the present invention will be described below in conjunction with examples. The present invention is not limited to this specific embodiment, and general substitutions well-known to those skilled in the art are also covered within the protection scope of the invention.

[0028] From Figure 3 It can be seen that due to the addition of N-type ion implantation, the maximum potential under the transfer gate is at a certain distance from the silicon-silicon dioxide interface. In Figure 2 , the dashed parts are the added N-type and P-type ion implantations. Due to the presence of P-type ions, the electrons thermally generated under the transfer gate cannot enter the photodiode.

[0029] The specific implementation case takes the structure in the appendix Figure 2 as an example. The first part is the formation of the buried channel region of the transfer gate. A layer of N-type ion implantation is added under the transfer gate. The process parameters mainly involve the energy and dose of ion implantation. The implantation energy affects the depth of the doped region in the implantation direction, and the implantation dose has a significant impact on the internal potential. By using low-dose and low-energy implantation, a thin N-type region is formed under the transfer gate, thus forming a potential distribution as shown in Figure 3 .

[0030] For the implantation under the transfer gate on the side close to the photodiode, by setting the position of the mask plate, there is a certain distance between the N-type ion implantation and the N-type implantation of the photodiode. When implanting this N-type region, the implantation position of the CPX layer can also be adjusted through this distance. For the transfer gate on the side close to the charge-voltage conversion node, similarly, by setting the position of the mask plate, the N-type ion implantation can extend beyond the transfer gate and be connected to the FD node region on the right, thereby eliminating the influence of the potential barrier under the gate caused by the presence of the sidewall of the transfer gate. In addition, during the charge transfer process, due to the implantation of this layer, the transfer rate of charges from the photodiode to the charge-voltage conversion node can be accelerated. The best implantation position is 0.2 um from the left edge of the transfer gate and extends 0.1 - 0.2 um beyond the right edge of the transfer gate.

[0031] The second part is the formation of the P-type ion implantation region. This layer of implantation is to prevent the charge in the photodiode from leaking into the FD node when the transfer gate is turned off. Since this layer is P-type ion implantation, it is possible to create a potential barrier in the charge transfer path when the transfer gate is conducting. Therefore, the implantation concentration of this layer needs to be strictly adjusted. At the same time, this potential barrier also has a certain effect on the dark current in the transfer gate. Due to the existence of the potential barrier, the electrons thermally generated at the silicon-silicon dioxide interface cannot cross the potential barrier and enter the photodiode, thus reducing the dark current. The ion implantation dose of this layer is 10 1 -10 2 orders of magnitude higher than the ion implantation dose of the previous step. When the transfer gate is conducting, the influence of this potential barrier can be eliminated by applying an external voltage. Its optimal implantation position is below the clamping layer (P-PD), in the transition region between the photodiode and the transfer gate. It occupies a length of 0.3 um under the transfer gate and a length of 0.1 um - 0.2 um in the N-type region of the photodiode.

[0032] The third part is the position adjustment of the N-type region of the photodiode and the N-type region of the CPXN layer. The position of the CPXN layer should be below the P-type ion implantation. Its optimal implantation position is at the junction of the N-type region of the photodiode and the transfer gate, extending 0.2 um - 0.25 um under both the N-type region of the photodiode and the transfer gate. The N-type region of the photodiode is implanted three times, and the maximum potential of the N-type region of the photodiode is adjusted by adjusting the energy and dose of the three implantations. After adjustment, the position of its maximum potential should be at the level of the CPXN layer to achieve the best charge transfer.

[0033] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An active pixel device for reducing dark current and noise, characterized in that, It includes a photodetector PD, a transfer gate TG, a reset transistor RST, a source follower SF, and a row strobe transistor SEL. Among them, the TG is responsible for transferring the photoelectrons collected in the PD to the charge-voltage conversion node FD. The reset transistor RST resets FD and PD. The SF is responsible for buffering the voltage signal of the FD node. The SEL transistor strobes a certain row when the row select signal arrives. A layer of N-type ion implantation is added under the transfer gate TG to form a thin N-type region. Among them, for the N-type ion implantation under the transfer gate TG near the photodiode side, by setting the position of the mask plate, there is a certain distance between the N-type ion implantation and the N-type implantation of the photodiode. While implanting this N-type region, the implantation position of the CPX layer is also adjusted through this distance. The CPX layer is a P-type ion implantation layer. For the transfer gate near the charge-voltage conversion node side, by setting the position of the mask plate in the same way, the N-type ion implantation extends beyond the transfer gate and can be connected to the FD node region on the right, so as to eliminate the influence of the potential barrier under the gate caused by the existence of the sidewall of the transfer gate. The optimal implantation position is 0.2um away from the left edge of the transfer gate and extends 0.1 - 0.2um beyond the right edge of the transfer gate.

2. The active pixel device for reducing dark current and noise as described in claim 1, wherein According to the formula of electron potential energy: E p = -|q| × ψ q is the charge of an electron, Ψ is the electrostatic potential, and the place where the electron potential energy is the smallest is located in the N-type region.

3. The active pixel device for reducing dark current and noise according to claim 2, wherein A P-type ion implantation region is formed at the connection between the photodiode and the transfer gate. The position of the CPXN layer is adjusted to be below the P-type ion implantation region. The optimal implantation position of the CPXN layer is at the junction between the N-type region of the photodiode and the transfer gate, and extends 0.2um - 0.25um under the N-type region of the photodiode and the transfer gate respectively.

4. The active pixel device for reducing dark current and noise according to claim 3, wherein The ion implantation dose of the P-type ion implantation region is 10 1 to 10 2 orders of magnitude higher than that of the N-type ion implantation dose. Its optimal implantation position is below the clamping layer P-PD, in the transition region between the photodiode and the transfer gate. It occupies a length of 0.3 um under the transfer gate and a length of 0.1 um to 0.2 um in the N-type region of the photodiode.

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