Three-dimensional memory device and its formation method

Abstract

A three-dimensional (3D) memory device and a method for forming the same are disclosed. In some aspects, a 3D memory device includes a stacked structure comprising a core region and a stepped region, a channel structure extending through the stacked structure in the core region, and a first support structure extending through the stacked structure in the stepped region. The first support structure includes a first portion extending along a first direction and a second portion protruding from the first portion along a second direction perpendicular to the first direction.

Description

Background Technology

[0001] This disclosure relates to a three-dimensional (3D) memory device and a method of manufacturing the same.

[0002] By improving process technology, circuit design, programming algorithms, and manufacturing processes, planar memory cells have been scaled down to smaller sizes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the storage density of planar memory cells is approaching its upper limit.

[0003] 3D memory architecture can address the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention

[0004] This article discloses a 3D memory device and its manufacturing method.

[0005] In one aspect, a 3D memory device includes a stacked structure comprising a core region and a stepped region, a channel structure extending through the stacked structure in the core region, and a first support structure extending through the stacked structure in the stepped region. The first support structure includes a first portion extending along a first direction and a second portion projecting from the first portion along a second direction perpendicular to the first direction.

[0006] In another aspect, a 3D memory device includes a stacked structure comprising a core region and a stepped region, a channel structure extending through the stacked structure in the core region, and a first support structure extending through the stacked structure in the stepped region. The first support structure has a beaded strip shape in a plan view.

[0007] In another aspect, a method for forming a three-dimensional (3D) memory device includes: forming a stacked structure including a core region and a stepped region; forming a channel structure extending through the stacked structure in the core region; and forming a first support structure extending through the stacked structure in the stepped region. The first support structure has a beaded strip shape in a plan view.

[0008] In another aspect, a system includes a 3D memory device configured to store data and a memory controller coupled to the 3D memory device and configured to control the 3D memory device. The 3D memory device includes a stacked structure comprising a core region and a stepped region, a channel structure extending through the stacked structure in the core region, and a first support structure extending through the stacked structure in the stepped region. The first support structure has a beaded strip shape in a plan view. Attached Figure Description

[0009] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various aspects of this disclosure and, together with the textual description, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0010] Figure 1A A side view of a cross section of an exemplary 3D memory device according to some embodiments of the present disclosure is shown.

[0011] Figure 1B A top view of a cross-section of a stepped region of an exemplary 3D memory device including a strip-shaped support structure according to some embodiments of the present disclosure is shown.

[0012] Figure 1C A top view of a cross section of a stepped region of an exemplary 3D memory device including a beaded strip-shaped support structure according to some embodiments of the present disclosure is shown.

[0013] Figure 2A A schematic diagram of a seam break in a beaded strip-shaped support structure according to some embodiments of the present disclosure is shown.

[0014] Figure 2B A schematic diagram of stress distribution on a beaded strip-shaped support structure according to some embodiments of the present disclosure is shown.

[0015] Figure 2C A schematic diagram of stress distribution on a strip-shaped support structure without embedded beads, according to some embodiments of the present disclosure, is shown.

[0016] Figure 3A Simulation results of stresses experienced by strip-shaped support structures with different joint lengths according to some embodiments of the present disclosure are shown.

[0017] Figure 3B Simulation results of stresses experienced by a strip-shaped support structure without embedded beads and a strip-shaped support structure with two embedded beads, according to some embodiments of the present disclosure, are shown.

[0018] Figure 4A A side view of a cross section of an exemplary 3D memory device according to some embodiments of the present disclosure is shown.

[0019] Figure 4B A top view of a cross section of an exemplary 3D memory device according to some embodiments of the present disclosure is shown.

[0020] Figure 4C A top view of a cross-section of a stepped region of an exemplary 3D memory device according to some embodiments of the present disclosure is shown.

[0021] Figure 4DAn exemplary design pattern of a support structure in a stepped area of ​​a 3D memory device according to some embodiments of the present disclosure is shown.

[0022] Figure 5A-5M A manufacturing process for forming an exemplary 3D memory device according to some embodiments of the present disclosure is shown.

[0023] Figure 6 A flowchart is shown of a method for forming an exemplary 3D memory device according to some embodiments of the present disclosure.

[0024] Figure 7 A block diagram of an exemplary system having a 3D memory device according to some embodiments of the present disclosure is shown.

[0025] Figure 8A A schematic diagram of an exemplary memory card having a 3D memory device according to some embodiments of the present disclosure is shown.

[0026] Figure 8B A schematic diagram of an exemplary solid-state drive (SSD) with a 3D memory device according to some embodiments of the present disclosure is shown.

[0027] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0028] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Thus, other constructions and arrangements can be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other in a manner not specifically depicted in the drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0029] Generally, terms can be understood at least in part based on their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Additionally, also depending at least in part on the context, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described.

[0030] It should be readily understood that the meanings of “above,” “above,” and “on top” in this disclosure should be interpreted in the broadest sense, such that “above” not only means directly “on” something, but also includes the meaning of being “on” something with an intermediate feature or layer in between, and that “above” or “on top” not only means being “above” or “on top” something, but can also include the meaning of being “above” or “on top” something without an intermediate feature or layer in between (i.e., directly on something).

[0031] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figures. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 180 degrees or in other orientations), and the spatial relative descriptive terms used herein can be interpreted similarly accordingly.

[0032] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entire underlying or upper layer structure, or may have a range smaller than or equal to that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. Layers may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which interconnect lines and / or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

[0033] NAND flash memory devices are widely used in various electronic products due to their non-volatility, light weight, low power consumption, and good performance. Currently, planar NAND flash memory devices have reached their storage limits. To further increase storage capacity and reduce the cost per bit, 3D NAND memory devices have been proposed. For example... Figure 1AAs shown, the 3D NAND memory device 100 may include a substrate 102, a stacked structure 120 above the substrate 102, and an outer insulating layer 122 above the stacked structure 120, such that the stacked structure 120 is located inside the outer insulating layer. The stacked structure 120 may include a plurality of conductive layers 126 and a plurality of dielectric layers 128 interleaved with each other, thereby forming a plurality of conductor / dielectric layer pairs. The 3D memory device 100 may include a core region 121 and one or more stepped regions 123 adjacent to the core region (two stepped regions are shown in the 3D NAND memory device 100). In the core region 121, the 3D memory device 100 may include a plurality of channel structures 110 extending vertically through the stacked structure 120 into the substrate 102, such as... Figure 1A As shown. In the stepped region 123, the stacked structure 120 may include a step having a plurality of steps 112 extending laterally in the planar direction. The 3D memory device 100 may include a plurality of contact plugs 124 extending in the outer insulating layer 122 and landing on a corresponding step 112 and contacting a corresponding conductive layer 126. In some embodiments, the 3D memory device 100 may also include a plurality of gate slots (GLS) (not shown) formed in the stepped region 123.

[0034] In a 3D NAND memory device, the number of conductor / dielectric layer pairs 112 in the stacked structure 120 determines the number of memory cells in the 3D memory device 100. As the number of conductor / dielectric layer pairs 112 increases to achieve higher storage capacity, more stress is introduced into the 3D NAND memory device due to the weight and distribution of the conductive layers, causing deformation, such as bending, of the existing support structure. Sometimes, even the channel structure 110 deforms due to stress. To reduce stress in the conductive layers, support structures, such as dummy channel structures, can be formed in the 3D NAND memory device. For example, a number of support structures 125 can be formed in the stepped region 123 of the 3D NAND memory device 100 to balance the mechanical stress in the conductive layer 126 and the mechanical load / stress between the stepped region 123 and the core region 121.

[0035] However, in existing 3D NAND memory devices, the density of the support structure (e.g., the number of support structures in a cell region) can be limited and therefore insufficient to provide the desired support for the conductive layer due to the space occupied by the gate gaps (GLS) and contact plugs in the stepped regions. As a result, the conductive layer remains susceptible to bending, and the support structure may shift laterally, particularly in the lateral direction of the step extension in the stepped regions. The support structure may deviate undesirably from its claimed position. Therefore, deviations / offsets in the lateral plane may cause the support structure to overlap with openings formed in the outer insulating layer used to form the contact plugs. That is, at least some openings may land completely or partially on the support structure. Because the outer insulating layer and the support structure can comprise similar or identical materials, the conductive layer, acting as an etch-stop layer for the openings, may not stop the etching of the openings in the overlapping region. As a result, the support structure may be etched. Damage to the support structure can affect stress balance. Short circuits may also occur when conductive material is deposited to fill the openings used to form the contact plugs.

[0036] In some embodiments, an elongated strip-shaped support structure may then be included in the stepped region of the 3D memory device 100 to provide improved support for the conductive layer of the 3D memory device 100. Figure 1B A top view 130 of a cross-section along the A-A' direction of the stepped region 123 according to some embodiments is shown. For ease of illustration, also... Figure 1A The A-A' direction is shown as an example. It should be understood that... Figure 1B This disclosure is intended only to illustrate the structure of the support structure, contact plug, and GLS, and is not intended to limit the number or exact location of these structures. Figure 1B As shown, the stepped area of ​​the 3D NAND memory device 100 includes support structures 113 / 103, contact plugs 124, and GLS 105. A cross-section shows the lateral plane of the support structures 113 / 103, contact plugs 124, and GLS 105. The lateral plane is defined by two lateral directions: the x-direction (the direction in which the steps in the stepped area extend) and the y-direction (another lateral direction perpendicular to the x-direction). The vertical direction (i.e., the z-direction) is perpendicular to the lateral plane and therefore perpendicular to both the x-direction and the y-direction. Unless otherwise stated, the same concepts used to describe spatial relationships apply throughout this disclosure.

[0037] In the 3D NAND memory device 100, contact plugs 124 are in contact with a conductive layer, thereby providing electrical signals to or transmitting electrical signals out of the semiconductor structure through the formed contact plugs. For example... Figure 1BAs shown, each contact plug 124 is surrounded from different sides by support structures 113 / 103, which support the semiconductor structure and prevent the conductive layer in the region near the contact plug 124 from bending when external forces are applied beyond a tolerable level. Figure 1B As shown, the support structure 113 / 103 may include a first support structure 103 and a set of second support structures 113. The first support structure 103 may be a strip-shaped support structure having an elongated strip shape extending along a first direction (e.g., the x-direction). The first support structure may therefore be referred to as the strip-shaped support structure 103. The second support structures 113 may include a plurality of support structures employing a block shape. Here, the block shape may represent a square, rectangle, L-shape, pentagon, hexagon, rhombus, etc. Figure 1B As shown, these block shapes can be the same or different in shape and size, even within the same step region 123. In some embodiments, the precise shape of the block shape support structure 113 in the fabricated 3D NAND memory device can be more rounded, such as close to a circle, ellipse, etc., but not the precise angular shape as described above, due to diffraction, process effects, or other reasons typically associated with nanoscale lithography. For the first support structure 103, the gaps in the design pattern used in the lithography for forming the strip shape support structure can extend laterally along the word line direction in a straight line pattern in a plan view (parallel to the wafer plane). Therefore, the first support structure 103 can extend along the word line in the step region. In some embodiments, by including multiple strip shape support structures 103, the 3D NAND memory device can also be divided into different memory regions, such as different memory fingers or blocks, by these strip shape support structures. That is, in addition to providing support for the conductive layer, the strip shape support structure 103 can also divide the 3D NAND memory device into multiple blocks and / or fingers, such as Figure 4B The details are described in further detail below.

[0038] In some embodiments, the manufacturing process for forming the first support structure 103 may include photolithography, etching trenches in the stacked structure 120 and the outer insulating layer 122, depositing insulating material into the trenches, and chemical mechanical polishing (CMP). Due to the nature of chemical vapor deposition (CVD) to deposit insulation in narrow trenches, seams and voids are likely to form after CVD. For example, after CVD, an elongated seam 104 may be formed inside the first support structure 103, such as... Figure 1BAs shown. In some embodiments, the elongated seam 104 thus formed may cause the first support structure 103 to crack due to certain stresses (e.g., thermal stress) placed on the formed seam. For example, the elongated seam 104 thus formed may cause the first support structure 103 to crack during subsequent gate line annealing processes in the manufacture of 3D NAND memory devices, or during thermal processing to remove hydrogen or other residues after the formation of the conductive layer. A cracked support structure may lead to degradation or even loss of the support provided by the first support structure 103 to the semiconductor structure.

[0039] In some embodiments, in order to prevent the formation of one or more cracks in the first support structure caused by stress placed on the formed joint 104, according to some embodiments of the present disclosure, the shape of the first support structure 103 may be modified to have a shape including a string of beads aligned along the strip-shaped support structure. Figure 1C A top view of a cross-section 150 of an exemplary 3D memory device having a beaded strip-shaped support structure according to some embodiments of the present disclosure is shown. As shown, instead of simply including an elongated strip-shaped support structure, the first support structure 131 included in the stepped region of the 3D NAND memory device comprises two distinct portions. The first portion 133 may include an elongated central strip-shaped portion extending along a first direction (e.g., the x-direction), similar to... Figure 1B The first support structure 103 is shown. The second part may include a plurality of curved portions 116 projecting from two opposite sides of the elongated central strip-shaped portion. These curved portions 116 may be aligned in pairs along the first part 133, and each pair may appear as a "bead" as a whole. Figure 1B As shown. In order to compare it with Figure 1B The first support structure 103 shown is distinguished as follows: Figure 1C The first support structure 131 shown may also be referred to as a "beaded strip shape support structure," wherein each pair of curved portions, together with the corresponding central strip segment, may be referred to as a "bead." In some embodiments, the curved portion 116 may extend to varying degrees along a second direction (e.g., the y-direction). Thus, the bead referred to in the beaded strip shape support structure may be circular, elliptical in various shapes, etc.

[0040] In some embodiments, to form this beaded strip-shaped support structure, the design pattern used in the photolithography process can be modified to include strings of beads for forming the beaded strip-shaped support structure. Therefore, when elongated trenches are etched in the outer insulating layer and stacked structure to form the strip-shaped support structure, the etched trenches may also include curved portions on two opposite sides of the elongated trenches. For ease of explanation, a segment 135 of the first support structure 131 having curved portions may hereinafter be referred to as a "curved segment," such as... Figure 1C As shown. Compared to the uncurved section 134 of the first support structure 131 (hereinafter referred to as the "narrow section"), these curved sections have more space for the gas deposition process. Therefore, during the deposition process, more gas will enter the curved sections due to the greater open space in these sections. In some embodiments, the gas filling the curved sections will also enter the narrow sections from both sides in the x-direction, which then results in more gaseous dielectric material entering and depositing on the edges of the narrow sections adjacent to the curved sections. Because more dielectric material is deposited on the edges of the narrow sections, the likelihood of seams forming in these edges is greatly reduced, thereby preventing issues such as... Figure 1B The example shown illustrates the formation of an elongated seam typically formed in a strip-shaped support structure. Conversely, shorter seam segments are formed within the beaded strip structure 131, as shown... Figure 1C As shown, the shorter seam segment includes a plurality of short seams 114. Here, a seam refers to a narrow opening formed in a direction (e.g., the x-direction in the formed seams 104 or 114) along the interior and / or surface of a structure (e.g., a strip-shaped support structure) after certain materials have condensed due to an evaporation process. It should be understood that the formed seam ( Figure 1B The elongated joint 104 or Figure 1C The short seam 114 in the diagram does not necessarily extend over the entire support structure in the z direction. Furthermore, the width of each seam in the y direction can also vary over the entire support structure in the z direction. For example, the formed seams (elongated seam 104 or short seam 114) may be narrower, or there may be no seam at all in a vertical position near the substrate 102.

[0041] In some embodiments, the risk of breakage along the beaded strip-shaped support structure 131 can be significantly reduced by breaking the elongated seam 104 into a shorter seam 114 by introducing a bend 116 along the elongated central strip-shaped portion 133, as follows: Figures 2A-3B It is described in further detail in the text.

[0042] Figure 2A A schematic diagram showing a broken seam on a beaded strip-shaped support structure according to some embodiments of the present disclosure is shown. Figure 1A In the strip-shaped support structure shown, an elongated seam is formed within the strip-shaped support structure after the deposition process. In contrast, in the beaded strip-shaped support structure, multiple shorter seams 214 are formed within the beaded strip-shaped support structure, such as... Figure 2AAs shown. The elongated seam breaks into multiple shorter seams primarily due to the uneven distribution of the dielectric material during the deposition process. This uneven distribution is mainly caused by the bends introduced by the support structure along the elongated central strip shape. These bends cause the deposited gaseous dielectric material to flow from the bends into the narrow sections, resulting in more dielectric material being deposited in the bottleneck edge region of the narrow section (one of such regions is formed by...). Figure 2A (Indicated by dashed box 216 in the text). As more dielectric material is deposited in these edge regions, the likelihood of seams forming in these regions is greatly reduced. Therefore, elongated seams that would typically form in a strip-shaped support structure without bends can be broken into multiple seams along the strip-shaped support structure, including the bends, as shown in the example. Figure 1B As shown.

[0043] In some implementations, when the elongated seam is broken into multiple shorter seams, the stress experienced by each seam can be reduced, thus reducing the total stress experienced by the beaded strip-shaped support structure, thereby reducing the risk of cracking during gate line annealing or other heat treatment processes in the manufacturing process of 3D memory devices.

[0044] Figure 3A Simulation results of stresses experienced by strip-shaped support structures of varying lengths are shown. Black boxes 301, 303, and 305 correspond to the simulation results for these support structures if they are incorporated into a 3D NAND memory device. In some embodiments, when the length of the strip-shaped support structure is shorter, the resulting seam length is also shorter (or even no seam is formed after the deposition process). That is, if the width remains constant, the seam length is positively correlated with the length of the strip-shaped support structure. Figure 3A In the simulation results, the darkness of the central portion (indicated by boxes 302, 304, and 306) indicates the stress experienced by the corresponding support structure; therefore, boxes 302, 304, and 306 can also be referred to as stress concentration areas 302, 304, and 306. The larger the stress concentration area, the greater the stress experienced by the corresponding support structure. Figure 3A As can be seen, when the length of the supporting structure is short, as shown in box 301, it is actually a square supporting structure, and the resulting joint length is also short (or there is no joint), and the supporting structure may not experience any stress at all. When the resulting joint becomes longer due to the longer supporting structure, the stress experienced by the corresponding strip-shaped supporting structure also increases because the stress concentration areas in these boxes 304 and 306 are larger. Therefore, the longer the strip-shaped supporting structure, the longer the resulting joint, the larger the stress concentration area, and the greater the stress experienced by the corresponding strip-shaped supporting structure. Figure 3AThe simulation results show that by introducing curved sections along the elongated central strip-shaped support structure, multiple shorter seams are formed instead of elongated seams, thus reducing the stress experienced by the beaded strip-shaped support structure. This can then reduce the risk of cracking during gate line annealing or other heat treatment processes.

[0045] In some implementations, the stress distribution can further reduce the stress experienced by the beaded strip-shaped support structure due to the Prince Rupert's Drop effect. According to the Prince Rupert's Drop theory, large compressive residual stresses in the bending section are distributed near the outer surface of the beads, resulting in a reduction in stress in the y-direction. Due to the distributed residual compressive stresses, the bending portion along the strip-shaped support structure exhibits high fracture toughness, thereby significantly reducing the risk of fracture of the beaded strip-shaped support structure.

[0046] Figure 2B A schematic diagram of stress distribution in a cross-section of a beaded strip-shaped support structure according to some embodiments of the present disclosure is shown, and Figure 2C A schematic diagram of stress distribution in a cross-section of a strip-shaped support structure without beads according to some embodiments of the present disclosure is shown. It can be seen that in the strip-shaped support structure 218 with beads 220, stress is distributed to the surface of the beads, which then leads to a decrease in the y-direction stress of the beaded strip-shaped support structure. In the strip-shaped support structure 222 without beads, the y-direction stress is maintained along the strip-shaped support structure, thus the risk of cracking remains high in the corresponding strip-shaped support structure.

[0047] Figure 3B The simulation results of stresses experienced by strip-shaped support structures with and without beading are further shown. In the strip-shaped support structure indicated by box 311, there are no beads, therefore the simulated y-direction stress remains high along the corresponding strip-shaped support structure, as indicated by the stress concentration area inside the corresponding inner box 312. In the beaded strip-shaped support structures indicated by boxes 313 and 315, the simulated stress in the y-direction is significantly reduced due to the stress distribution caused by the Rupert's Tear effect. From Figure 3B As can be seen from the stress concentration areas in the corresponding inner frames 314 and 316, the strip-shaped support structure indicated in frame 313 has lower stress compared to the strip-shaped support structure indicated in frame 315. This is mainly due to the higher density of the beads 320 embedded along the strip-shaped support structure. Therefore, the stress experienced by the beaded support structure can also be modified by adjusting the density of the embedded beads.

[0048] In some implementations, in addition to density, the shape and size of the beads may also affect the stress experienced by the beaded strip shape support structure. For example, within a certain range, increasing the size of the beads can further reduce the stress experienced by the beaded strip shape support structure. Similarly, changing the curvature of the beads can also modify the stress experienced by the beaded strip shape support structure. Certain other parameters related to the beads can also be adjusted. Accordingly, by adjusting different parameters of the beads, the stress experienced by the beaded strip shape support structure can be optimized, thereby minimizing the risk of cracking during gate line annealing processes or other similar processes that may lead to cracking along the support structure.

[0049] In light of the foregoing, the reduced stress experienced by the beaded strip-shaped support structure may be due to stress redistribution caused by the beaded structure and the elongated seams breaking into multiple short seams. Since the risk of cracking between the corresponding support structures is reduced, the performance of the disclosed 3D memory device can be improved.

[0050] Figure 4A A side view of a cross-section of an exemplary 3D memory device 400 according to some aspects of this disclosure is shown. It should be understood that... Figure 4A A 3D memory device 400 is illustrated during a manufacturing process, which may include a substrate 402 and a stacked structure 420 laterally formed on the substrate 402. The substrate 402 may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In some embodiments, the substrate 402 is a thinned substrate (e.g., a semiconductor layer) thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. The substrate 402 of the 3D memory device 400 may include two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in a plane defined by the x and y directions.

[0051] Consistent with this disclosure, the stacked structure 420 may include a core region 421 and two stepped regions 423-1 and 423-2 on two opposite sides adjacent to the core region 421. It should be understood that, although only one cross-section of the 3D memory device 400 is shown... Figure 4A The diagram shows two stepped regions 423-1 and 423-2, but the 3D memory device according to this disclosure may include three or more stepped regions surrounding the core region. Furthermore, in some embodiments, the stepped regions may alternatively be located between two core regions.

[0052] Figure 4BA top view of a cross-section of an exemplary 3D memory device 440 having a stepped region located between two core regions according to some embodiments of the present disclosure is shown. As shown, the exemplary 3D memory device 440 may include core regions 421-1 and 421-2 and a stepped region 423. The stepped region 423 may be a central stepped region that equally divides the core regions 421-1 / 421-2 into first and second core regions. For example, the first and second core regions 421-1 and 421-2 may be symmetrical about the central stepped region 423 in the x-direction. It should be understood that in some examples, the stepped region 423 may be in the middle, but not in the middle (central) of the core regions 421-1 and 421-2, such that the first and second core regions 421-1 and 421-2 may have different dimensions. Figure 4B As shown and as previously described, the stepped area 423 may include a contact plug, a support structure, and a GLS. The support structure may include one or more beaded strip-shaped support structures. For example, three beaded strip-shaped support structures 413 may be included in a portion of the stepped area, such as... Figure 4B As shown.

[0053] In some embodiments, in addition to providing mechanical support, these beaded strip-shaped support structures 413 can also divide the 3D memory device 440 into different blocks and / or fingers, as described above. For example, as Figure 4B As shown, when combined with GLS 438 in core regions 421-1 and 421-2, the beaded strip-shaped support structure 413 in the stepped region 423 can divide the 3D memory device 440 into different blocks 433. In some embodiments where the 3D memory device 440 is a NAND flash memory device, the block 433 is the smallest erasable cell of the NAND flash memory device. In some embodiments, each block 433 may also include multiple fingers (e.g., fingers 431) separated in the y-direction by certain GLSs (e.g., GLS 438). It should be understood that although GLS 438 is shown as dividing the 3D memory device 440 into different fingers in core regions 421-1 and 421-2, in some embodiments, one or more beaded strip-shaped support structures 413 may also extend into or be included in core regions 421-1 and 421-2 to replace the GLS in the core regions to divide the 3D memory device 440 into blocks and / or fingers. That is, the GLS used to separate the 3D memory device 440 in the core region can be partially or completely replaced by the beaded strip-shaped support structure 413. In some embodiments, the GLS can also extend from the core region 421-1 / 421-2 into the stepped region 423 to divide the 3D memory device 440 into different blocks 433. For example, as Figure 4BAs shown, the GLS 436 can extend continuously across core regions 421-1 and 421-2 and stepped region 423 to divide the 3D memory device 440 into different blocks 433. When both the GLS 436 and the beaded strip-shaped support structure 413 are used to divide the 3D memory device 440 into blocks 433, the GLS 436 and the beaded strip-shaped support structure 413 can be alternately aligned between adjacent blocks in the stepped region 423, and other arrangements of the GLS 436 and the beaded strip-shaped support structure 413 are also possible and envisioned.

[0054] Return to reference Figure 4A In some embodiments, multiple channel structures 422 may be further formed in the core region (e.g., Figure 4A Core area 421 or Figure 4B In the core regions 421-1 and 421-2, a channel structure 422 extends vertically through the stacked structure 420. In some embodiments, each channel structure 422 includes a storage film 4220, which sequentially includes a tunneling layer 4226, a storage layer 4224 (also referred to as a "charge trap layer"), and a barrier layer 4222. The channel structure 422 may also include a semiconductor channel 4228, which is formed by filling the channel structure 422 with semiconductor material. In some embodiments, the channel structure 422 has a cylindrical shape, and the semiconductor channel 4228 and the tunneling layer 4226, storage layer 4224, and barrier layer 4222 of the storage film 4220 are arranged radially from the center of the cylinder to the outer surface in this order. A semiconductor plug (not shown) may be provided in the lower portion of the channel structure 422, which contacts the semiconductor channel 4228 and acts as a channel controlled by the source selection gate of the channel structure 422.

[0055] In some embodiments, the stacked structure 420 may further include a plurality of interleaved conductive layers 426 and dielectric layers 428, which are vertically stacked in a stepped manner in the stepped region 423, such as... Figure 4A As shown. The staggered conductive layers 426 and dielectric layers 428 are part of a memory stack (not shown). The number of pairs of conductive layers 426 and dielectric layers 428 in the memory stack determines the number of memory cells in the 3D memory device 400. It should be understood that in some embodiments, the memory stack may have a multi-layer stack architecture (not shown), which includes multiple memory stacks stacked on top of each other. The number of pairs of conductive layers 426 and dielectric layers 428 in each memory stack may be the same or different.

[0056] The conductive layers 426 and dielectric layers 428 in the stacked structure 420 may alternate in the vertical direction. In other words, in addition to the layers at the top or bottom of the memory stack, each conductive layer 426 may be adjacent to two dielectric layers 428 on both sides, and each dielectric layer 428 may be adjacent to two conductive layers 426 on both sides. The conductive layers 426 and dielectric layers 428 may form multiple steps in the stepped region 423. The conductive layer 426 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), tantalum (Ta), polysilicon, doped silicon, silicide, or any combination thereof. Each conductive layer 426 may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the conductive layer 426 may extend laterally as a word line, terminating at one or more stepped structures in the stepped region 423. Each dielectric layer 428 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. It can act as an insulating layer to separate conductive layers and / or lines from contact with each other, which could otherwise cause a short circuit or malfunction in a semiconductor device. The channel structure 422 can extend through multiple pairs, each pair comprising a conductive layer 426 and a dielectric layer 428 (referred to herein as a “conductive / dielectric layer pair”). The number of conductive / dielectric layer pairs in the stacked structure 420 (e.g., 32, 64, or any other number) determines the number of memory cells in the 3D memory device 400.

[0057] In some embodiments, the 3D memory device 400 further includes a plurality of contact plugs 424 formed in the stepped region 423, which are electrically connected to the stacked structure 420, such as Figure 4A As shown. Each contact plug 424 can extend vertically through the outer insulating layer 427 covering the stacked structure 420 until it reaches and contacts the conductive layer 426 of the stacked structure 420, thus electrically connecting to the conductive layer 426. The farther the contact plug 424 is from the core region 421 of the stacked structure 420, the greater the depth to which the contact plug 424 extends vertically through the stacked structure 420 to reach its corresponding conductive layer 426. The contact plug 424 may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, Al, or Ta) or a silicide layer surrounded by an adhesive layer (e.g., TiN). In some embodiments, the 3D memory device 400 further includes a plurality of support structures 425 in a stepped region. These support structures 425 may have different shapes and sizes, as shown below. Figure 4C Further details are provided below.

[0058] Figure 4C Some aspects of this disclosure are shown. Figure 4AA top view 460 of a cross-section of the stepped region of the 3D memory device 400 shown in Figure / 4B. As shown, the stepped region includes multiple arrays of contact plugs 424, multiple arrays of block-shaped (e.g., square or rectangular) support structures 412, and multiple beaded strip-shaped support structures 413. Figure 4C (Only one is shown in the diagram). Although only one stepped area is used as an exemplary embodiment of this disclosure, it should be understood that the same support structure design can be applied in the same way to other stepped areas or even the core area of ​​the 3D memory device according to this disclosure. For example, the core area 421 of the 3D memory device 400 may include one or more beaded strip-shaped support structures.

[0059] In some embodiments, each bead 414, including its central strip segment 416, may have a circular shape based on the design pattern used for the support structure. Alternatively, each curved portion above or below the elongated central strip segment may be a semicircle. Other bead shapes are also possible. For example, each curved portion above or below the elongated central strip segment may be greater than half a circle, less than half a circle, or may be a semi-ellipse, greater than a semi-ellipse, less than a semi-ellipse, etc. In some embodiments, the radius r of the aforementioned circle or ellipse may also vary and may have a specific proportion with respect to the width d1 of the elongated central strip segment. For example, the radius r of the aforementioned circle or ellipse may be between 1 / 4 of d1 and twice d1. Additionally, the distance d2 between the edges of adjacent beads may also vary and may be within a specific range (e.g., between 1 / 6 of d1 and three times d1), and may be optimized to a specific value depending on the shape and size of the bead. In some embodiments, the beads supporting the structure along a single strip shape may have the same shape and size. In some embodiments, the beads supporting the structure along a single strip shape may have different shapes and sizes. For example, two types of beads may be alternately aligned along the strip-shaped support structure. In some embodiments, two different strip-shaped support structures in the same or different stepped areas may have the same or different types of embedded beads.

[0060] In some embodiments, the stepped region of the 3D memory device 400 may further include a plurality of gate slots 405. The plurality of gate slots 405 may extend parallel to each other along a first direction (e.g., the x-direction) while being aligned with each other at a distance along a second direction perpendicular to the first direction (e.g., the y-direction), such as... Figure 4C As shown.

[0061] According to this disclosure, the stepped area of ​​the 3D memory device 400, including contact plugs, support structures, and gate gaps, can be adjusted through various modifications. In some embodiments, the block-shaped support structures created by filling holes with insulating material can be arranged in a two-dimensional array, such as... Figure 4CAs shown. Similarly, contact plugs created by filling contact holes with conductive material can also be arranged in a two-dimensional array in a top view. Each row of the contact plug array can be surrounded by one or more rows of block-shaped support structure arrays (e.g., two adjacent rows of block-shaped support structures) and a beaded strip-shaped support structure, as shown. Figure 4C As shown. This arrangement of the support structure and contact plugs can provide structural support over the entire stepped area where the support structure and contact plugs are located. In some embodiments, each contact plug 424 is surrounded by three or more block-shaped support structures 412 from three different sides and beaded strip-shaped support structures 413 on a fourth side in the stepped area 423, as shown. Figure 4C As shown. This provides all-around protection for the vertical structure of the contact plug 424 to prevent unwanted squeezing or bending forces that would arise when the stacked structure 420 is manufactured very high, thus preventing excessive stress on the internal components of the 3D memory device. It should be understood that the support structure 412 in the array is not limited to a block shape, but can take many other shapes (e.g., ellipse, circle).

[0062] In some embodiments, three or more block-shaped support structures and beaded strip-shaped support structures may be equally separated along a circle surrounding the contact plug on the transverse plane of the stepped area. It should be understood that the above should also include cases where the three or more block-shaped support structures and beaded strip-shaped support structures are substantially equally separated along the circumference. The term "substantially," when used to describe the separation between support structures, means that the variation in distance between adjacent support structures or the angle toward the surrounded contact plug 424 does not exceed a range such as ±10%. For example, when three block-shaped support structures 412 and one beaded strip-shaped support structure 413 are present, they may be separated at 90 degrees between each pair of adjacent support structures. This provides equal protection to the vertical structure of the contact plug 424 against forces from all directions. In some embodiments, the diameter of the three or more block-shaped support structures and beaded strip-shaped support structures along their equally separated circumference is equal to or less than half the transverse distance between adjacent contact plugs 424. Therefore, the overlap between the contact plug 424 and its surrounding support structures can be reduced.

[0063] Figure 7 A block diagram of an exemplary system 700 having a 3D memory device according to some aspects of this disclosure is shown. System 700 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 7As shown, system 700 may include a host 708 and a memory system 702 having one or more 3D memory devices 704 and a memory controller 706. The host 708 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-a-chip (SoC), such as an application processor (AP). The host 708 may be configured to send or receive data stored in the memory device 704.

[0064] 3D memory device 704 can be any 3D memory device disclosed herein, such as Figure 4A The 3D memory device 400 shown is illustrated. In some embodiments, each 3D memory device 704 includes NAND flash memory. Consistent with the scope of this disclosure, the 3D memory device 704 can be fabricated by laterally forming a stacked structure on a substrate. The stacked structure may have a central region and a stepped region. Subsequently, a plurality of support structures extending vertically in the stepped regions and a plurality of channel structures extending vertically in the central region can be formed. The vertical projection of at least one of the support structures onto the lateral surface of the substrate may have a beaded strip shape. Therefore, the risk of cracking in the 3D memory device due to gate line annealing processes or other similar processes can be greatly reduced. As a result, the electrical performance of the 3D memory device 704 can be improved, which in turn improves the performance of the memory system 702 and system 700, for example, achieving more stable electrical characteristics and increasing its service life.

[0065] According to some embodiments, a memory controller 706 is coupled to a 3D memory device 704 and a host 708 and is configured to control the 3D memory device 704. The memory controller 706 can manage data stored in the 3D memory device 704 and communicate with the host 708. In some embodiments, the memory controller 706 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 706 is designed to operate in a high duty cycle environment, such as an SSD, or as an embedded multimedia card (eMMC) used as a data storage device in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays. The memory controller 706 can be configured to control the operation of the 3D memory device 704, such as read, erase, and program operations. The memory controller 706 can also be configured to manage various functions relating to data stored or to be stored in the 3D memory device 704, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 706 is also configured to process error correction codes (ECC) relating to data read from or written to the 3D memory device 704. The memory controller 706 can also perform any other suitable function, such as formatting the 3D memory device 704. The memory controller 706 can communicate with an external device (e.g., a host 708) according to a specific communication protocol. For example, the memory controller 706 can communicate with an external device via at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0066] The memory controller 706 and one or more 3D memory devices 704 can be integrated into various types of memory devices, for example, included in the same package such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the memory system 702 can be implemented and packaged into different types of end electronic products. Figure 8AIn one example shown, the memory controller 706 and a single 3D memory device 704 can be integrated into a memory card 802. The memory card 802 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 802 may also include a connection between the memory card 802 and a host computer (e.g., Figure 7 The memory card connector 804 is coupled to the host 708. In such a... Figure 8B In another example shown, the memory controller 706 and multiple memory devices 704 can be integrated into the SSD 806. The SSD 806 may also include components for connecting the SSD 806 to a host computer (e.g., Figure 7 The SSD connector 808 is coupled to the host 708 in the memory card 802. In some implementations, the storage capacity and / or operating speed of the SSD 806 is greater than that of the memory card 802.

[0067] Figure 5A-5M A manufacturing process for forming an exemplary 3D memory device 500 according to some embodiments of the present disclosure is shown. Figure 6 A flowchart is shown of a method 600 for forming an exemplary 3D memory device 500 according to some embodiments of the present disclosure. Figure 5A-5M and Figure 6 Examples of the 3D memory device 500 depicted include Figure 4A The 3D memory device 400 depicted herein will be described together. Figure 5A-5M and Figure 6 It should be understood that the operations shown in method 600 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 6 The different execution orders shown.

[0068] refer to Figure 6Method 600 begins at operation 602, wherein a substrate 502 is provided. Substrate 502 may comprise silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In some embodiments, substrate 502 is a thinned substrate (e.g., a semiconductor layer) thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. Substrate 502 of the 3D memory device 500 may comprise two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in a plane defined by x and y directions, both perpendicular to the z direction. In some embodiments, a stop layer (not shown) may be formed on the top surface of substrate 502 using one or more thin-film deposition processes, including but not limited to CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The stop layer may serve as an etch stop. The stop layer may include any dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, or any combination thereof. It should be understood that, in some examples, a pad oxide layer (e.g., a silicon oxide layer) may be formed between the substrate 502 and the stop layer to mitigate stress between the different layers and prevent peeling. It should be understood that, in some examples, the substrate 502 may be removed from the final product of the 3D memory device. For example, the substrate 502 may be replaced by a semiconductor layer, such as a polysilicon layer, formed by a thin-film deposition process.

[0069] Method 600 proceeds to operation 604, wherein a stacked structure can be formed on substrate 502, such as Figure 5A As shown. At the start of this operation, a dielectric stack 529 comprising multiple pairs of first dielectric layer 525 (referred to herein as a “sacrificial layer”) and second dielectric layer 528 (referred to herein as a “dielectric layer”, and collectively as a “dielectric layer pair”) may be formed on substrate 502. According to some embodiments, the dielectric stack 529 may include staggered sacrificial layers 525 and dielectric layers 528. In some embodiments, the sacrificial layer 525 is subsequently replaced by a conductive layer 526, which will be described in detail below. The dielectric layers 528 and sacrificial layers 525 may be deposited alternately on substrate 502 to form the dielectric stack 529. In some embodiments, each dielectric layer 528 comprises a silicon oxide layer, and each sacrificial layer 525 comprises a silicon nitride layer. The dielectric stack 529 may be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0070] In some embodiments, the dielectric stack 529 may include a central core region 521 and two stepped regions 523-1, 523-2 on the sides adjacent to the core region 521. It should be understood that, although only one cross-section of the fabrication of the intermediate 3D memory device 500 is shown... Figure 5A Two stepped regions 523-1 and 523-2 are shown, but the 3D memory device 500 according to this disclosure may include three or four stepped regions surrounding a core region. The two or more stepped regions are collectively referred to as stepped region 523. As will be described in further detail below, a plurality of channel structures 522 are formed in the core region, and a plurality of support structures (not shown) and a plurality of contact plugs 524 are formed in the stepped regions.

[0071] In some embodiments, the stepped structure 540 may be further formed in the stepped regions 523-1, 523-2 of the dielectric stack 529, such as Figure 5B As shown. A stepped structure 540 can be formed by performing multiple so-called “trimming etch” cycles on the dielectric layer pairs of the dielectric stack 529 toward the substrate 502. Due to the repeated trimming etch cycles applied to the dielectric layer pairs of the dielectric stack 529, the dielectric stack 529 may have one or more sloping edges, and the upper dielectric layer may be shorter than the lower dielectric layer.

[0072] Method 600 then proceeds to operation 606, in which multiple channel structures extending vertically in the core region 521 are formed. For example... Figure 5C As shown, multiple channel holes 533 are vertically etched in the core region 521. In some embodiments, multiple openings are formed such that each opening becomes the location for the channel structure 522 of an individual to be grown in a subsequent process (e.g., Figure 5D (As shown). The fabrication process for forming the channel via 533 may include wet etching and / or dry etching, such as deep reactive ion etching (DRIE). Etching of the channel via 533 may continue until it reaches the substrate 502. In some embodiments, etching conditions, such as etching rate and time, may be controlled to ensure that each channel via 533 has reached the substrate 502, sometimes by means of a stop layer, to minimize the borehole variation between the channel via 533 formed therein and the channel structure 522.

[0073] In some embodiments, each channel structure 522 may include a storage film 5220 and a semiconductor channel 5228. For example... Figure 5DAs shown, to form the channel structure 522, a memory film 5220 and a semiconductor channel 5228 can be sequentially formed along the sidewalls and bottom surface of the channel via 533. In some embodiments, the memory film 5220 may include a barrier layer 5222, a memory layer 5224, and a tunneling layer 5226. In some embodiments, the barrier layer 5222, the memory layer 5224, and the tunneling layer 5226 are first deposited in this order along the sidewalls and bottom surface of the channel via 533 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable processes, or any combination thereof to form the memory film 5220. The semiconductor channel 5228 can then be formed by depositing a semiconductor material such as polycrystalline silicon (e.g., undoped polycrystalline silicon) over the tunneling layer 5226 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (“SONO” structure) are sequentially deposited to form a barrier layer 5222, a memory layer 5224, and a tunneling layer 5226 of a semiconductor channel 5228 and a memory film 5220.

[0074] In some embodiments, the outer insulating layer 560 may be formed on the dielectric stack 529, such as Figure 5E As shown. In some embodiments, the outer insulation layer 560 may at least cover the stepped region 523. In other embodiments, the outer insulation layer 560 may completely cover both the stepped region 523 and the core region 521. The outer insulation layer 560 can protect the channel structure 522 from damage by subsequent manufacturing processes.

[0075] Method 600 then proceeds to operation 608, in which a plurality of support structures are formed through the stacked structure in the outer insulating layer 560 and the stepped region 523. In some embodiments, to form support structures in the dielectric stack 529, a plurality of holes 531 are vertically etched in the stepped region 523, such as... Figure 5F As shown.

[0076] According to some embodiments of this disclosure, the etching of the hole 531 can be performed using a photomask (not shown) with a design pattern having a beaded strip shape 435 (seamless) and a block shape, such as Figure 4D As shown, Figure 4DThe diagram illustrates a design pattern of a support structure within a portion of a stepped region according to some embodiments. Therefore, the formed aperture 531 can have certain square or rectangular shapes, beaded stripe-shaped apertures (or trenches), or certain other types of apertures. In some embodiments, the photomask pattern can be optimized to obtain apertures with suitable shapes and sizes (e.g., suitable bead shapes and sizes for beaded stripe-shaped apertures). The fabrication process for forming aperture 531 can include wet etching and / or dry etching, such as DRIE. Aperture 531 can be etched to extend through the entire height of the dielectric stack 529 and reach the substrate 502, as... Figure 5F As shown.

[0077] In some embodiments, the holes 531 can be filled with insulating material to form multiple support structures 532, such as Figure 5G As shown. The insulating material may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectric, or any combination thereof. The filled support structure 532 can support the overall structural robustness of the stacked structure and prevent bending of various internal components (e.g., word lines to be formed). In some embodiments, the filled support structure (e.g., a strip-shaped support structure) can additionally divide the 3D memory device 500 into multiple blocks or fingers. In other embodiments, depending on the manufacturer's needs and / or the application of the 3D memory device 500, the support structure 532 may also be formed in the core region 521.

[0078] In some embodiments, a plurality of gate gaps 535 may be further formed in the outer insulating layer 560 and the dielectric stack 529 and extend vertically through the outer insulating layer 560 and the dielectric stack 529, such as Figure 5H The diagram is shown as a top view 550 of a cross-section of the stepped region of the 3D memory device 500. In some embodiments, the manufacturing process for forming the gate slot 535 includes wet etching and / or dry etching, such as DRIE. In some embodiments, the gate slot 535 may extend laterally through both the core region 521 and the stepped region 523 in a first direction (e.g., the x-direction) on a plane defined by the x and y directions. The gate slots 535 may be spaced apart from each other along a second direction (e.g., the y-direction) perpendicular to the first direction. Although the gate slots 535 are... Figure 5H The grid is shown to have one or more gaps therebetween, but it should be understood that continuous grid gaps 535 are also contemplated according to this disclosure, which means that no gaps are generated along the extended grid gaps 535.

[0079] Subsequently, a gate replacement process can be performed through the gate gap 535 to replace the dielectric stack 529 within the stacked structure 520, which is also referred to as the memory stack (e.g., ...). Figure 5J(As shown). Specifically, the lateral recess 537 is first formed by removing the sacrificial layer 525 through the gate gap 535, as shown. Figure 5I As shown. In some embodiments, by passing through the gate slot 535 ( Figure 5I An etchant (not shown) is applied to remove the sacrificial layer 525 to create lateral recesses 537 interleaved between the dielectric layers 528. The etchant may include any suitable etchant that selectively etches the sacrificial layer 525 relative to the dielectric layers 528. In some embodiments, the removal of the sacrificial layer 525 may result in stress imbalances on the stacked structure, particularly in the step region 523. During the removal of the sacrificial layer 525, the resulting support structure 532 may provide necessary support to the stacked structure in the step region. In some embodiments, after the removal of the sacrificial layer 525, the conductive layer 526 (including the gate electrode and adhesive layer) may be further deposited into the lateral recesses 537 through the gate gaps 535, such as... Figure 5J As shown. In some embodiments, a gate dielectric layer (not shown) is deposited into the lateral recess 537 prior to the conductive layer 526, such that the conductive layer 526 is deposited on the gate dielectric layer. The conductive layer 526, such as a metal layer, can be deposited using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a gate dielectric layer, such as a high-k dielectric layer, is also formed along the sidewalls of the gate slot 535 and at the bottom of the gate slot 535. According to some embodiments, this forms a stacked structure 520 comprising staggered conductive layers 526 and dielectric layers 528, replacing the dielectric stack 529. In some embodiments, a portion of the substrate 502 is replaced with a conductive material via the gate slot 535. Thus, the substrate 502 can be electrically connected to the channel structure 522. Subsequently, the gate slot 535 can be filled with an insulating material to form a gate line. Similar to the gate slot 535, the gate line can extend continuously or discretely through the core region 521 and the stepped region 523.

[0080] In some embodiments, a gate line annealing process can be performed after the gate line is formed to remove hydrogen or other residues. However, the gate line annealing process may exert stress on the seams formed along the strip-shaped support structure, which could lead to the risk of cracking if the seams formed along the strip-shaped support structure are not stress-resistant. In the disclosed 3D memory device, because the beads are included along the elongated central strip-shaped support structure 435 during the photolithography process... Figure 4D In the design pattern 480, the formed beaded strip-shaped support structure can effectively reduce the stress placed on the support structure, thereby reducing the risk of cracking in the gate line annealing process or other similar or different processes that may lead to increased stress on the formed strip-shaped support structure.

[0081] Method 600 then proceeds to operation 610, wherein a plurality of contact plugs electrically connected to the stacked structure 520 are formed in the stepped region 523. In some embodiments, a plurality of contact holes 539 may be formed by vertical etching in the stepped region 523 of the stacked structure 520, such as Figure 5K As shown. This formation process may include wet etching and / or dry etching, such as DRIE. Each contact hole 539 may be etched until its bottom reaches the conductive layer 526. Therefore, an electrical connection can be established between the word lines of the stacked structure 520 and the peripheral circuitry (not shown) of the 3D memory device 500 via contact plugs 524, as... Figure 5L As shown, it is formed by filling contact hole 539 with conductive material using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. The contact material may include, but is not limited to, W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the upper surface of contact plug 524 is flush with the upper surface of dielectric overlay 560 (not shown).

[0082] Figure 5M A top view of a cross-section of a stepped region 523-1 of a 3D memory device 500 after support structures and contact plugs have been formed in the stepped region according to some embodiments of the present disclosure is shown. As shown, the stepped region 523-1 may include multiple arrays of contact plugs 524 and various support structures 512 / 513. Although only the stepped region 523-1 is used as an exemplary embodiment of the present disclosure, it should be understood that, according to the present disclosure, the same support structures can be similarly applied to other stepped regions or even some core regions 521 of the 3D memory device 500.

[0083] The support structure according to this disclosure may include at least one beaded strip-shaped support structure 513. In some embodiments, the support structure according to this disclosure may further include a block-shaped support structure 512, which, together with at least one beaded strip-shaped support structure 513, provides support for the conductive layer in the 3D memory device.

[0084] In some embodiments, the 3D memory device 500 further includes at least one gate slot 530. In some embodiments, the gate slot 530 extends continuously through the core region 521 and the stepped region 523. In other embodiments, the gate slots 530 extend discretely through the same region, meaning that one or more gaps are created along the extended at least one gate slot 530. Multiple gate slots 530 may extend parallel to each other along a first direction (e.g., the x-direction) while being aligned with each other at a distance along a second direction perpendicular to the first direction (e.g., the y-direction), such as... Figure 5M As shown.

[0085] According to this disclosure, the stepped area, including the contact plug and support structure, such as stepped area 570, can be modified through various improvements. In some embodiments, the block-shaped support structure 512 can be arranged in a two-dimensional array, such as... Figure 5M As shown. Similarly, the contact plugs 524 can also be arranged in a two-dimensional array. Each row of the array of contact plugs 524 can be separated by one or more rows of a block-shaped support structure array. In some embodiments, contact plugs 524 are not formed between certain adjacent rows of the support structure array. Figure 5M (Not shown in the diagram). For example, there is an additional row of block-shaped support structures 512 aligned between the current row of the block-shaped support structure and the extended gate slot 530. This arrangement of the support structures and contact plugs can provide structural support over the entire substrate region where such support structures and contact plugs are located. In some embodiments, each contact plug 524 is surrounded in a stepped region 523 by three or more block-shaped support structures 512 and a beaded strip-shaped support structure 513. This provides all-around protection for the vertical structure of the contact plugs 524 against unwanted compressive or bending forces that may arise when the stacked structure 520 is manufactured very high, thereby preventing excessive stress on the internal components of the substrate.

[0086] In some embodiments, three or more block-shaped support structures 512 and beaded strip-shaped support structures 513 may be equidistantly separated along the circumference of the surrounding contact plug 524 on the lateral surface of the stacked structure. It should be understood that the above should also include cases where the three or more block-shaped support structures and beaded strip-shaped support structures are substantially equidistant along the circumference. The term "substantially," when used to describe the separation between support structures, means that the variation in distance between adjacent support structures or the angle toward the surrounded contact plug 524 does not exceed a range such as ±10%. For example, when three block-shaped support structures and one strip-shaped support structure are present, they may be separated at 90 degrees between each pair of adjacent support structures. This provides equal protection to the vertical structure of the contact plug 524 against forces from all directions. In some embodiments, the diameter of the three or more block-shaped support structures and beaded strip-shaped support structures along their equally separated circumferences is equal to or less than half the lateral distance between adjacent contact plugs 524. Therefore, overlap between the contact plug 524 and its surrounding support structures can be reduced.

[0087] According to one aspect of this disclosure, a 3D memory device includes a stacked structure comprising a core region and a stepped region, a channel structure extending through the stacked structure in the core region, and a first support structure extending through the stacked structure in the stepped region. The first support structure includes a first portion extending along a first direction and a second portion projecting from the first portion along a second direction perpendicular to the first direction.

[0088] In some implementations, the first support structure is located between two blocks of the 3D memory device.

[0089] In some embodiments, the 3D memory device further includes a second support structure. The second support structure includes a set of block-shaped support structures arranged in a two-dimensional array.

[0090] In some implementations, the second support structure is located within the same storage block.

[0091] In some embodiments, at least one of the block-shaped support structures has a square shape, a rectangular shape, or an L-shaped shape.

[0092] In some embodiments, the second portion of the first support structure includes a plurality of curved portions protruding from two opposite sides of the first portion of the first support structure.

[0093] In some embodiments, multiple curved portions are aligned in pairs along two opposite sides of a first portion of the first support structure.

[0094] In some implementations, two adjacent curved portions are equidistant along a first direction.

[0095] In some embodiments, the radius of the curved portion is between one-quarter of the width of the first portion in the second direction and twice the width of the first portion in the second direction.

[0096] In some implementations, the distance between the edges of two adjacent curved portions is between 1 / 6 of the width of the first portion in the second direction and three times the width of the first portion in the second direction.

[0097] In some implementations, each curved portion has the same shape.

[0098] In some implementations, each curved portion has the shape of a portion of a circle.

[0099] In some implementations, each curved portion has the shape of a portion of an ellipse.

[0100] In some embodiments, the 3D memory device further includes a plurality of gate slots extending discontinuously along a first direction. The plurality of gate slots are located in the same memory block of the 3D memory device.

[0101] According to another aspect of this disclosure, the 3D memory device includes a stacked structure comprising a core region and a stepped region, a channel structure extending through the stacked structure in the core region, and a first support structure extending through the stacked structure in the stepped region. The first support structure has a beaded strip shape in a plan view.

[0102] In some embodiments, the first support structure includes an elongated central strip extending along a first direction.

[0103] In some embodiments, the first support structure also includes one or more beads aligned in pairs along the extended central strip.

[0104] In some implementations, one or more beads have the same shape.

[0105] In some implementations, one or more beads comprise two sets of beads with different shapes, each set having the same shape.

[0106] In some implementations, the edges of adjacent beads are equidistant along a first direction.

[0107] In some embodiments, the first support structure includes one or more joints within the elongated central strip structure.

[0108] In some embodiments, the 3D memory device further includes a plurality of gate slots extending discontinuously along a first direction. The plurality of gate slots are located in the same memory block of the 3D memory device.

[0109] In some embodiments, the 3D memory device further includes a second support structure. The second support structure includes a set of block-shaped support structures arranged in a two-dimensional array.

[0110] In some embodiments, the 3D memory device also includes a plurality of contact plugs formed in a stepped region.

[0111] In some implementations, each contact plug is surrounded by three or more block-shaped support structures and a first support structure in a stepped area.

[0112] According to another aspect of this disclosure, a method for forming a three-dimensional (3D) memory device includes: forming a stacked structure including a core region and a stepped region; forming a channel structure extending through the stacked structure in the core region; and forming a first support structure extending through the stacked structure in the stepped region. The first support structure has a beaded strip shape in a plan view.

[0113] In some embodiments, forming the first support structure further includes forming an elongated groove through the stacked structure in the stepped area and filling the elongated groove with an insulating material to form the first support structure. The elongated groove includes a plurality of curved portions projecting from two opposite sides of the elongated slot.

[0114] In some embodiments, the beaded strip shape is a shape that includes an elongated central strip shape along which one or more beads are embedded.

[0115] In some implementations, elongated trenches are etched at the location of the stacked structure between two adjacent blocks of the 3D memory device.

[0116] In some embodiments, the method further includes forming a second support structure. The second support structure comprises a set of block-shaped support structures arranged in a two-dimensional array.

[0117] In some embodiments, the method further includes etching multiple channel holes through the stacked structure in the core region and filling the channel holes with a semiconductor layer and a composite dielectric layer to form multiple channel structures.

[0118] In some embodiments, the method further includes forming a plurality of contact plugs in the stepped area.

[0119] According to another aspect of this disclosure, a system includes a 3D memory device configured to store data and a memory controller coupled to the 3D memory device and configured to control the 3D memory device. The 3D memory device includes a stacked structure comprising a core region and a stepped region, a channel structure extending through the stacked structure in the core region, and a first support structure extending through the stacked structure in the stepped region. The first support structure has a beaded strip shape in a plan view.

[0120] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Therefore, based on the teachings and guidance set forth herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0121] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A three-dimensional (3D) memory device, comprising: Stacked structure, including core area and stepped area; A channel structure extends through the stacked structure within the core region; as well as A first support structure extends through the stacked structure within the stepped area. The first support structure includes a first portion extending along a first direction and a second portion protruding from the first portion along a second direction perpendicular to the first direction. Wherein, the first support structure is located between two storage blocks of the three-dimensional memory device along the first direction, and The first support structure includes one or more seams within the elongated central strip structure.

2. The three-dimensional memory device according to claim 1, further comprising a second support structure, wherein, The second support structure includes a set of block-shaped support structures arranged in a two-dimensional array.

3. The three-dimensional memory device according to claim 2, wherein, The second support structure is located within the same storage block.

4. The three-dimensional memory device according to claim 2, wherein, At least one of the block-shaped support structures has a square shape, a rectangular shape, or an L-shaped shape.

5. The three-dimensional memory device according to claim 1, wherein, The second portion of the first support structure includes a plurality of curved portions protruding from two opposite sides of the first portion of the first support structure.

6. The three-dimensional memory device according to claim 5, wherein, The plurality of curved portions are aligned in pairs along the two opposite sides of the first portion of the first support structure.

7. The three-dimensional memory device according to claim 5, wherein, The two adjacent curved sections are equidistant from each other along the first direction.

8. The three-dimensional memory device according to any one of claims 5-7, wherein, The radius of the curved portion is between 1 / 4 of the width of the first portion in the second direction and twice the width of the first portion in the second direction.

9. The three-dimensional memory device according to any one of claims 5-7, wherein, The distance between the edges of two adjacent curved portions is between 1 / 6 of the width of the first portion in the second direction and three times the width of the first portion in the second direction.

10. The three-dimensional memory device according to any one of claims 5-7, wherein, Each of the curved sections has the same shape.

11. The three-dimensional memory device according to any one of claims 5-7, wherein, Each of the curved sections has the shape of a portion of a circle.

12. The three-dimensional memory device according to any one of claims 5-7, wherein, Each of the curved sections has the shape of a portion of an ellipse.

13. The three-dimensional memory device according to any one of claims 1-7, further comprising a plurality of gate slots extending discontinuously along the first direction, wherein, The plurality of gate gaps are located in the same storage block of the three-dimensional memory device.

14. A three-dimensional (3D) memory device, comprising: Stacked structure, including core area and stepped area; A channel structure extends through the stacked structure within the core region; as well as A first support structure extends through the stacked structure within the stepped area. The first support structure has a beaded strip shape in the plan view. Wherein, the first support structure is located between two storage blocks of the three-dimensional memory device along a first direction, and The first support structure includes one or more seams within the elongated central strip structure.

15. The three-dimensional memory device according to claim 14, wherein, The first support structure also includes one or more beads aligned in pairs along the elongated central strip structure.

16. The three-dimensional memory device according to claim 15, wherein, The one or more beads have the same shape.

17. The three-dimensional memory device according to claim 15, wherein, The one or more beads comprise two sets of beads with different shapes, each set having the same shape.

18. The three-dimensional memory device according to claim 15, wherein, The edges of adjacent beads are equidistant along the first direction.

19. The three-dimensional memory device according to any one of claims 14-18, further comprising a plurality of gate slots extending discontinuously along the first direction, wherein, The plurality of gate gaps are located in the same storage block of the three-dimensional memory device.

20. The three-dimensional memory device according to any one of claims 14-18, further comprising a second support structure, wherein, The second support structure includes a set of block-shaped support structures arranged in a two-dimensional array.

21. The three-dimensional memory device according to any one of claims 14-18, further comprising a plurality of contact plugs formed in the stepped region.

22. The three-dimensional memory device according to claim 21, wherein, Each contact plug is surrounded by three or more block-shaped support structures and the first support structure in the stepped area.

23. A method for forming a three-dimensional (3D) memory device, comprising: A stacked structure is formed, the stacked structure including a core area and a stepped area; A channel structure is formed that extends through the stacked structure in the core region; as well as A first support structure is formed extending through the stacked structure in the stepped area, wherein the first support structure has a beaded strip shape in a plan view. The first support structure is located between two storage blocks of the three-dimensional memory device along a first direction. The first support structure includes one or more seams within the elongated central strip structure.

24. The method according to claim 23, wherein, One or more beads are embedded along the elongated central strip structure.

25. The method according to claim 23 or 24, wherein, The first support structure also includes: An elongated groove is formed in the stepped area, penetrating the stacked structure, wherein the elongated groove includes a plurality of curved portions projecting from two opposite sides of the elongated gap; and The elongated groove is filled with insulating material to form the first support structure.

26. The method of claim 25, wherein, The elongated trench is etched at the location of the stacked structure between two adjacent blocks of the three-dimensional memory device.

27. The method according to any one of claims 23, 24 and 26, further comprising: A second support structure is formed, wherein the second support comprises a set of block-shaped support structures arranged in a two-dimensional array.

28. The method according to any one of claims 23, 24 and 26, further comprising: Multiple channel holes are etched through the stacked structure in the core region; as well as The channel holes are filled with semiconductor layers and composite dielectric layers to form multiple channel structures.

29. The method according to any one of claims 23, 24 and 26, further comprising: Multiple contact plugs are formed in the stepped area.

30. A memory system comprising: A three-dimensional (3D) memory device configured to store data, the three-dimensional memory device comprising: Stacked structure, including core area and stepped area; Channels extending through the stacked structure in the core region; and A first support structure extends through the stacked structure in the stepped area, wherein the first support structure has a beaded strip shape in a plan view, wherein the first support structure is located between two memory blocks of the three-dimensional memory device along a first direction, and wherein the first support structure includes one or more seams within an elongated central strip structure; and A memory controller is coupled to the three-dimensional memory device and configured to control the three-dimensional memory device.

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