Storage system and semiconductor storage device

Abstract

Embodiments of the present invention provide a storage system and a semiconductor storage device capable of improving the performance of an erase operation. The storage system of the embodiment includes: a semiconductor storage device including a first storage cell capable of storing data; and a controller that outputs a first parameter related to an erase voltage used in a first erase operation on the first storage cell and a first command instructing the first erase operation to be performed. The controller outputs the first command after outputting the parameter to the semiconductor storage device. The semiconductor storage device of the embodiment includes: a storage cell capable of storing data; and a control circuit that performs an erase operation on the storage cell. The control circuit receives a parameter related to the erase voltage used in the erase operation, then receives a first command instructing the first erase operation to be performed, and then performs the erase operation using the parameter.

Description

[0001] This application claims priority from Japanese Patent Application No. 2020-124259 (filing date: July 21, 2020), the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments relate to a storage system and a semiconductor storage device. Background Art

[0003] As a nonvolatile semiconductor memory device, for example, a NAND flash memory in which memory cells are arranged two-dimensionally or three-dimensionally is known. A memory system is composed of the NAND flash memory and a controller that controls the NAND flash memory. Summary of the Invention

[0004] Embodiments of the present invention provide a storage system and a semiconductor storage device capable of improving the performance of an erase operation.

[0005] A storage system of an embodiment comprises: a semiconductor storage device including a first storage unit capable of storing data; and a controller which outputs a first parameter related to an erase voltage used in a first erase operation on the first storage unit and a first command for performing the first erase operation, wherein the controller outputs the first command after outputting the parameters to the semiconductor storage device.

[0006] A semiconductor storage device of an embodiment includes: a storage unit that can store data; and a control circuit that performs an erasing operation on the storage unit, wherein the control circuit receives parameters related to an erasing voltage used in the erasing operation, then receives a first command instructing to perform the erasing operation, and then uses the parameters to perform the erasing operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram showing the configuration of the storage system according to the first embodiment.

[0008] Figure 2 This is a block diagram showing the structure of a memory chip in a semiconductor memory device.

[0009] Figure 3 This is a circuit diagram of a block within a memory cell array.

[0010] Figure 4 This is a cross-sectional view of a portion of a block within a memory cell array.

[0011] Figure 5A This is a diagram showing the relationship between the threshold voltage distribution that a memory cell transistor can take and data.

[0012] Figure 5B This is a diagram showing the erase depth of the memory cell transistor after the erase operation.

[0013] Figure 6 This is a diagram showing a basic erasing operation in the storage system according to the first embodiment.

[0014] Figure 7 3 is a diagram showing the voltage waveforms of various signals during the erase operation.

[0015] Figure 8 This is a flowchart showing a first example of the erasing operation in the storage system according to the first embodiment.

[0016] Figure 9 This diagram shows the interaction (communication) of operations performed between a memory controller and a semiconductor memory device.

[0017] Figure 10 This is a diagram showing an example of a pulse timing management table provided in the memory of the memory controller.

[0018] Figure 11A Yes Figure 8 Flowchart of the process of “determining the pulse time of the erase voltage VERA” in FIG.

[0019] Figure 11B Yes Figure 11A Graph showing the relationship between the reference value Y1 and the number of write and erase operations.

[0020] Figure 12 This is a diagram showing a threshold voltage distribution and a determination level, illustrating a method of determining an erase depth in a first example of an erase operation.

[0021] Figure 13 This is a diagram showing an example of the number of off bits stored in a buffer when reading is performed at a determination level.

[0022] Figure 14 This is a diagram showing another example of the number of cutoff bits stored in the buffer when reading is performed at the determination level.

[0023] Figure 15 This is a diagram showing a command sequence in a first example of the erase operation according to the first embodiment.

[0024] Figure 16 This is a flowchart showing the process of “determining the pulse time of the erase voltage VERA” according to a modification of the first example.

[0025] Figure 17This is a flowchart showing a second example of the erasing operation in the storage system according to the first embodiment.

[0026] Figure 18 Yes Figure 17 Flowchart of the process of “determining the pulse time of the erase voltage VERA” in FIG.

[0027] Figure 19 This is a diagram showing a method for determining the erase depth in a second example of the erase operation, and shows a threshold voltage distribution, a determination level, and data for calculating the number of cutoff bits.

[0028] Figure 20 This is a diagram showing a command sequence in a second example of the erase operation according to the first embodiment.

[0029] Figure 21 This is a diagram showing the relationship between the number of write / erase operations and the erase depth of a memory cell by the erase operation as a comparative example.

[0030] Figure 22 This is a diagram showing the relationship between the number of write / erase operations and the erase depth of the memory cell by the erase operation in the first embodiment.

[0031] Figure 23 This is a flowchart showing a first example of the erasing operation in the storage system according to the second embodiment.

[0032] Figure 24 This diagram shows the interaction of operations performed between a memory controller and a semiconductor memory device.

[0033] Figure 25 This is a diagram showing an example of a voltage value management table provided in the memory of the memory controller.

[0034] Figure 26 Yes Figure 23 Flowchart of the process of “determining the initial voltage value of the erase voltage VERA” in FIG.

[0035] Figure 27 This is a diagram showing a command sequence in a first example of the erase operation according to the second embodiment.

[0036] Figure 28 This is a flowchart showing a second example of the erase operation in the storage system according to the second embodiment.

[0037] Figure 29 Yes Figure 28 Flowchart of the process of “determining the initial voltage value of the erase voltage VERA” in FIG.

[0038] Figure 30This is a diagram showing a command sequence in a second example of the erase operation according to the second embodiment.

[0039] Figure 31 This is a flowchart showing a first example of the erasing operation in the storage system according to the third embodiment.

[0040] Figure 32 This diagram shows the interaction of operations performed between a memory controller and a semiconductor memory device.

[0041] Figure 33 This is a diagram showing an example of a pulse time and voltage value management table provided in the memory of the memory controller.

[0042] Figure 34 This is a diagram showing a command sequence in a first example of the erase operation according to the third embodiment.

[0043] Figure 35 This is a flowchart showing a second example of the erasing operation in the storage system according to the third embodiment.

[0044] Figure 36 This is a diagram showing a command sequence in a second example of the erase operation according to the third embodiment.

[0045] Figure 37 This is a diagram showing a command sequence in a first example of the erase operation according to the fourth embodiment.

[0046] Figure 38 This is a flowchart showing a second example of the erasing operation in the storage system according to the fourth embodiment.

[0047] Figure 39 Yes Figure 38 Flowchart of the process of “determining the pulse time of the erase voltage VERA” in FIG.

[0048] Figure 40 It means relative to Figure 39 Graph showing threshold voltage distributions of memory cells at decision levels AR1 to AR4 used in the illustrated process.

[0049] Figure 41 This is a diagram showing the relationship between the number of cutoff bits obtained at the determination levels AR1 to AR4 and the erase state.

[0050] Figure 42 This is a flowchart showing the process of “determining the pulse time of the erase voltage VERA” in the third example of the erase operation according to the fourth embodiment.

[0051] Description of labels

[0052] 1 Memory system, 2 Host device, 10 Semiconductor memory device, 10_0 to 10_n memory chips, 11 Memory cell array, 12 Input / output circuit, 13 Logic control circuit, 14 Ready / busy circuit, 15 Register group, 15A Status register, 15B Address register, 15C Command register, 15D Register, 16 Sequencer, 17 Voltage generation circuit, 18 Driver, 19 Row decoder module, 20 Memory controller, 21 CPU, 22 Memory, 22A Buffer, 22B_1 Pulse time management table, 22B_2 Voltage value management table, 22B_3 Pulse time and voltage value management table, 23 Host interface, 24 ECC circuit, 25 NAND interface, 26 RAM interface, 30 buffer memory, 31 column decoder, 32 sense amplifier module, BL0~BLi bit lines, BLK0~BLKm blocks, MT0~MT7 storage cell transistors, PD0~PDm pulse time, PA0~PAm initial voltage value, SGD0~SGD3 selection gate lines, ST1 selection transistor, ST2 selection transistor, SU0~SU3 string units, WL0~WL7 word lines. DETAILED DESCRIPTION

[0053] The following describes the embodiments with reference to the accompanying drawings. In the following description, components having the same function and structure are given the same reference numerals. Each embodiment described below is intended to exemplify a device or method for embodying the technical concept of that embodiment and does not necessarily specify the material, shape, structure, or arrangement of the components.

[0054] Each functional block can be implemented as either hardware, computer software, or a combination of both. The functional blocks do not necessarily need to be distinguished as shown in the following examples. For example, a portion of the functions may be performed by a functional block different from the illustrated functional blocks. Furthermore, the illustrated functional blocks may be further divided into subdivided functional sub-blocks. Here, a semiconductor memory device included in the memory system is described using a three-dimensional stacked NAND flash memory having memory cell transistors stacked on a semiconductor substrate as an example.

[0055] 1. First Implementation

[0056] Hereinafter, a storage system according to the first embodiment will be described.

[0057] 1.1 Composition

[0058] 1.1.1 Storage System Structure

[0059] First, use Figure 1 The configuration of the storage system according to the first embodiment will be described. Figure 1This is a block diagram showing the configuration of a storage system according to the first embodiment. Storage system 1 includes a semiconductor storage device 10, a storage controller 20, and a buffer memory 30. Storage system 1 is connected to an external host device 2 and can execute various operations in response to commands from host device 2.

[0060] The semiconductor memory device 10 includes one or more memory chips 10_0, 10_1, 10_2, ..., 10_n (n is a natural number greater than or equal to 0). The memory chip 10_n has multiple memory cells and stores data in a nonvolatile manner. The semiconductor memory device 10 will be described in detail later.

[0061] The memory controller 20 is connected to the semiconductor memory device 10 via a NAND bus. The NAND bus transmits and receives signals in accordance with the NAND interface. Furthermore, the memory controller 20 is connected to the host device 2 via a host bus. The memory controller 20 controls the semiconductor memory device 10. Furthermore, the memory controller 20 accesses the semiconductor memory device 10 in response to commands received from the host device 2.

[0062] Buffer memory 30 temporarily stores write data and read data transmitted and received between semiconductor storage device 10 and host device 2. Buffer memory 30 is composed of, for example, DRAM (dynamic random access memory) or SRAM (static random access memory).

[0063] The semiconductor memory device 10 and the memory controller 20 may be combined to form a single semiconductor device, for example, including SD TM Examples thereof include a memory card, an SSD (solid state drive), etc. In addition, the storage controller 20 may be, for example, a SoC (system-on-a-chip) or the like.

[0064] The host device 2 is, for example, a digital camera, a personal computer, etc., and the host bus is, for example, compliant with SD TM Interface bus.

[0065] 1.1.2 Structure of the Storage Controller 20

[0066] Next, use Figure 1The following describes the structure of the memory controller 20. The memory controller 20 includes a CPU (central processing unit) (or processor) 21, memory 22, a host interface (host I / F) 23, an ECC (error checking and correcting) circuit 24, a NAND interface (NAND I / F) 25, and a RAM interface (RAM I / F) 26.

[0067] The CPU 21 controls the overall operation of the storage controller 20. For example, when the CPU 21 receives a write command from the host device 2, it responds by issuing a write command to the NAND interface 25. The same applies to reading and erasing. Furthermore, the CPU 21 performs various processes for managing the semiconductor storage device 10, such as wear leveling. The operations of the storage controller 20 described below can be implemented by software (or firmware) executed by the CPU 21, or by hardware.

[0068] The memory 22 is a semiconductor memory such as DRAM or SRAM, and is used as a work area for the CPU 21. The memory 22 holds a buffer 22A for storing various information, firmware for managing the semiconductor memory device 10, and various management tables 22B. The buffer 22A stores, for example, information related to the erase results of memory cells after an erase operation or a write operation after an erase operation, that is, information indicating the erase status of a group of memory cells (e.g., a block) to be erased after an erase operation or a write operation. The management table 22B includes, for example, parameters for the erase voltage VERA associated with each block. The parameters include, for example, the pulse duration or initial voltage value of the erase voltage VERA. The management table 22B includes management tables 22B_1, 22B_2, and 22B_3, which will be described later.

[0069] The host interface 23 is connected to the host device 2 via a host bus and is responsible for communicating with the host device 2. The host interface 23 transmits commands and data received from the host device 2 to the CPU 21, the memory 22, and the buffer memory 30. In addition, the host interface 23 transmits data in the buffer memory 30 to the host device 2 in response to commands from the CPU 21.

[0070] The ECC circuit 24 performs error correction on data. During a write operation, the ECC circuit 24 generates parity bits based on the write data received from the host device 2 and applies the generated parity bits to the write data. During a read operation, the ECC circuit 24 generates a syndrome based on the read data received from the semiconductor memory device 10 and detects and corrects errors in the read data based on the generated syndrome.

[0071] NAND interface 25 is connected to semiconductor storage device 10 via a NAND bus and is responsible for communication with semiconductor storage device 10. NAND interface 25 transmits and receives various signals to and from semiconductor storage device 10 based on commands received from CPU 21.

[0072] 1.1.3 Structure of Semiconductor Memory Device 10

[0073] Next, the structure of the semiconductor memory device 10 will be described. Figure 1 As shown, the semiconductor memory device 10 includes a plurality of memory chips 10_n. The memory chips 10_n include, for example, NAND flash memories capable of storing data in a nonvolatile manner.

[0074] 1.1.3.1 Memory Chip Structure

[0075] use Figure 2 The structure of the memory chip 10_n will be described. Figure 2 This is a block diagram showing the structure of a memory chip 10_n within a semiconductor memory device 10. Memory chip 10_n includes a memory cell array 11, an input / output circuit 12, a logic control circuit 13, a ready / busy circuit 14, a register group 15, a sequencer (or control circuit) 16, a voltage generation circuit 17, a driver 18, a row decoder module 19, a column decoder 31, and a sense amplifier module 32. Register group 15 includes a status register 15A, an address register 15B, a command register 15C, and a register 15D.

[0076] The memory cell array 11 has one or more blocks BLK0, BLK1, BLK2, ..., BLKm (m is an integer greater than or equal to 0). Each of the multiple blocks BLK0 to BLKm includes a plurality of memory cell transistors (hereinafter also referred to as memory cells) associated with rows and columns. The memory cell transistors are non-volatile memory cells that can be electrically erased and programmed. The memory cell array 11 includes a plurality of word lines, a plurality of bit lines, and a source line for applying voltage to the memory cell transistors. Hereinafter, when recorded as a block BLKr (r is an integer greater than or equal to 0 and less than or equal to m), it is assumed to represent each of the blocks BLK0 to BLKm. The specific structure of the block BLKr will be described later.

[0077] The input / output circuit 12 and the logic control circuit 13 are connected to the memory controller 20 via input / output terminals (or a NAND bus). I / O signals DQ (e.g., DQ0, DQ1, DQ2, ..., DQ7) are transmitted and received between the input / output circuit 12 and the memory controller 20 via the input / output terminals. The I / O signals DQ communicate commands, addresses, and data.

[0078] The logic control circuit 13 receives external control signals from the memory controller 20 via input / output terminals (or a NAND bus). Examples of these external control signals include a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, and a write protect signal WPn. The "n" appended to a signal name indicates that the signal is active low.

[0079] The chip enable signal CEn enables the selection of the memory chip 10_n and is asserted when the memory chip 10_n is selected. The command latch enable signal CLE latches the command sent as the signal DQ into the command register 15C. The address latch enable signal ALE latches the address sent as the signal DQ into the address register 15B. The write enable signal WEn holds the data sent as the signal DQ in the input / output circuit 12. The read enable signal REn outputs the data read from the memory cell array 11 as the signal DQ. The write protect signal WPn is asserted when writing and erasing to the memory chip 10_n are prohibited.

[0080] The ready / busy circuit 14 generates a ready / busy signal R / Bn in response to control from the sequencer 16. The ready / busy signal R / Bn indicates whether the memory chip 10_n is in a ready state or a busy state. The ready state indicates that the memory chip 10_n is able to accept commands from the memory controller 20. The busy state indicates that the memory chip 10_n is unable to accept commands from the memory controller 20. By receiving the ready / busy signal R / Bn from the memory chip 10_n, the memory controller 20 can determine whether the memory chip 10_n is in a ready state or a busy state.

[0081] The status register 15A holds status information STS required for the operation of the memory chip 10_n, and transmits the status information STS to the input / output circuit 12 based on the instruction of the sequencer 16. The address register 15B holds the address ADD transmitted from the input / output circuit 12. The address ADD includes a row address and a column address. The row address includes, for example, a block address that specifies the block BLKr of the action object and a page address that specifies the word line WL of the action object within the specified block. The command register 15C holds the command CMD transmitted from the input / output circuit 12. The command CMD includes, for example, a write command that instructs the sequencer 16 to perform a write operation and a read command that instructs the sequencer 16 to perform a read operation. The register 15D holds the parameters (such as pulse time or initial voltage value) of the erase voltage VERA sent from the memory controller 20 and transmitted by the input / output circuit 12. The register 15D includes registers 15D_1 and 15D_2 described later. For example, SRAM is used for the status register 15A, the address register 15B, the command register 15C, and the register 15D.

[0082] The sequencer 16 receives commands from the command register 15C and comprehensively controls the memory chip 10_n according to a sequence based on the commands. The sequencer 16 controls the row decoder module 19, column decoder 31, sense amplifier module 32, and voltage generator circuit 17 to perform write, read, and erase operations. Specifically, based on the write command received from the command register 15C, the sequencer 16 controls the row decoder module 19, driver 18, and sense amplifier module 32 to write data to the multiple memory cell transistors specified by the address ADD. Furthermore, based on the read command received from the command register 15C, the sequencer 16 controls the row decoder module 19, driver 18, column decoder 31, and sense amplifier module 32 to read data from the multiple memory cell transistors specified by the address ADD. Furthermore, the sequencer 16 controls the row decoder module 19 , the driver 18 , the column decoder 31 , and the sense amplifier module 32 based on the erase command received from the command register 15C, and erases the data stored in the block specified by the address ADD.

[0083] The voltage generation circuit 17 receives a power supply voltage from outside the memory chip 10_n via a power supply terminal (not shown). Using this power supply voltage, it generates multiple voltages required for write, read, and erase operations. The voltage generation circuit 17 supplies the generated voltages to the memory cell array 11, the driver 18, the sense amplifier module 32, and the like.

[0084] Driver 18 receives multiple voltages from voltage generating circuit 17. Driver 18 supplies multiple voltages selected from the multiple voltages supplied from voltage generating circuit 17 according to read, write, and erase operations to row decoder block 19 via multiple signal lines. For example, during an erase operation, driver 18 supplies an erase voltage VERA to well wiring CPWELL (described later).

[0085] The row decoder module 19 receives the row address from the address register 15B and decodes it. Based on the decoded row address, the row decoder module 19 selects one of the multiple blocks and further selects a word line WL within the selected block BLKr. Furthermore, the row decoder module 19 transmits multiple voltages supplied by the driver 18 to the selected block BLKr.

[0086] The column decoder 31 receives a column address from the address register 15B and decodes the column address. The column decoder 31 selects a bit line based on the decoded result of the column address.

[0087] During a data read operation, the sense amplifier module 32 detects and amplifies data read from the memory cell transistor to the bit line. Furthermore, the sense amplifier module 32 temporarily holds the read data DAT read from the memory cell transistor and transmits the held read data DAT to the input / output circuit 12. Furthermore, during a data write operation, the sense amplifier module 32 temporarily holds the write data DAT transmitted from the input / output circuit 12. Furthermore, the sense amplifier module 32 transmits the write data DAT to the bit line.

[0088] 1.1.3.2 Block Structure

[0089] Next, use Figure 3 The circuit structure of the memory cell array 11 in the memory chip 10_n will be described. As described above, the memory cell array 11 includes a plurality of blocks BLK0 to BLKm. Here, the circuit structure of one block BLKr will be described, but the circuit structures of the other blocks are similar.

[0090] Figure 3This is a circuit diagram of a block BLKr within the memory cell array 11. Block BLKr includes, for example, multiple string units SU0, SU1, SU2, and SU3. Hereinafter, when referred to as a string unit SU, this refers to each of the string units SU0-SU3. Each of the string units SU0-SU3 includes multiple NAND strings (or memory strings) NS.

[0091] The NAND string NS includes a plurality of memory cell transistors MT0, MT1, MT2, ..., MT7 and select transistors ST1 and ST2. Here, for the sake of simplicity, an example is shown in which the NAND string NS includes eight memory cell transistors MT0 to MT7 and two select transistors ST1 and ST2. Hereinafter, when the term "memory cell transistor MT" is used, it is assumed to refer to each of the memory cell transistors MT0 to MT7.

[0092] Each of the memory cell transistors MT0 to MT7 includes a control gate and a charge storage layer, and stores data in a nonvolatile manner. The memory cell transistors MT0 to MT7 are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2.

[0093] The memory cell transistor MT can store 1-bit data or 2-bit or more data.

[0094] The gates of the select transistors ST1 included in string unit SU0 are connected to select gate line SGD0. Similarly, the gates of the select transistors ST1 in string units SU1-SU3 are connected to select gate lines SGD1-SGD3, respectively. The select gate lines SGD0-SGD3 are independently controlled by row decoder module 19.

[0095] The gates of the multiple select transistors ST2 included in string unit SU0 are connected to select gate line SGS. Similarly, the gates of the select transistors ST2 in each of string units SU1-SU3 are connected to select gate line SGS. Alternatively, the gates of the select transistors ST2 in string units SU0-SU3 may be connected to separate select gate lines SGS. Select transistors ST1 and ST2 are used to select string unit SU during various operations.

[0096] The control gates of the memory cell transistors MT0 to MT7 included in the block BLKr are connected to word lines WL0 to WL7 , respectively. The word lines WL0 to WL7 are independently controlled by the row decoder module 19 .

[0097] Each of the bit lines BL0 through BLi (i is an integer greater than or equal to 0) is connected to multiple blocks BLK0 through BLKm and to a NAND string NS within a string unit SU included in block BLKr. Specifically, each of the bit lines BL0 through BLi is connected to the drains of the select transistors ST1 of multiple NAND strings NS in the same column of the NAND strings NS arranged in a matrix within block BLKr. Furthermore, the source line SL is connected to multiple blocks BLK0 through BLKm. Specifically, the source line SL is connected to the sources of multiple select transistors ST2 included in block BLKr.

[0098] In summary, a string unit SU includes multiple NAND strings NS connected to different bit lines BL and the same select gate line SGD. In addition, a block BLKr includes multiple string units SU sharing a word line WL. Furthermore, the memory cell array 11 includes multiple blocks BLK0 to BLKm sharing a bit line BL.

[0099] The block BLKr is, for example, a data erasing unit. That is, the data held by the memory cell transistors MT included in the block BLKr is erased all at once. In addition, data can be erased in units of string units SU or in units smaller than the string unit SU.

[0100] The multiple memory cell transistors MT that share a word line WL in a string unit SU are called a cell unit CU. The set of 1-bit data stored by each of the multiple memory cell transistors MT included in the cell unit CU is called a page. The storage capacity of the cell unit CU varies depending on the number of bits of data stored by the memory cell transistor MT. For example, when each memory cell transistor MT stores 1 bit of data, the cell unit CU stores 1 page of data. When storing 2 bits of data, the cell unit CU stores 2 pages of data. When storing 3 bits of data, the cell unit CU stores 3 pages of data.

[0101] The write operation and the read operation are performed on the cell unit CU in units of pages. In other words, the read and write operations are performed collectively on a plurality of memory cell transistors MT connected to one word line WL in one string unit SU.

[0102] In addition, the number of string units in the block BLKr is not limited to SU0 to SU3 and can be set arbitrarily. In addition, the number of NAND strings NS included in the string unit SU, the number of memory cell transistors and the number of select transistors included in the NAND string NS can also be set arbitrarily. Furthermore, the memory cell transistor MT can be either a MONOS (metal-oxide-nitride-oxide-silicon) type using an insulating film as a charge storage layer, or an FG (floating gate) type using a conductive layer as a charge storage layer.

[0103] Next, use Figure 4 The cross-sectional structure of the block BLKr will be described. Figure 4 This is a cross-sectional view of a portion of block BLKr. As shown, a p-type well region 40P is provided on semiconductor substrate 40. Multiple NAND strings NS are arranged on p-type well region 40P. Specifically, wiring layer 41, eight wiring layers 42, and wiring layer 43 are stacked in sequence on p-type well region 40P. Wiring layer 41 functions as select gate line SGS, wiring layer 42 functions as word lines WL0 to WL7, and wiring layer 43 functions as select gate line SGD. Insulating layers (not shown) are provided between the stacked wiring layers.

[0104] A columnar conductor 44 is provided that penetrates these wiring layers 41, 42, and 43 and reaches the p-type well region 40P. A gate insulating layer 45, a charge storage layer (insulating layer) 46, and a block insulating layer 47 are sequentially provided on the side of the conductor 44. These form the memory cell transistor MT and the select transistors ST1 and ST2. The conductor 44 functions as a current path for the NAND string NS and is a region that forms the channel of each transistor. The upper end of the conductor 44 is connected to the metal wiring layer 49 via a via 48. The metal wiring layer 49 functions as the bit line BL.

[0105] An n+ type impurity diffusion layer 40S is provided in the surface region of the p-type well region 40P. A contact plug 50 is provided on the diffusion layer 40S. The contact plug 50 is connected to a metal wiring layer 51. The metal wiring layer 51 functions as a source line SL.

[0106] Furthermore, a p+-type impurity diffusion layer 40C is provided in the surface region of the p-type well region 40P. A contact plug 52 is provided on the diffusion layer 40C. Contact plug 52 is connected to a metal wiring layer 53. Metal wiring layer 53 functions as well wiring CPWELL. Well wiring CPWELL is used to apply a potential to the conductor 44 via the p-type well region 40P.

[0107] The above structure is recorded in Figure 4 A plurality of NAND strings NS are arranged in a direction perpendicular to the paper (depth direction), and a string unit SU is formed by a collection of the plurality of NAND strings NS arranged in the depth direction.

[0108] Furthermore, the memory cell array 11 may have another structure. Specifically, the structure of the memory cell array 11 is described in, for example, US Patent Application No. 12 / 407,403, filed on March 19, 2009, entitled “THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY.” Furthermore, the present invention is described in U.S. Patent Application No. 12 / 406,524, filed on March 18, 2009, entitled "THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY," U.S. Patent Application No. 12 / 679,991, filed on March 25, 2010, entitled "NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME," and U.S. Patent Application No. 12 / 532,030, filed on March 23, 2009, entitled "SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING SAME." These patent applications are incorporated herein by reference in their entirety.

[0109] In addition, data erasure can be performed in units of blocks or smaller than blocks. Erasure methods are described, for example, in U.S. patent application No. 13 / 235,389, filed on September 18, 2011, for "Novolatile Semiconductor Memory Device." They are also described in U.S. patent application No. 12 / 694,690, filed on January 27, 2010, for "Non-Volatile Semiconductor Storage Device." Furthermore, they are described in U.S. patent application No. 13 / 483,610, filed on May 30, 2012, for "Novolatile Semiconductor Memory Device and Data Erase Method Thereof." These patent applications are incorporated herein by reference in their entirety.

[0110] 1.1.3.3 Threshold Voltage Distribution of Memory Cell Transistors

[0111] Next, the relationship between the threshold voltage distribution that the memory cell transistor MT can take and data in this embodiment will be described. Figure 5A This is a diagram showing the relationship between the threshold voltage distribution and data that can be taken by the memory cell transistor MT. Here, as a storage method of the memory cell transistor MT, an example of a TLC (Triple-Level Cell) method that can store 3 bits of data in one memory cell transistor MT is shown. In addition, this embodiment can also be applied to situations where other storage methods are used, such as an SLC (Single-Level Cell) method that can store 1 bit of data in one memory cell transistor MT, an MLC (Multi-Level Cell) method that can store 2 bits of data in one memory cell transistor MT, and a QLC (Quad-Level Cell) method that can store 4 bits of data in one memory cell transistor MT.

[0112] The 3-bit data that the memory cell transistor MT can store is specified by a lower bit, a middle bit, and an upper bit. When the memory cell transistor MT stores 3 bits, the memory cell transistor MT can take any of 8 states corresponding to multiple threshold voltages. The 8 states are referred to as states "Er", "A", "B", "C", "D", "E", "F", and "G" in order from the lowest. A plurality of memory cell transistors MT belonging to each state of "Er", "A", "B", "C", "D", "E", "F", and "G" are formed as shown below. Figure 5A The threshold voltage distribution is shown.

[0113] For example, the data "111," "110," "100," "000," "010," "011," "001," and "101" are assigned to states "Er," "A," "B," "C," "D," "E," "F," and "G," respectively. If the lower bit is "X," the middle bit is "Y," and the upper bit is "Z," the bit arrangement becomes "Z, Y, X." The threshold voltage distribution and data assignment can be arbitrarily set.

[0114] In order to read data stored in the memory cell transistor MT to be read, it is determined which state the threshold voltage of the memory cell transistor MT belongs to. For determining the state, read voltages AR, BR, CR, DR, ER, FR, and GR can be used.

[0115] State “Er” corresponds to a state where data is erased (erased state), for example. The threshold voltage of memory cell transistor MT in state “Er” is lower than voltage AR, and has a negative value, for example.

[0116] States "A" to "G" correspond to states in which charge is injected into the charge storage layer and data is written into the memory cell transistor MT. The threshold voltages of the memory cell transistors MT in states "A" to "G" have positive values, for example. The threshold voltage of the memory cell transistor MT in state "A" is higher than the read voltage AR and lower than the read voltage BR. The threshold voltage of the memory cell transistor MT in state "B" is higher than the read voltage BR and lower than the read voltage CR. The threshold voltage of the memory cell transistor MT in state "C" is higher than the read voltage CR and lower than the read voltage DR. The threshold voltage of the memory cell transistor MT in state "D" is higher than the read voltage DR and lower than the read voltage ER. The threshold voltage of the memory cell transistor MT in state "E" is higher than the read voltage ER and lower than the read voltage FR. The threshold voltage of the memory cell transistor MT in state "F" is higher than the read voltage FR and lower than the read voltage GR. The threshold voltage of the memory cell transistor MT in state "G" is higher than the read voltage GR and lower than voltage VREAD.

[0117] The voltage VREAD is applied to the word line WL connected to the memory cell transistors MT of the cell group CU not to be read, and is higher than the threshold voltage of the memory cell transistors MT in any state. Therefore, the memory cell transistors MT to which the voltage VREAD is applied to the control gate are turned on regardless of the data being stored.

[0118] Furthermore, verify voltages used in write operations are set between adjacent threshold distributions. Specifically, verify voltages AV, BV, CV, DV, EV, FV, and GV are set corresponding to states "A," "B," "C," "D," "E," "F," and "G," respectively. For example, verify voltages AV, BV, CV, DV, EV, FV, and GV are set slightly higher than read voltages AR, BR, CR, DR, ER, FR, and GR, respectively.

[0119] As described above, each memory cell transistor MT is set to one of 8 states and can store 3 bits of data. In addition, writing and reading are performed in units of pages within a unit group CU. When the memory cell transistor MT stores 3 bits of data, the three pages within a unit group CU are respectively allocated low bits, middle bits, and high bits. The pages to which the low bits, middle bits, and high bits are written by a single write operation or read by a single read operation, that is, the set of low bits, the set of middle bits, and the set of high bits maintained by the unit group CU, are respectively referred to as low (lower) pages, middle (middle) pages, and high (upper) pages.

[0120] When the above data allocation is applied, the lower page is determined by a read operation using read voltages AR and ER, the middle page is determined by a read operation using read voltages BR, DR, and FR, and the upper page is determined by a read operation using read voltages CR and GR.

[0121] 1.2 Action

[0122] The following describes the erase operation in the memory system 1 according to the first embodiment. The erase operation sets the memory cell to an erased state. In other words, the erase operation extracts electrons accumulated in the charge storage layer of the memory cell transistor MT, thereby shifting the threshold voltage of the memory cell transistor MT to within the threshold voltage distribution of the state "Er."

[0123] Figure 5B This diagram shows the threshold voltage distribution of the memory cell transistor MT after the erase operation. When the memory cell transistor MT is erased, the erased state of the memory cell transistor MT in state "Er" changes to one of the under-erased state, the properly erased state, and the over-erased state.

[0124] The under-erase state is, for example, Figure 5B As shown in (a) of FIG. 1 , the state "Er" enters the lower end (lower end) of the state "A" in the threshold voltage distribution, which is a state where the electrons accumulated in the charge storage layer of the memory cell transistor MT are insufficiently extracted. The erased state is as follows: Figure 5B As shown in (b) of FIG. 1 , the state "Er" and the state "A" are separated by an appropriate distance in the threshold voltage distribution, and the amount of electrons accumulated in the charge storage layer of the memory cell transistor MT is appropriate. Figure 5B As shown in (c), the state "Er" and the state "A" are separated by a larger distance than the appropriate distance in the threshold voltage distribution, which means that the electrons accumulated in the charge storage layer of the memory cell transistor MT are excessively extracted.

[0125] After the erase operation, the erase state of the memory cell transistor MT is in one of the under-erased state, the properly-erased state, and the over-erased state. The erase state of the memory cell transistor MT after the erase operation is defined as the erase depth.

[0126] By preventing the memory cell transistor MT from being over-erased, in other words, by preventing the erase depth of the memory cell transistor MT from becoming deeper, damage to the memory cell can be reduced. Furthermore, by preventing the memory cell transistor MT from being under-erased, in other words, by preventing the erase depth of the memory cell from becoming shallower, read errors during page reading can be reduced.

[0127] 1.2.1 Storage System Erase Action

[0128] The data stored in the semiconductor memory device 10 is erased based on an erase command output from the memory controller 20 to the semiconductor memory device 10. As described above, the erase operation in the semiconductor memory device 10 can be performed, for example, in units of blocks or in units smaller than blocks. Here, the case where the erase operation is performed in units of blocks is shown as an example.

[0129] Hereinafter, a basic data erasing operation in the storage system 1 will be described. Figure 6 1 is a diagram showing a basic erasing operation in the storage system 1. Figure 6 In FIG. 1 , commands output from the memory controller 20 through the I / O signals DQ0 to DQ7 are represented by hexagons, and addresses are represented by rounded squares (or oval shapes).

[0130] like Figure 6 As shown, the memory controller 20 outputs an erase setup command "60h" to the semiconductor memory device 10, then outputs the address "ADD" of the erase target block, and then outputs an erase execution command "D0h". The sequencer 16 recognizes that the erase setup command "60h" is received based on the fact that the command register 15C holds the erase setup command "60h". Furthermore, the sequencer 16 responds to the fact that the erase execution command "D0h" is received and starts the erase operation. Figure 6 As shown, the erase operation includes data erasure and erase verification. The sequencer 16 changes the ready / busy signal R / Bn from the ready state to the busy state (R / Bn = "L") at the start of the erase operation. Furthermore, the "h" appended to a command (or address) indicates that the value is expressed in hexadecimal.

[0131] The erase process is an action to erase the data stored in the memory cell transistor MT in the erase target block. Specifically, the erase process is an action to apply the erase voltage VERA to the well wiring CPWELL to extract electrons from the charge storage layer of the memory cell transistor MT in the erase target block. The pulse time of the applied erase voltage VERA can be set to a predetermined value. The pulse time is the time for maintaining the voltage level of the erase voltage VERA, also known as the pulse width or pulse length. The erase verification process is an action to verify the data erased from the memory cell transistor MT by the erase process. In other words, the erase verification process is a read operation to confirm whether the threshold voltage of the memory cell transistor MT has changed to the threshold voltage of the erased state.

[0132] The erase operation consists of an erase process and an erase verification process performed after the erase process, which constitutes an erase cycle. Figure 6 The first and second erase cycles are illustrated in the example of FIG. In the verification performed by the erase verification process, when the number of memory cell transistors MT having a threshold voltage higher than a certain value is less than a predetermined number, it is determined that the erase verification has passed. On the other hand, when the number of memory cell transistors MT having a threshold voltage higher than the certain value is greater than a predetermined number, it is determined that the erase verification has failed. When these determinations are completed, the sequencer 16 ends the erase verification process. The combination of the erase process and the erase verification process described above corresponds to one erase cycle. When the erase verification fails, the sequencer 16 repeatedly performs the erase cycle, and when the erase verification passes, the sequencer 16 ends the erase operation.

[0133] The number of electrons injected into the charge storage layer of the memory cell transistor MT does not decrease below the predetermined number in the first erase cycle, but decreases below the predetermined number through multiple erase cycles. Figure 6 As shown, if the erase verify fails in the first erase cycle, a second erase cycle is performed. During the repeated erase cycles, the erase voltage VERA is set to a value increased by ΔVERA. When the erase verify passes and the erase operation is completed, the sequencer 16 causes the semiconductor memory device 10 to transition from the busy state to the ready state. This transition to the ready state completes the erase process.

[0134] Figure 7 3 is a diagram showing the voltage waveforms of various signals during the erase operation.

[0135] First, an erase process is performed at time t0 to t5, and then an erase verification process is performed at time t5 to t10. This series of processes from t0 to t10 corresponds to one erase cycle.

[0136] The erase process will be described below. At time t0, the bit line BL, select gate lines SGD and SGS, word line WL, source line SELSRC, and well wiring CPWELL are set to voltage VSS (eg, 0 V).

[0137] Next, between times t1 and t3, for example, driver 18 applies erase voltage VERA to well wiring CPWELL. Consequently, between times t1 and t3, the channel region of memory cell transistor MT is boosted to erase voltage VERA. Furthermore, through capacitive coupling caused by voltage VERA applied to well wiring CPWELL, bit line BL, select gate lines SGD and SGS, word lines WL of non-erased blocks (or unselected blocks), and source line SELSRC are boosted to voltage VERA. Furthermore, select gate line SGS is boosted to a voltage Δ lower than voltage VERA.

[0138] Furthermore, at times t1-t3, the row decoder module 19 applies a voltage Vwl, which is lower than the erase voltage VERA, to the word line WL of the block to be erased (or the selected block). This creates a potential difference between the erase voltage VERA in the channel region of the memory cell transistor MT and the voltage Vwl on the word line WL of the block to be erased, causing electrons to be drawn from the charge storage layer of the memory cell transistor MT in the block to be erased into the channel layer. In other words, the data in the memory cell transistor MT in the block to be erased is erased.

[0139] Then, at time t3-t5, the bit line BL, the select gate lines SGD and SGS, the word line WL, the source line SELSRC, and the well line CPWELL are set to the voltage VSS.

[0140] Next, the erase verify process at times t5 to t10 will be described.

[0141] At time t6, the row decoder block 19 applies a voltage VSG to the select gate lines SGD and SGS of the selected block. The voltage VSG is a voltage that turns on the select transistors ST1 and ST2.

[0142] Next, at times t7-t9, the row decoder module 19 applies an erase verify voltage Vev to the word lines WL of the erase target block. Furthermore, the row decoder module 19 applies a voltage VREAD to the word lines WL of blocks not being erased. The erase verify voltage Vev is a read voltage used to determine the erased state of the memory cell transistors MT in the erase target block.

[0143] The sense amplifier module 32 then senses and amplifies the data read from the bit line BL. Based on the read results, the sequencer 16 determines whether the erase operation for the erase target block has completed, that is, whether the erase verification has passed or failed. If the erase operation is not completed, the erase operation, including the erase process and the erase verification process, is repeated for the erase target block.

[0144] 1.2.2 Erase Operation in the First Embodiment

[0145] In the erase operation of the first embodiment, the pulse duration of the erase voltage VERA is adjusted (or changed) based on the erase result of the memory cell after the erase operation, or based on the erase result of the memory cell after the write operation after the erase operation. For example, the pulse duration of the erase voltage VERA is increased or decreased. The erase result of the memory cell refers to the determination result of the erase depth of the memory cell after the erase operation. In other words, the erase result of the memory cell refers to the state of the memory cell after the erase operation, namely, an under-erased state, a properly erased state, or an over-erased state.

[0146] 1.2.2.1 The first example of erasing

[0147] In the first example, after an erase operation, the pulse duration of the erase voltage VERA is updated based on the erase results of the memory cells included in the word lines WL and string units SU within the erase target block. This example shows how the pulse duration of the erase voltage VERA is increased based on the erase results of the memory cells.

[0148] Figure 8 This is a flowchart showing a first example of the erasing operation in the storage system 1 according to the first embodiment. Figure 9 1 is a diagram showing the interaction of operations performed between the memory controller 20 and the semiconductor memory device 10 . Figure 10 This is a diagram showing an example of a pulse time management table 22B_1 provided in the memory 22 of the storage controller 20. The pulse time management table 22B_1 manages the pulse time of the erase voltage VERA. In the pulse time management table 22B_1, a pulse time PDr used in the erase operation of a block BLKr (r is an integer greater than or equal to 0 and less than or equal to m) is associated with the block. In addition, Figure 8 The processing shown is commanded and controlled by the storage controller 20 (or the CPU 21 ).

[0149] like Figure 8 and Figure 9As shown, when an erase operation begins, the memory controller 20 first transmits the pulse time PDr of the erase voltage VERA corresponding to the erase target block BLKr from the pulse time management table 22B_1 to the semiconductor memory device 10, and sets the pulse time PDr in the register 15D_1 of the semiconductor memory device 10. Specifically, the memory controller 20 obtains the pulse time PDr of the erase voltage VERA corresponding to the erase target block BLKr from the pulse time management table 22B_1 and transmits it to the semiconductor memory device 10, which stores the pulse time PDr in the register 15D_1 (step S1). For example, if the erase target block is block BLK0, the pulse time PD0 corresponding to block BLK0 is transmitted to the semiconductor memory device 10 and stored in the register 15D_1.

[0150] Next, the memory controller 20 instructs the semiconductor memory device 10 to perform an erase operation (step S2). The sequencer 16 of the semiconductor memory device 10 performs an erase operation on the erase target block BLKr using the pulse time PDr of the erase voltage VERA stored in the register 15D_1.

[0151] Next, after the semiconductor memory device 10 enters the ready state, the memory controller 20 obtains the erase result of the memory cell based on the erase operation from the semiconductor memory device 10. Based on the erase result of the memory cell obtained from the semiconductor memory device 10, the memory controller 20 determines whether to update the pulse time PDr of the erase voltage VERA (hereinafter also referred to as "determining the pulse time of the erase voltage VERA") (step S3). For example, the process of "determining the pulse time of the erase voltage VERA" in step S3 is executed each time an erase operation is performed, each time a predetermined number of write operations / erase operations are performed, or when the number of write operations / erase operations reaches a predetermined number of times. The details of the process of "determining the pulse time of the erase voltage VERA" in step S3 will be described later.

[0152] Next, based on the result of "determining the pulse duration of the erase voltage VERA" in step S3, the memory controller 20 updates the pulse duration PDr corresponding to the erase target block BLKr in the pulse duration management table 22B_1 of the memory 22, or maintains it unchanged (step S4). This completes the erase operation.

[0153] Then, Figure 8 The process of "determining the pulse time of the erase voltage VERA" (step S3) in step S3 in the flowchart shown will be described in detail. Figure 11A This is a flowchart showing the process of "determining the pulse time of the erase voltage VERA" in step S3. Figure 12: is a diagram showing a threshold voltage distribution and a determination level for explaining a method of determining an erase depth in a first example of an erase operation. Figure 11A The processing shown is commanded and controlled by the storage controller 20 (or the CPU 21 ).

[0154] First, a read operation is performed to determine the erase depth of the memory cell after the erase operation. Figure 11A As shown in step S11, the memory controller 20 sets the read voltage to the read voltage AR of state "A", and further sets an offset value (voltage value) that is offset from the read voltage AR to the low voltage side. Figure 12 As shown, the read voltage that is offset from the read voltage AR by the offset value is defined as the judgment level AR2. The judgment level AR2 is a voltage level for judging the erase depth of the memory cell after the erase operation. The memory controller 20 sets the judgment level AR2 that is offset from the read voltage AR by the offset value to the semiconductor memory device 10. In addition, depending on the erase depth of the memory cell, the read voltage AR can be used directly as the judgment level AR2, or the read voltage AR can be offset to the high voltage side and used as the judgment level AR2. Furthermore, the memory controller 20 specifies the word line WL and string unit SU to be measured in the erase target block (step S11). In addition, the word line WL to be measured can be one word line, multiple word lines, or all word lines.

[0155] Next, the storage controller 20 instructs the semiconductor storage device 10 to perform a "single-level read" of state "A" (step S12). "Single-level read" is a process of obtaining read data representing the magnitude of a threshold voltage of a read voltage for one of the states. For example, in the case of TLC, the read voltage of one of the states "A" to "G" is specified. Here, the read operation is performed using the judgment level AR2 that is offset from the read voltage AR by an offset value. When receiving the "single-level read" command of state "A", the sequencer 16 of the semiconductor storage device 10 performs a read operation on the memory cell to be measured at the set judgment level AR2. In this read operation, as Figure 12 As shown, memory cells with a threshold voltage higher than the determination level AR2 are not in the on state but in the off state. Sequencer 16 outputs the read result RA2R at the determination level AR2 from semiconductor memory device 10 to memory controller 20. As the erase result after the erase operation, memory controller 20 counts the number of memory cells in the off state (hereinafter referred to as the off-bit number) "DO1." The counted off-bit number is stored in buffer 22A within memory 22.

[0156] Next, the memory controller 20 determines the erase depth of the memory cell after the erase operation based on the read result at the determination level AR2 (step S13). Specifically, the memory controller 20 determines the erase depth of the memory cell after the erase operation based on the number of cutoff bits obtained through the read operation at the determination level AR2. Specifically, the memory controller 20 performs a read operation at the determination level AR2 each time an erase operation is performed on the erase target block BLKr, or once in a series of erase operations. When the number of AR2 read operations during the erase operation reaches X (e.g., four times), the memory controller 20 determines whether the average number of cutoff bits for X times exceeds a reference value Y1 (step S14). If the average number of cutoff bits exceeds the reference value Y1 (yes), the memory controller 20 increases the pulse duration PDr of the erase voltage VERA by a predetermined time (step S15). On the other hand, if the average number of cutoff bits does not exceed the reference value Y1 (no), the memory controller 20 terminates the "determining the pulse duration of the erase voltage VERA" process.

[0157] Furthermore, in step S14, the average value of the number of cutoff bits for the number of times X is compared with the reference value Y1. However, the maximum value of the number of cutoff bits in one or more word lines WL when the operation is performed the number of times X may be compared with the reference value Y1, or the maximum value of the number of cutoff bits in all word lines WL when the operation is performed the number of times X may be compared with the reference value Y1.

[0158] In addition, the reference value Y1 may be changed according to the number of write operations / erase operations of the memory cell. Figure 11B An example of the relationship between the number of write operations / erase operations and the reference value Y1 is shown in FIG. Figure 11B As shown, the reference value Y1 can also be decreased as the number of write / erase operations on the memory cell increases. More specifically, the reference value Y1 can be gradually decreased each time the number of write / erase operations increases by a predetermined number of times. As the number of write / erase operations increases, memory cell fatigue progresses. By setting the reference value Y1 in accordance with the increase in the number of write / erase operations, the erase depth of the memory cell can be kept constant in finer units.

[0159] Next, use Figure 13 and Figure 14 The determination of whether the number of cutoff bits exceeds the reference value Y1 in step S14 will be described. That is, a specific example of the determination of whether the pulse time PDr is to be updated will be described. Figure 13 and Figure 14This diagram shows the number of cutoff bits stored in buffer 22A when the target memory cell is read at decision level AR2. t-3 represents the number of cutoff bits obtained by the read operation three times previously, t-2 represents the number of cutoff bits obtained by the read operation two times previously, and t-1 represents the number of cutoff bits obtained by the read operation one time previously (i.e., the previous time). Furthermore, t-0 represents the number of cutoff bits obtained by the most recent (current) read operation. For example, reference value Y1 is set to 30.

[0160] Figure 13 This is an example where buffer 22A stores cutoff bit counts of 29, 35, and 29 at t-3, t-2, and t-1, respectively, and stores the latest cutoff bit count of 23 at t-0. In this case, the average of the cutoff bit counts stored at t-3, t-2, t-1, and t-0 is 29. Since the average cutoff bit count of 29 does not exceed the reference value of 30, the memory controller 20 terminates the process without changing the pulse time PDr of the erase voltage VERA. For example, CPU 21 of memory controller 20 includes a circuit capable of calculating the pulse time PDr using the average cutoff bit count and the reference value as parameters. This allows memory controller 20 to calculate the pulse time PDr based on the average cutoff bit count and reflect this calculated pulse time PDr in pulse time management table 22B_1 of memory 22.

[0161] Furthermore, at the end, the memory controller 20 deletes the oldest cutoff bit number stored in the buffer 22A at t-3 and shifts the values ​​of t-2, t-1, and t-0 in sequence. After the shift, the buffer 22A stores 35, 29, and 23 at t-3, t-2, and t-1, respectively.

[0162] Figure 14 In this example, the buffer 22A stores cutoff bit numbers 29, 35, and 29 at t-3, t-2, and t-1, respectively, and stores the latest cutoff bit number 32 at t-0. In this case, the average of the cutoff bit numbers stored at t-3, t-2, t-1, and t-0 is 31. Since the average cutoff bit number 31 exceeds the reference value 30, the memory controller 20 increases the pulse time PDr of the erase voltage VERA by a predetermined time and then terminates the process.

[0163] Furthermore, at the end, the memory controller 20 clears all of t3, t2, and t1 in the buffer 22A.

[0164] Next, the input and output of commands, addresses, and data between the memory controller 20 and the semiconductor memory device 10 in the first example of the erase operation described above will be described.

[0165] Figure 15This is a diagram showing a command sequence in a first example of the erase operation according to the first embodiment. Figure 15 The command sequence shown includes commands, addresses, and data input / output cycles. Commands are represented by hexagons, addresses by rounded rectangles (or oval shapes), and data input / output cycles by quadrilaterals. The output of commands and addresses from the memory controller 20 to the semiconductor memory device 10, as described below, and the input / output of data between the memory controller 20 and the semiconductor memory device 10, are performed using I / O signals DQ0 to DQ7.

[0166] like Figure 15 As shown, the command sequence has a phase (phase) P1 corresponding to "setting the pulse time of the erase voltage VERA (step S1)", a phase P2 corresponding to "command to perform the erase action (step S2)", a phase P3 corresponding to "setting the judgment level AR2 (step S11)" in the offset reading of the single-level reading, and phases P3 and P4 corresponding to "command to perform single-level reading (step S12)" in the offset reading.

[0167] First, in phase P1 of setting the pulse duration of the erase voltage VERA, the memory controller 20 sequentially outputs a command "0Xh", an address "00h", and data "PDr" to the semiconductor memory device 10. The command "0Xh" specifies the erase mode. The address "00h" sets the pulse duration of the erase voltage VERA. The data "PDr" indicates the pulse duration of the erase voltage VERA corresponding to the erase target block BLKr and is stored in the register 15D_1. Thus, the memory controller 20 specifies the erase mode for the semiconductor memory device 10 and sets the pulse duration PDr of the erase voltage VERA used in the erase operation on the erase target block BLKr in the register 15D_1 of the semiconductor memory device 10.

[0168] Next, in phase P2, which instructs the erase operation to proceed, the memory controller 20 sequentially outputs an erase setup command "60h," the address "ADD" of the erase target block BLKr, and an erase execution command "D0h" to the semiconductor memory device 10. Consequently, the sequencer 16 applies an erase voltage VERA for a pulse duration PDr to the well wiring CPWELL, executing the erase operation on the erase target block BLKr. During this erase operation, the sequencer 16 transitions the ready / busy signal R / Bn from the ready state to the busy state (R / Bn = "L").

[0169] Then, the memory controller 20 outputs a status read command "70h" to the semiconductor memory device 10. Upon receiving the status read command "70h," the semiconductor memory device 10 outputs data indicating whether the erase operation has passed or failed to the memory controller 20. For example, the semiconductor memory device 10 outputs data "PASS" indicating that the erase operation has passed to the memory controller 20.

[0170] Next, in phase P3 for setting the determination level AR2, the memory controller 20 sequentially outputs a single-level read command "X1h" and an address "01h" indicating the read voltage AR in state "A" to the semiconductor memory device 10. Furthermore, the memory controller 20 sequentially outputs a shift read command "X2h," an address "01h," and data "SHIFT" indicating an offset value from the read voltage AR to the semiconductor memory device 10. Consequently, the memory controller 20 sets the determination level AR2 used in the shift read of the single-level read to the semiconductor memory device 10.

[0171] Next, in phase P4, where a read command is executed, the memory controller 20 sequentially outputs a read setup command "00h," the measurement target addresses "ADD1-ADD5," and a read execution command "30h" to start the read operation to the semiconductor memory device 10. Upon receiving the read execution command "30h," the sequencer 16 of the semiconductor memory device 10 performs a read operation at the determination level AR2 for the measurement target memory cells specified by the addresses "ADD1-ADD5." During this read operation, the sequencer 16 transitions the ready / busy signal R / Bn from the ready state to the busy state (R / Bn = "L"). Then, during the read operation at the determination level AR2, the sequencer 16 outputs the read result RA2R from the semiconductor memory device 10 to the memory controller 20. The memory controller 20 counts the number of memory cells (i.e., the number of off-bit bits) "DO1" that remain off instead of on.

[0172] As described above, in the first example, the controller 20 counts the number of cutoff bits in the memory cells to be measured within the erase target block BLKr during the read operation after the erase operation. Based on the number of cutoff bits, the memory controller 20 updates the pulse time PDr of the erase voltage VERA or maintains it without updating.

[0173] <Modification of Example 1>

[0174] Next, a modification of the first example of the erase operation of the first embodiment will be described. This modification shows an example in which the pulse time of the erase voltage VERA is shortened or lengthened based on the erase result of the memory cell after the erase operation.

[0175] As in the first example above, the erasing operation of the modified example is performed according to Figure 8 The erase action is executed according to the flowchart shown. Figure 8 The processing of step S3 in the flowchart of Figure 16 The processing shown. Figure 16 This is a flowchart showing the process of “determining the pulse time of the erase voltage VERA” (step S3 ) according to the modification. Figure 16 The processing shown is commanded and controlled by the storage controller 20 (or the CPU 21 ).

[0176] Figure 16 The processing of steps S11 to S15 shown in FIG. Figure 11A The processing of steps S11 to S15 shown is the same. That is, the memory controller 20 sets the determination level AR2 for determining the erase depth of the memory cell after the erase operation in the semiconductor memory device 10. Furthermore, the memory controller 20 specifies the word line WL and string unit SU to be measured within the erase target block BLKr (step S11).

[0177] Next, the memory controller 20 instructs the semiconductor memory device 10 to perform a "single level read" (step S12). Upon receiving the "single level read" command, the sequencer 16 of the semiconductor memory device 10 reads the memory cell to be measured at the set determination level AR2, for example.

[0178] Next, the memory controller 20 determines the erase depth of the memory cell after the erase operation based on the cutoff bit count calculated from the read result RA2R at the determination level AR2 (step S13). Specifically, after determining the erase depth of the memory cell after the erase operation, the memory controller 20 performs a read operation at the determination level AR2. When the read operation at the determination level AR2 reaches a number X, the memory controller 20 determines whether the average value of the cutoff bit count for the number X exceeds the reference value Y1 (step S14). If, in step S14, the average value of the cutoff bit count for the number X exceeds the reference value Y1 (yes), the memory controller 20 increases the pulse duration PDr of the erase voltage VERA by a predetermined time (step S15), terminating the process. On the other hand, if the average value of the cutoff bit count for the number X does not exceed the reference value Y1 (no), the memory controller 20 determines whether the average value of the cutoff bit count for the number X reaches the reference value Y2 (step S16).

[0179] If, in step S16, the average value of the number of cutoff bits for the number of times X has not reached the reference value Y2 (No), the memory controller 20 shortens the pulse duration PDr of the erase voltage VERA by a predetermined time (step S17) and terminates the process. On the other hand, if the average value of the number of cutoff bits for the number of times X has reached the reference value Y2 (Yes), the memory controller 20 terminates the process without updating the pulse duration of the erase voltage VERA.

[0180] As described above, in a variation of the first example, the cutoff bit count of the memory cell to be measured within the erase target block BLKr is output from the semiconductor memory device 10 to the memory controller 20 through a read operation after an erase operation. Based on the cutoff bit count, the memory controller 20 determines whether the memory cell is in an under-erased state, a properly erased state, or an over-erased state. If the memory cell is in the over-erased state ("No" in step S16), the memory controller 20 shortens the pulse time PDr of the erase voltage VERA (step S17). If the memory cell is in the properly erased state ("Yes" in step S16), the pulse time PDr is not updated. If the memory cell is in the under-erased state ("Yes" in step S14), the pulse time PDr is increased (step S15).

[0181] 1.2.2.2 Example 2 of Erase Action

[0182] In the second example, after the write operation following the erase operation, the pulse duration of the erase voltage VERA is updated based on the erase results of the memory cells included in the word lines WL and string units SU within the erase target block. This example shows an example of increasing the pulse duration. In the second example, a write operation is added between the erase operation and the decision on whether to update the pulse duration.

[0183] Figure 17 This is a flowchart showing a second example of the erase operation in the storage system 1 according to the first embodiment. Figure 17 The processing shown is commanded and controlled by the storage controller 20 (or the CPU 21 ).

[0184] Similar to the first example, the memory controller 20 transmits the pulse time PDr of the erase voltage VERA corresponding to the erase target block BLKr in the pulse time management table 22B_1 to the semiconductor memory device 10 and sets it in the register 15D_1 of the semiconductor memory device 10 (step S1). Furthermore, the memory controller 20 instructs the semiconductor memory device 10 to perform an erase operation (step S2). Upon receiving the erase operation command, the sequencer 16 of the semiconductor memory device 10 executes the erase operation on the erase target block BLKr.

[0185] After executing the erase operation on the erase target block BLKr, the memory controller 20 instructs the semiconductor memory device 10 to perform a write operation (step S5). Upon receiving the write operation command, the sequencer 16 of the semiconductor memory device 10 executes the write operation on the write target memory cells within the erase target block BLKr. The write operation command is repeated until either a partial write to the block or a full write to the block is completed (step S6).

[0186] Next, the memory controller 20 determines whether to update the pulse duration PDr of the erase voltage VERA based on the erase state of the memory cell after the write operation (step S3A). For example, similar to the first example, the process of "determining the pulse duration of the erase voltage VERA" in step S3A is executed each time a write operation is performed after an erase operation, each time a predetermined number of write / erase operations are performed, or each time the predetermined number of write / erase operations are performed. The details of the process of "determining the pulse duration of the erase voltage VERA" in step S3A will be described later.

[0187] Next, based on the result of "determining the pulse duration of the erase voltage VERA" in step S3A, the memory controller 20 updates the pulse duration PDr corresponding to the erase target block BLKr in the pulse duration management table 22B_1 of the memory 22, or maintains it unchanged without updating (step S4). This completes the erase operation.

[0188] Then, Figure 17 The process of "determining the pulse time of the erase voltage VERA" in step S3A in the flowchart shown in FIG. Figure 18 This is a flowchart showing the process of "determining the pulse time of the erase voltage VERA" in step S3A. Figure 19 This is a diagram showing the threshold voltage distribution and the judgment level and data for calculating the number of cutoff bits, for explaining the method of determining the erase depth in the second example of the erase operation. Figure 18 The processing shown is commanded and controlled by the storage controller 20 (or the CPU 21 ).

[0189] First, if Figure 18 As shown in FIG. 1 , the memory controller 20 sets an offset value from the read voltage AR. Figure 19As shown in (A), the read voltage after being offset from the read voltage AR by the offset value is defined as the judgment level AR3. The judgment level AR3 is a voltage level for judging the erase depth of the memory cell after the write operation. The storage controller 20 sets the judgment level AR3 after being offset from the read voltage AR by the offset value to the semiconductor memory device 10. In addition, depending on the erase depth of the memory cell, the read voltage AR can be used directly as the judgment level AR3, or it can be offset from the read voltage AR to the high voltage side and used as the judgment level AR3. Further, the storage controller 20 specifies the word line WL and string unit SU of the measurement object in the erase object block BLKr (step S21). In addition, the word line WL of the measurement object can be one word line, multiple word lines, or all word lines. In the following description, Figure 5A The memory map shown is read below. Figure 5A In FIG, the read voltage AR is mapped to the read of the “lower page”.

[0190] Next, the memory controller 20 instructs the semiconductor memory device 10 to perform a "lower page read" including AR (step S22). "Low page read" is, for example, an operation of reading data of a lower page by a read operation using read voltages AR and ER. Here, the determination level AR3 is used instead of the read voltage AR. Upon receiving the "lower page read" command, the sequencer 16 of the semiconductor memory device 10 performs a read operation on the memory cell to be measured using the set determination level AR3 and read voltage ER, for example, to obtain Figure 19 (B) shows lower page data RLP before error correction. Lower page data RLP is data immediately after being read using decision level AR3 and read voltage ER, and is data for which error correction has not been performed.

[0191] Next, the memory controller 20 receives the lower page data RLP before error correction obtained in the read operation of the decision level AR3 and the read voltage ER from the semiconductor memory device 10. The memory controller 20 corrects the error of the lower page data RLP before error correction through the ECC circuit 24 and obtains Figure 19 The lower page data CLP after error correction shown in (B) is obtained (step S23).

[0192] Next, the memory controller 20 separates the read data corresponding only to the determination level AR3 from the read lower page data. For example, the read voltage CR for state "C" is set in the semiconductor memory device 10. In this embodiment, the state "C" is not limited; any state "B," "C," or "D" is acceptable as long as the states "A" and "E" can be separated. Furthermore, the memory controller 20 specifies the word line WL and string unit SU to be measured within the erase target block BLKr in the semiconductor memory device 10 (step S24).

[0193] Next, the memory controller 20 instructs the semiconductor memory device 10 to perform a "single-level read" in state "C" (step S25). Upon receiving the "single-level read" command, the sequencer 16 of the semiconductor memory device 10 performs a read operation on the memory cell to be measured at the set read voltage CR, and obtains Figure 19 (B) shows the readout result RCR of state "C".

[0194] The memory controller 20 performs a logical AND operation on the data RLP2 obtained by applying a logical NOT operation to the pre-error-corrected lower page data RLP obtained in step S22, and the two data CLP and RCR obtained in steps S23 and S25, thereby counting the number of cutoff bits used to determine the erase depth. The memory controller 20 stores the obtained cutoff bit number in a buffer 22A within the memory 22.

[0195] Next, the storage controller 20 determines the erase depth of the memory cell to be erased after the write operation based on the erase state of the memory cell after the write operation. That is, the storage controller 20 determines the erase depth of the memory cell to be erased after the write operation based on the cutoff bit count stored in the buffer 22A (step S26). In detail, when the storage controller 20 determines the erase depth of the memory cell after the write operation after the erase operation, it executes the processing of steps S22, S23, and S25 on the memory cell to be measured. When the processing of steps S22, S23, and S25 reaches a number of times X (for example, 4 times), the storage controller 20 determines whether the average value of the cutoff bit count for the number of times X exceeds the reference value Y1 (step S27). When the average value of the cutoff bit count for the number of times X exceeds the reference value Y1 (yes), the storage controller 20 increases the pulse time PDr of the erase voltage VERA by a predetermined time (step S28). On the other hand, when the average value of the number of cutoff bits of the times X does not exceed the reference value Y1 (No), the memory controller 20 ends the process of “determining the pulse time of the erase voltage VERA”.

[0196] Furthermore, in step S27, the average value of the number of cutoff bits for the number of times X is compared with the reference value Y1. However, the maximum value of the number of cutoff bits in one or more word lines WL when the operation is performed the number of times X may be compared with the reference value Y1, or the maximum value of the number of cutoff bits in all word lines WL when the operation is performed the number of times X may be compared with the reference value Y1.

[0197] The specific example of determining whether the number of cutoff bits exceeds the reference value Y1 in step S27, that is, whether to update the pulse duration, is the same as in Example 1. If the average of the number of cutoff bits at t-3, t-2, t-1, and t-0 stored in buffer 22A does not exceed the reference value 30, memory controller 20 does not update the pulse duration of erase voltage VERA and immediately terminates the process. On the other hand, if the average of the number of cutoff bits at t-3, t-2, t-1, and t-0 stored in buffer 22A exceeds the reference value 30, memory controller 20 increases the pulse duration of erase voltage VERA by a predetermined time and then terminates the process.

[0198] Next, the input and output of commands, addresses, and data between the memory controller 20 and the semiconductor memory device 10 in the second example of the erase operation according to the first embodiment will be described.

[0199] Figure 20 This diagram shows a command sequence in the second example of the erase operation of Embodiment 1. The output of commands and addresses from the memory controller 20 to the semiconductor memory device 10, as well as the input and output of data between the memory controller 20 and the semiconductor memory device 10, described below, are performed using I / O signals DQ0 to DQ7. Figure 20 The command sequence shown includes commands, addresses, and data input / output cycles. Commands are represented by hexagons, addresses by rounded quadrangles (or oval shapes), and data input / output cycles by quadrangles.

[0200] like Figure 20 As shown, the command sequence includes: a phase P1 corresponding to "setting the pulse time of the erase voltage VERA (step S1)", a phase P2 corresponding to "commanding to perform an erase operation (step S2)", a phase P5 corresponding to "commanding to perform a write operation (step S5)", a phase P3A corresponding to "setting the determination level AR3 (step S21)" in the offset read of the lower page read, a phase P4A corresponding to "commanding to perform a lower page read (step S22)" in the offset read, and a phase P6 corresponding to "commanding to perform a single-level read (step S25)". In addition, phases P1 and P2 are similar to the aforementioned Figure 15 The phases P1 and P2 shown are identical.

[0201] First, in phase P1 for setting the pulse duration of the erase voltage VERA, the memory controller 20 sequentially outputs a command "0Xh," an address "00h," and data "PDr" to the semiconductor memory device 10. Thus, the memory controller 20 specifies an erase mode for the semiconductor memory device 10 and sets the pulse duration PDr of the erase voltage VERA used in the erase target block BLKr in the register 15D_1 of the semiconductor memory device 10.

[0202] Next, in phase P2, which instructs the erase operation to proceed, the memory controller 20 sequentially outputs an erase setup command "60h," the address "ADD" of the erase target block BLKr, and an erase execution command "D0h" to the semiconductor memory device 10. Upon receiving the erase execution command "D0h," the sequencer 16 of the semiconductor memory device 10 applies an erase voltage VERA for a pulse duration PDr to the well wiring CPWELL, thereby executing the erase operation on the erase target block BLKr. Next, the memory controller 20 outputs a status read command "70h" to the semiconductor memory device 10. Upon receiving the status read command "70h," the semiconductor memory device 10 outputs data "PASS" to the memory controller 20, indicating that the erase operation has passed, for example.

[0203] Next, in stage P5, which instructs a write operation, the memory controller 20 sequentially outputs a write setup command "80h," the write target addresses "ADD1-ADD5," the write data "DI," and a write execute command "10h" to the semiconductor memory device 10. Upon receiving the write execute command "10h," the sequencer 16 of the semiconductor memory device 10 executes a write operation corresponding to the write data "DI" on the write target memory cells specified by the addresses "ADD1-ADD5." During this write operation, the sequencer 16 transitions the ready / busy signal R / Bn from the ready state to the busy state (R / Bn = "L"). Furthermore, stage P5 is a write operation to a specific address within a block. The memory controller 20 may also repeatedly execute stage P5 to write to a portion of the addresses within a block or to all addresses within the block.

[0204] Next, in phase P3A for setting the decision level AR3, the memory controller 20 sequentially outputs an offset read command "X2h," an address "01h" indicating the read voltage AR, and data "SHIFT" indicating an offset value from the read voltage AR to the semiconductor memory device 10. Consequently, the memory controller 20 sets the decision level AR3 used for the offset read of the lower page in the semiconductor memory device 10.

[0205] Next, in phase P4A, which instructs a lower page read, the memory controller 20 sequentially outputs a lower page command "01h," a read setup command "00h," the measurement target addresses "ADD1-ADD5," and a read execution command "30h" to the semiconductor memory device 10. Upon receiving the read execution command "30h," the sequencer 16 of the semiconductor memory device 10 performs a read operation at decision level AR3 and a read operation at read voltage ER in state "E" on the measurement target memory cells specified by addresses "ADD1-ADD5." During this read operation, the sequencer 16 transitions the ready / busy signal R / Bn from the ready state to the busy state (R / Bn = "L"). The sequencer 16 then outputs the uncorrected lower page data RLP obtained through the read operation at decision level AR3 and read voltage ER to the memory controller 20. The memory controller 20 performs error correction on the received lower page data RLP before error correction using the ECC circuit 24 and calculates lower page data CLP after error correction.

[0206] Next, in phase P6, which instructs a single-level read, the memory controller 20 sequentially outputs a single-level read command "X1h," an address "03h" indicating a read voltage CR in state "C," a read setup command "00h," the measurement target addresses "ADD1-ADD5," and a read execution command "30h" to the semiconductor memory device 10. Upon receiving the read execution command "30h," the sequencer 16 of the semiconductor memory device 10 executes a read operation at the read voltage CR on the memory cells designated by the measurement targets at the addresses "ADD1-ADD5." During this read operation, the sequencer 16 transitions the ready / busy signal R / Bn from the ready state to the busy state (R / Bn = "L"). The semiconductor memory device 10 then outputs the read result RCR obtained by the read operation at the read voltage CR to the memory controller 20.

[0207] Then, as described above, the memory controller 20 performs a logical AND operation on the data RLP2 obtained by performing a logical NOT operation on the lower page data RLP before error correction and the two data CLP and RCR to calculate the number of cutoff bits for determining the erase depth.

[0208] In the second example, the memory controller 20 obtains the cutoff bit count of the memory cell to be measured in the erase target block BLKr by a read operation after a write operation. Based on the cutoff bit count, the memory controller 20 updates or maintains the pulse time PDr of the erase voltage VERA.

[0209] 1.3 Effects of the First Implementation

[0210] According to the first embodiment, by adjusting or updating the pulse duration of the erase voltage VERA after an erase operation or a write operation, the erase of the memory cell achieved by the erase operation can be optimized. In other words, by adjusting or updating the pulse duration of the erase voltage VERA, the memory cell can be prevented from transitioning to an under-erased state or an over-erased state due to the erase operation.

[0211] By preventing the memory cell from transitioning to an over-erased state due to an erase operation, damage to the memory cell caused by the erase operation can be reduced. Furthermore, by preventing the memory cell from transitioning to an under-erased state due to an erase operation, read errors in page reads, such as those in state A, can be reduced.

[0212] Hereinafter, comparative examples will be shown and the effects of the first embodiment will be described in detail. Figure 21 This is a graph showing the relationship between the number of write / erase operations on a memory cell and the erase depth of the memory cell achieved by the erase operation as a comparative example. As the number of write / erase operations on a memory cell increases, the fatigue of the memory cell progresses. Therefore, as the number of write / erase operations increases, even if the memory cell is erased, the amount of electrons extracted from the charge storage layer of the memory cell gradually decreases, and the erase depth gradually becomes shallower. Therefore, as Figure 21 As shown in the figure, when the erase operation is performed with a constant number of erase cycles, the erase depth of the memory cell gradually becomes shallower, approaching the upper limit of the allowable erase depth range. Therefore, the number of erase cycles is increased until the erase depth exceeds the allowable range. When the number of erase cycles is increased, the erase depth of the memory cell becomes deeper immediately after the increase, which causes the memory cell to tire.

[0213] In the aforementioned first embodiment, based on the erasure result (or erasure state, erasure depth) of the erased object storage unit after the erase action or the write action, the pulse time of the erase voltage VERA used in the next erase action for the erased object storage unit is adjusted or updated.

[0214] Specifically, based on the threshold voltage distribution of the memory cell in state "Er" after an erase operation or a write operation, it is determined whether the erase depth of the memory cell is in an under-erased state, a properly erased state, or an over-erased state. Furthermore, based on the erase depth, the pulse duration of the erase voltage VERA is adjusted or updated. For example, if the erase depth of the memory cell is in an under-erased state, the pulse duration of the erase voltage VERA is increased. On the other hand, if the erase depth of the memory cell is in an over-erased state, the pulse duration of the erase voltage VERA is shortened.

[0215] The relationship between the number of times of writing / erasing the memory cell in the erasing operation of the first embodiment and the erasing depth of the memory cell achieved by the erasing operation is shown in FIG. Figure 22 In the first embodiment, as described above, by adjusting the pulse time of the erase voltage VERA, it is possible to achieve fine erasure of the memory cell. Figure 22 As shown, Figure 21 Compared to the comparative example, the erase depth of the memory cell can be prevented from becoming deeper or shallower. By preventing the erase depth of the memory cell from becoming deeper, in other words, by preventing the memory cell from becoming over-erased, damage to the memory cell can be reduced. Furthermore, by preventing the erase depth of the memory cell from becoming shallower, in other words, by preventing the memory cell from becoming under-erased, read errors during page reads can be reduced.

[0216] As described above, according to the first embodiment, it is possible to provide a storage system and a semiconductor storage device that can reduce damage to memory cells and read errors and improve the performance of an erase operation.

[0217] 2. Second Implementation

[0218] The following describes an erase operation in the storage system 1 according to the second embodiment. The storage system 1 according to the second embodiment has the same configuration as that of the first embodiment. The second embodiment will be described mainly with respect to differences from the first embodiment.

[0219] 2.1 Erase Operation in the Second Embodiment

[0220] In the erase operation of the second embodiment, the initial voltage value of the erase voltage VERA is adjusted (or changed) based on the erase result of the memory cell after the erase operation, or based on the erase result of the memory cell after the write operation after the erase operation. For example, the initial voltage value of the erase voltage VERA is increased or decreased. The initial voltage value of the erase voltage VERA adjusted in the second embodiment is the voltage value of the erase voltage VERA in the first erase cycle.

[0221] 2.1.1 The first example of erasing

[0222] In the first example, after the erase operation, the initial voltage value of the erase voltage VERA is updated based on the erase results of the memory cells included in the word lines WL and string units SU to be measured within the erase target block. This example shows how the initial voltage value of the erase voltage VERA is increased based on the erase results of the memory cells.

[0223] Figure 23 This is a flowchart showing a first example of the erase operation in the storage system 1 according to the second embodiment. Figure 241 is a diagram showing the interaction of operations performed between the memory controller 20 and the semiconductor memory device 10 . Figure 25 This diagram shows an example of a voltage value management table 22B_2 provided within the memory 22 of the storage controller 20. The voltage value management table 22B_2 manages the initial voltage value of the erase voltage VERA. In the voltage value management table 22B_2, the initial voltage value PAr used during the erase operation for a block BLKr (r is an integer from 0 to m) is associated with the block BLKr. Figure 23 The processing shown is commanded and controlled by the storage controller 20 (or the CPU 21 ).

[0224] like Figure 23 and Figure 24 As shown, when an erase operation begins, the memory controller 20 first transmits the initial voltage value PAr of the erase voltage VERA corresponding to the erase target block BLKr from the voltage value management table 22B_2 to the semiconductor memory device 10 and sets it in the register 15D_2 of the semiconductor memory device 10. Specifically, the memory controller 20 obtains the initial voltage value PAr of the erase voltage VERA corresponding to the erase target block BLKr from the voltage value management table 22B_2 and transmits it to the semiconductor memory device 10, which stores it in the register 15D_2 (step S31). For example, if the erase target block is block BLK0, the memory controller 20 transmits the initial voltage value PA0 corresponding to block BLK0 to the semiconductor memory device 10, which stores it in the register 15D_2.

[0225] Next, the memory controller 20 instructs the semiconductor memory device 10 to perform an erase operation (step S32). The sequencer 16 of the semiconductor memory device 10 performs an erase operation on the erase target block BLKr using the initial voltage value PAr of the erase voltage VERA stored in the register 15D_2.

[0226] Next, the memory controller 20 obtains the erase results of the memory cells from the semiconductor memory device 10 based on the erase operation. Based on the erase results of the memory cells obtained from the semiconductor memory device 10, the memory controller 20 determines whether to update the initial voltage value PAr of the erase voltage VERA (hereinafter referred to as "determining the initial voltage value of the erase voltage VERA") (step S33). For example, the "determining the initial voltage value of the erase voltage VERA" process in step S33 is executed each time an erase operation is performed, each time a predetermined number of write / erase operations are performed, or when the number of write / erase operations reaches a predetermined number. The details of the "determining the initial voltage value of the erase voltage VERA" process in step S33 will be described later.

[0227] Next, based on the result of "determining the initial voltage value of the erase voltage VERA" in step S33, the memory controller 20 updates the initial voltage value PAr corresponding to the erase target block BLKr in the voltage value management table 22B_2 of the memory 22, or maintains it unchanged without updating (step S34). This completes the erase operation.

[0228] Then, Figure 23 The process of "determining the initial voltage value of the erase voltage VERA" in step S33 in the flowchart shown in FIG. Figure 26 This is a flowchart showing the process of "determining the initial voltage value of the erase voltage VERA" in step S33. Figure 26 The processing shown is commanded and controlled by the storage controller 20 (or the CPU 21 ).

[0229] Figure 26 The processing of steps S11 to S14 shown in FIG. Figure 11A The processes in steps S11 to S14 shown are the same.

[0230] like Figure 26 As shown in step S11, the memory controller 20 sets the read voltage to the read voltage AR of state "A" and further sets an offset value from the read voltage AR. Here, the read voltage offset by the offset value from the read voltage AR is defined as the judgment level AR2. The judgment level AR2 is a voltage level used to determine the erase depth of the memory cell after the erase operation. The memory controller 20 sets the judgment level AR2 offset by the offset value from the read voltage AR to the semiconductor memory device 10. Furthermore, the memory controller 20 specifies the word line WL and string unit SU to be measured within the erase target block in the semiconductor memory device 10 (step S11).

[0231] Next, the memory controller 20 instructs the semiconductor memory device 10 to perform a "single-level read" in state "A" (step S12). Upon receiving the "single-level read" command in state "A," the sequencer 16 of the semiconductor memory device 10 reads the memory cell to be measured at the set determination level AR2. The sequencer 16 outputs the read result RA2R from the semiconductor memory device 10 to the memory controller 20 at the determination level AR2. Based on the read result RA2R, the memory controller 20 counts the number of cutoff bits as the erase result after the erase operation. The number of cutoff bits is stored in the buffer 22A within the memory 22.

[0232] Next, the memory controller 20 determines the erase depth of the memory cell after the erase operation based on the read result at the determination level AR2. Specifically, the memory controller 20 determines the erase depth of the memory cell after the erase operation based on the obtained cutoff bit count (step S13). Specifically, the memory controller 20 performs a read operation at the determination level AR2 while determining the erase depth of the memory cell after the erase operation. When the read operation reaches a number X, the memory controller 20 determines whether the average number of cutoff bit counts for the number X exceeds a reference value Y1 (step S14).

[0233] In step S14, if the average value of the number of cutoff bits exceeds the reference value Y1 (Yes), the memory controller 20 increases the initial voltage value PAr of the erase voltage VERA by a predetermined value (step S18). On the other hand, if the average value of the number of cutoff bits does not exceed the reference value Y1 (No), the memory controller 20 ends the process of "determining the initial voltage value of the erase voltage VERA."

[0234] The specific example of determining whether the number of cutoff bits exceeds the reference value Y1 in step S14 is the same as in the first embodiment. If the average of the number of cutoff bits at t-3, t-2, t-1, and t-0 stored in buffer 22A does not exceed the reference value 30, memory controller 20 does not change initial voltage value PAr of erase voltage VERA and terminates the process. On the other hand, if the average of the number of cutoff bits at t-3, t-2, t-1, and t-0 stored in buffer 22A exceeds the reference value 30, memory controller 20 increases initial voltage value PAr of erase voltage VERA by a predetermined value and terminates the process.

[0235] Next, the input and output of commands, addresses, and data between the memory controller 20 and the semiconductor memory device 10 in the first example of the erase operation according to the second embodiment will be described.

[0236] Figure 27 This diagram shows a command sequence in a first example of an erase operation according to Embodiment 2. The output of commands and addresses from the memory controller 20 to the semiconductor memory device 10, as well as the input and output of data between the memory controller 20 and the semiconductor memory device 10, described below, are performed using I / O signals DQ0 to DQ7. Figure 27 The command sequence shown includes commands, addresses, and data input / output cycles. Commands are represented by hexagons, addresses by rounded quadrangles (or oval shapes), and data input / output cycles by quadrangles.

[0237] like Figure 27As shown, the command sequence includes a phase P11 corresponding to "setting the initial voltage value of the erase voltage VERA (step S21)", a phase P2 corresponding to "commanding to perform an erase operation (step S22)", a phase P3 corresponding to "setting the determination level AR2 (step S11)" in the offset read of the single-level read, and phases P3 and P4 corresponding to "commanding to perform a single-level read (step S12)" in the offset read. In addition, phases P2, P3, and P4 are similar to the aforementioned Figure 15 The stages P2, P3, and P4 shown are identical.

[0238] First, in stage P11, which sets the initial voltage value of the erase voltage VERA, the memory controller 20 sequentially outputs a command "0Xh," an address "01h," and data "PAr" to the semiconductor memory device 10. The command "0Xh" specifies the erase mode. The address "01h" sets the initial voltage value of the erase voltage VERA. The data "PAr" indicates the initial voltage value of the erase voltage VERA corresponding to the erase target block BLKr. Thus, the memory controller 20 specifies the erase mode for the semiconductor memory device 10 and sets the initial voltage value PAr of the erase voltage VERA used in the erase operation on the erase target block BLKr in the register 15D_2 of the semiconductor memory device 10.

[0239] Next, in phase P2, which instructs the erase operation to be performed, the memory controller 20 sequentially outputs an erase setup command "60h," the address "ADD" of the erase target block BLKr, and an erase execution command "D0h" to the semiconductor memory device 10. Upon receiving the erase execution command "D0h," the sequencer 16 of the semiconductor memory device 10 applies an erase voltage VERA having an initial voltage value PAr to the well wiring CPWELL, thereby executing the erase operation on the erase target block BLKr.

[0240] Then, the memory controller 20 outputs a status read command "70h" to the semiconductor memory device 10. Upon receiving the status read command "70h," the semiconductor memory device 10 outputs data indicating whether the erase operation has passed or failed to the memory controller 20. For example, the semiconductor memory device 10 outputs data "PASS" indicating that the erase operation has passed to the memory controller 20.

[0241] Next, in phase P3 for setting the determination level AR2, the memory controller 20 sequentially outputs a single-level read command "X1h" for state "A" and an address "01h" indicating the read voltage AR for state "A" to the semiconductor memory device 10. Furthermore, the memory controller 20 sequentially outputs a shift read command "X2h," an address "01h," and data "SHIFT" indicating an offset value from the read voltage AR to the semiconductor memory device 10. Consequently, the memory controller 20 sets the determination level AR2 used for the shift read in the single-level read to the semiconductor memory device 10.

[0242] Next, in phase P4, where the command is read, the memory controller 20 sequentially outputs a read setup command "00h," the measurement target addresses "ADD1-ADD5," and a read execution command "30h" to the semiconductor memory device 10. Upon receiving the read execution command "30h," the sequencer 16 of the semiconductor memory device 10 performs a read operation at the determination level AR2 on the measurement target memory cells specified by the addresses "ADD1-ADD5." The sequencer 16 then outputs a read result RA2R obtained from the read operation at the determination level AR2 from the semiconductor memory device 10 to the memory controller 20. Based on the read result RA2R, the memory controller 20 counts the number of off-bit bits "DO2" that remain off instead of on.

[0243] As mentioned above, in the first example, an example of increasing the initial voltage value PAr of the erase voltage VERA is described, but similarly to the modified example of the first example of the first embodiment, the initial voltage value PAr of the erase voltage VERA can also be increased or decreased based on the erase result of the storage cell.

[0244] In the first example, during a read operation after an erase operation, the semiconductor memory device 10 outputs the number of cutoff bits in the memory cells to be measured within the erase target block BLKr to the memory controller 20. Based on the number of cutoff bits, the memory controller 20 updates the initial voltage value PAr of the erase voltage VERA or maintains it without updating.

[0245] 2.1.2 Second Example of Erase Action

[0246] In the second example, after a write operation following an erase operation, the initial voltage value of erase voltage VERA is updated based on the erase results of the memory cells included in the word lines WL and string units SU to be measured within the erase target block. This example shows how the initial voltage value of erase voltage VERA is increased based on the erase results of the memory cells. In the second example, a write operation is added between the erase operation and the determination of whether to update the initial voltage value.

[0247] Figure 28 This is a flowchart showing a second example of the erasing operation in the storage system 1 according to the second embodiment. Figure 28 The processing shown is commanded and controlled by the storage controller 20 (or the CPU 21 ).

[0248] Similar to the first example, the memory controller 20 transmits the initial voltage value PAr of the erase voltage VERA corresponding to the erase target block BLKr from the voltage value management table 22B_2 to the semiconductor memory device 10, causing it to be stored in the register 15D_2 of the semiconductor memory device 10 (step S31). Furthermore, the memory controller 20 instructs the semiconductor memory device 10 to perform an erase operation (step S32). Upon receiving the erase operation command, the sequencer 16 of the semiconductor memory device 10 executes the erase operation on the erase target block BLKr.

[0249] After erasing the erase target block BLKr, the memory controller 20 instructs the semiconductor memory device 10 to perform a write operation (step S35). Upon receiving the write operation command, the sequencer 16 of the semiconductor memory device 10 performs a write operation on the write target memory cells in the erase target block BLKr.

[0250] Next, the memory controller 20 determines whether to update the initial voltage value PAr of the erase voltage VERA based on the erase state of the memory cell after the write operation (hereinafter referred to as "determining the initial voltage value of the erase voltage VERA") (step S33A). For example, the process of "determining the initial voltage value of the erase voltage VERA" in step S33A is executed similarly to the first example, each time a write operation is performed after an erase operation, each time a predetermined number of write operations / erase operations are executed, or each time the predetermined number of write operations / erase operations are executed. The details of the process of "determining the initial voltage value of the erase voltage VERA" in step S33A will be described later.

[0251] Next, based on the result of "determining the initial voltage value of the erase voltage VERA" in step S33A, the memory controller 20 updates the initial voltage value PAr corresponding to the erase target block BLKr in the voltage value management table 22B_2 of the memory 22, or maintains it unchanged without updating (step S34). This completes the erase operation.

[0252] Then, Figure 28 The process of "determining the initial voltage value of the erase voltage VERA" in step S33A in the flowchart shown in FIG. Figure 294 is a flowchart showing the process of "determining the initial voltage value of the erase voltage VERA" in step S33A. Figure 29 The processing shown is commanded and controlled by the storage controller 20 (or the CPU 21 ).

[0253] Figure 29 The processing of steps S21 to S27 shown in FIG. Figure 18 The processes in steps S21 to S27 shown are the same.

[0254] like Figure 29 As shown, the memory controller 20 sets the read voltage to the read voltage AR in state "A" and further sets an offset value from the read voltage AR. Here, the read voltage offset by the offset value from the read voltage AR is defined as the judgment level AR3. The judgment level AR3 is a voltage level used to determine the erase depth of the memory cell after the erase operation. The memory controller 20 sets the judgment level AR3, which is offset by the offset value from the read voltage AR, in the semiconductor memory device 10. Furthermore, the memory controller 20 specifies the word line WL and string unit SU to be measured within the erase target block in the semiconductor memory device 10 (step S21).

[0255] Next, the memory controller 20 instructs the semiconductor memory device 10 to "read the lower page" (step S22). Upon receiving the "read lower page" command, the sequencer 16 of the semiconductor memory device 10 reads the memory cell being measured using, for example, the set decision level AR3 and read voltage ER, obtaining lower page data RLP before error correction. Lower page data RLP is data immediately after being read using the decision level AR3 and read voltage ER, and is not error-corrected.

[0256] Next, the memory controller 20 receives the uncorrected lower page data RLP from the semiconductor memory device 10. The memory controller 20 corrects errors in the uncorrected lower page data RLP using the ECC circuit 24 to obtain corrected lower page data CLP (step S23).

[0257] Next, the memory controller 20 sets the read voltage CR of the state "C" to the semiconductor memory device 10. Furthermore, the memory controller 20 specifies the word line WL and string unit SU to be measured in the erase target block BLKr to the semiconductor memory device 10 (step S24).

[0258] Next, the memory controller 20 instructs the semiconductor memory device 10 to perform a "single-level read" in state "C" (step S25). Upon receiving the "single-level read" in state "C" command, the sequencer 16 performs a read operation on the memory cell to be measured, for example, at a set read voltage CR, obtains a read result RCR in state "C," and outputs it to the memory controller 20.

[0259] The memory controller 20 performs a logical AND operation on the data RLP2 obtained by performing a logical NOT operation on the pre-error-corrected lower page data RLP obtained in step S22, and the two data CLP and RCR obtained in steps S23 and S25, to obtain a cutoff bit number for determining the erase depth. The memory controller 20 stores the obtained cutoff bit number in a buffer 22A within the memory 22.

[0260] Next, the memory controller 20 determines the erase depth of the memory cell to be erased after the write operation based on the erase state of the memory cell after the write operation. Specifically, the memory controller 20 determines the erase depth of the memory cell to be erased after the write operation based on the cutoff bit count stored in the buffer 22A (step S26). Specifically, when determining the erase depth of the memory cell after the write operation, the memory controller 20 executes steps S22, S23, and S25 for the memory cell to be measured. When the processing of steps S22, S23, and S25 reaches a number X, the memory controller 20 determines whether the average value of the cutoff bit count for the number X exceeds a reference value Y1 (step S27). If the average value of the cutoff bit count for the number X exceeds the reference value Y1 (yes), the memory controller 20 increases the initial voltage value PAr of the erase voltage VERA by a predetermined value (step S29). On the other hand, if the average value of the cutoff bit count for the number X does not exceed the reference value Y1 (no), the memory controller 20 ends the process of "determining the initial voltage value of the erase voltage VERA."

[0261] The specific example of the determination of whether the number of cutoff digits exceeds the reference value Y1 in the aforementioned step S27 is the same as that of the first embodiment.

[0262] Next, the input and output of commands, addresses, and data between the memory controller 20 and the semiconductor memory device 10 in the second example of the erase operation according to the second embodiment will be described.

[0263] Figure 30 This diagram shows a command sequence in a second example of an erase operation according to Embodiment 2. The output of commands and addresses from the memory controller 20 to the semiconductor memory device 10, as well as the input and output of data between the memory controller 20 and the semiconductor memory device 10, described below, are performed using I / O signals DQ0 to DQ7. Figure 30The command sequence shown includes commands, addresses, and data input / output cycles. Commands are represented by hexagons, addresses by rounded quadrangles (or oval shapes), and data input / output cycles by quadrangles.

[0264] like Figure 30 As shown, the command sequence includes a phase P11 corresponding to "setting the initial voltage value of the erase voltage VERA (step S31)", a phase P2 corresponding to "commanding to perform an erase operation (step S32)", a phase P5 corresponding to "commanding to perform a write operation (step S35)", a phase P3A corresponding to "setting the determination level AR3 (step S21)" in the offset read of the lower page read, a phase P4A corresponding to "commanding to perform a lower page read (step S22)" in the offset read, and a phase P6 corresponding to "commanding to perform a single-level read (step S25)". In addition, the phase P11 is similar to the aforementioned Figure 27 The stage P11 shown is the same as the previous stage P2, P5, P3A, P4A, P6. Figure 20 The stages P2, P5, P3A, P4A, and P6 shown are identical.

[0265] First, in step P11, which sets the initial voltage value of the erase voltage VERA, the memory controller 20 sequentially outputs a command "0Xh" designating an erase mode, an address "00h," and data "PAr" to the semiconductor memory device 10. Thus, the memory controller 20 designates the erase mode to the semiconductor memory device 10 and sets the initial voltage value PAr of the erase voltage VERA used in the erase target block BLKr in the register 15D_2 of the semiconductor memory device 10.

[0266] Next, in phase P2, which instructs the erase operation to proceed, the memory controller 20 sequentially outputs an erase setup command "60h," the address "ADD" of the erase target block BLKr, and an erase execution command "D0h" to the semiconductor memory device 10. Upon receiving the erase execution command "D0h," the sequencer 16 of the semiconductor memory device 10 applies an erase voltage VERA having an initial voltage value PAr to the well wiring CPWELL, thereby executing the erase operation on the erase target block BLKr. Next, the memory controller 20 outputs a status read command "70h" to the semiconductor memory device 10. Upon receiving the status read command "70h," the semiconductor memory device 10 outputs data "PASS" indicating that the erase operation has passed to the memory controller 20, for example.

[0267] Next, in stage P5, which instructs a write operation, the memory controller 20 sequentially outputs a write setup command "80h," the write target addresses "ADD1-ADD5," the write data "DI," and a write execute command "10h" to the semiconductor memory device 10. Upon receiving the write execute command "10h," the sequencer 16 of the semiconductor memory device 10 executes a write operation corresponding to the write data "DI" on the write target memory cells specified by the addresses "ADD1-ADD5." Furthermore, stage P5 involves a write operation to a specific address within a block. The memory controller 20 may also repeatedly execute stage P5 to write to a portion of or all addresses within a block.

[0268] Next, in phase P3A for setting the decision level AR3, the memory controller 20 sequentially outputs an offset read command "X2h," an address "01h" indicating the read voltage AR, and data "SHIFT" indicating an offset value from the read voltage AR to the semiconductor memory device 10. Consequently, the memory controller 20 sets the decision level AR3 used for the offset read of the lower page in the semiconductor memory device 10.

[0269] Next, in phase P4A, which instructs a lower page read, the memory controller 20 sequentially outputs a lower page command "01h," a read setup command "00h," the measurement target addresses "ADD1-ADD5," and a read execution command "30h" to the semiconductor memory device 10. Upon receiving the read execution command "30h," the sequencer 16 of the semiconductor memory device 10 performs a read operation at the decision level AR3 and a read operation at the read voltage ER on the measurement target memory cells specified by the addresses "ADD1-ADD5." The sequencer 16 then outputs the pre-error-corrected lower page data "RLP" obtained through the read operation at the decision level AR3 and the read voltage ER to the memory controller 20. The memory controller 20 then performs error correction on the received pre-error-corrected lower page data "RLP" using the ECC circuit 24, calculating the post-error-corrected lower page data CLP.

[0270] Next, in phase P6, which instructs a single-level read, the memory controller 20 sequentially outputs a single-level read command "X1h," an address "03h" indicating a read voltage CR in state "C," a read setup command "00h," the measurement target addresses "ADD1-ADD5," and a read execution command "30h" to the semiconductor memory device 10. Upon receiving the read execution command "30h," the sequencer 16 of the semiconductor memory device 10 executes a read operation at the read voltage CR on the measurement target memory cells specified by the addresses "ADD1-ADD5." The semiconductor memory device 10 then outputs a read result RCR obtained by the read operation at the read voltage CR to the memory controller 20.

[0271] Then, as described above, the memory controller 20 performs a logical AND operation on the data RLP2 obtained by performing a logical NOT operation on the lower page data RLP before error correction and the two data CLP and RCR to calculate the number of cutoff bits for determining the erase depth.

[0272] In the second example, the memory controller 20 obtains the cutoff bit count of the memory cell to be measured in the erase target block BLKr through a read operation after a write operation. Based on the cutoff bit count, the memory controller 20 updates the initial voltage value PAr of the erase voltage VERA or maintains it without updating.

[0273] 2.2 Effects of the Second Implementation

[0274] According to the second embodiment, by adjusting or updating the initial voltage value of the erase voltage VERA in the first erase cycle after the erase operation or the write operation, the erasure of the memory cell by the erase operation can be optimized. In other words, by adjusting or updating the initial voltage value of the erase voltage VERA in the first erase cycle, the memory cell can be prevented from transitioning to an under-erased state or an over-erased state due to the erase operation.

[0275] By preventing the memory cell from transitioning to an over-erased state due to an erase operation, damage to the memory cell caused by the erase operation can be reduced. Furthermore, by preventing the memory cell from transitioning to an under-erased state due to an erase operation, read errors during page reads, such as those involving state A, can be reduced. Other structures and effects are the same as those of the first embodiment.

[0276] 3. Third Implementation Method

[0277] The following describes an erase operation in the storage system 1 according to the third embodiment. The storage system 1 according to the third embodiment has the same configuration as that of the first embodiment. The third embodiment will be described mainly focusing on differences from the first and second embodiments.

[0278] 3.1 Erase Operation in the Third Embodiment

[0279] In the erase operation of the third embodiment, at least one of the initial voltage value or the pulse time of the erase voltage VERA is adjusted (or changed) based on the erase result of the memory cell after the erase operation or based on the erase result of the memory cell after the write operation after the erase operation. The initial voltage value of the erase voltage VERA adjusted in the third embodiment is the voltage value of the erase voltage VERA in the first erase cycle.

[0280] 3.1.1 The first example of erasing

[0281] In the first example, after an erase operation, at least one of the initial voltage value and pulse duration of erase voltage VERA is updated based on the erase results of the memory cells included in the word lines WL and string units SU to be measured within the erase target block. This example shows a method in which, if the initial voltage value of erase voltage VERA does not exceed a reference value, a determination is made as to whether the initial voltage value of erase voltage VERA should be updated; and, if the initial voltage value of erase voltage VERA exceeds the reference value, a determination is made as to whether the pulse duration of erase voltage VERA should be updated.

[0282] Figure 31 This is a flowchart showing a first example of the erase operation in the storage system 1 according to the third embodiment. Figure 32 1 is a diagram showing the interaction of operations performed between the memory controller 20 and the semiconductor memory device 10 . Figure 33 This diagram shows an example of a pulse time and voltage value management table 22B_3 provided within the memory 22 of the storage controller 20. Management table 22B_3 manages the pulse time and initial voltage value of the erase voltage VERA. Management table 22B_3 associates the pulse time PDr and initial voltage value PAr used in the erase operation for each block BLKr. Figure 31 The processing shown is commanded and controlled by the storage controller 20 (or the CPU 21 ).

[0283] like Figure 31 and Figure 32 As shown, when the erase operation starts, the memory controller 20 first sends the pulse time PDr of the erase voltage VERA corresponding to the erase target block BLKr in the management table 22B_3 to the semiconductor memory device 10 and stores it in the register 15D_1 of the semiconductor memory device 10 (step S41).

[0284] Next, the memory controller 20 transmits the initial voltage value PAr of the erase voltage VERA corresponding to the erase target block BLKr in the management table 22B_3 to the semiconductor memory device 10 and stores it in the register 15D_2 of the semiconductor memory device 10 (step S42).

[0285] Next, the memory controller 20 instructs the semiconductor memory device 10 to perform an erase operation (step S43). Upon receiving the erase operation command, the sequencer 16 of the semiconductor memory device 10 executes the erase operation on the erase target block BLKr using the pulse time PDr and initial voltage value PAr stored in registers 15D_1 and 15D_2.

[0286] Next, the memory controller 20 determines whether the initial voltage value PAr of the erase voltage VERA used in the erase operation exceeds the reference value Y (step S44). If the initial voltage value PAr does not exceed the reference value Y (no), the memory controller 20 transitions to "determine the initial voltage value of the erase voltage VERA" (step S45). The processing of step S45 is the same as the above-mentioned Figure 23 The processing of step S33 shown is the same.

[0287] Next, the memory controller 20 updates the initial voltage value PAr corresponding to the erase target block BLKr in the management table 22B_3 of the memory 22 based on the determination result of “determining the initial voltage value of the erase voltage VERA” in step S45 (step S46 ).

[0288] On the other hand, in the judgment of step S44, when the initial voltage value PAr of the erase voltage VERA exceeds the reference value Y (yes), the memory controller 20 changes to "judging the pulse time of the erase voltage VERA" (step S47). The processing of step S47 is the same as the above-mentioned Figure 8 The processing of step S3 shown is the same.

[0289] Next, the memory controller 20 updates the pulse time PDr corresponding to the erase target block BLKr in the management table 22B_3 of the memory 22 based on the result of "judging the pulse time of the erase voltage VERA" in step S47 (step S48).

[0290] Next, the input and output of commands, addresses, and data between the memory controller 20 and the semiconductor memory device 10 in the first example of the erase operation according to the third embodiment will be described.

[0291] Figure 34 This diagram shows a command sequence in a first example of an erase operation according to Embodiment 3. The output of commands and addresses from the memory controller 20 to the semiconductor memory device 10, and the output of data between the memory controller 20 and the semiconductor memory device 10, described below, are performed using I / O signals DQ0 to DQ7. Figure 34 The command sequence shown includes commands, addresses, and data input / output cycles. Commands are represented by hexagons, addresses by rounded quadrangles (or oval shapes), and data input / output cycles by quadrangles.

[0292] like Figure 34As shown, the command sequence has a phase P1 corresponding to "setting the pulse time of the erase voltage VERA (step S41)", a phase P11 corresponding to "setting the initial voltage value of the erase voltage VERA (step S42)", a phase P2 corresponding to "commanding to perform an erase operation (step S43)", a phase P3 corresponding to "setting the determination level AR2 (step S11)", and a phase P4 corresponding to "commanding to perform a single-level read (step S12)". In addition, the phases P1, P11, P2, P3, and P4 are similar to the aforementioned Figure 15 and Figure 27 The stages P1 , P11 , P2 , P3 , and P4 shown are identical.

[0293] First, in phase P1 of setting the pulse duration of the erase voltage VERA, the memory controller 20 sequentially outputs a command "0Xh," an address "00h," and data "PDr" to the semiconductor memory device 10. The command "0Xh" specifies the erase mode. The address "00h" sets the pulse duration of the erase voltage VERA. The data "PDr" indicates the pulse duration of the erase voltage VERA corresponding to the erase target block BLKr. Thus, the memory controller 20 specifies the erase mode for the semiconductor memory device 10 and sets the pulse duration PDr of the erase voltage VERA used in the erase operation on the erase target block BLKr in the register 15D_1 of the semiconductor memory device 10.

[0294] Next, in stage P11 of setting the initial voltage value of the erase voltage VERA, the memory controller 20 sequentially outputs the command "0Xh", the address "01h", and "PAr" to the semiconductor memory device 10. The command "0Xh" specifies the erase mode. The address "01h" is an address for setting the initial voltage value of the erase voltage VERA. The data "PAr" is data indicating the initial voltage value of the erase voltage VERA corresponding to the erase target block BLKr. Thus, the memory controller 20 specifies the erase mode for the semiconductor memory device 10 and sets the initial voltage value PAr of the erase voltage VERA used in the erase operation on the erase target block BLKr in the register 15D_2 of the semiconductor memory device 10.

[0295] Next, in phase P2, which instructs the erase operation to be performed, the memory controller 20 sequentially outputs an erase setup command "60h," the address "ADD" of the erase target block BLKr, and an erase execution command "D0h" to the semiconductor memory device 10. Upon receiving the erase execution command "D0h," the sequencer 16 of the semiconductor memory device 10 applies an erase voltage VERA having a pulse duration PDr and an initial voltage value PAr to the well wiring CPWELL, thereby executing the erase operation on the erase target block BLKr.

[0296] Then, the memory controller 20 outputs a status read command "70h" to the semiconductor memory device 10. Upon receiving the status read command "70h", the semiconductor memory device 10 outputs data "PASS" indicating that the erase operation has passed to the memory controller 20, for example.

[0297] Next, in phase P3 for setting determination level AR2, memory controller 20 sequentially outputs a single-state command "X1h" for state "A," an address "01h" indicating read voltage AR for state "A," an offset read command "X2h," an address "01h," and data "SHIFT" indicating an offset value from read voltage AR to semiconductor memory device 10. Consequently, memory controller 20 sets determination level AR2, used for offset read in single-level read, to semiconductor memory device 10.

[0298] Next, in phase P4, where the command is read, the memory controller 20 sequentially outputs a read setup command "00h," addresses "ADD1-ADD5," and a read execution command "30h" to the semiconductor memory device 10. Upon receiving the read execution command "30h," the sequencer 16 of the semiconductor memory device 10 performs a read operation at the determination level AR2 on the memory cells to be measured, which are specified by the addresses "ADD1-ADD5." The sequencer 16 then outputs the read result RA2R from the semiconductor memory device 10 to the memory controller 20 at the determination level AR2. The memory controller 20 counts the number of cutoff bits "DO3" based on the read result RA2R.

[0299] In the first example, after the erase action, the storage controller 20 determines whether to update the initial voltage value of the erase voltage VERA if the initial voltage value of the erase voltage VERA does not exceed the reference value, and determines whether to update the pulse time of the erase voltage VERA if the initial voltage value of the erase voltage VERA exceeds the reference value.

[0300] Furthermore, in the first example, the memory controller 20 first determines whether the initial voltage value of the erase voltage VERA exceeds the reference value. If the initial voltage value exceeds the reference value, the memory controller 20 determines whether to update the pulse duration of the erase voltage VERA. However, the present invention is not limited to this embodiment. Alternatively, the initial voltage value and the pulse duration may be swapped, and the memory controller 20 first determines whether the pulse duration of the erase voltage VERA exceeds the reference value. If the pulse duration exceeds the reference value, the memory controller 20 determines whether to update the initial voltage value of the erase voltage VERA.

[0301] 3.1.2 The second example of erasing action

[0302] In the second example, after the write operation following the erase operation, at least one of the initial voltage value and pulse duration of the erase voltage VERA is updated based on the erase results of the memory cells included in the word lines WL and string units SU to be measured within the erase target block. In the second example, a write operation is added between the erase operation and the determination of whether the initial voltage value of the erase voltage VERA exceeds a reference value.

[0303] Figure 35 This is a flowchart showing a second example of the erasing operation in the storage system 1 according to the third embodiment. Figure 35 The processing shown is commanded and controlled by the storage controller 20 (or the CPU 21 ).

[0304] Similar to the first example, the memory controller 20 transmits the pulse time PDr of the erase voltage VERA corresponding to the erase target block BLKr in the management table 22B_3 to the semiconductor memory device 10 and sets it in the register 15D_1 of the semiconductor memory device 10 (step S41).

[0305] Next, the memory controller 20 transmits the initial voltage value PAr of the erase voltage VERA corresponding to the erase target block BLKr in the management table 22B_3 to the semiconductor memory device 10 and sets it in the register 15D_2 of the semiconductor memory device 10 (step S42).

[0306] Furthermore, the memory controller 20 instructs the semiconductor memory device 10 to perform an erase operation (step S43). Upon receiving the erase operation instruction, the sequencer 16 of the semiconductor memory device 10 executes the erase operation on the erase target block BLKr.

[0307] After erasing the erase target block BLKr, the memory controller 20 instructs the semiconductor memory device 10 to perform a write operation (step S49). Upon receiving the write operation command, the sequencer 16 of the semiconductor memory device 10 performs a write operation on the write target memory cells in the erase target block BLKr.

[0308] The subsequent steps S44, S45, S46 and the processing of steps S44, S47, S48 are the same as Figure 31 The first example shown is similar. Specifically, the memory controller 20 determines whether the initial voltage value PAr of the erase voltage VERA used in the erase operation exceeds the reference value Y (step S44). If the initial voltage value PAr does not exceed the reference value Y (no), the memory controller 20 determines whether to update the initial voltage value PAr (step S45). Based on the determination result, the memory controller 20 updates the initial voltage value PAr of the erase voltage VERA or maintains it without updating (step S46).

[0309] On the other hand, if the initial voltage value PAr exceeds the reference value Y in step S44 (Yes), the memory controller 20 determines whether to update the pulse time PDr of the erase voltage VERA (step S47). Based on the determination result, the memory controller 20 updates the pulse time PDr of the erase voltage VERA or maintains it without updating (step S48). This completes the erase operation.

[0310] Next, the input and output of commands, addresses, and data between the memory controller 20 and the semiconductor memory device 10 in the second example of the erase operation according to the third embodiment will be described.

[0311] Figure 36 This diagram shows a command sequence in the second example of the erase operation according to the third embodiment. The output of commands and addresses from the memory controller 20 to the semiconductor memory device 10, as well as the input and output of data between the memory controller 20 and the semiconductor memory device 10, described below, are performed using I / O signals DQ0 to DQ7. Figure 36 The command sequence shown includes commands, addresses, and data input / output cycles. Commands are represented by hexagons, addresses by rounded quadrangles (or oval shapes), and data input / output cycles by quadrangles.

[0312] like Figure 36 As shown, the command sequence includes a stage P1 corresponding to "setting the pulse time of the erase voltage VERA (step S41)", a stage P11 corresponding to "setting the initial voltage value of the erase voltage VERA (step S42)", a stage P2 corresponding to "commanding to perform an erase operation (step S43)", a stage P5 corresponding to "commanding to perform a write operation (step S49)", a stage P3A corresponding to "setting the determination level AR3 (step S21)" in the offset read of the lower page read, a stage P4A corresponding to "commanding to perform a lower page read (step S22)" in the offset read, and a stage P6 corresponding to "commanding to perform a single-level read (step S25)". In addition, the stages P1, P11, P2, P5, P3A, P4A, and P6 are similar to the above-mentioned Figure 15 、 Figure 20 as well as Figure 27 The stages P1 , P11 , P2 , P5 , P3A, P4A, and P6 shown are identical.

[0313] As in the first example, first, in phase P1 for setting the pulse duration of the erase voltage VERA, the memory controller 20 sequentially outputs a command "0Xh," an address "00h," and data "PDr" indicating the pulse duration to the semiconductor memory device 10. Consequently, the memory controller 20 sets the pulse duration PDr of the erase voltage VERA in the register 15D_1 of the semiconductor memory device 10.

[0314] Next, in step P11 for setting the initial voltage value of erase voltage VERA, memory controller 20 sequentially outputs command "0Xh," address "01h," and data "PAr" indicating the initial voltage value to semiconductor memory device 10. Consequently, memory controller 20 sets initial voltage value PAr of erase voltage VERA in register 15D_2 of semiconductor memory device 10.

[0315] Next, in phase P2, which instructs the erase operation to be performed, the memory controller 20 sequentially outputs an erase setup command "60h," the address "ADD" of the erase target block BLKr, and an erase execution command "D0h" to the semiconductor memory device 10. Upon receiving the erase execution command "D0h," the sequencer 16 of the semiconductor memory device 10 applies an erase voltage VERA having a pulse duration PDr and an initial voltage value PAr to the well wiring CPWELL, thereby executing the erase process on the erase target block BLKr.

[0316] Then, the memory controller 20 outputs a status read command "70h" to the semiconductor memory device 10. Upon receiving the status read command "70h", the semiconductor memory device 10 outputs data "PASS" indicating that the erase operation has passed to the memory controller 20, for example.

[0317] Next, in stage P5, which instructs a write operation, the memory controller 20 sequentially outputs a write setup command "80h," the write target addresses "ADD1-ADD5," the write data "DI," and a write execute command "10h" to the semiconductor memory device 10. Upon receiving the write execute command "10h," the sequencer 16 of the semiconductor memory device 10 executes a write operation corresponding to the write data "DI" on the write target memory cells specified by the addresses "ADD1-ADD5." Furthermore, stage P5 involves a write operation to a specific address within a block. The memory controller 20 may also repeatedly execute stage P5 to write to a portion or all of the addresses within a block.

[0318] Next, in phase P3A for setting the decision level AR3, the memory controller 20 sequentially outputs an offset read command "X2h," an address "01h" indicating the read voltage AR, and data "SHIFT" indicating an offset value from the read voltage AR to the semiconductor memory device 10. Consequently, the memory controller 20 sets the decision level AR3 used for the offset read of the lower page in the semiconductor memory device 10.

[0319] Next, in phase P4A, which instructs a lower page read, the memory controller 20 sequentially outputs a lower page command "01h," a read setup command "00h," the measurement target addresses "ADD1-ADD5," and a read execution command "30h" to the semiconductor memory device 10. Upon receiving the read execution command "30h," the sequencer 16 of the semiconductor memory device 10 performs a read operation at decision level AR3 and a read operation at read voltage ER in state "E" on the measurement target memory cells specified by addresses "ADD1-ADD5." During this read operation, the sequencer 16 transitions the ready / busy signal R / Bn from the ready state to the busy state (R / Bn = "L"). The sequencer 16 then outputs the uncorrected lower page data RLP obtained through the read operation at decision level AR3 and read voltage ER to the memory controller 20. The memory controller 20 performs error correction on the received lower page data RLP before error correction using the ECC circuit 24 and calculates lower page data CLP after error correction.

[0320] Next, in phase P6, which instructs a single-level read, the memory controller 20 sequentially outputs a single-level read command "X1h," an address "03h" indicating a read voltage CR in state "C," a read setup command "00h," the measurement target addresses "ADD1-ADD5," and a read execution command "30h" to the semiconductor memory device 10. Upon receiving the read execution command "30h," the sequencer 16 of the semiconductor memory device 10 executes a read operation at the read voltage CR on the memory cells designated by the measurement targets at the addresses "ADD1-ADD5." During this read operation, the sequencer 16 transitions the ready / busy signal R / Bn from the ready state to the busy state (R / Bn = "L"). The semiconductor memory device 10 then outputs the read result RCR obtained by the read operation at the read voltage CR to the memory controller 20.

[0321] Then, as described above, the memory controller 20 performs a logical AND operation on the data RLP2 obtained by performing a logical NOT operation on the lower page data RLP before error correction and the two data CLP and RCR to calculate the number of cutoff bits for determining the erase depth.

[0322] In the second example, after the write action after the erase action, the storage controller 20 determines whether to update the initial voltage value of the erase voltage VERA if the initial voltage value of the erase voltage VERA does not exceed the reference value, and determines whether to update the pulse time of the erase voltage VERA if the initial voltage value of the erase voltage VERA exceeds the reference value.

[0323] Furthermore, in the second example, the memory controller 20 also first determines whether the initial voltage value of the erase voltage VERA exceeds the reference value. If the initial voltage value exceeds the reference value, the memory controller 20 determines whether to update the pulse duration of the erase voltage VERA. However, this is not limiting. Alternatively, the initial voltage value and the pulse duration may be swapped, and the memory controller 20 first determines whether the pulse duration of the erase voltage VERA exceeds the reference value. If the pulse duration exceeds the reference value, the memory controller 20 determines whether to update the initial voltage value of the erase voltage VERA.

[0324] 3.2 Effects of the Third Implementation

[0325] According to the third embodiment, by adjusting or updating at least one of the initial voltage value and pulse duration of the erase voltage VERA in the first erase cycle after the erase operation or the write operation, the erasure of the memory cell achieved by the erase operation can be optimized. In other words, by adjusting or updating at least one of the initial voltage value and pulse duration of the erase voltage VERA in the first erase cycle, the memory cell can be prevented from transitioning to an under-erased state or an over-erased state due to the erase operation.

[0326] By preventing the memory cell from transitioning to an over-erased state due to an erase operation, damage to the memory cell caused by the erase operation can be reduced. Furthermore, by preventing the memory cell from transitioning to an under-erased state due to an erase operation, read errors during page reads, such as those involving state A, can be reduced. Other structures and effects are the same as those of the first embodiment.

[0327] 4. Fourth Implementation Method

[0328] The following describes an erase operation in the storage system 1 according to the fourth embodiment. The storage system 1 according to the fourth embodiment has the same configuration as that of the first embodiment. The fourth embodiment will be described mainly with respect to differences from the first embodiment.

[0329] 4.1 Erasing Operation in the Fourth Embodiment

[0330] In the erasing action of the fourth embodiment, the first example of judging the erasure depth of the storage cell after the erasing action in the semiconductor storage device 10 and notifying the storage controller 20 of the judgment result and the second example of adjusting the pulse time of the erasing voltage VERA based on the erasing result obtained with multiple judgment levels in the read action are described.

[0331] 4.1.1 The first example of erasing

[0332] In the first example, after the erase operation, the erase depth of the memory cells included in the word lines WL and string units SU to be measured within the erase target block is determined within the semiconductor memory device 10, and the determination result is notified to the memory controller 20. The memory controller 20 updates the pulse duration of the erase voltage VERA according to the received determination result.

[0333] Hereinafter, input and output of commands, addresses, and data between the memory controller 20 and the semiconductor memory device 10 in a first example of the erase operation according to the fourth embodiment will be described.

[0334] Figure 37 This diagram shows a command sequence in the first example of an erase operation according to the fourth embodiment. The output of commands and addresses from the memory controller 20 to the semiconductor memory device 10, as well as the input and output of data between the memory controller 20 and the semiconductor memory device 10, described below, are performed using I / O signals DQ0 to DQ7. Furthermore, the determination level prepared in a normal erase verify process is used as the determination level for determining the number of cutoff bits. Figure 37 The command sequence shown includes commands, addresses, and data input / output cycles. Commands are represented by hexagons, addresses by rounded quadrangles (or oval shapes), and data input / output cycles by quadrangles.

[0335] like Figure 37 As shown, the command sequence includes a phase P1 corresponding to "setting the pulse time of the erase voltage VERA", a phase P21 corresponding to "commanding to perform an erase operation", and a phase P22 corresponding to "outputting the erase depth (judgment result)".

[0336] The command "Y0h" included in stage P21 instructs the semiconductor memory device 10 to perform an erase operation and then count the number of cutoff bits. Command "Y0h" includes stage P3 corresponding to "setting the determination level AR2 (step S11)", stage P4 or P4A corresponding to "instructing to read a lower page (step S22)", and stage P6 corresponding to "instructing to perform a single-level read (step S25)". Furthermore, this embodiment includes processing for counting the number of cutoff bits processed by the memory controller 20 to date in the semiconductor memory device 10. Therefore, the memory controller 20 can obtain the number of cutoff bits indicating the erase depth of the memory cell by simply specifying stage P21, without specifying stages P3, P4 (or P4A), and P6 to the semiconductor memory device 10.

[0337] First, in phase P1 of setting the pulse duration of the erase voltage VERA, the memory controller 20 sequentially outputs a command "0Xh," an address "00h," and data "PDr" to the semiconductor memory device 10. The command "0Xh" specifies the erase mode. The address "00h" sets the pulse duration of the erase voltage VERA. The data "PDr" indicates the pulse duration of the erase voltage VERA corresponding to the erase target block BLKr. Thus, the memory controller 20 specifies the erase mode for the semiconductor memory device 10 and sets the pulse duration PDr of the erase voltage VERA in the register 15D_1 of the semiconductor memory device 10.

[0338] Next, in stage P21, which instructs an erase operation, the memory controller 20 sequentially outputs an erase command "Y0h," which includes a process for calculating the number of cutoff bits required for the erase operation, an erase setup command "60h," the address "ADD" of the erase target block BLKr, and an erase execution command "D0h," to the semiconductor memory device 10. Upon receiving command "Y0h," the sequencer 16 of the semiconductor memory device 10 executes stage P3, which corresponds to "setting the determination level AR2 (step S11)," stage P4 or P4A, which corresponds to "instructing a lower page read (step S22)," and stage P6, which corresponds to "instructing a single-level read (step S25)." Then, upon receiving the erase execution command "D0h," the sequencer 16 of the semiconductor memory device 10 applies an erase voltage VERA for a pulse duration PDr to the well wiring CPWELL, thereby executing the erase operation on the erase target block BLKr.

[0339] Furthermore, the sequencer 16 performs an erase verification process on the erase target block BLKr to obtain the cutoff bit count. Specifically, the sequencer 16 reads data from the memory cells within the erase target block BLKr using the determination level used in the erase verification process to obtain the cutoff bit count. Based on the obtained cutoff bit count, the sequencer 16 determines the erase depth of the memory cells after the erase operation (i.e., whether they are in an under-erased state, a properly erased state, or an over-erased state).

[0340] Next, the memory controller 20 outputs a status read command "70h" to the semiconductor memory device 10. Upon receiving the status read command "70h", the semiconductor memory device 10 outputs data "PASS" indicating that the erase operation has passed to the memory controller 20, for example.

[0341] Next, as shown in stage P22, the memory controller 20 outputs a status read command "7Xh" for outputting data indicating the erase depth to the semiconductor memory device 10. Upon receiving the status read command "7Xh," the sequencer 16 of the semiconductor memory device 10 outputs data "DO5" indicating the erase depth to the memory controller 20.

[0342] The storage controller 20 then compares the data "DO5" indicating the erase depth with a pre-set threshold and updates the pulse time PDr of the erase voltage VERA based on the comparison result. For example, if the data "DO5" indicating the erase depth indicates an over-erased state, the storage controller 20 shortens the pulse time PDr of the erase voltage VERA by a predetermined time. Alternatively, if the data "DO5" indicating the erase depth indicates a properly erased state, the storage controller 20 does not update the pulse time PDr of the erase voltage VERA and maintains it unchanged. If the data "DO5" indicating the erase depth indicates an under-erased state, the storage controller 20 increases the pulse time PDr of the erase voltage VERA by a predetermined time.

[0343] In the first example, after the erase operation, the sequencer 16 in the semiconductor memory device 10 determines the erase depth of the memory cells based on the number of cutoff bits obtained in the read operation on the memory cells in the erase target block BLKr, and notifies the memory controller 20 of data indicating the erase depth. Based on the data indicating the erase depth, the memory controller 20 updates the pulse time PDr of the erase voltage VERA or maintains it without updating.

[0344] In addition, in the first example, the storage controller 20 determines whether to update the pulse time of the erase voltage VERA based on the data representing the erase depth, and updates the pulse time, but instead of this, it can determine whether to update the initial voltage value of the erase voltage VERA based on the data representing the erase depth, and update the initial voltage value.

[0345] 4.1.2 Second Example of Erase Action

[0346] The second example shows an example in which, after the erase operation, the pulse time of the erase voltage VERA is updated based on the erase result obtained in the read operation using a plurality of determination levels.

[0347] Figure 38 This is a flowchart showing a second example of the erasing operation in the storage system 1 according to the fourth embodiment. The flowchart showing the second example of the erasing operation is the same as the flowchart showing the second example of the erasing operation except for "judging the pulse time of the erasing voltage VERA" (step S3B). Figure 8 The flowchart of the first example of the erasing operation of the first embodiment shown in FIG. Figure 38 The process of "determining the pulse time of the erase voltage VERA" in step S3B shown in FIG.

[0348] Figure 39 Yes Figure 38 Flowchart of the process of "determining the pulse time of the erase voltage VERA" in step S3B in FIG. Figure 39 The processing shown is commanded and controlled by the storage controller 20 (or the CPU 21 ). Figure 40 3B is a diagram showing the threshold voltage distribution of memory cells for the determination levels AR1 to AR4 used in the judgment in step S3B. Figure 41 This diagram shows the relationship between the number of cutoff bits and the erased state, as determined by judgment levels AR1 to AR4. The magnitude relationship between judgment levels AR1 to AR4 is AR4 < AR3 < AR2 < AR1. Furthermore, it is assumed that the erase depth is determined to be appropriate when the lower end of the threshold voltage distribution of an erased memory cell lies between judgment levels AR3 and AR2.

[0349] like Figure 39 As shown, first, the memory controller 20 sets the read voltage to the read voltage AR of state "A" and further sets an offset value F3 offset from the read voltage AR. Here, the read voltage offset by the offset value F3 from the read voltage AR is defined as the judgment level AR3. The judgment level AR3 is a voltage level for judging the erase depth of the memory cell after the erase operation. The memory controller 20 sets the judgment level AR3 offset by the offset value F3 from the read voltage AR (refer to Figure 40 ) is set in the semiconductor memory device 10. Furthermore, the memory controller 20 specifies the word line WL and the string unit SU to be measured in the erase target block BLKr to the semiconductor memory device 10 (step S51).

[0350] Next, the memory controller 20 instructs the semiconductor memory device 10 to perform a "single-level read" (step S52). Upon receiving the "single-level read" command, the sequencer 16 of the semiconductor memory device 10 reads the memory cell being measured at the set judgment level AR3. During this read operation, memory cells with a threshold voltage higher than the judgment level AR3 do not become conductive and remain in the off state. The sequencer 16 outputs a read result RA3R at the judgment level AR3 from the semiconductor memory device 10 to the memory controller 20. Based on the read result RA3R, the memory controller 20 counts the number of memory cells that do not become conductive and remain in the off state (hereinafter referred to as the first cutoff bit count). The memory controller 20 stores the first cutoff bit count in the buffer 22A within the memory 22.

[0351] Next, the memory controller 20 determines the erase depth of the memory cell after the erase operation based on the read result at the determination level AR3. Specifically, the memory controller 20 determines the erase depth of the memory cell after the erase operation based on the first cutoff bit number obtained by the read operation at the determination level AR3. Specifically, the memory controller 20 determines whether the first cutoff bit number exceeds a reference value Y3 (step S53).

[0352] In step S53, if the first cutoff bit number exceeds the reference value Y3 (Yes), the memory controller 20 sets the read voltage to the read voltage AR of state "A" and further sets the offset value F2 offset from the read voltage AR. Here, the read voltage offset by the offset value F2 from the read voltage AR is defined as the judgment level AR2. The judgment level AR2 is a voltage level for judging the erase depth of the memory cell after the erase operation. The memory controller 20 sets the judgment level AR2 offset by the offset value F2 from the read voltage AR (refer to Figure 40 ) is set in the semiconductor memory device 10. Furthermore, the memory controller 20 specifies the word line WL and the string unit SU to be measured in the erase target block BLKr to the semiconductor memory device 10 (step S54).

[0353] Next, the memory controller 20 instructs the semiconductor memory device 10 to perform a "single-level read" in state "A" (step S55). Upon receiving the "single-level read" command in state "A," the sequencer 16 of the semiconductor memory device 10 performs a read operation on the memory cell to be measured at the set judgment level AR2. During this read operation, memory cells with a threshold voltage higher than the judgment level AR2 do not become conductive and remain in the off state. The sequencer 16 outputs a read result RA2R at the judgment level AR2 from the semiconductor memory device 10 to the memory controller 20. Based on the read result RA2R, the memory controller 20 counts the number of memory cells that do not become conductive and remain in the off state (hereinafter referred to as the second cutoff bit number). The memory controller 20 stores the second cutoff bit number in the buffer 22A within the memory 22.

[0354] Next, the memory controller 20 determines the erase depth of the memory cell based on the read result at the determination level AR2. Specifically, the memory controller 20 determines the erase depth of the memory cell based on the second cutoff bit number obtained by the read operation at the determination level AR2. Specifically, the memory controller 20 determines whether the second cutoff bit number exceeds a reference value Y2 (step S56).

[0355] In step S56 , if the second cutoff bit number does not exceed the reference value Y2 (No), the memory controller 20 determines that the erase depth of the memory cell is in the erase proper state and ends the pulse time determination process.

[0356] On the other hand, in step S56, when the second cutoff bit number exceeds the reference value Y2 (yes), the memory controller 20 sets the read voltage to the read voltage AR of state "A", and further sets the offset value F1 offset from the read voltage AR. Here, the read voltage offset by the offset value F1 from the read voltage AR is defined as the judgment level AR1. The judgment level AR1 is a voltage level for judging the erase depth of the memory cell after the erase operation. The memory controller 20 sets the judgment level AR1 offset by the offset value F1 from the read voltage AR (refer to Figure 40 ) is set in the semiconductor memory device 10. Furthermore, the memory controller 20 specifies the word line WL and the string unit SU to be measured in the erase target block BLKr to the semiconductor memory device 10 (step S57).

[0357] Next, the memory controller 20 instructs the semiconductor memory device 10 to perform a "single-level read" (step S58). Upon receiving the "single-level read" command, the sequencer 16 of the semiconductor memory device 10 performs a read operation on the memory cell being measured at the set judgment level AR1. During this read operation, memory cells whose threshold voltage is higher than the judgment level AR1 do not enter the conducting state and remain in the off state. The sequencer 16 outputs a read result RA1R at the judgment level AR1 from the semiconductor memory device 10 to the memory controller 20. Based on the read result RA1R, the memory controller 20 counts the number of memory cells that do not enter the conducting state and remain in the off state (hereinafter referred to as the third cutoff bit number). The memory controller 20 stores the third cutoff bit number in the buffer 22A within the memory 22.

[0358] Next, the memory controller 20 determines the erase depth of the memory cell based on the read result at the determination level AR1. Specifically, the memory controller 20 determines the erase depth of the memory cell based on the third cutoff bit number obtained by the read operation at the determination level AR1. Specifically, the memory controller 20 determines whether the third cutoff bit number exceeds a reference value Y1 (step S59).

[0359] If the third cutoff bit number does not exceed the reference value Y1 in step S59 (No), the memory controller 20 determines that the erase depth of the memory cell is slightly under-erased and increases the pulse time PDr of the erase voltage VERA by one step (step S60). The pulse time determination process then ends.

[0360] On the other hand, if the third cutoff bit number exceeds the reference value Y1 in step S59 (Yes), the memory controller 20 determines that the erase depth of the memory cell is insufficiently erased and increases the pulse time PDr of the erase voltage VERA by two steps (step S61). The pulse time determination process then ends.

[0361] In addition, in step S53, if the first cutoff bit number does not exceed the reference value Y3 (No), the memory controller 20 sets the read voltage to the read voltage AR of state "A" and further sets the offset value F4 offset from the read voltage AR. Here, the read voltage offset by the offset value F4 from the read voltage AR is defined as the judgment level AR4. The judgment level AR4 is a voltage level for judging the erase depth of the memory cell after the erase operation. The memory controller 20 sets the judgment level AR4 offset by the offset value F4 from the read voltage AR (refer to Figure 40 ) is set in the semiconductor memory device 10. Furthermore, the memory controller 20 specifies the word line WL and the string unit SU to be measured in the erase target block BLKr to the semiconductor memory device 10 (step S62).

[0362] Next, the memory controller 20 instructs the semiconductor memory device 10 to perform a "single-level read" in state "A" (step S63). Upon receiving the "single-level read" command in state "A," the sequencer 16 of the semiconductor memory device 10 performs a read operation on the memory cell to be measured at the set judgment level AR4. During this read operation, memory cells with a threshold voltage higher than the judgment level AR4 do not become conductive and remain in the off state. The sequencer 16 outputs a read result RA4R at the judgment level AR4 from the semiconductor memory device 10 to the memory controller 20. Based on the read result RA4R, the memory controller 20 counts the number of memory cells that do not become conductive and remain in the off state (hereinafter referred to as the fourth cutoff bit number). The memory controller 20 stores the fourth cutoff bit number in the buffer 22A within the memory 22.

[0363] Next, the memory controller 20 determines the erase depth of the memory cell based on the read result at the determination level AR4. Specifically, the memory controller 20 determines the erase depth of the memory cell based on the fourth cutoff bit number obtained by the read operation at the determination level AR4. Specifically, the memory controller 20 determines whether the fourth cutoff bit number exceeds a reference value Y4 (step S64).

[0364] In step S64, if the fourth cutoff bit number exceeds the reference value Y4 (Yes), the memory controller 20 determines that the erase depth of the memory cell is slightly over-erased and shortens the pulse time PDr of the erase voltage VERA by one step (step S65). The pulse time determination process then ends.

[0365] On the other hand, if the fourth cutoff bit number does not exceed the reference value Y4 in step S64 (No), the memory controller 20 determines that the erase depth of the memory cell is in the over-erase state and shortens the pulse time PDr of the erase voltage VERA by two steps (step S66). The pulse time determination process then ends.

[0366] In the second example, after an erase operation, the memory controller 20 determines whether the memory cell is in an over-erased state, a slightly over-erased state, a properly erased state, a slightly under-erased state, or an under-erased state based on the number of cutoff bits obtained during a read operation using multiple determination levels for the memory cell being measured within the erase target block. Based on these determination results, the memory controller 20 updates the pulse duration PDr of the erase voltage VERA in four steps or maintains it without updating.

[0367] In addition, in the second example, the storage controller 20 determines whether to update the pulse time PDr of the erase voltage VERA based on the judgment result of the erase depth, and updates the pulse time PDr, but it can also determine whether to update the initial voltage value PAr of the erase voltage VERA instead of this, and update the initial voltage value PAr.

[0368] 4.1.3 The third example of erasing action

[0369] The third example is another embodiment of the second example. This third example shows another example of updating the pulse duration of the erase voltage VERA based on the erase result obtained in the read operation using a plurality of determination levels after the erase operation.

[0370] The flowchart showing the third example of the erasing operation is the same as the flowchart of the third example except for "judging the pulse time of the erasing voltage VERA" (step S3B). Figure 38 The flowchart of the second example shown is the same.

[0371] Below, use Figure 42 The process of “determining the pulse time of the erase voltage VERA” which is different from the second example will be described. Figure 42 This is a flowchart showing the process of “determining the pulse time of the erase voltage VERA” in the third example of the erase operation. Figure 42 The processing shown is commanded and controlled by the storage controller 20 (or the CPU 21 ).

[0372] like Figure 42 As shown, the memory controller 20 first sets the read voltage to the read voltage AR in state "A" and further sets an offset value F3 from the read voltage AR. Here, the read voltage offset by the offset value F3 from the read voltage AR is defined as the judgment level AR3. The judgment level AR3 is a voltage level used to determine the erase depth of the memory cell after the erase operation. The memory controller 20 sets the judgment level AR3, which is offset by the offset value F3 from the read voltage AR, in the semiconductor memory device 10. Furthermore, the memory controller 20 specifies the word line WL and string unit SU to be measured within the erase target block BLKr in the semiconductor memory device 10 (step S71).

[0373] Next, the memory controller 20 instructs the semiconductor memory device 10 to perform a "single-level read" in state "A" (step S72). Upon receiving the "single-level read" command in state "A," the sequencer 16 of the semiconductor memory device 10 reads the memory cell being measured at the set determination level AR3. The sequencer 16 outputs a read result RA3R at the determination level AR3 from the semiconductor memory device 10 to the memory controller 20. Based on the read result RA3R, the memory controller 20 counts the number of memory cells in the off state (the first off-bit number).

[0374] Next, the memory controller 20 sets the read voltage to the read voltage AR of state "A" and further sets an offset value F4 from the read voltage AR. Here, the read voltage offset by the offset value F4 from the read voltage AR is defined as the judgment level AR4. The judgment level AR4 is a voltage level used to determine the erase depth of the memory cell after the erase operation. The memory controller 20 sets the judgment level AR4, which is offset by the offset value F4 from the read voltage AR, in the semiconductor memory device 10. Furthermore, the memory controller 20 specifies the word line WL and string unit SU to be measured within the erase target block BLKr to the semiconductor memory device 10 (step S73).

[0375] Next, the memory controller 20 instructs the semiconductor memory device 10 to perform a "single-level read" in state "A" (step S74). Upon receiving the "single-level read" command in state "A," the sequencer 16 reads the memory cell being measured at the set determination level AR4. The sequencer 16 outputs a read result RA4R at the determination level AR4 from the semiconductor memory device 10 to the memory controller 20. Based on the read result RA4R, the memory controller 20 counts the number of memory cells in the off state (the second off-bit number).

[0376] Next, the memory controller 20 sets the read voltage to the read voltage AR of state "A" and further sets an offset value F2 from the read voltage AR. Here, the read voltage offset by the offset value F2 from the read voltage AR is defined as the judgment level AR2. The judgment level AR2 is a voltage level used to determine the erase depth of the memory cell after the erase operation. The memory controller 20 sets the judgment level AR2, which is offset by the offset value F2 from the read voltage AR, in the semiconductor memory device 10. Furthermore, the memory controller 20 specifies the word line WL and string unit SU to be measured within the erase target block BLKr to the semiconductor memory device 10 (step S75).

[0377] Next, the memory controller 20 instructs the semiconductor memory device 10 to perform a "single-level read" in state "A" (step S76). Upon receiving the "single-level read" command in state "A," the sequencer 16 reads the memory cell being measured at the set determination level AR2. The sequencer 16 outputs a read result RA2R at the determination level AR2 from the semiconductor memory device 10 to the memory controller 20. Based on the read result RA2R, the memory controller 20 counts the number of memory cells in the off state (the third number of off bits).

[0378] Next, the memory controller 20 sets the read voltage to the read voltage AR of state "A" and further sets an offset value F1 from the read voltage AR. Here, the read voltage offset by the offset value F1 from the read voltage AR is defined as the judgment level AR1. The judgment level AR1 is a voltage level used to determine the erase depth of the memory cell after the erase operation. The memory controller 20 sets the judgment level AR1, which is offset by the offset value F1 from the read voltage AR, in the semiconductor memory device 10. Furthermore, the memory controller 20 specifies the word line WL and string unit SU to be measured within the erase target block BLKr in the semiconductor memory device 10 (step S77).

[0379] Next, the memory controller 20 instructs the semiconductor memory device 10 to perform a "single-level read" in state "A" (step S78). Upon receiving the "single-level read" command in state "A," the sequencer 16 reads the memory cell being measured at the set determination level AR1. The sequencer 16 outputs a read result RA1R at the determination level AR1 from the semiconductor memory device 10 to the memory controller 20. Based on the read result RA1R, the memory controller 20 counts the number of memory cells in the off state (the fourth off-bit number).

[0380] Next, the memory controller 20 determines the erase depth of the memory cell based on whether the first to fourth cutoff bits obtained during the read operation at read voltages AR1 to AR4 exceed a reference value. Furthermore, the memory controller 20 updates the pulse time PDr based on the erase depth determination result (step S79). This completes the pulse time determination process.

[0381] In the third example, similar to the second example, the memory controller 20 determines whether the memory cell is in an over-erased state, a slightly over-erased state, a properly erased state, a slightly under-erased state, or an under-erased state based on the number of cutoff bits obtained in a read operation using multiple determination levels. Furthermore, based on these determination results, the memory controller 20 updates the pulse time PDr of the erase voltage VERA or maintains it without updating.

[0382] In addition, in the third example, the storage controller 20 determines whether to update the pulse time PDr of the erase voltage VERA based on the judgment result of the erase depth, and updates the pulse time PDr, but it can also determine whether to update the initial voltage value PAr of the erase voltage VERA instead of this, and update the initial voltage value PAr.

[0383] 4.2 Effects of the Fourth Implementation

[0384] According to the fourth embodiment, by adjusting or updating the pulse duration of the erase voltage VERA after the erase operation, the erasure of the memory cell by the erase operation can be optimized. In other words, by adjusting or updating the pulse duration of the erase voltage VERA, the memory cell can be prevented from transitioning to an under-erased state or an over-erased state due to the erase operation.

[0385] By preventing the memory cell from transitioning to an over-erased state due to an erase operation, damage to the memory cell caused by the erase operation can be reduced. Furthermore, by preventing the memory cell from transitioning to an under-erased state due to an erase operation, read errors during page reads, such as those involving state A, can be reduced. Other structures and effects are the same as those of the first embodiment.

[0386] 5. Other modifications, etc.

[0387] Furthermore, while the above embodiments describe NAND flash memory as an example of a semiconductor memory device, the present invention is not limited to NAND flash memory and can be applied to all other semiconductor memory devices, and further, to various memory devices other than semiconductor memory devices. Furthermore, the order of the processing in the flowcharts described in the above embodiments can be reversed, if appropriate.

[0388] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways and can be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention and, likewise, within the scope of the invention described in the claims and their equivalents.

Claims

1. A storage system comprising: A semiconductor memory device including a first memory cell capable of storing data; and a controller that outputs a first parameter and a first command, wherein the first parameter is a parameter related to an erase voltage used in a first erase operation on the first memory cell, and the first command is a command to instruct the first erase operation to be performed; After outputting the parameters to the semiconductor storage device, the controller outputs the first command. The first erasing operation includes a first process, the first process including an erasing process of applying an erasing voltage to the first memory cell and an erasing verification process of verifying whether a verification result obtained by performing a verification process on the first memory cell is a pass or fail after the erasing process. The controller executes the first process again when the result is failure, and terminates the first erasing operation when the result is pass. The semiconductor memory device includes a plurality of memory cells including the first memory cell. After performing the first erasing operation on the plurality of memory cells and then performing a writing operation on a portion of the plurality of memory cells, the controller updates the parameters based on the result of a reading operation on at least another portion of the plurality of memory cells after the first erasing operation.

2. The storage system according to claim 1, The first parameter includes at least one of a pulse duration and a voltage value of an erase voltage applied to the first memory cell when performing the first erase operation.

3. The storage system according to claim 1, The semiconductor memory device includes a block including a plurality of the first memory cells. The controller instructs the first erasing operation to be performed on the block.

4. The storage system according to claim 1, the controller, outputting a second parameter related to a first voltage used in a read operation on the first memory cell, obtaining a first number, the first number being the number of memory cells in the OFF state during the read operation, among the plurality of memory cells; When the first number is greater than the first value, the parameter is updated.

5. The storage system according to claim 1, The semiconductor memory device outputs a result to the controller, the result being a result of a read operation on the first memory cell after the first erase operation. The controller updates the parameters based on the results.

6. The storage system according to claim 1, The controller stores a table including the parameters corresponding to the first storage unit.

7. The storage system according to claim 1, The semiconductor memory device performs the erase process using the parameters.

8. The storage system according to claim 1, When the first erasing operation is performed a plurality of times on the first memory cell, the controller updates the parameter based on a result of a read operation on the first memory cell after the first erasing operation each time the first erasing operation is performed.

9. The storage system according to claim 1, When the first erasing operation is performed a plurality of times on the first memory cell, the controller updates the parameter based on a result of a read operation on the first memory cell after the first erasing operation each time the first erasing operation is performed a predetermined number of times.

10. The storage system according to claim 4, The semiconductor memory device includes a first word line connected to the plurality of memory cells.

11. The storage system according to claim 1, The semiconductor memory device includes a plurality of first word lines connected to the plurality of memory cells. the controller, outputting a second parameter related to a first voltage used in a read operation on the first memory cell, obtaining a second number, the second number being the number of memory cells in the plurality of memory cells that are in an off state during a read operation for each of the first word lines; When the second number is greater than the first value, the parameter is updated.

12. The storage system according to claim 1, The semiconductor memory device includes a second word line connected to a portion of the plurality of memory cells and a third word line connected to another portion of the plurality of memory cells. the controller, outputting a second parameter related to a first voltage used in a read operation on the first memory cell, obtaining a third number, the third number being the number of memory cells in the OFF state during the read operation of the second word line among the plurality of memory cells; obtaining a fourth number, the fourth number being the number of memory cells in the OFF state during the read operation of the third word line among the plurality of memory cells; When at least one of the third number and the fourth number is larger than the first value, the parameter is updated.

13. The storage system according to claim 1, The plurality of memory cells are stacked over a semiconductor substrate.

14. The storage system according to claim 4, When the controller performs the first erase operation a plurality of times on the plurality of memory cells, the controller changes the first value according to the number of times the first erase operation is performed.

15. The storage system according to claim 1, After the first command is output to the semiconductor memory device, After outputting a second parameter different from the first parameter, the controller outputs a second command, wherein the second parameter is a parameter related to the erase voltage used in the second erase operation on the first storage unit, and the second command is a command to perform the second erase operation.

16. A storage system comprising: A semiconductor memory device including a first memory cell capable of storing data; and a controller that outputs a first parameter and a first command, wherein the first parameter is a parameter related to an erase voltage used in a first erase operation on the first memory cell, and the first command is a command to instruct the first erase operation to be performed; After outputting the parameters to the semiconductor storage device, the controller outputs the first command. The semiconductor memory device includes a plurality of memory cells including the first memory cell. the controller, outputting a second parameter related to a first voltage used in a first read operation on the first memory cell, and obtaining a first number, wherein the second parameter is a parameter related to a first voltage used in a first read operation on the first memory cell, and the first number is the number of memory cells in an off state in the first read operation among the plurality of memory cells; When the first number is greater than a first value, a third parameter is output, a second number is acquired, and the parameter is updated based on whether the second number is greater than the second value, the third parameter being a parameter related to a second voltage used in a second read operation on the first memory cell, the second number being the number of memory cells in an off state in the second read operation among the plurality of memory cells, When the first number is smaller than the first value, a fourth parameter is output to obtain a third number, and the parameter is updated based on whether the third number is larger than the third value, wherein the fourth parameter is a parameter related to a third voltage used in a third read operation on the first memory cell, and the third number is the number of memory cells in an off state in the third read operation among the plurality of memory cells. The second voltage is greater than the first voltage, The third voltage is lower than the first voltage.

17. A semiconductor memory device comprising: a plurality of memory cells capable of storing data; and a control circuit for performing an erasing operation on the plurality of storage cells; The control circuit receives parameters related to the erase voltage used in the erase operation, then receives a first command for instructing to perform the erase operation, and then performs the erase operation using the parameters. After performing the erase operation on the plurality of memory cells and then performing the write operation on a portion of the plurality of memory cells, the parameters are updated based on the result of the read operation on at least another portion of the plurality of memory cells after the erase operation.

18. The semiconductor memory device according to claim 17, The control circuit performs the erasing operation on the multiple storage units that are the objects of the erasing operation when it receives the second command specifying that the object of use of the parameter is an erasing operation, then receives an address specifying the category of the parameter, then receives data indicating the set value of the parameter, then receives the first command, then receives the address of the object of the erasing operation, and then receives the third command for starting the erasing operation.

Images